1 /** 2 * @file dvs_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the DVS Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup dvs_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78002_INCLUDE_DVS_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78002_INCLUDE_DVS_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup dvs 67 * @defgroup dvs_registers DVS_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the DVS Peripheral Module. 69 * @details Dynamic Voltage Scaling 70 */ 71 72 /** 73 * @ingroup dvs_registers 74 * Structure type to access the DVS Registers. 75 */ 76 typedef struct { 77 __IO uint32_t ctl; /**< <tt>\b 0x00:</tt> DVS CTL Register */ 78 __IO uint32_t stat; /**< <tt>\b 0x04:</tt> DVS STAT Register */ 79 __IO uint32_t direct; /**< <tt>\b 0x08:</tt> DVS DIRECT Register */ 80 __IO uint32_t mon; /**< <tt>\b 0x00C:</tt> DVS MON Register */ 81 __IO uint32_t adj_up; /**< <tt>\b 0x010:</tt> DVS ADJ_UP Register */ 82 __IO uint32_t adj_dwn; /**< <tt>\b 0x014:</tt> DVS ADJ_DWN Register */ 83 __IO uint32_t thres_cmp; /**< <tt>\b 0x018:</tt> DVS THRES_CMP Register */ 84 __IO uint32_t tap_sel[5]; /**< <tt>\b 0x1C:</tt> DVS TAP_SEL Register */ 85 } mxc_dvs_regs_t; 86 87 /* Register offsets for module DVS */ 88 /** 89 * @ingroup dvs_registers 90 * @defgroup DVS_Register_Offsets Register Offsets 91 * @brief DVS Peripheral Register Offsets from the DVS Base Peripheral Address. 92 * @{ 93 */ 94 #define MXC_R_DVS_CTL ((uint32_t)0x00000000UL) /**< Offset from DVS Base Address: <tt> 0x0000</tt> */ 95 #define MXC_R_DVS_STAT ((uint32_t)0x00000004UL) /**< Offset from DVS Base Address: <tt> 0x0004</tt> */ 96 #define MXC_R_DVS_DIRECT ((uint32_t)0x00000008UL) /**< Offset from DVS Base Address: <tt> 0x0008</tt> */ 97 #define MXC_R_DVS_MON ((uint32_t)0x0000000CUL) /**< Offset from DVS Base Address: <tt> 0x000C</tt> */ 98 #define MXC_R_DVS_ADJ_UP ((uint32_t)0x00000010UL) /**< Offset from DVS Base Address: <tt> 0x0010</tt> */ 99 #define MXC_R_DVS_ADJ_DWN ((uint32_t)0x00000014UL) /**< Offset from DVS Base Address: <tt> 0x0014</tt> */ 100 #define MXC_R_DVS_THRES_CMP ((uint32_t)0x00000018UL) /**< Offset from DVS Base Address: <tt> 0x0018</tt> */ 101 #define MXC_R_DVS_TAP_SEL ((uint32_t)0x0000001CUL) /**< Offset from DVS Base Address: <tt> 0x001C</tt> */ 102 /**@} end of group dvs_registers */ 103 104 /** 105 * @ingroup dvs_registers 106 * @defgroup DVS_CTL DVS_CTL 107 * @brief Control Register 108 * @{ 109 */ 110 #define MXC_F_DVS_CTL_MON_ENA_POS 0 /**< CTL_MON_ENA Position */ 111 #define MXC_F_DVS_CTL_MON_ENA ((uint32_t)(0x1UL << MXC_F_DVS_CTL_MON_ENA_POS)) /**< CTL_MON_ENA Mask */ 112 113 #define MXC_F_DVS_CTL_ADJ_ENA_POS 1 /**< CTL_ADJ_ENA Position */ 114 #define MXC_F_DVS_CTL_ADJ_ENA ((uint32_t)(0x1UL << MXC_F_DVS_CTL_ADJ_ENA_POS)) /**< CTL_ADJ_ENA Mask */ 115 116 #define MXC_F_DVS_CTL_PS_FB_DIS_POS 2 /**< CTL_PS_FB_DIS Position */ 117 #define MXC_F_DVS_CTL_PS_FB_DIS ((uint32_t)(0x1UL << MXC_F_DVS_CTL_PS_FB_DIS_POS)) /**< CTL_PS_FB_DIS Mask */ 118 119 #define MXC_F_DVS_CTL_CTRL_TAP_ENA_POS 3 /**< CTL_CTRL_TAP_ENA Position */ 120 #define MXC_F_DVS_CTL_CTRL_TAP_ENA ((uint32_t)(0x1UL << MXC_F_DVS_CTL_CTRL_TAP_ENA_POS)) /**< CTL_CTRL_TAP_ENA Mask */ 121 122 #define MXC_F_DVS_CTL_PROP_DLY_POS 4 /**< CTL_PROP_DLY Position */ 123 #define MXC_F_DVS_CTL_PROP_DLY ((uint32_t)(0x3UL << MXC_F_DVS_CTL_PROP_DLY_POS)) /**< CTL_PROP_DLY Mask */ 124 125 #define MXC_F_DVS_CTL_MON_ONESHOT_POS 6 /**< CTL_MON_ONESHOT Position */ 126 #define MXC_F_DVS_CTL_MON_ONESHOT ((uint32_t)(0x1UL << MXC_F_DVS_CTL_MON_ONESHOT_POS)) /**< CTL_MON_ONESHOT Mask */ 127 128 #define MXC_F_DVS_CTL_GO_DIRECT_POS 7 /**< CTL_GO_DIRECT Position */ 129 #define MXC_F_DVS_CTL_GO_DIRECT ((uint32_t)(0x1UL << MXC_F_DVS_CTL_GO_DIRECT_POS)) /**< CTL_GO_DIRECT Mask */ 130 131 #define MXC_F_DVS_CTL_DIRECT_REG_POS 8 /**< CTL_DIRECT_REG Position */ 132 #define MXC_F_DVS_CTL_DIRECT_REG ((uint32_t)(0x1UL << MXC_F_DVS_CTL_DIRECT_REG_POS)) /**< CTL_DIRECT_REG Mask */ 133 134 #define MXC_F_DVS_CTL_PRIME_ENA_POS 9 /**< CTL_PRIME_ENA Position */ 135 #define MXC_F_DVS_CTL_PRIME_ENA ((uint32_t)(0x1UL << MXC_F_DVS_CTL_PRIME_ENA_POS)) /**< CTL_PRIME_ENA Mask */ 136 137 #define MXC_F_DVS_CTL_LIMIT_IE_POS 10 /**< CTL_LIMIT_IE Position */ 138 #define MXC_F_DVS_CTL_LIMIT_IE ((uint32_t)(0x1UL << MXC_F_DVS_CTL_LIMIT_IE_POS)) /**< CTL_LIMIT_IE Mask */ 139 140 #define MXC_F_DVS_CTL_RANGE_IE_POS 11 /**< CTL_RANGE_IE Position */ 141 #define MXC_F_DVS_CTL_RANGE_IE ((uint32_t)(0x1UL << MXC_F_DVS_CTL_RANGE_IE_POS)) /**< CTL_RANGE_IE Mask */ 142 143 #define MXC_F_DVS_CTL_ADJ_IE_POS 12 /**< CTL_ADJ_IE Position */ 144 #define MXC_F_DVS_CTL_ADJ_IE ((uint32_t)(0x1UL << MXC_F_DVS_CTL_ADJ_IE_POS)) /**< CTL_ADJ_IE Mask */ 145 146 #define MXC_F_DVS_CTL_REF_SEL_POS 13 /**< CTL_REF_SEL Position */ 147 #define MXC_F_DVS_CTL_REF_SEL ((uint32_t)(0xFUL << MXC_F_DVS_CTL_REF_SEL_POS)) /**< CTL_REF_SEL Mask */ 148 149 #define MXC_F_DVS_CTL_INC_VAL_POS 17 /**< CTL_INC_VAL Position */ 150 #define MXC_F_DVS_CTL_INC_VAL ((uint32_t)(0x7UL << MXC_F_DVS_CTL_INC_VAL_POS)) /**< CTL_INC_VAL Mask */ 151 152 #define MXC_F_DVS_CTL_DVS_PS_APB_DIS_POS 20 /**< CTL_DVS_PS_APB_DIS Position */ 153 #define MXC_F_DVS_CTL_DVS_PS_APB_DIS ((uint32_t)(0x1UL << MXC_F_DVS_CTL_DVS_PS_APB_DIS_POS)) /**< CTL_DVS_PS_APB_DIS Mask */ 154 155 #define MXC_F_DVS_CTL_DVS_HI_RANGE_ANY_POS 21 /**< CTL_DVS_HI_RANGE_ANY Position */ 156 #define MXC_F_DVS_CTL_DVS_HI_RANGE_ANY ((uint32_t)(0x1UL << MXC_F_DVS_CTL_DVS_HI_RANGE_ANY_POS)) /**< CTL_DVS_HI_RANGE_ANY Mask */ 157 158 #define MXC_F_DVS_CTL_FB_TO_IE_POS 22 /**< CTL_FB_TO_IE Position */ 159 #define MXC_F_DVS_CTL_FB_TO_IE ((uint32_t)(0x1UL << MXC_F_DVS_CTL_FB_TO_IE_POS)) /**< CTL_FB_TO_IE Mask */ 160 161 #define MXC_F_DVS_CTL_FC_LV_IE_POS 23 /**< CTL_FC_LV_IE Position */ 162 #define MXC_F_DVS_CTL_FC_LV_IE ((uint32_t)(0x1UL << MXC_F_DVS_CTL_FC_LV_IE_POS)) /**< CTL_FC_LV_IE Mask */ 163 164 #define MXC_F_DVS_CTL_PD_ACK_ENA_POS 24 /**< CTL_PD_ACK_ENA Position */ 165 #define MXC_F_DVS_CTL_PD_ACK_ENA ((uint32_t)(0x1UL << MXC_F_DVS_CTL_PD_ACK_ENA_POS)) /**< CTL_PD_ACK_ENA Mask */ 166 167 #define MXC_F_DVS_CTL_ADJ_ABORT_POS 25 /**< CTL_ADJ_ABORT Position */ 168 #define MXC_F_DVS_CTL_ADJ_ABORT ((uint32_t)(0x1UL << MXC_F_DVS_CTL_ADJ_ABORT_POS)) /**< CTL_ADJ_ABORT Mask */ 169 170 /**@} end of group DVS_CTL_Register */ 171 172 /** 173 * @ingroup dvs_registers 174 * @defgroup DVS_STAT DVS_STAT 175 * @brief Status Fields 176 * @{ 177 */ 178 #define MXC_F_DVS_STAT_DVS_STATE_POS 0 /**< STAT_DVS_STATE Position */ 179 #define MXC_F_DVS_STAT_DVS_STATE ((uint32_t)(0xFUL << MXC_F_DVS_STAT_DVS_STATE_POS)) /**< STAT_DVS_STATE Mask */ 180 181 #define MXC_F_DVS_STAT_ADJ_UP_ENA_POS 4 /**< STAT_ADJ_UP_ENA Position */ 182 #define MXC_F_DVS_STAT_ADJ_UP_ENA ((uint32_t)(0x1UL << MXC_F_DVS_STAT_ADJ_UP_ENA_POS)) /**< STAT_ADJ_UP_ENA Mask */ 183 184 #define MXC_F_DVS_STAT_ADJ_DWN_ENA_POS 5 /**< STAT_ADJ_DWN_ENA Position */ 185 #define MXC_F_DVS_STAT_ADJ_DWN_ENA ((uint32_t)(0x1UL << MXC_F_DVS_STAT_ADJ_DWN_ENA_POS)) /**< STAT_ADJ_DWN_ENA Mask */ 186 187 #define MXC_F_DVS_STAT_ADJ_ACTIVE_POS 6 /**< STAT_ADJ_ACTIVE Position */ 188 #define MXC_F_DVS_STAT_ADJ_ACTIVE ((uint32_t)(0x1UL << MXC_F_DVS_STAT_ADJ_ACTIVE_POS)) /**< STAT_ADJ_ACTIVE Mask */ 189 190 #define MXC_F_DVS_STAT_CTR_TAP_OK_POS 7 /**< STAT_CTR_TAP_OK Position */ 191 #define MXC_F_DVS_STAT_CTR_TAP_OK ((uint32_t)(0x1UL << MXC_F_DVS_STAT_CTR_TAP_OK_POS)) /**< STAT_CTR_TAP_OK Mask */ 192 193 #define MXC_F_DVS_STAT_CTR_TAP_SEL_POS 8 /**< STAT_CTR_TAP_SEL Position */ 194 #define MXC_F_DVS_STAT_CTR_TAP_SEL ((uint32_t)(0x1UL << MXC_F_DVS_STAT_CTR_TAP_SEL_POS)) /**< STAT_CTR_TAP_SEL Mask */ 195 196 #define MXC_F_DVS_STAT_SLOW_TRIP_DET_POS 9 /**< STAT_SLOW_TRIP_DET Position */ 197 #define MXC_F_DVS_STAT_SLOW_TRIP_DET ((uint32_t)(0x1UL << MXC_F_DVS_STAT_SLOW_TRIP_DET_POS)) /**< STAT_SLOW_TRIP_DET Mask */ 198 199 #define MXC_F_DVS_STAT_FAST_TRIP_DET_POS 10 /**< STAT_FAST_TRIP_DET Position */ 200 #define MXC_F_DVS_STAT_FAST_TRIP_DET ((uint32_t)(0x1UL << MXC_F_DVS_STAT_FAST_TRIP_DET_POS)) /**< STAT_FAST_TRIP_DET Mask */ 201 202 #define MXC_F_DVS_STAT_PS_IN_RANGE_POS 11 /**< STAT_PS_IN_RANGE Position */ 203 #define MXC_F_DVS_STAT_PS_IN_RANGE ((uint32_t)(0x1UL << MXC_F_DVS_STAT_PS_IN_RANGE_POS)) /**< STAT_PS_IN_RANGE Mask */ 204 205 #define MXC_F_DVS_STAT_PS_VCNTR_POS 12 /**< STAT_PS_VCNTR Position */ 206 #define MXC_F_DVS_STAT_PS_VCNTR ((uint32_t)(0x7FUL << MXC_F_DVS_STAT_PS_VCNTR_POS)) /**< STAT_PS_VCNTR Mask */ 207 208 #define MXC_F_DVS_STAT_MON_DLY_OK_POS 19 /**< STAT_MON_DLY_OK Position */ 209 #define MXC_F_DVS_STAT_MON_DLY_OK ((uint32_t)(0x1UL << MXC_F_DVS_STAT_MON_DLY_OK_POS)) /**< STAT_MON_DLY_OK Mask */ 210 211 #define MXC_F_DVS_STAT_ADJ_DLY_OK_POS 20 /**< STAT_ADJ_DLY_OK Position */ 212 #define MXC_F_DVS_STAT_ADJ_DLY_OK ((uint32_t)(0x1UL << MXC_F_DVS_STAT_ADJ_DLY_OK_POS)) /**< STAT_ADJ_DLY_OK Mask */ 213 214 #define MXC_F_DVS_STAT_LO_LIMIT_DET_POS 21 /**< STAT_LO_LIMIT_DET Position */ 215 #define MXC_F_DVS_STAT_LO_LIMIT_DET ((uint32_t)(0x1UL << MXC_F_DVS_STAT_LO_LIMIT_DET_POS)) /**< STAT_LO_LIMIT_DET Mask */ 216 217 #define MXC_F_DVS_STAT_HI_LIMIT_DET_POS 22 /**< STAT_HI_LIMIT_DET Position */ 218 #define MXC_F_DVS_STAT_HI_LIMIT_DET ((uint32_t)(0x1UL << MXC_F_DVS_STAT_HI_LIMIT_DET_POS)) /**< STAT_HI_LIMIT_DET Mask */ 219 220 #define MXC_F_DVS_STAT_VALID_TAP_POS 23 /**< STAT_VALID_TAP Position */ 221 #define MXC_F_DVS_STAT_VALID_TAP ((uint32_t)(0x1UL << MXC_F_DVS_STAT_VALID_TAP_POS)) /**< STAT_VALID_TAP Mask */ 222 223 #define MXC_F_DVS_STAT_LIMIT_ERR_POS 24 /**< STAT_LIMIT_ERR Position */ 224 #define MXC_F_DVS_STAT_LIMIT_ERR ((uint32_t)(0x1UL << MXC_F_DVS_STAT_LIMIT_ERR_POS)) /**< STAT_LIMIT_ERR Mask */ 225 226 #define MXC_F_DVS_STAT_RANGE_ERR_POS 25 /**< STAT_RANGE_ERR Position */ 227 #define MXC_F_DVS_STAT_RANGE_ERR ((uint32_t)(0x1UL << MXC_F_DVS_STAT_RANGE_ERR_POS)) /**< STAT_RANGE_ERR Mask */ 228 229 #define MXC_F_DVS_STAT_ADJ_ERR_POS 26 /**< STAT_ADJ_ERR Position */ 230 #define MXC_F_DVS_STAT_ADJ_ERR ((uint32_t)(0x1UL << MXC_F_DVS_STAT_ADJ_ERR_POS)) /**< STAT_ADJ_ERR Mask */ 231 232 #define MXC_F_DVS_STAT_REF_SEL_ERR_POS 27 /**< STAT_REF_SEL_ERR Position */ 233 #define MXC_F_DVS_STAT_REF_SEL_ERR ((uint32_t)(0x1UL << MXC_F_DVS_STAT_REF_SEL_ERR_POS)) /**< STAT_REF_SEL_ERR Mask */ 234 235 #define MXC_F_DVS_STAT_FB_TO_ERR_POS 28 /**< STAT_FB_TO_ERR Position */ 236 #define MXC_F_DVS_STAT_FB_TO_ERR ((uint32_t)(0x1UL << MXC_F_DVS_STAT_FB_TO_ERR_POS)) /**< STAT_FB_TO_ERR Mask */ 237 238 #define MXC_F_DVS_STAT_FB_TO_ERR_S_POS 29 /**< STAT_FB_TO_ERR_S Position */ 239 #define MXC_F_DVS_STAT_FB_TO_ERR_S ((uint32_t)(0x1UL << MXC_F_DVS_STAT_FB_TO_ERR_S_POS)) /**< STAT_FB_TO_ERR_S Mask */ 240 241 #define MXC_F_DVS_STAT_FC_LV_DET_INT_POS 30 /**< STAT_FC_LV_DET_INT Position */ 242 #define MXC_F_DVS_STAT_FC_LV_DET_INT ((uint32_t)(0x1UL << MXC_F_DVS_STAT_FC_LV_DET_INT_POS)) /**< STAT_FC_LV_DET_INT Mask */ 243 244 #define MXC_F_DVS_STAT_FC_LV_DET_S_POS 31 /**< STAT_FC_LV_DET_S Position */ 245 #define MXC_F_DVS_STAT_FC_LV_DET_S ((uint32_t)(0x1UL << MXC_F_DVS_STAT_FC_LV_DET_S_POS)) /**< STAT_FC_LV_DET_S Mask */ 246 247 /**@} end of group DVS_STAT_Register */ 248 249 /** 250 * @ingroup dvs_registers 251 * @defgroup DVS_DIRECT DVS_DIRECT 252 * @brief Direct control of target voltage 253 * @{ 254 */ 255 #define MXC_F_DVS_DIRECT_VOLTAGE_POS 0 /**< DIRECT_VOLTAGE Position */ 256 #define MXC_F_DVS_DIRECT_VOLTAGE ((uint32_t)(0x7FUL << MXC_F_DVS_DIRECT_VOLTAGE_POS)) /**< DIRECT_VOLTAGE Mask */ 257 258 /**@} end of group DVS_DIRECT_Register */ 259 260 /** 261 * @ingroup dvs_registers 262 * @defgroup DVS_MON DVS_MON 263 * @brief Monitor Delay 264 * @{ 265 */ 266 #define MXC_F_DVS_MON_DLY_POS 0 /**< MON_DLY Position */ 267 #define MXC_F_DVS_MON_DLY ((uint32_t)(0xFFFFFFUL << MXC_F_DVS_MON_DLY_POS)) /**< MON_DLY Mask */ 268 269 #define MXC_F_DVS_MON_PRE_POS 24 /**< MON_PRE Position */ 270 #define MXC_F_DVS_MON_PRE ((uint32_t)(0xFFUL << MXC_F_DVS_MON_PRE_POS)) /**< MON_PRE Mask */ 271 272 /**@} end of group DVS_MON_Register */ 273 274 /** 275 * @ingroup dvs_registers 276 * @defgroup DVS_ADJ_UP DVS_ADJ_UP 277 * @brief Up Delay Register 278 * @{ 279 */ 280 #define MXC_F_DVS_ADJ_UP_DLY_POS 0 /**< ADJ_UP_DLY Position */ 281 #define MXC_F_DVS_ADJ_UP_DLY ((uint32_t)(0xFFFFUL << MXC_F_DVS_ADJ_UP_DLY_POS)) /**< ADJ_UP_DLY Mask */ 282 283 #define MXC_F_DVS_ADJ_UP_PRE_POS 16 /**< ADJ_UP_PRE Position */ 284 #define MXC_F_DVS_ADJ_UP_PRE ((uint32_t)(0xFFUL << MXC_F_DVS_ADJ_UP_PRE_POS)) /**< ADJ_UP_PRE Mask */ 285 286 /**@} end of group DVS_ADJ_UP_Register */ 287 288 /** 289 * @ingroup dvs_registers 290 * @defgroup DVS_ADJ_DWN DVS_ADJ_DWN 291 * @brief Down Delay Register 292 * @{ 293 */ 294 #define MXC_F_DVS_ADJ_DWN_DLY_POS 0 /**< ADJ_DWN_DLY Position */ 295 #define MXC_F_DVS_ADJ_DWN_DLY ((uint32_t)(0xFFFFUL << MXC_F_DVS_ADJ_DWN_DLY_POS)) /**< ADJ_DWN_DLY Mask */ 296 297 #define MXC_F_DVS_ADJ_DWN_PRE_POS 16 /**< ADJ_DWN_PRE Position */ 298 #define MXC_F_DVS_ADJ_DWN_PRE ((uint32_t)(0xFFUL << MXC_F_DVS_ADJ_DWN_PRE_POS)) /**< ADJ_DWN_PRE Mask */ 299 300 /**@} end of group DVS_ADJ_DWN_Register */ 301 302 /** 303 * @ingroup dvs_registers 304 * @defgroup DVS_THRES_CMP DVS_THRES_CMP 305 * @brief Up Delay Register 306 * @{ 307 */ 308 #define MXC_F_DVS_THRES_CMP_VCNTR_THRES_CNT_POS 0 /**< THRES_CMP_VCNTR_THRES_CNT Position */ 309 #define MXC_F_DVS_THRES_CMP_VCNTR_THRES_CNT ((uint32_t)(0x7FUL << MXC_F_DVS_THRES_CMP_VCNTR_THRES_CNT_POS)) /**< THRES_CMP_VCNTR_THRES_CNT Mask */ 310 311 #define MXC_F_DVS_THRES_CMP_VCNTR_THRES_MASK_POS 8 /**< THRES_CMP_VCNTR_THRES_MASK Position */ 312 #define MXC_F_DVS_THRES_CMP_VCNTR_THRES_MASK ((uint32_t)(0x7FUL << MXC_F_DVS_THRES_CMP_VCNTR_THRES_MASK_POS)) /**< THRES_CMP_VCNTR_THRES_MASK Mask */ 313 314 /**@} end of group DVS_THRES_CMP_Register */ 315 316 /** 317 * @ingroup dvs_registers 318 * @defgroup DVS_TAP_SEL DVS_TAP_SEL 319 * @brief DVS Tap Select Register 320 * @{ 321 */ 322 #define MXC_F_DVS_TAP_SEL_LO_POS 0 /**< TAP_SEL_LO Position */ 323 #define MXC_F_DVS_TAP_SEL_LO ((uint32_t)(0x1FUL << MXC_F_DVS_TAP_SEL_LO_POS)) /**< TAP_SEL_LO Mask */ 324 325 #define MXC_F_DVS_TAP_SEL_LO_TAP_STAT_POS 5 /**< TAP_SEL_LO_TAP_STAT Position */ 326 #define MXC_F_DVS_TAP_SEL_LO_TAP_STAT ((uint32_t)(0x1UL << MXC_F_DVS_TAP_SEL_LO_TAP_STAT_POS)) /**< TAP_SEL_LO_TAP_STAT Mask */ 327 328 #define MXC_F_DVS_TAP_SEL_CTR_TAP_STAT_POS 6 /**< TAP_SEL_CTR_TAP_STAT Position */ 329 #define MXC_F_DVS_TAP_SEL_CTR_TAP_STAT ((uint32_t)(0x1UL << MXC_F_DVS_TAP_SEL_CTR_TAP_STAT_POS)) /**< TAP_SEL_CTR_TAP_STAT Mask */ 330 331 #define MXC_F_DVS_TAP_SEL_HI_TAP_STAT_POS 7 /**< TAP_SEL_HI_TAP_STAT Position */ 332 #define MXC_F_DVS_TAP_SEL_HI_TAP_STAT ((uint32_t)(0x1UL << MXC_F_DVS_TAP_SEL_HI_TAP_STAT_POS)) /**< TAP_SEL_HI_TAP_STAT Mask */ 333 334 #define MXC_F_DVS_TAP_SEL_HI_POS 8 /**< TAP_SEL_HI Position */ 335 #define MXC_F_DVS_TAP_SEL_HI ((uint32_t)(0x1FUL << MXC_F_DVS_TAP_SEL_HI_POS)) /**< TAP_SEL_HI Mask */ 336 337 #define MXC_F_DVS_TAP_SEL_CTR_POS 16 /**< TAP_SEL_CTR Position */ 338 #define MXC_F_DVS_TAP_SEL_CTR ((uint32_t)(0x1FUL << MXC_F_DVS_TAP_SEL_CTR_POS)) /**< TAP_SEL_CTR Mask */ 339 340 #define MXC_F_DVS_TAP_SEL_COARSE_POS 24 /**< TAP_SEL_COARSE Position */ 341 #define MXC_F_DVS_TAP_SEL_COARSE ((uint32_t)(0x7UL << MXC_F_DVS_TAP_SEL_COARSE_POS)) /**< TAP_SEL_COARSE Mask */ 342 343 #define MXC_F_DVS_TAP_SEL_DET_DLY_POS 29 /**< TAP_SEL_DET_DLY Position */ 344 #define MXC_F_DVS_TAP_SEL_DET_DLY ((uint32_t)(0x3UL << MXC_F_DVS_TAP_SEL_DET_DLY_POS)) /**< TAP_SEL_DET_DLY Mask */ 345 346 #define MXC_F_DVS_TAP_SEL_DELAY_ACT_POS 31 /**< TAP_SEL_DELAY_ACT Position */ 347 #define MXC_F_DVS_TAP_SEL_DELAY_ACT ((uint32_t)(0x1UL << MXC_F_DVS_TAP_SEL_DELAY_ACT_POS)) /**< TAP_SEL_DELAY_ACT Mask */ 348 349 /**@} end of group DVS_TAP_SEL_Register */ 350 351 #ifdef __cplusplus 352 } 353 #endif 354 355 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78002_INCLUDE_DVS_REGS_H_ 356
