1 /** 2 * @file csi2_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the CSI2 Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup csi2_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78002_INCLUDE_CSI2_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78002_INCLUDE_CSI2_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup csi2 67 * @defgroup csi2_registers CSI2_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the CSI2 Peripheral Module. 69 * @details Camera Serial Interface Registers. 70 */ 71 72 /** 73 * @ingroup csi2_registers 74 * Structure type to access the CSI2 Registers. 75 */ 76 typedef struct { 77 __IO uint32_t cfg_num_lanes; /**< <tt>\b 0x000:</tt> CSI2 CFG_NUM_LANES Register */ 78 __IO uint32_t cfg_clk_lane_en; /**< <tt>\b 0x004:</tt> CSI2 CFG_CLK_LANE_EN Register */ 79 __IO uint32_t cfg_data_lane_en; /**< <tt>\b 0x008:</tt> CSI2 CFG_DATA_LANE_EN Register */ 80 __IO uint32_t cfg_flush_count; /**< <tt>\b 0x00C:</tt> CSI2 CFG_FLUSH_COUNT Register */ 81 __IO uint32_t cfg_bit_err; /**< <tt>\b 0x010:</tt> CSI2 CFG_BIT_ERR Register */ 82 __IO uint32_t irq_status; /**< <tt>\b 0x014:</tt> CSI2 IRQ_STATUS Register */ 83 __IO uint32_t irq_enable; /**< <tt>\b 0x018:</tt> CSI2 IRQ_ENABLE Register */ 84 __IO uint32_t irq_clr; /**< <tt>\b 0x01C:</tt> CSI2 IRQ_CLR Register */ 85 __IO uint32_t ulps_clk_status; /**< <tt>\b 0x020:</tt> CSI2 ULPS_CLK_STATUS Register */ 86 __IO uint32_t ulps_status; /**< <tt>\b 0x024:</tt> CSI2 ULPS_STATUS Register */ 87 __IO uint32_t ulps_clk_mark_status; /**< <tt>\b 0x028:</tt> CSI2 ULPS_CLK_MARK_STATUS Register */ 88 __IO uint32_t ulps_mark_status; /**< <tt>\b 0x02C:</tt> CSI2 ULPS_MARK_STATUS Register */ 89 __IO uint32_t ppi_errsot_hs; /**< <tt>\b 0x030:</tt> CSI2 PPI_ERRSOT_HS Register */ 90 __IO uint32_t ppi_errsotsync_hs; /**< <tt>\b 0x034:</tt> CSI2 PPI_ERRSOTSYNC_HS Register */ 91 __IO uint32_t ppi_erresc; /**< <tt>\b 0x038:</tt> CSI2 PPI_ERRESC Register */ 92 __IO uint32_t ppi_errsyncesc; /**< <tt>\b 0x03C:</tt> CSI2 PPI_ERRSYNCESC Register */ 93 __IO uint32_t ppi_errcontrol; /**< <tt>\b 0x040:</tt> CSI2 PPI_ERRCONTROL Register */ 94 __IO uint32_t cfg_cphy_en; /**< <tt>\b 0x044:</tt> CSI2 CFG_CPHY_EN Register */ 95 __IO uint32_t cfg_ppi_16_en; /**< <tt>\b 0x048:</tt> CSI2 CFG_PPI_16_EN Register */ 96 __IO uint32_t cfg_packet_interface_en; /**< <tt>\b 0x04C:</tt> CSI2 CFG_PACKET_INTERFACE_EN Register */ 97 __IO uint32_t cfg_vcx_en; /**< <tt>\b 0x050:</tt> CSI2 CFG_VCX_EN Register */ 98 __IO uint32_t cfg_byte_data_format; /**< <tt>\b 0x054:</tt> CSI2 CFG_BYTE_DATA_FORMAT Register */ 99 __IO uint32_t cfg_disable_payload_0; /**< <tt>\b 0x058:</tt> CSI2 CFG_DISABLE_PAYLOAD_0 Register */ 100 __IO uint32_t cfg_disable_payload_1; /**< <tt>\b 0x05C:</tt> CSI2 CFG_DISABLE_PAYLOAD_1 Register */ 101 __R uint32_t rsv_0x60_0x7f[8]; 102 __IO uint32_t cfg_vid_ignore_vc; /**< <tt>\b 0x080:</tt> CSI2 CFG_VID_IGNORE_VC Register */ 103 __IO uint32_t cfg_vid_vc; /**< <tt>\b 0x084:</tt> CSI2 CFG_VID_VC Register */ 104 __IO uint32_t cfg_p_fifo_send_level; /**< <tt>\b 0x088:</tt> CSI2 CFG_P_FIFO_SEND_LEVEL Register */ 105 __IO uint32_t cfg_vid_vsync; /**< <tt>\b 0x08C:</tt> CSI2 CFG_VID_VSYNC Register */ 106 __IO uint32_t cfg_vid_hsync_fp; /**< <tt>\b 0x090:</tt> CSI2 CFG_VID_HSYNC_FP Register */ 107 __IO uint32_t cfg_vid_hsync; /**< <tt>\b 0x094:</tt> CSI2 CFG_VID_HSYNC Register */ 108 __IO uint32_t cfg_vid_hsync_bp; /**< <tt>\b 0x098:</tt> CSI2 CFG_VID_HSYNC_BP Register */ 109 __R uint32_t rsv_0x9c_0x3ff[217]; 110 __IO uint32_t cfg_databus16_sel; /**< <tt>\b 0x400:</tt> CSI2 CFG_DATABUS16_SEL Register */ 111 __IO uint32_t cfg_d0_swap_sel; /**< <tt>\b 0x404:</tt> CSI2 CFG_D0_SWAP_SEL Register */ 112 __IO uint32_t cfg_d1_swap_sel; /**< <tt>\b 0x408:</tt> CSI2 CFG_D1_SWAP_SEL Register */ 113 __IO uint32_t cfg_d2_swap_sel; /**< <tt>\b 0x40C:</tt> CSI2 CFG_D2_SWAP_SEL Register */ 114 __IO uint32_t cfg_d3_swap_sel; /**< <tt>\b 0x410:</tt> CSI2 CFG_D3_SWAP_SEL Register */ 115 __IO uint32_t cfg_c0_swap_sel; /**< <tt>\b 0x414:</tt> CSI2 CFG_C0_SWAP_SEL Register */ 116 __IO uint32_t cfg_dpdn_swap; /**< <tt>\b 0x418:</tt> CSI2 CFG_DPDN_SWAP Register */ 117 __IO uint32_t rg_cfgclk_1us_cnt; /**< <tt>\b 0x41C:</tt> CSI2 RG_CFGCLK_1US_CNT Register */ 118 __IO uint32_t rg_hsrx_clk_pre_time_grp0; /**< <tt>\b 0x420:</tt> CSI2 RG_HSRX_CLK_PRE_TIME_GRP0 Register */ 119 __IO uint32_t rg_hsrx_data_pre_time_grp0; /**< <tt>\b 0x424:</tt> CSI2 RG_HSRX_DATA_PRE_TIME_GRP0 Register */ 120 __IO uint32_t reset_deskew; /**< <tt>\b 0x428:</tt> CSI2 RESET_DESKEW Register */ 121 __IO uint32_t pma_rdy; /**< <tt>\b 0x42C:</tt> CSI2 PMA_RDY Register */ 122 __IO uint32_t xcfgi_dw00; /**< <tt>\b 0x430:</tt> CSI2 XCFGI_DW00 Register */ 123 __IO uint32_t xcfgi_dw01; /**< <tt>\b 0x434:</tt> CSI2 XCFGI_DW01 Register */ 124 __IO uint32_t xcfgi_dw02; /**< <tt>\b 0x438:</tt> CSI2 XCFGI_DW02 Register */ 125 __IO uint32_t xcfgi_dw03; /**< <tt>\b 0x43C:</tt> CSI2 XCFGI_DW03 Register */ 126 __IO uint32_t xcfgi_dw04; /**< <tt>\b 0x440:</tt> CSI2 XCFGI_DW04 Register */ 127 __IO uint32_t xcfgi_dw05; /**< <tt>\b 0x444:</tt> CSI2 XCFGI_DW05 Register */ 128 __IO uint32_t xcfgi_dw06; /**< <tt>\b 0x448:</tt> CSI2 XCFGI_DW06 Register */ 129 __IO uint32_t xcfgi_dw07; /**< <tt>\b 0x44C:</tt> CSI2 XCFGI_DW07 Register */ 130 __IO uint32_t xcfgi_dw08; /**< <tt>\b 0x450:</tt> CSI2 XCFGI_DW08 Register */ 131 __IO uint32_t xcfgi_dw09; /**< <tt>\b 0x454:</tt> CSI2 XCFGI_DW09 Register */ 132 __IO uint32_t xcfgi_dw0a; /**< <tt>\b 0x458:</tt> CSI2 XCFGI_DW0A Register */ 133 __IO uint32_t xcfgi_dw0b; /**< <tt>\b 0x45C:</tt> CSI2 XCFGI_DW0B Register */ 134 __IO uint32_t xcfgi_dw0c; /**< <tt>\b 0x460:</tt> CSI2 XCFGI_DW0C Register */ 135 __IO uint32_t xcfgi_dw0d; /**< <tt>\b 0x464:</tt> CSI2 XCFGI_DW0D Register */ 136 __IO uint32_t gpio_mode; /**< <tt>\b 0x468:</tt> CSI2 GPIO_MODE Register */ 137 __IO uint32_t gpio_dp_ie; /**< <tt>\b 0x46C:</tt> CSI2 GPIO_DP_IE Register */ 138 __IO uint32_t gpio_dn_ie; /**< <tt>\b 0x470:</tt> CSI2 GPIO_DN_IE Register */ 139 __IO uint32_t gpio_dp_c; /**< <tt>\b 0x474:</tt> CSI2 GPIO_DP_C Register */ 140 __IO uint32_t gpio_dn_c; /**< <tt>\b 0x478:</tt> CSI2 GPIO_DN_C Register */ 141 __IO uint32_t vcontrol; /**< <tt>\b 0x47C:</tt> CSI2 VCONTROL Register */ 142 __IO uint32_t mpsov1; /**< <tt>\b 0x480:</tt> CSI2 MPSOV1 Register */ 143 __IO uint32_t mpsov2; /**< <tt>\b 0x484:</tt> CSI2 MPSOV2 Register */ 144 __IO uint32_t mpsov3; /**< <tt>\b 0x488:</tt> CSI2 MPSOV3 Register */ 145 __R uint32_t rsv_0x48c; 146 __IO uint32_t rg_cdrx_dsirx_en; /**< <tt>\b 0x490:</tt> CSI2 RG_CDRX_DSIRX_EN Register */ 147 __IO uint32_t rg_cdrx_l012_sublvds_en; /**< <tt>\b 0x494:</tt> CSI2 RG_CDRX_L012_SUBLVDS_EN Register */ 148 __IO uint32_t rg_cdrx_l012_hsrt_ctrl; /**< <tt>\b 0x498:</tt> CSI2 RG_CDRX_L012_HSRT_CTRL Register */ 149 __IO uint32_t rg_cdrx_bisths_pll_en; /**< <tt>\b 0x49C:</tt> CSI2 RG_CDRX_BISTHS_PLL_EN Register */ 150 __IO uint32_t rg_cdrx_bisths_pll_pre_div2; /**< <tt>\b 0x4A0:</tt> CSI2 RG_CDRX_BISTHS_PLL_PRE_DIV2 Register */ 151 __IO uint32_t rg_cdrx_bisths_pll_fbk_int; /**< <tt>\b 0x4A4:</tt> CSI2 RG_CDRX_BISTHS_PLL_FBK_INT Register */ 152 __IO uint32_t dbg1_mux_sel; /**< <tt>\b 0x4A8:</tt> CSI2 DBG1_MUX_SEL Register */ 153 __IO uint32_t dbg2_mux_sel; /**< <tt>\b 0x4AC:</tt> CSI2 DBG2_MUX_SEL Register */ 154 __IO uint32_t dbg1_mux_dout; /**< <tt>\b 0x4B0:</tt> CSI2 DBG1_MUX_DOUT Register */ 155 __IO uint32_t dbg2_mux_dout; /**< <tt>\b 0x4B4:</tt> CSI2 DBG2_MUX_DOUT Register */ 156 __IO uint32_t aon_power_ready_n; /**< <tt>\b 0x4B8:</tt> CSI2 AON_POWER_READY_N Register */ 157 __IO uint32_t dphy_rst_n; /**< <tt>\b 0x4BC:</tt> CSI2 DPHY_RST_N Register */ 158 __IO uint32_t rxbyteclkhs_inv; /**< <tt>\b 0x4C0:</tt> CSI2 RXBYTECLKHS_INV Register */ 159 __R uint32_t rsv_0x4c4_0x4ff[15]; 160 __IO uint32_t vfifo_cfg0; /**< <tt>\b 0x500:</tt> CSI2 VFIFO_CFG0 Register */ 161 __IO uint32_t vfifo_cfg1; /**< <tt>\b 0x504:</tt> CSI2 VFIFO_CFG1 Register */ 162 __IO uint32_t vfifo_ctrl; /**< <tt>\b 0x508:</tt> CSI2 VFIFO_CTRL Register */ 163 __IO uint32_t vfifo_sts; /**< <tt>\b 0x50C:</tt> CSI2 VFIFO_STS Register */ 164 __IO uint32_t vfifo_line_num; /**< <tt>\b 0x510:</tt> CSI2 VFIFO_LINE_NUM Register */ 165 __IO uint32_t vfifo_pixel_num; /**< <tt>\b 0x514:</tt> CSI2 VFIFO_PIXEL_NUM Register */ 166 __IO uint32_t vfifo_line_cnt; /**< <tt>\b 0x518:</tt> CSI2 VFIFO_LINE_CNT Register */ 167 __IO uint32_t vfifo_pixel_cnt; /**< <tt>\b 0x51C:</tt> CSI2 VFIFO_PIXEL_CNT Register */ 168 __IO uint32_t vfifo_frame_sts; /**< <tt>\b 0x520:</tt> CSI2 VFIFO_FRAME_STS Register */ 169 __IO uint32_t vfifo_raw_ctrl; /**< <tt>\b 0x524:</tt> CSI2 VFIFO_RAW_CTRL Register */ 170 __IO uint32_t vfifo_raw_buf0_addr; /**< <tt>\b 0x528:</tt> CSI2 VFIFO_RAW_BUF0_ADDR Register */ 171 __IO uint32_t vfifo_raw_buf1_addr; /**< <tt>\b 0x52C:</tt> CSI2 VFIFO_RAW_BUF1_ADDR Register */ 172 __IO uint32_t vfifo_ahbm_ctrl; /**< <tt>\b 0x530:</tt> CSI2 VFIFO_AHBM_CTRL Register */ 173 __IO uint32_t vfifo_ahbm_sts; /**< <tt>\b 0x534:</tt> CSI2 VFIFO_AHBM_STS Register */ 174 __IO uint32_t vfifo_ahbm_start_addr; /**< <tt>\b 0x538:</tt> CSI2 VFIFO_AHBM_START_ADDR Register */ 175 __IO uint32_t vfifo_ahbm_addr_range; /**< <tt>\b 0x53C:</tt> CSI2 VFIFO_AHBM_ADDR_RANGE Register */ 176 __IO uint32_t vfifo_ahbm_max_trans; /**< <tt>\b 0x540:</tt> CSI2 VFIFO_AHBM_MAX_TRANS Register */ 177 __IO uint32_t vfifo_ahbm_trans_cnt; /**< <tt>\b 0x544:</tt> CSI2 VFIFO_AHBM_TRANS_CNT Register */ 178 __R uint32_t rsv_0x548_0x5ff[46]; 179 __IO uint32_t rx_eint_vff_ie; /**< <tt>\b 0x600:</tt> CSI2 RX_EINT_VFF_IE Register */ 180 __IO uint32_t rx_eint_vff_if; /**< <tt>\b 0x604:</tt> CSI2 RX_EINT_VFF_IF Register */ 181 __IO uint32_t rx_eint_ppi_ie; /**< <tt>\b 0x608:</tt> CSI2 RX_EINT_PPI_IE Register */ 182 __IO uint32_t rx_eint_ppi_if; /**< <tt>\b 0x60C:</tt> CSI2 RX_EINT_PPI_IF Register */ 183 __IO uint32_t rx_eint_ctrl_ie; /**< <tt>\b 0x610:</tt> CSI2 RX_EINT_CTRL_IE Register */ 184 __IO uint32_t rx_eint_ctrl_if; /**< <tt>\b 0x614:</tt> CSI2 RX_EINT_CTRL_IF Register */ 185 __R uint32_t rsv_0x618_0x6ff[58]; 186 __IO uint32_t ppi_stopstate; /**< <tt>\b 0x700:</tt> CSI2 PPI_STOPSTATE Register */ 187 __IO uint32_t ppi_turnaround_cfg; /**< <tt>\b 0x704:</tt> CSI2 PPI_TURNAROUND_CFG Register */ 188 } mxc_csi2_regs_t; 189 190 /* Register offsets for module CSI2 */ 191 /** 192 * @ingroup csi2_registers 193 * @defgroup CSI2_Register_Offsets Register Offsets 194 * @brief CSI2 Peripheral Register Offsets from the CSI2 Base Peripheral Address. 195 * @{ 196 */ 197 #define MXC_R_CSI2_CFG_NUM_LANES ((uint32_t)0x00000000UL) /**< Offset from CSI2 Base Address: <tt> 0x0000</tt> */ 198 #define MXC_R_CSI2_CFG_CLK_LANE_EN ((uint32_t)0x00000004UL) /**< Offset from CSI2 Base Address: <tt> 0x0004</tt> */ 199 #define MXC_R_CSI2_CFG_DATA_LANE_EN ((uint32_t)0x00000008UL) /**< Offset from CSI2 Base Address: <tt> 0x0008</tt> */ 200 #define MXC_R_CSI2_CFG_FLUSH_COUNT ((uint32_t)0x0000000CUL) /**< Offset from CSI2 Base Address: <tt> 0x000C</tt> */ 201 #define MXC_R_CSI2_CFG_BIT_ERR ((uint32_t)0x00000010UL) /**< Offset from CSI2 Base Address: <tt> 0x0010</tt> */ 202 #define MXC_R_CSI2_IRQ_STATUS ((uint32_t)0x00000014UL) /**< Offset from CSI2 Base Address: <tt> 0x0014</tt> */ 203 #define MXC_R_CSI2_IRQ_ENABLE ((uint32_t)0x00000018UL) /**< Offset from CSI2 Base Address: <tt> 0x0018</tt> */ 204 #define MXC_R_CSI2_IRQ_CLR ((uint32_t)0x0000001CUL) /**< Offset from CSI2 Base Address: <tt> 0x001C</tt> */ 205 #define MXC_R_CSI2_ULPS_CLK_STATUS ((uint32_t)0x00000020UL) /**< Offset from CSI2 Base Address: <tt> 0x0020</tt> */ 206 #define MXC_R_CSI2_ULPS_STATUS ((uint32_t)0x00000024UL) /**< Offset from CSI2 Base Address: <tt> 0x0024</tt> */ 207 #define MXC_R_CSI2_ULPS_CLK_MARK_STATUS ((uint32_t)0x00000028UL) /**< Offset from CSI2 Base Address: <tt> 0x0028</tt> */ 208 #define MXC_R_CSI2_ULPS_MARK_STATUS ((uint32_t)0x0000002CUL) /**< Offset from CSI2 Base Address: <tt> 0x002C</tt> */ 209 #define MXC_R_CSI2_PPI_ERRSOT_HS ((uint32_t)0x00000030UL) /**< Offset from CSI2 Base Address: <tt> 0x0030</tt> */ 210 #define MXC_R_CSI2_PPI_ERRSOTSYNC_HS ((uint32_t)0x00000034UL) /**< Offset from CSI2 Base Address: <tt> 0x0034</tt> */ 211 #define MXC_R_CSI2_PPI_ERRESC ((uint32_t)0x00000038UL) /**< Offset from CSI2 Base Address: <tt> 0x0038</tt> */ 212 #define MXC_R_CSI2_PPI_ERRSYNCESC ((uint32_t)0x0000003CUL) /**< Offset from CSI2 Base Address: <tt> 0x003C</tt> */ 213 #define MXC_R_CSI2_PPI_ERRCONTROL ((uint32_t)0x00000040UL) /**< Offset from CSI2 Base Address: <tt> 0x0040</tt> */ 214 #define MXC_R_CSI2_CFG_CPHY_EN ((uint32_t)0x00000044UL) /**< Offset from CSI2 Base Address: <tt> 0x0044</tt> */ 215 #define MXC_R_CSI2_CFG_PPI_16_EN ((uint32_t)0x00000048UL) /**< Offset from CSI2 Base Address: <tt> 0x0048</tt> */ 216 #define MXC_R_CSI2_CFG_PACKET_INTERFACE_EN ((uint32_t)0x0000004CUL) /**< Offset from CSI2 Base Address: <tt> 0x004C</tt> */ 217 #define MXC_R_CSI2_CFG_VCX_EN ((uint32_t)0x00000050UL) /**< Offset from CSI2 Base Address: <tt> 0x0050</tt> */ 218 #define MXC_R_CSI2_CFG_BYTE_DATA_FORMAT ((uint32_t)0x00000054UL) /**< Offset from CSI2 Base Address: <tt> 0x0054</tt> */ 219 #define MXC_R_CSI2_CFG_DISABLE_PAYLOAD_0 ((uint32_t)0x00000058UL) /**< Offset from CSI2 Base Address: <tt> 0x0058</tt> */ 220 #define MXC_R_CSI2_CFG_DISABLE_PAYLOAD_1 ((uint32_t)0x0000005CUL) /**< Offset from CSI2 Base Address: <tt> 0x005C</tt> */ 221 #define MXC_R_CSI2_CFG_VID_IGNORE_VC ((uint32_t)0x00000080UL) /**< Offset from CSI2 Base Address: <tt> 0x0080</tt> */ 222 #define MXC_R_CSI2_CFG_VID_VC ((uint32_t)0x00000084UL) /**< Offset from CSI2 Base Address: <tt> 0x0084</tt> */ 223 #define MXC_R_CSI2_CFG_P_FIFO_SEND_LEVEL ((uint32_t)0x00000088UL) /**< Offset from CSI2 Base Address: <tt> 0x0088</tt> */ 224 #define MXC_R_CSI2_CFG_VID_VSYNC ((uint32_t)0x0000008CUL) /**< Offset from CSI2 Base Address: <tt> 0x008C</tt> */ 225 #define MXC_R_CSI2_CFG_VID_HSYNC_FP ((uint32_t)0x00000090UL) /**< Offset from CSI2 Base Address: <tt> 0x0090</tt> */ 226 #define MXC_R_CSI2_CFG_VID_HSYNC ((uint32_t)0x00000094UL) /**< Offset from CSI2 Base Address: <tt> 0x0094</tt> */ 227 #define MXC_R_CSI2_CFG_VID_HSYNC_BP ((uint32_t)0x00000098UL) /**< Offset from CSI2 Base Address: <tt> 0x0098</tt> */ 228 #define MXC_R_CSI2_CFG_DATABUS16_SEL ((uint32_t)0x00000400UL) /**< Offset from CSI2 Base Address: <tt> 0x0400</tt> */ 229 #define MXC_R_CSI2_CFG_D0_SWAP_SEL ((uint32_t)0x00000404UL) /**< Offset from CSI2 Base Address: <tt> 0x0404</tt> */ 230 #define MXC_R_CSI2_CFG_D1_SWAP_SEL ((uint32_t)0x00000408UL) /**< Offset from CSI2 Base Address: <tt> 0x0408</tt> */ 231 #define MXC_R_CSI2_CFG_D2_SWAP_SEL ((uint32_t)0x0000040CUL) /**< Offset from CSI2 Base Address: <tt> 0x040C</tt> */ 232 #define MXC_R_CSI2_CFG_D3_SWAP_SEL ((uint32_t)0x00000410UL) /**< Offset from CSI2 Base Address: <tt> 0x0410</tt> */ 233 #define MXC_R_CSI2_CFG_C0_SWAP_SEL ((uint32_t)0x00000414UL) /**< Offset from CSI2 Base Address: <tt> 0x0414</tt> */ 234 #define MXC_R_CSI2_CFG_DPDN_SWAP ((uint32_t)0x00000418UL) /**< Offset from CSI2 Base Address: <tt> 0x0418</tt> */ 235 #define MXC_R_CSI2_RG_CFGCLK_1US_CNT ((uint32_t)0x0000041CUL) /**< Offset from CSI2 Base Address: <tt> 0x041C</tt> */ 236 #define MXC_R_CSI2_RG_HSRX_CLK_PRE_TIME_GRP0 ((uint32_t)0x00000420UL) /**< Offset from CSI2 Base Address: <tt> 0x0420</tt> */ 237 #define MXC_R_CSI2_RG_HSRX_DATA_PRE_TIME_GRP0 ((uint32_t)0x00000424UL) /**< Offset from CSI2 Base Address: <tt> 0x0424</tt> */ 238 #define MXC_R_CSI2_RESET_DESKEW ((uint32_t)0x00000428UL) /**< Offset from CSI2 Base Address: <tt> 0x0428</tt> */ 239 #define MXC_R_CSI2_PMA_RDY ((uint32_t)0x0000042CUL) /**< Offset from CSI2 Base Address: <tt> 0x042C</tt> */ 240 #define MXC_R_CSI2_XCFGI_DW00 ((uint32_t)0x00000430UL) /**< Offset from CSI2 Base Address: <tt> 0x0430</tt> */ 241 #define MXC_R_CSI2_XCFGI_DW01 ((uint32_t)0x00000434UL) /**< Offset from CSI2 Base Address: <tt> 0x0434</tt> */ 242 #define MXC_R_CSI2_XCFGI_DW02 ((uint32_t)0x00000438UL) /**< Offset from CSI2 Base Address: <tt> 0x0438</tt> */ 243 #define MXC_R_CSI2_XCFGI_DW03 ((uint32_t)0x0000043CUL) /**< Offset from CSI2 Base Address: <tt> 0x043C</tt> */ 244 #define MXC_R_CSI2_XCFGI_DW04 ((uint32_t)0x00000440UL) /**< Offset from CSI2 Base Address: <tt> 0x0440</tt> */ 245 #define MXC_R_CSI2_XCFGI_DW05 ((uint32_t)0x00000444UL) /**< Offset from CSI2 Base Address: <tt> 0x0444</tt> */ 246 #define MXC_R_CSI2_XCFGI_DW06 ((uint32_t)0x00000448UL) /**< Offset from CSI2 Base Address: <tt> 0x0448</tt> */ 247 #define MXC_R_CSI2_XCFGI_DW07 ((uint32_t)0x0000044CUL) /**< Offset from CSI2 Base Address: <tt> 0x044C</tt> */ 248 #define MXC_R_CSI2_XCFGI_DW08 ((uint32_t)0x00000450UL) /**< Offset from CSI2 Base Address: <tt> 0x0450</tt> */ 249 #define MXC_R_CSI2_XCFGI_DW09 ((uint32_t)0x00000454UL) /**< Offset from CSI2 Base Address: <tt> 0x0454</tt> */ 250 #define MXC_R_CSI2_XCFGI_DW0A ((uint32_t)0x00000458UL) /**< Offset from CSI2 Base Address: <tt> 0x0458</tt> */ 251 #define MXC_R_CSI2_XCFGI_DW0B ((uint32_t)0x0000045CUL) /**< Offset from CSI2 Base Address: <tt> 0x045C</tt> */ 252 #define MXC_R_CSI2_XCFGI_DW0C ((uint32_t)0x00000460UL) /**< Offset from CSI2 Base Address: <tt> 0x0460</tt> */ 253 #define MXC_R_CSI2_XCFGI_DW0D ((uint32_t)0x00000464UL) /**< Offset from CSI2 Base Address: <tt> 0x0464</tt> */ 254 #define MXC_R_CSI2_GPIO_MODE ((uint32_t)0x00000468UL) /**< Offset from CSI2 Base Address: <tt> 0x0468</tt> */ 255 #define MXC_R_CSI2_GPIO_DP_IE ((uint32_t)0x0000046CUL) /**< Offset from CSI2 Base Address: <tt> 0x046C</tt> */ 256 #define MXC_R_CSI2_GPIO_DN_IE ((uint32_t)0x00000470UL) /**< Offset from CSI2 Base Address: <tt> 0x0470</tt> */ 257 #define MXC_R_CSI2_GPIO_DP_C ((uint32_t)0x00000474UL) /**< Offset from CSI2 Base Address: <tt> 0x0474</tt> */ 258 #define MXC_R_CSI2_GPIO_DN_C ((uint32_t)0x00000478UL) /**< Offset from CSI2 Base Address: <tt> 0x0478</tt> */ 259 #define MXC_R_CSI2_VCONTROL ((uint32_t)0x0000047CUL) /**< Offset from CSI2 Base Address: <tt> 0x047C</tt> */ 260 #define MXC_R_CSI2_MPSOV1 ((uint32_t)0x00000480UL) /**< Offset from CSI2 Base Address: <tt> 0x0480</tt> */ 261 #define MXC_R_CSI2_MPSOV2 ((uint32_t)0x00000484UL) /**< Offset from CSI2 Base Address: <tt> 0x0484</tt> */ 262 #define MXC_R_CSI2_MPSOV3 ((uint32_t)0x00000488UL) /**< Offset from CSI2 Base Address: <tt> 0x0488</tt> */ 263 #define MXC_R_CSI2_RG_CDRX_DSIRX_EN ((uint32_t)0x00000490UL) /**< Offset from CSI2 Base Address: <tt> 0x0490</tt> */ 264 #define MXC_R_CSI2_RG_CDRX_L012_SUBLVDS_EN ((uint32_t)0x00000494UL) /**< Offset from CSI2 Base Address: <tt> 0x0494</tt> */ 265 #define MXC_R_CSI2_RG_CDRX_L012_HSRT_CTRL ((uint32_t)0x00000498UL) /**< Offset from CSI2 Base Address: <tt> 0x0498</tt> */ 266 #define MXC_R_CSI2_RG_CDRX_BISTHS_PLL_EN ((uint32_t)0x0000049CUL) /**< Offset from CSI2 Base Address: <tt> 0x049C</tt> */ 267 #define MXC_R_CSI2_RG_CDRX_BISTHS_PLL_PRE_DIV2 ((uint32_t)0x000004A0UL) /**< Offset from CSI2 Base Address: <tt> 0x04A0</tt> */ 268 #define MXC_R_CSI2_RG_CDRX_BISTHS_PLL_FBK_INT ((uint32_t)0x000004A4UL) /**< Offset from CSI2 Base Address: <tt> 0x04A4</tt> */ 269 #define MXC_R_CSI2_DBG1_MUX_SEL ((uint32_t)0x000004A8UL) /**< Offset from CSI2 Base Address: <tt> 0x04A8</tt> */ 270 #define MXC_R_CSI2_DBG2_MUX_SEL ((uint32_t)0x000004ACUL) /**< Offset from CSI2 Base Address: <tt> 0x04AC</tt> */ 271 #define MXC_R_CSI2_DBG1_MUX_DOUT ((uint32_t)0x000004B0UL) /**< Offset from CSI2 Base Address: <tt> 0x04B0</tt> */ 272 #define MXC_R_CSI2_DBG2_MUX_DOUT ((uint32_t)0x000004B4UL) /**< Offset from CSI2 Base Address: <tt> 0x04B4</tt> */ 273 #define MXC_R_CSI2_AON_POWER_READY_N ((uint32_t)0x000004B8UL) /**< Offset from CSI2 Base Address: <tt> 0x04B8</tt> */ 274 #define MXC_R_CSI2_DPHY_RST_N ((uint32_t)0x000004BCUL) /**< Offset from CSI2 Base Address: <tt> 0x04BC</tt> */ 275 #define MXC_R_CSI2_RXBYTECLKHS_INV ((uint32_t)0x000004C0UL) /**< Offset from CSI2 Base Address: <tt> 0x04C0</tt> */ 276 #define MXC_R_CSI2_VFIFO_CFG0 ((uint32_t)0x00000500UL) /**< Offset from CSI2 Base Address: <tt> 0x0500</tt> */ 277 #define MXC_R_CSI2_VFIFO_CFG1 ((uint32_t)0x00000504UL) /**< Offset from CSI2 Base Address: <tt> 0x0504</tt> */ 278 #define MXC_R_CSI2_VFIFO_CTRL ((uint32_t)0x00000508UL) /**< Offset from CSI2 Base Address: <tt> 0x0508</tt> */ 279 #define MXC_R_CSI2_VFIFO_STS ((uint32_t)0x0000050CUL) /**< Offset from CSI2 Base Address: <tt> 0x050C</tt> */ 280 #define MXC_R_CSI2_VFIFO_LINE_NUM ((uint32_t)0x00000510UL) /**< Offset from CSI2 Base Address: <tt> 0x0510</tt> */ 281 #define MXC_R_CSI2_VFIFO_PIXEL_NUM ((uint32_t)0x00000514UL) /**< Offset from CSI2 Base Address: <tt> 0x0514</tt> */ 282 #define MXC_R_CSI2_VFIFO_LINE_CNT ((uint32_t)0x00000518UL) /**< Offset from CSI2 Base Address: <tt> 0x0518</tt> */ 283 #define MXC_R_CSI2_VFIFO_PIXEL_CNT ((uint32_t)0x0000051CUL) /**< Offset from CSI2 Base Address: <tt> 0x051C</tt> */ 284 #define MXC_R_CSI2_VFIFO_FRAME_STS ((uint32_t)0x00000520UL) /**< Offset from CSI2 Base Address: <tt> 0x0520</tt> */ 285 #define MXC_R_CSI2_VFIFO_RAW_CTRL ((uint32_t)0x00000524UL) /**< Offset from CSI2 Base Address: <tt> 0x0524</tt> */ 286 #define MXC_R_CSI2_VFIFO_RAW_BUF0_ADDR ((uint32_t)0x00000528UL) /**< Offset from CSI2 Base Address: <tt> 0x0528</tt> */ 287 #define MXC_R_CSI2_VFIFO_RAW_BUF1_ADDR ((uint32_t)0x0000052CUL) /**< Offset from CSI2 Base Address: <tt> 0x052C</tt> */ 288 #define MXC_R_CSI2_VFIFO_AHBM_CTRL ((uint32_t)0x00000530UL) /**< Offset from CSI2 Base Address: <tt> 0x0530</tt> */ 289 #define MXC_R_CSI2_VFIFO_AHBM_STS ((uint32_t)0x00000534UL) /**< Offset from CSI2 Base Address: <tt> 0x0534</tt> */ 290 #define MXC_R_CSI2_VFIFO_AHBM_START_ADDR ((uint32_t)0x00000538UL) /**< Offset from CSI2 Base Address: <tt> 0x0538</tt> */ 291 #define MXC_R_CSI2_VFIFO_AHBM_ADDR_RANGE ((uint32_t)0x0000053CUL) /**< Offset from CSI2 Base Address: <tt> 0x053C</tt> */ 292 #define MXC_R_CSI2_VFIFO_AHBM_MAX_TRANS ((uint32_t)0x00000540UL) /**< Offset from CSI2 Base Address: <tt> 0x0540</tt> */ 293 #define MXC_R_CSI2_VFIFO_AHBM_TRANS_CNT ((uint32_t)0x00000544UL) /**< Offset from CSI2 Base Address: <tt> 0x0544</tt> */ 294 #define MXC_R_CSI2_RX_EINT_VFF_IE ((uint32_t)0x00000600UL) /**< Offset from CSI2 Base Address: <tt> 0x0600</tt> */ 295 #define MXC_R_CSI2_RX_EINT_VFF_IF ((uint32_t)0x00000604UL) /**< Offset from CSI2 Base Address: <tt> 0x0604</tt> */ 296 #define MXC_R_CSI2_RX_EINT_PPI_IE ((uint32_t)0x00000608UL) /**< Offset from CSI2 Base Address: <tt> 0x0608</tt> */ 297 #define MXC_R_CSI2_RX_EINT_PPI_IF ((uint32_t)0x0000060CUL) /**< Offset from CSI2 Base Address: <tt> 0x060C</tt> */ 298 #define MXC_R_CSI2_RX_EINT_CTRL_IE ((uint32_t)0x00000610UL) /**< Offset from CSI2 Base Address: <tt> 0x0610</tt> */ 299 #define MXC_R_CSI2_RX_EINT_CTRL_IF ((uint32_t)0x00000614UL) /**< Offset from CSI2 Base Address: <tt> 0x0614</tt> */ 300 #define MXC_R_CSI2_PPI_STOPSTATE ((uint32_t)0x00000700UL) /**< Offset from CSI2 Base Address: <tt> 0x0700</tt> */ 301 #define MXC_R_CSI2_PPI_TURNAROUND_CFG ((uint32_t)0x00000704UL) /**< Offset from CSI2 Base Address: <tt> 0x0704</tt> */ 302 /**@} end of group csi2_registers */ 303 304 /** 305 * @ingroup csi2_registers 306 * @defgroup CSI2_CFG_NUM_LANES CSI2_CFG_NUM_LANES 307 * @brief CFG_NUM_LANES. 308 * @{ 309 */ 310 #define MXC_F_CSI2_CFG_NUM_LANES_LANES_POS 0 /**< CFG_NUM_LANES_LANES Position */ 311 #define MXC_F_CSI2_CFG_NUM_LANES_LANES ((uint32_t)(0xFUL << MXC_F_CSI2_CFG_NUM_LANES_LANES_POS)) /**< CFG_NUM_LANES_LANES Mask */ 312 313 /**@} end of group CSI2_CFG_NUM_LANES_Register */ 314 315 /** 316 * @ingroup csi2_registers 317 * @defgroup CSI2_CFG_CLK_LANE_EN CSI2_CFG_CLK_LANE_EN 318 * @brief CFG_CLK_LANE_EN. 319 * @{ 320 */ 321 #define MXC_F_CSI2_CFG_CLK_LANE_EN_EN_POS 0 /**< CFG_CLK_LANE_EN_EN Position */ 322 #define MXC_F_CSI2_CFG_CLK_LANE_EN_EN ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_CLK_LANE_EN_EN_POS)) /**< CFG_CLK_LANE_EN_EN Mask */ 323 324 /**@} end of group CSI2_CFG_CLK_LANE_EN_Register */ 325 326 /** 327 * @ingroup csi2_registers 328 * @defgroup CSI2_CFG_DATA_LANE_EN CSI2_CFG_DATA_LANE_EN 329 * @brief CFG_DATA_LANE_EN. 330 * @{ 331 */ 332 #define MXC_F_CSI2_CFG_DATA_LANE_EN_EN_POS 0 /**< CFG_DATA_LANE_EN_EN Position */ 333 #define MXC_F_CSI2_CFG_DATA_LANE_EN_EN ((uint32_t)(0xFFUL << MXC_F_CSI2_CFG_DATA_LANE_EN_EN_POS)) /**< CFG_DATA_LANE_EN_EN Mask */ 334 335 /**@} end of group CSI2_CFG_DATA_LANE_EN_Register */ 336 337 /** 338 * @ingroup csi2_registers 339 * @defgroup CSI2_CFG_FLUSH_COUNT CSI2_CFG_FLUSH_COUNT 340 * @brief CFG_FLUSH_COUNT. 341 * @{ 342 */ 343 #define MXC_F_CSI2_CFG_FLUSH_COUNT_COUNT_POS 0 /**< CFG_FLUSH_COUNT_COUNT Position */ 344 #define MXC_F_CSI2_CFG_FLUSH_COUNT_COUNT ((uint32_t)(0xFUL << MXC_F_CSI2_CFG_FLUSH_COUNT_COUNT_POS)) /**< CFG_FLUSH_COUNT_COUNT Mask */ 345 346 /**@} end of group CSI2_CFG_FLUSH_COUNT_Register */ 347 348 /** 349 * @ingroup csi2_registers 350 * @defgroup CSI2_CFG_BIT_ERR CSI2_CFG_BIT_ERR 351 * @brief CFG_BIT_ERR. 352 * @{ 353 */ 354 #define MXC_F_CSI2_CFG_BIT_ERR_MBE_POS 0 /**< CFG_BIT_ERR_MBE Position */ 355 #define MXC_F_CSI2_CFG_BIT_ERR_MBE ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_BIT_ERR_MBE_POS)) /**< CFG_BIT_ERR_MBE Mask */ 356 357 #define MXC_F_CSI2_CFG_BIT_ERR_SBE_POS 1 /**< CFG_BIT_ERR_SBE Position */ 358 #define MXC_F_CSI2_CFG_BIT_ERR_SBE ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_BIT_ERR_SBE_POS)) /**< CFG_BIT_ERR_SBE Mask */ 359 360 #define MXC_F_CSI2_CFG_BIT_ERR_HEADER_POS 2 /**< CFG_BIT_ERR_HEADER Position */ 361 #define MXC_F_CSI2_CFG_BIT_ERR_HEADER ((uint32_t)(0x1FUL << MXC_F_CSI2_CFG_BIT_ERR_HEADER_POS)) /**< CFG_BIT_ERR_HEADER Mask */ 362 363 #define MXC_F_CSI2_CFG_BIT_ERR_CRC_POS 7 /**< CFG_BIT_ERR_CRC Position */ 364 #define MXC_F_CSI2_CFG_BIT_ERR_CRC ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_BIT_ERR_CRC_POS)) /**< CFG_BIT_ERR_CRC Mask */ 365 366 #define MXC_F_CSI2_CFG_BIT_ERR_VID_ERR_SEND_LVL_POS 8 /**< CFG_BIT_ERR_VID_ERR_SEND_LVL Position */ 367 #define MXC_F_CSI2_CFG_BIT_ERR_VID_ERR_SEND_LVL ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_BIT_ERR_VID_ERR_SEND_LVL_POS)) /**< CFG_BIT_ERR_VID_ERR_SEND_LVL Mask */ 368 369 #define MXC_F_CSI2_CFG_BIT_ERR_VID_ERR_FIFO_WR_OV_POS 9 /**< CFG_BIT_ERR_VID_ERR_FIFO_WR_OV Position */ 370 #define MXC_F_CSI2_CFG_BIT_ERR_VID_ERR_FIFO_WR_OV ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_BIT_ERR_VID_ERR_FIFO_WR_OV_POS)) /**< CFG_BIT_ERR_VID_ERR_FIFO_WR_OV Mask */ 371 372 /**@} end of group CSI2_CFG_BIT_ERR_Register */ 373 374 /** 375 * @ingroup csi2_registers 376 * @defgroup CSI2_IRQ_STATUS CSI2_IRQ_STATUS 377 * @brief IRQ_STATUS. 378 * @{ 379 */ 380 #define MXC_F_CSI2_IRQ_STATUS_CRC_POS 0 /**< IRQ_STATUS_CRC Position */ 381 #define MXC_F_CSI2_IRQ_STATUS_CRC ((uint32_t)(0x1UL << MXC_F_CSI2_IRQ_STATUS_CRC_POS)) /**< IRQ_STATUS_CRC Mask */ 382 383 #define MXC_F_CSI2_IRQ_STATUS_SBE_POS 1 /**< IRQ_STATUS_SBE Position */ 384 #define MXC_F_CSI2_IRQ_STATUS_SBE ((uint32_t)(0x1UL << MXC_F_CSI2_IRQ_STATUS_SBE_POS)) /**< IRQ_STATUS_SBE Mask */ 385 386 #define MXC_F_CSI2_IRQ_STATUS_MBE_POS 2 /**< IRQ_STATUS_MBE Position */ 387 #define MXC_F_CSI2_IRQ_STATUS_MBE ((uint32_t)(0x1UL << MXC_F_CSI2_IRQ_STATUS_MBE_POS)) /**< IRQ_STATUS_MBE Mask */ 388 389 #define MXC_F_CSI2_IRQ_STATUS_ULPS_ACTIVE_POS 3 /**< IRQ_STATUS_ULPS_ACTIVE Position */ 390 #define MXC_F_CSI2_IRQ_STATUS_ULPS_ACTIVE ((uint32_t)(0x1UL << MXC_F_CSI2_IRQ_STATUS_ULPS_ACTIVE_POS)) /**< IRQ_STATUS_ULPS_ACTIVE Mask */ 391 392 #define MXC_F_CSI2_IRQ_STATUS_ULPS_MARK_ACTIVE_POS 4 /**< IRQ_STATUS_ULPS_MARK_ACTIVE Position */ 393 #define MXC_F_CSI2_IRQ_STATUS_ULPS_MARK_ACTIVE ((uint32_t)(0x1UL << MXC_F_CSI2_IRQ_STATUS_ULPS_MARK_ACTIVE_POS)) /**< IRQ_STATUS_ULPS_MARK_ACTIVE Mask */ 394 395 #define MXC_F_CSI2_IRQ_STATUS_VID_ERR_SEND_LVL_POS 5 /**< IRQ_STATUS_VID_ERR_SEND_LVL Position */ 396 #define MXC_F_CSI2_IRQ_STATUS_VID_ERR_SEND_LVL ((uint32_t)(0x1UL << MXC_F_CSI2_IRQ_STATUS_VID_ERR_SEND_LVL_POS)) /**< IRQ_STATUS_VID_ERR_SEND_LVL Mask */ 397 398 #define MXC_F_CSI2_IRQ_STATUS_VID_ERR_FIFO_WR_OV_POS 6 /**< IRQ_STATUS_VID_ERR_FIFO_WR_OV Position */ 399 #define MXC_F_CSI2_IRQ_STATUS_VID_ERR_FIFO_WR_OV ((uint32_t)(0x1UL << MXC_F_CSI2_IRQ_STATUS_VID_ERR_FIFO_WR_OV_POS)) /**< IRQ_STATUS_VID_ERR_FIFO_WR_OV Mask */ 400 401 /**@} end of group CSI2_IRQ_STATUS_Register */ 402 403 /** 404 * @ingroup csi2_registers 405 * @defgroup CSI2_IRQ_ENABLE CSI2_IRQ_ENABLE 406 * @brief IRQ_ENABLE. 407 * @{ 408 */ 409 #define MXC_F_CSI2_IRQ_ENABLE_CRC_POS 0 /**< IRQ_ENABLE_CRC Position */ 410 #define MXC_F_CSI2_IRQ_ENABLE_CRC ((uint32_t)(0x1UL << MXC_F_CSI2_IRQ_ENABLE_CRC_POS)) /**< IRQ_ENABLE_CRC Mask */ 411 412 #define MXC_F_CSI2_IRQ_ENABLE_SBE_POS 1 /**< IRQ_ENABLE_SBE Position */ 413 #define MXC_F_CSI2_IRQ_ENABLE_SBE ((uint32_t)(0x1UL << MXC_F_CSI2_IRQ_ENABLE_SBE_POS)) /**< IRQ_ENABLE_SBE Mask */ 414 415 #define MXC_F_CSI2_IRQ_ENABLE_MBE_POS 2 /**< IRQ_ENABLE_MBE Position */ 416 #define MXC_F_CSI2_IRQ_ENABLE_MBE ((uint32_t)(0x1UL << MXC_F_CSI2_IRQ_ENABLE_MBE_POS)) /**< IRQ_ENABLE_MBE Mask */ 417 418 #define MXC_F_CSI2_IRQ_ENABLE_ULPS_ACTIVE_POS 3 /**< IRQ_ENABLE_ULPS_ACTIVE Position */ 419 #define MXC_F_CSI2_IRQ_ENABLE_ULPS_ACTIVE ((uint32_t)(0x1UL << MXC_F_CSI2_IRQ_ENABLE_ULPS_ACTIVE_POS)) /**< IRQ_ENABLE_ULPS_ACTIVE Mask */ 420 421 #define MXC_F_CSI2_IRQ_ENABLE_ULPS_MARK_ACTIVE_POS 4 /**< IRQ_ENABLE_ULPS_MARK_ACTIVE Position */ 422 #define MXC_F_CSI2_IRQ_ENABLE_ULPS_MARK_ACTIVE ((uint32_t)(0x1UL << MXC_F_CSI2_IRQ_ENABLE_ULPS_MARK_ACTIVE_POS)) /**< IRQ_ENABLE_ULPS_MARK_ACTIVE Mask */ 423 424 #define MXC_F_CSI2_IRQ_ENABLE_VID_ERR_SEND_LVL_POS 5 /**< IRQ_ENABLE_VID_ERR_SEND_LVL Position */ 425 #define MXC_F_CSI2_IRQ_ENABLE_VID_ERR_SEND_LVL ((uint32_t)(0x1UL << MXC_F_CSI2_IRQ_ENABLE_VID_ERR_SEND_LVL_POS)) /**< IRQ_ENABLE_VID_ERR_SEND_LVL Mask */ 426 427 #define MXC_F_CSI2_IRQ_ENABLE_VID_ERR_FIFO_WR_OV_POS 6 /**< IRQ_ENABLE_VID_ERR_FIFO_WR_OV Position */ 428 #define MXC_F_CSI2_IRQ_ENABLE_VID_ERR_FIFO_WR_OV ((uint32_t)(0x1UL << MXC_F_CSI2_IRQ_ENABLE_VID_ERR_FIFO_WR_OV_POS)) /**< IRQ_ENABLE_VID_ERR_FIFO_WR_OV Mask */ 429 430 /**@} end of group CSI2_IRQ_ENABLE_Register */ 431 432 /** 433 * @ingroup csi2_registers 434 * @defgroup CSI2_IRQ_CLR CSI2_IRQ_CLR 435 * @brief IRQ_CLR. 436 * @{ 437 */ 438 #define MXC_F_CSI2_IRQ_CLR_CRC_POS 0 /**< IRQ_CLR_CRC Position */ 439 #define MXC_F_CSI2_IRQ_CLR_CRC ((uint32_t)(0x1UL << MXC_F_CSI2_IRQ_CLR_CRC_POS)) /**< IRQ_CLR_CRC Mask */ 440 441 #define MXC_F_CSI2_IRQ_CLR_SBE_POS 1 /**< IRQ_CLR_SBE Position */ 442 #define MXC_F_CSI2_IRQ_CLR_SBE ((uint32_t)(0x1UL << MXC_F_CSI2_IRQ_CLR_SBE_POS)) /**< IRQ_CLR_SBE Mask */ 443 444 #define MXC_F_CSI2_IRQ_CLR_MBE_POS 2 /**< IRQ_CLR_MBE Position */ 445 #define MXC_F_CSI2_IRQ_CLR_MBE ((uint32_t)(0x1UL << MXC_F_CSI2_IRQ_CLR_MBE_POS)) /**< IRQ_CLR_MBE Mask */ 446 447 #define MXC_F_CSI2_IRQ_CLR_ULPS_ACTIVE_POS 3 /**< IRQ_CLR_ULPS_ACTIVE Position */ 448 #define MXC_F_CSI2_IRQ_CLR_ULPS_ACTIVE ((uint32_t)(0x1UL << MXC_F_CSI2_IRQ_CLR_ULPS_ACTIVE_POS)) /**< IRQ_CLR_ULPS_ACTIVE Mask */ 449 450 #define MXC_F_CSI2_IRQ_CLR_ULPS_MARK_ACTIVE_POS 4 /**< IRQ_CLR_ULPS_MARK_ACTIVE Position */ 451 #define MXC_F_CSI2_IRQ_CLR_ULPS_MARK_ACTIVE ((uint32_t)(0x1UL << MXC_F_CSI2_IRQ_CLR_ULPS_MARK_ACTIVE_POS)) /**< IRQ_CLR_ULPS_MARK_ACTIVE Mask */ 452 453 #define MXC_F_CSI2_IRQ_CLR_VID_ERR_SEND_LVL_POS 5 /**< IRQ_CLR_VID_ERR_SEND_LVL Position */ 454 #define MXC_F_CSI2_IRQ_CLR_VID_ERR_SEND_LVL ((uint32_t)(0x1UL << MXC_F_CSI2_IRQ_CLR_VID_ERR_SEND_LVL_POS)) /**< IRQ_CLR_VID_ERR_SEND_LVL Mask */ 455 456 #define MXC_F_CSI2_IRQ_CLR_VID_ERR_FIFO_WR_OV_POS 6 /**< IRQ_CLR_VID_ERR_FIFO_WR_OV Position */ 457 #define MXC_F_CSI2_IRQ_CLR_VID_ERR_FIFO_WR_OV ((uint32_t)(0x1UL << MXC_F_CSI2_IRQ_CLR_VID_ERR_FIFO_WR_OV_POS)) /**< IRQ_CLR_VID_ERR_FIFO_WR_OV Mask */ 458 459 /**@} end of group CSI2_IRQ_CLR_Register */ 460 461 /** 462 * @ingroup csi2_registers 463 * @defgroup CSI2_ULPS_CLK_STATUS CSI2_ULPS_CLK_STATUS 464 * @brief ULPS_CLK_STATUS. 465 * @{ 466 */ 467 #define MXC_F_CSI2_ULPS_CLK_STATUS_FIFO_POS 0 /**< ULPS_CLK_STATUS_FIFO Position */ 468 #define MXC_F_CSI2_ULPS_CLK_STATUS_FIFO ((uint32_t)(0x1UL << MXC_F_CSI2_ULPS_CLK_STATUS_FIFO_POS)) /**< ULPS_CLK_STATUS_FIFO Mask */ 469 470 /**@} end of group CSI2_ULPS_CLK_STATUS_Register */ 471 472 /** 473 * @ingroup csi2_registers 474 * @defgroup CSI2_ULPS_STATUS CSI2_ULPS_STATUS 475 * @brief ULPS_STATUS. 476 * @{ 477 */ 478 #define MXC_F_CSI2_ULPS_STATUS_DATA_LANE0_POS 0 /**< ULPS_STATUS_DATA_LANE0 Position */ 479 #define MXC_F_CSI2_ULPS_STATUS_DATA_LANE0 ((uint32_t)(0x1UL << MXC_F_CSI2_ULPS_STATUS_DATA_LANE0_POS)) /**< ULPS_STATUS_DATA_LANE0 Mask */ 480 481 #define MXC_F_CSI2_ULPS_STATUS_DATA_LANE1_POS 1 /**< ULPS_STATUS_DATA_LANE1 Position */ 482 #define MXC_F_CSI2_ULPS_STATUS_DATA_LANE1 ((uint32_t)(0x1UL << MXC_F_CSI2_ULPS_STATUS_DATA_LANE1_POS)) /**< ULPS_STATUS_DATA_LANE1 Mask */ 483 484 /**@} end of group CSI2_ULPS_STATUS_Register */ 485 486 /** 487 * @ingroup csi2_registers 488 * @defgroup CSI2_ULPS_CLK_MARK_STATUS CSI2_ULPS_CLK_MARK_STATUS 489 * @brief ULPS_CLK_MARK_STATUS. 490 * @{ 491 */ 492 #define MXC_F_CSI2_ULPS_CLK_MARK_STATUS_CLK_LANE_POS 0 /**< ULPS_CLK_MARK_STATUS_CLK_LANE Position */ 493 #define MXC_F_CSI2_ULPS_CLK_MARK_STATUS_CLK_LANE ((uint32_t)(0x1UL << MXC_F_CSI2_ULPS_CLK_MARK_STATUS_CLK_LANE_POS)) /**< ULPS_CLK_MARK_STATUS_CLK_LANE Mask */ 494 495 /**@} end of group CSI2_ULPS_CLK_MARK_STATUS_Register */ 496 497 /** 498 * @ingroup csi2_registers 499 * @defgroup CSI2_ULPS_MARK_STATUS CSI2_ULPS_MARK_STATUS 500 * @brief ULPS_MARK_STATUS. 501 * @{ 502 */ 503 #define MXC_F_CSI2_ULPS_MARK_STATUS_DATA_LANE0_POS 0 /**< ULPS_MARK_STATUS_DATA_LANE0 Position */ 504 #define MXC_F_CSI2_ULPS_MARK_STATUS_DATA_LANE0 ((uint32_t)(0x1UL << MXC_F_CSI2_ULPS_MARK_STATUS_DATA_LANE0_POS)) /**< ULPS_MARK_STATUS_DATA_LANE0 Mask */ 505 506 #define MXC_F_CSI2_ULPS_MARK_STATUS_DATA_LANE1_POS 1 /**< ULPS_MARK_STATUS_DATA_LANE1 Position */ 507 #define MXC_F_CSI2_ULPS_MARK_STATUS_DATA_LANE1 ((uint32_t)(0x1UL << MXC_F_CSI2_ULPS_MARK_STATUS_DATA_LANE1_POS)) /**< ULPS_MARK_STATUS_DATA_LANE1 Mask */ 508 509 /**@} end of group CSI2_ULPS_MARK_STATUS_Register */ 510 511 /** 512 * @ingroup csi2_registers 513 * @defgroup CSI2_CFG_DISABLE_PAYLOAD_0 CSI2_CFG_DISABLE_PAYLOAD_0 514 * @brief CFG_DISABLE_PAYLOAD_0. 515 * @{ 516 */ 517 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_NULL_POS 0 /**< CFG_DISABLE_PAYLOAD_0_NULL Position */ 518 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_NULL ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_NULL_POS)) /**< CFG_DISABLE_PAYLOAD_0_NULL Mask */ 519 520 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_BLANK_POS 1 /**< CFG_DISABLE_PAYLOAD_0_BLANK Position */ 521 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_BLANK ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_BLANK_POS)) /**< CFG_DISABLE_PAYLOAD_0_BLANK Mask */ 522 523 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_EMBEDDED_POS 2 /**< CFG_DISABLE_PAYLOAD_0_EMBEDDED Position */ 524 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_EMBEDDED ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_EMBEDDED_POS)) /**< CFG_DISABLE_PAYLOAD_0_EMBEDDED Mask */ 525 526 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_YUV420_8BIT_POS 8 /**< CFG_DISABLE_PAYLOAD_0_YUV420_8BIT Position */ 527 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_YUV420_8BIT ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_YUV420_8BIT_POS)) /**< CFG_DISABLE_PAYLOAD_0_YUV420_8BIT Mask */ 528 529 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_YUV420_10BIT_POS 9 /**< CFG_DISABLE_PAYLOAD_0_YUV420_10BIT Position */ 530 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_YUV420_10BIT ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_YUV420_10BIT_POS)) /**< CFG_DISABLE_PAYLOAD_0_YUV420_10BIT Mask */ 531 532 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_YUV420_8BIT_LEG_POS 10 /**< CFG_DISABLE_PAYLOAD_0_YUV420_8BIT_LEG Position */ 533 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_YUV420_8BIT_LEG ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_YUV420_8BIT_LEG_POS)) /**< CFG_DISABLE_PAYLOAD_0_YUV420_8BIT_LEG Mask */ 534 535 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_YUV420_8BIT_CSP_POS 12 /**< CFG_DISABLE_PAYLOAD_0_YUV420_8BIT_CSP Position */ 536 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_YUV420_8BIT_CSP ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_YUV420_8BIT_CSP_POS)) /**< CFG_DISABLE_PAYLOAD_0_YUV420_8BIT_CSP Mask */ 537 538 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_YUV420_10BIT_CSP_POS 13 /**< CFG_DISABLE_PAYLOAD_0_YUV420_10BIT_CSP Position */ 539 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_YUV420_10BIT_CSP ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_YUV420_10BIT_CSP_POS)) /**< CFG_DISABLE_PAYLOAD_0_YUV420_10BIT_CSP Mask */ 540 541 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_YUV422_8BIT_POS 14 /**< CFG_DISABLE_PAYLOAD_0_YUV422_8BIT Position */ 542 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_YUV422_8BIT ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_YUV422_8BIT_POS)) /**< CFG_DISABLE_PAYLOAD_0_YUV422_8BIT Mask */ 543 544 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_YUV422_10BIT_POS 15 /**< CFG_DISABLE_PAYLOAD_0_YUV422_10BIT Position */ 545 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_YUV422_10BIT ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_YUV422_10BIT_POS)) /**< CFG_DISABLE_PAYLOAD_0_YUV422_10BIT Mask */ 546 547 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RGB444_POS 16 /**< CFG_DISABLE_PAYLOAD_0_RGB444 Position */ 548 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RGB444 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RGB444_POS)) /**< CFG_DISABLE_PAYLOAD_0_RGB444 Mask */ 549 550 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RGB555_POS 17 /**< CFG_DISABLE_PAYLOAD_0_RGB555 Position */ 551 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RGB555 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RGB555_POS)) /**< CFG_DISABLE_PAYLOAD_0_RGB555 Mask */ 552 553 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RGB565_POS 18 /**< CFG_DISABLE_PAYLOAD_0_RGB565 Position */ 554 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RGB565 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RGB565_POS)) /**< CFG_DISABLE_PAYLOAD_0_RGB565 Mask */ 555 556 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RGB666_POS 19 /**< CFG_DISABLE_PAYLOAD_0_RGB666 Position */ 557 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RGB666 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RGB666_POS)) /**< CFG_DISABLE_PAYLOAD_0_RGB666 Mask */ 558 559 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RGB888_POS 20 /**< CFG_DISABLE_PAYLOAD_0_RGB888 Position */ 560 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RGB888 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RGB888_POS)) /**< CFG_DISABLE_PAYLOAD_0_RGB888 Mask */ 561 562 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW6_POS 24 /**< CFG_DISABLE_PAYLOAD_0_RAW6 Position */ 563 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW6 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW6_POS)) /**< CFG_DISABLE_PAYLOAD_0_RAW6 Mask */ 564 565 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW7_POS 25 /**< CFG_DISABLE_PAYLOAD_0_RAW7 Position */ 566 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW7 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW7_POS)) /**< CFG_DISABLE_PAYLOAD_0_RAW7 Mask */ 567 568 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW8_POS 26 /**< CFG_DISABLE_PAYLOAD_0_RAW8 Position */ 569 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW8 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW8_POS)) /**< CFG_DISABLE_PAYLOAD_0_RAW8 Mask */ 570 571 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW10_POS 27 /**< CFG_DISABLE_PAYLOAD_0_RAW10 Position */ 572 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW10 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW10_POS)) /**< CFG_DISABLE_PAYLOAD_0_RAW10 Mask */ 573 574 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW12_POS 28 /**< CFG_DISABLE_PAYLOAD_0_RAW12 Position */ 575 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW12 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW12_POS)) /**< CFG_DISABLE_PAYLOAD_0_RAW12 Mask */ 576 577 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW14_POS 29 /**< CFG_DISABLE_PAYLOAD_0_RAW14 Position */ 578 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW14 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW14_POS)) /**< CFG_DISABLE_PAYLOAD_0_RAW14 Mask */ 579 580 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW16_POS 30 /**< CFG_DISABLE_PAYLOAD_0_RAW16 Position */ 581 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW16 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW16_POS)) /**< CFG_DISABLE_PAYLOAD_0_RAW16 Mask */ 582 583 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW20_POS 31 /**< CFG_DISABLE_PAYLOAD_0_RAW20 Position */ 584 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW20 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_0_RAW20_POS)) /**< CFG_DISABLE_PAYLOAD_0_RAW20 Mask */ 585 586 /**@} end of group CSI2_CFG_DISABLE_PAYLOAD_0_Register */ 587 588 /** 589 * @ingroup csi2_registers 590 * @defgroup CSI2_CFG_DISABLE_PAYLOAD_1 CSI2_CFG_DISABLE_PAYLOAD_1 591 * @brief CFG_DISABLE_PAYLOAD_1. 592 * @{ 593 */ 594 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE30_POS 0 /**< CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE30 Position */ 595 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE30 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE30_POS)) /**< CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE30 Mask */ 596 597 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE31_POS 1 /**< CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE31 Position */ 598 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE31 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE31_POS)) /**< CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE31 Mask */ 599 600 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE32_POS 2 /**< CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE32 Position */ 601 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE32 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE32_POS)) /**< CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE32 Mask */ 602 603 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE33_POS 3 /**< CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE33 Position */ 604 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE33 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE33_POS)) /**< CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE33 Mask */ 605 606 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE34_POS 4 /**< CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE34 Position */ 607 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE34 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE34_POS)) /**< CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE34 Mask */ 608 609 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE35_POS 5 /**< CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE35 Position */ 610 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE35 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE35_POS)) /**< CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE35 Mask */ 611 612 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE36_POS 6 /**< CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE36 Position */ 613 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE36 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE36_POS)) /**< CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE36 Mask */ 614 615 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE37_POS 7 /**< CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE37 Position */ 616 #define MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE37 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE37_POS)) /**< CFG_DISABLE_PAYLOAD_1_USR_DEF_TYPE37 Mask */ 617 618 /**@} end of group CSI2_CFG_DISABLE_PAYLOAD_1_Register */ 619 620 /** 621 * @ingroup csi2_registers 622 * @defgroup CSI2_CFG_DATABUS16_SEL CSI2_CFG_DATABUS16_SEL 623 * @brief CFG_DATABUS16_SEL. 624 * @{ 625 */ 626 #define MXC_F_CSI2_CFG_DATABUS16_SEL_EN_POS 0 /**< CFG_DATABUS16_SEL_EN Position */ 627 #define MXC_F_CSI2_CFG_DATABUS16_SEL_EN ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DATABUS16_SEL_EN_POS)) /**< CFG_DATABUS16_SEL_EN Mask */ 628 629 /**@} end of group CSI2_CFG_DATABUS16_SEL_Register */ 630 631 /** 632 * @ingroup csi2_registers 633 * @defgroup CSI2_CFG_D0_SWAP_SEL CSI2_CFG_D0_SWAP_SEL 634 * @brief CFG_D0_SWAP_SEL. 635 * @{ 636 */ 637 #define MXC_F_CSI2_CFG_D0_SWAP_SEL_SRC_POS 0 /**< CFG_D0_SWAP_SEL_SRC Position */ 638 #define MXC_F_CSI2_CFG_D0_SWAP_SEL_SRC ((uint32_t)(0x7UL << MXC_F_CSI2_CFG_D0_SWAP_SEL_SRC_POS)) /**< CFG_D0_SWAP_SEL_SRC Mask */ 639 #define MXC_V_CSI2_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L0 ((uint32_t)0x0UL) /**< CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L0 Value */ 640 #define MXC_S_CSI2_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L0 (MXC_V_CSI2_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L0 << MXC_F_CSI2_CFG_D0_SWAP_SEL_SRC_POS) /**< CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L0 Setting */ 641 #define MXC_V_CSI2_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L1 ((uint32_t)0x1UL) /**< CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L1 Value */ 642 #define MXC_S_CSI2_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L1 (MXC_V_CSI2_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L1 << MXC_F_CSI2_CFG_D0_SWAP_SEL_SRC_POS) /**< CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L1 Setting */ 643 #define MXC_V_CSI2_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L2 ((uint32_t)0x2UL) /**< CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L2 Value */ 644 #define MXC_S_CSI2_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L2 (MXC_V_CSI2_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L2 << MXC_F_CSI2_CFG_D0_SWAP_SEL_SRC_POS) /**< CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L2 Setting */ 645 #define MXC_V_CSI2_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L3 ((uint32_t)0x3UL) /**< CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L3 Value */ 646 #define MXC_S_CSI2_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L3 (MXC_V_CSI2_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L3 << MXC_F_CSI2_CFG_D0_SWAP_SEL_SRC_POS) /**< CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L3 Setting */ 647 #define MXC_V_CSI2_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L4 ((uint32_t)0x4UL) /**< CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L4 Value */ 648 #define MXC_S_CSI2_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L4 (MXC_V_CSI2_CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L4 << MXC_F_CSI2_CFG_D0_SWAP_SEL_SRC_POS) /**< CFG_D0_SWAP_SEL_SRC_PAD_CDRX_L4 Setting */ 649 650 /**@} end of group CSI2_CFG_D0_SWAP_SEL_Register */ 651 652 /** 653 * @ingroup csi2_registers 654 * @defgroup CSI2_CFG_D1_SWAP_SEL CSI2_CFG_D1_SWAP_SEL 655 * @brief CFG_D1_SWAP_SEL. 656 * @{ 657 */ 658 #define MXC_F_CSI2_CFG_D1_SWAP_SEL_SRC_POS 0 /**< CFG_D1_SWAP_SEL_SRC Position */ 659 #define MXC_F_CSI2_CFG_D1_SWAP_SEL_SRC ((uint32_t)(0x7UL << MXC_F_CSI2_CFG_D1_SWAP_SEL_SRC_POS)) /**< CFG_D1_SWAP_SEL_SRC Mask */ 660 #define MXC_V_CSI2_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L0 ((uint32_t)0x0UL) /**< CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L0 Value */ 661 #define MXC_S_CSI2_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L0 (MXC_V_CSI2_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L0 << MXC_F_CSI2_CFG_D1_SWAP_SEL_SRC_POS) /**< CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L0 Setting */ 662 #define MXC_V_CSI2_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L1 ((uint32_t)0x1UL) /**< CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L1 Value */ 663 #define MXC_S_CSI2_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L1 (MXC_V_CSI2_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L1 << MXC_F_CSI2_CFG_D1_SWAP_SEL_SRC_POS) /**< CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L1 Setting */ 664 #define MXC_V_CSI2_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L2 ((uint32_t)0x2UL) /**< CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L2 Value */ 665 #define MXC_S_CSI2_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L2 (MXC_V_CSI2_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L2 << MXC_F_CSI2_CFG_D1_SWAP_SEL_SRC_POS) /**< CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L2 Setting */ 666 #define MXC_V_CSI2_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L3 ((uint32_t)0x3UL) /**< CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L3 Value */ 667 #define MXC_S_CSI2_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L3 (MXC_V_CSI2_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L3 << MXC_F_CSI2_CFG_D1_SWAP_SEL_SRC_POS) /**< CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L3 Setting */ 668 #define MXC_V_CSI2_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L4 ((uint32_t)0x4UL) /**< CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L4 Value */ 669 #define MXC_S_CSI2_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L4 (MXC_V_CSI2_CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L4 << MXC_F_CSI2_CFG_D1_SWAP_SEL_SRC_POS) /**< CFG_D1_SWAP_SEL_SRC_PAD_CDRX_L4 Setting */ 670 671 /**@} end of group CSI2_CFG_D1_SWAP_SEL_Register */ 672 673 /** 674 * @ingroup csi2_registers 675 * @defgroup CSI2_CFG_D2_SWAP_SEL CSI2_CFG_D2_SWAP_SEL 676 * @brief CFG_D2_SWAP_SEL. 677 * @{ 678 */ 679 #define MXC_F_CSI2_CFG_D2_SWAP_SEL_SRC_POS 0 /**< CFG_D2_SWAP_SEL_SRC Position */ 680 #define MXC_F_CSI2_CFG_D2_SWAP_SEL_SRC ((uint32_t)(0x7UL << MXC_F_CSI2_CFG_D2_SWAP_SEL_SRC_POS)) /**< CFG_D2_SWAP_SEL_SRC Mask */ 681 #define MXC_V_CSI2_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L0 ((uint32_t)0x0UL) /**< CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L0 Value */ 682 #define MXC_S_CSI2_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L0 (MXC_V_CSI2_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L0 << MXC_F_CSI2_CFG_D2_SWAP_SEL_SRC_POS) /**< CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L0 Setting */ 683 #define MXC_V_CSI2_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L1 ((uint32_t)0x1UL) /**< CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L1 Value */ 684 #define MXC_S_CSI2_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L1 (MXC_V_CSI2_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L1 << MXC_F_CSI2_CFG_D2_SWAP_SEL_SRC_POS) /**< CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L1 Setting */ 685 #define MXC_V_CSI2_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L2 ((uint32_t)0x2UL) /**< CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L2 Value */ 686 #define MXC_S_CSI2_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L2 (MXC_V_CSI2_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L2 << MXC_F_CSI2_CFG_D2_SWAP_SEL_SRC_POS) /**< CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L2 Setting */ 687 #define MXC_V_CSI2_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L3 ((uint32_t)0x3UL) /**< CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L3 Value */ 688 #define MXC_S_CSI2_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L3 (MXC_V_CSI2_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L3 << MXC_F_CSI2_CFG_D2_SWAP_SEL_SRC_POS) /**< CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L3 Setting */ 689 #define MXC_V_CSI2_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L4 ((uint32_t)0x4UL) /**< CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L4 Value */ 690 #define MXC_S_CSI2_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L4 (MXC_V_CSI2_CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L4 << MXC_F_CSI2_CFG_D2_SWAP_SEL_SRC_POS) /**< CFG_D2_SWAP_SEL_SRC_PAD_CDRX_L4 Setting */ 691 692 /**@} end of group CSI2_CFG_D2_SWAP_SEL_Register */ 693 694 /** 695 * @ingroup csi2_registers 696 * @defgroup CSI2_CFG_D3_SWAP_SEL CSI2_CFG_D3_SWAP_SEL 697 * @brief CFG_D3_SWAP_SEL. 698 * @{ 699 */ 700 #define MXC_F_CSI2_CFG_D3_SWAP_SEL_SRC_POS 0 /**< CFG_D3_SWAP_SEL_SRC Position */ 701 #define MXC_F_CSI2_CFG_D3_SWAP_SEL_SRC ((uint32_t)(0x7UL << MXC_F_CSI2_CFG_D3_SWAP_SEL_SRC_POS)) /**< CFG_D3_SWAP_SEL_SRC Mask */ 702 #define MXC_V_CSI2_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L0 ((uint32_t)0x0UL) /**< CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L0 Value */ 703 #define MXC_S_CSI2_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L0 (MXC_V_CSI2_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L0 << MXC_F_CSI2_CFG_D3_SWAP_SEL_SRC_POS) /**< CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L0 Setting */ 704 #define MXC_V_CSI2_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L1 ((uint32_t)0x1UL) /**< CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L1 Value */ 705 #define MXC_S_CSI2_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L1 (MXC_V_CSI2_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L1 << MXC_F_CSI2_CFG_D3_SWAP_SEL_SRC_POS) /**< CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L1 Setting */ 706 #define MXC_V_CSI2_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L2 ((uint32_t)0x2UL) /**< CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L2 Value */ 707 #define MXC_S_CSI2_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L2 (MXC_V_CSI2_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L2 << MXC_F_CSI2_CFG_D3_SWAP_SEL_SRC_POS) /**< CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L2 Setting */ 708 #define MXC_V_CSI2_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L3 ((uint32_t)0x3UL) /**< CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L3 Value */ 709 #define MXC_S_CSI2_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L3 (MXC_V_CSI2_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L3 << MXC_F_CSI2_CFG_D3_SWAP_SEL_SRC_POS) /**< CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L3 Setting */ 710 #define MXC_V_CSI2_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L4 ((uint32_t)0x4UL) /**< CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L4 Value */ 711 #define MXC_S_CSI2_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L4 (MXC_V_CSI2_CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L4 << MXC_F_CSI2_CFG_D3_SWAP_SEL_SRC_POS) /**< CFG_D3_SWAP_SEL_SRC_PAD_CDRX_L4 Setting */ 712 713 /**@} end of group CSI2_CFG_D3_SWAP_SEL_Register */ 714 715 /** 716 * @ingroup csi2_registers 717 * @defgroup CSI2_CFG_C0_SWAP_SEL CSI2_CFG_C0_SWAP_SEL 718 * @brief CFG_C0_SWAP_SEL. 719 * @{ 720 */ 721 #define MXC_F_CSI2_CFG_C0_SWAP_SEL_SRC_POS 0 /**< CFG_C0_SWAP_SEL_SRC Position */ 722 #define MXC_F_CSI2_CFG_C0_SWAP_SEL_SRC ((uint32_t)(0x7UL << MXC_F_CSI2_CFG_C0_SWAP_SEL_SRC_POS)) /**< CFG_C0_SWAP_SEL_SRC Mask */ 723 #define MXC_V_CSI2_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L0 ((uint32_t)0x0UL) /**< CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L0 Value */ 724 #define MXC_S_CSI2_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L0 (MXC_V_CSI2_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L0 << MXC_F_CSI2_CFG_C0_SWAP_SEL_SRC_POS) /**< CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L0 Setting */ 725 #define MXC_V_CSI2_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L1 ((uint32_t)0x1UL) /**< CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L1 Value */ 726 #define MXC_S_CSI2_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L1 (MXC_V_CSI2_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L1 << MXC_F_CSI2_CFG_C0_SWAP_SEL_SRC_POS) /**< CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L1 Setting */ 727 #define MXC_V_CSI2_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L2 ((uint32_t)0x2UL) /**< CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L2 Value */ 728 #define MXC_S_CSI2_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L2 (MXC_V_CSI2_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L2 << MXC_F_CSI2_CFG_C0_SWAP_SEL_SRC_POS) /**< CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L2 Setting */ 729 #define MXC_V_CSI2_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L3 ((uint32_t)0x3UL) /**< CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L3 Value */ 730 #define MXC_S_CSI2_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L3 (MXC_V_CSI2_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L3 << MXC_F_CSI2_CFG_C0_SWAP_SEL_SRC_POS) /**< CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L3 Setting */ 731 #define MXC_V_CSI2_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L4 ((uint32_t)0x4UL) /**< CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L4 Value */ 732 #define MXC_S_CSI2_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L4 (MXC_V_CSI2_CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L4 << MXC_F_CSI2_CFG_C0_SWAP_SEL_SRC_POS) /**< CFG_C0_SWAP_SEL_SRC_PAD_CDRX_L4 Setting */ 733 734 /**@} end of group CSI2_CFG_C0_SWAP_SEL_Register */ 735 736 /** 737 * @ingroup csi2_registers 738 * @defgroup CSI2_CFG_DPDN_SWAP CSI2_CFG_DPDN_SWAP 739 * @brief CFG_DPDN_SWAP. 740 * @{ 741 */ 742 #define MXC_F_CSI2_CFG_DPDN_SWAP_SWAP_DATA_LANE0_POS 0 /**< CFG_DPDN_SWAP_SWAP_DATA_LANE0 Position */ 743 #define MXC_F_CSI2_CFG_DPDN_SWAP_SWAP_DATA_LANE0 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DPDN_SWAP_SWAP_DATA_LANE0_POS)) /**< CFG_DPDN_SWAP_SWAP_DATA_LANE0 Mask */ 744 745 #define MXC_F_CSI2_CFG_DPDN_SWAP_SWAP_DATA_LANE1_POS 1 /**< CFG_DPDN_SWAP_SWAP_DATA_LANE1 Position */ 746 #define MXC_F_CSI2_CFG_DPDN_SWAP_SWAP_DATA_LANE1 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DPDN_SWAP_SWAP_DATA_LANE1_POS)) /**< CFG_DPDN_SWAP_SWAP_DATA_LANE1 Mask */ 747 748 #define MXC_F_CSI2_CFG_DPDN_SWAP_SWAP_DATA_LANE2_POS 2 /**< CFG_DPDN_SWAP_SWAP_DATA_LANE2 Position */ 749 #define MXC_F_CSI2_CFG_DPDN_SWAP_SWAP_DATA_LANE2 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DPDN_SWAP_SWAP_DATA_LANE2_POS)) /**< CFG_DPDN_SWAP_SWAP_DATA_LANE2 Mask */ 750 751 #define MXC_F_CSI2_CFG_DPDN_SWAP_SWAP_DATA_LANE3_POS 3 /**< CFG_DPDN_SWAP_SWAP_DATA_LANE3 Position */ 752 #define MXC_F_CSI2_CFG_DPDN_SWAP_SWAP_DATA_LANE3 ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DPDN_SWAP_SWAP_DATA_LANE3_POS)) /**< CFG_DPDN_SWAP_SWAP_DATA_LANE3 Mask */ 753 754 #define MXC_F_CSI2_CFG_DPDN_SWAP_SWAP_CLK_LANE_POS 4 /**< CFG_DPDN_SWAP_SWAP_CLK_LANE Position */ 755 #define MXC_F_CSI2_CFG_DPDN_SWAP_SWAP_CLK_LANE ((uint32_t)(0x1UL << MXC_F_CSI2_CFG_DPDN_SWAP_SWAP_CLK_LANE_POS)) /**< CFG_DPDN_SWAP_SWAP_CLK_LANE Mask */ 756 757 /**@} end of group CSI2_CFG_DPDN_SWAP_Register */ 758 759 /** 760 * @ingroup csi2_registers 761 * @defgroup CSI2_RESET_DESKEW CSI2_RESET_DESKEW 762 * @brief RESET_DESKEW. 763 * @{ 764 */ 765 #define MXC_F_CSI2_RESET_DESKEW_DATA_LANE0_POS 0 /**< RESET_DESKEW_DATA_LANE0 Position */ 766 #define MXC_F_CSI2_RESET_DESKEW_DATA_LANE0 ((uint32_t)(0x1UL << MXC_F_CSI2_RESET_DESKEW_DATA_LANE0_POS)) /**< RESET_DESKEW_DATA_LANE0 Mask */ 767 768 #define MXC_F_CSI2_RESET_DESKEW_DATA_LANE1_POS 1 /**< RESET_DESKEW_DATA_LANE1 Position */ 769 #define MXC_F_CSI2_RESET_DESKEW_DATA_LANE1 ((uint32_t)(0x1UL << MXC_F_CSI2_RESET_DESKEW_DATA_LANE1_POS)) /**< RESET_DESKEW_DATA_LANE1 Mask */ 770 771 #define MXC_F_CSI2_RESET_DESKEW_DATA_LANE2_POS 2 /**< RESET_DESKEW_DATA_LANE2 Position */ 772 #define MXC_F_CSI2_RESET_DESKEW_DATA_LANE2 ((uint32_t)(0x1UL << MXC_F_CSI2_RESET_DESKEW_DATA_LANE2_POS)) /**< RESET_DESKEW_DATA_LANE2 Mask */ 773 774 #define MXC_F_CSI2_RESET_DESKEW_DATA_LANE3_POS 3 /**< RESET_DESKEW_DATA_LANE3 Position */ 775 #define MXC_F_CSI2_RESET_DESKEW_DATA_LANE3 ((uint32_t)(0x1UL << MXC_F_CSI2_RESET_DESKEW_DATA_LANE3_POS)) /**< RESET_DESKEW_DATA_LANE3 Mask */ 776 777 /**@} end of group CSI2_RESET_DESKEW_Register */ 778 779 /** 780 * @ingroup csi2_registers 781 * @defgroup CSI2_VCONTROL CSI2_VCONTROL 782 * @brief PMA_RDY. 783 * @{ 784 */ 785 #define MXC_F_CSI2_VCONTROL_NORMAL_MODE_POS 0 /**< VCONTROL_NORMAL_MODE Position */ 786 #define MXC_F_CSI2_VCONTROL_NORMAL_MODE ((uint32_t)(0x1UL << MXC_F_CSI2_VCONTROL_NORMAL_MODE_POS)) /**< VCONTROL_NORMAL_MODE Mask */ 787 788 #define MXC_F_CSI2_VCONTROL_LP_RX_DC_TEST_POS 1 /**< VCONTROL_LP_RX_DC_TEST Position */ 789 #define MXC_F_CSI2_VCONTROL_LP_RX_DC_TEST ((uint32_t)(0x1UL << MXC_F_CSI2_VCONTROL_LP_RX_DC_TEST_POS)) /**< VCONTROL_LP_RX_DC_TEST Mask */ 790 791 #define MXC_F_CSI2_VCONTROL_LP_RX_DC_1_POS 2 /**< VCONTROL_LP_RX_DC_1 Position */ 792 #define MXC_F_CSI2_VCONTROL_LP_RX_DC_1 ((uint32_t)(0x1UL << MXC_F_CSI2_VCONTROL_LP_RX_DC_1_POS)) /**< VCONTROL_LP_RX_DC_1 Mask */ 793 794 #define MXC_F_CSI2_VCONTROL_LP_RX_DC_0_POS 3 /**< VCONTROL_LP_RX_DC_0 Position */ 795 #define MXC_F_CSI2_VCONTROL_LP_RX_DC_0 ((uint32_t)(0x1UL << MXC_F_CSI2_VCONTROL_LP_RX_DC_0_POS)) /**< VCONTROL_LP_RX_DC_0 Mask */ 796 797 #define MXC_F_CSI2_VCONTROL_CAL_SEN_1_POS 4 /**< VCONTROL_CAL_SEN_1 Position */ 798 #define MXC_F_CSI2_VCONTROL_CAL_SEN_1 ((uint32_t)(0x1UL << MXC_F_CSI2_VCONTROL_CAL_SEN_1_POS)) /**< VCONTROL_CAL_SEN_1 Mask */ 799 800 #define MXC_F_CSI2_VCONTROL_CAL_SEN_0_POS 5 /**< VCONTROL_CAL_SEN_0 Position */ 801 #define MXC_F_CSI2_VCONTROL_CAL_SEN_0 ((uint32_t)(0x1UL << MXC_F_CSI2_VCONTROL_CAL_SEN_0_POS)) /**< VCONTROL_CAL_SEN_0 Mask */ 802 803 #define MXC_F_CSI2_VCONTROL_HSRT_0_POS 7 /**< VCONTROL_HSRT_0 Position */ 804 #define MXC_F_CSI2_VCONTROL_HSRT_0 ((uint32_t)(0x1UL << MXC_F_CSI2_VCONTROL_HSRT_0_POS)) /**< VCONTROL_HSRT_0 Mask */ 805 806 #define MXC_F_CSI2_VCONTROL_HSRT_1_POS 8 /**< VCONTROL_HSRT_1 Position */ 807 #define MXC_F_CSI2_VCONTROL_HSRT_1 ((uint32_t)(0x1UL << MXC_F_CSI2_VCONTROL_HSRT_1_POS)) /**< VCONTROL_HSRT_1 Mask */ 808 809 #define MXC_F_CSI2_VCONTROL_LP_RX_PARTBERT_POS 10 /**< VCONTROL_LP_RX_PARTBERT Position */ 810 #define MXC_F_CSI2_VCONTROL_LP_RX_PARTBERT ((uint32_t)(0x1UL << MXC_F_CSI2_VCONTROL_LP_RX_PARTBERT_POS)) /**< VCONTROL_LP_RX_PARTBERT Mask */ 811 812 #define MXC_F_CSI2_VCONTROL_HS_INT_LOOPBACK_POS 11 /**< VCONTROL_HS_INT_LOOPBACK Position */ 813 #define MXC_F_CSI2_VCONTROL_HS_INT_LOOPBACK ((uint32_t)(0x1UL << MXC_F_CSI2_VCONTROL_HS_INT_LOOPBACK_POS)) /**< VCONTROL_HS_INT_LOOPBACK Mask */ 814 815 #define MXC_F_CSI2_VCONTROL_HS_RX_PARTBERT_POS 27 /**< VCONTROL_HS_RX_PARTBERT Position */ 816 #define MXC_F_CSI2_VCONTROL_HS_RX_PARTBERT ((uint32_t)(0x1UL << MXC_F_CSI2_VCONTROL_HS_RX_PARTBERT_POS)) /**< VCONTROL_HS_RX_PARTBERT Mask */ 817 818 #define MXC_F_CSI2_VCONTROL_HS_RX_PRBS9_POS 28 /**< VCONTROL_HS_RX_PRBS9 Position */ 819 #define MXC_F_CSI2_VCONTROL_HS_RX_PRBS9 ((uint32_t)(0x1UL << MXC_F_CSI2_VCONTROL_HS_RX_PRBS9_POS)) /**< VCONTROL_HS_RX_PRBS9 Mask */ 820 821 #define MXC_F_CSI2_VCONTROL_SUSPEND_MODE_POS 31 /**< VCONTROL_SUSPEND_MODE Position */ 822 #define MXC_F_CSI2_VCONTROL_SUSPEND_MODE ((uint32_t)(0x1UL << MXC_F_CSI2_VCONTROL_SUSPEND_MODE_POS)) /**< VCONTROL_SUSPEND_MODE Mask */ 823 824 /**@} end of group CSI2_VCONTROL_Register */ 825 826 /** 827 * @ingroup csi2_registers 828 * @defgroup CSI2_RG_CDRX_DSIRX_EN CSI2_RG_CDRX_DSIRX_EN 829 * @brief RG_CDRX_DSIRX_EN. 830 * @{ 831 */ 832 #define MXC_F_CSI2_RG_CDRX_DSIRX_EN_RXMODE_POS 0 /**< RG_CDRX_DSIRX_EN_RXMODE Position */ 833 #define MXC_F_CSI2_RG_CDRX_DSIRX_EN_RXMODE ((uint32_t)(0x1UL << MXC_F_CSI2_RG_CDRX_DSIRX_EN_RXMODE_POS)) /**< RG_CDRX_DSIRX_EN_RXMODE Mask */ 834 835 /**@} end of group CSI2_RG_CDRX_DSIRX_EN_Register */ 836 837 /** 838 * @ingroup csi2_registers 839 * @defgroup CSI2_RG_CDRX_BISTHS_PLL_PRE_DIV2 CSI2_RG_CDRX_BISTHS_PLL_PRE_DIV2 840 * @brief RG_CDRX_BISTHS_PLL_PRE_DIV2. 841 * @{ 842 */ 843 #define MXC_F_CSI2_RG_CDRX_BISTHS_PLL_PRE_DIV2_RXMODE_POS 0 /**< RG_CDRX_BISTHS_PLL_PRE_DIV2_RXMODE Position */ 844 #define MXC_F_CSI2_RG_CDRX_BISTHS_PLL_PRE_DIV2_RXMODE ((uint32_t)(0x1UL << MXC_F_CSI2_RG_CDRX_BISTHS_PLL_PRE_DIV2_RXMODE_POS)) /**< RG_CDRX_BISTHS_PLL_PRE_DIV2_RXMODE Mask */ 845 846 /**@} end of group CSI2_RG_CDRX_BISTHS_PLL_PRE_DIV2_Register */ 847 848 /** 849 * @ingroup csi2_registers 850 * @defgroup CSI2_VFIFO_CFG0 CSI2_VFIFO_CFG0 851 * @brief Video FIFO Configuration Register 0. 852 * @{ 853 */ 854 #define MXC_F_CSI2_VFIFO_CFG0_VC_POS 0 /**< VFIFO_CFG0_VC Position */ 855 #define MXC_F_CSI2_VFIFO_CFG0_VC ((uint32_t)(0x3UL << MXC_F_CSI2_VFIFO_CFG0_VC_POS)) /**< VFIFO_CFG0_VC Mask */ 856 857 #define MXC_F_CSI2_VFIFO_CFG0_DMAMODE_POS 6 /**< VFIFO_CFG0_DMAMODE Position */ 858 #define MXC_F_CSI2_VFIFO_CFG0_DMAMODE ((uint32_t)(0x3UL << MXC_F_CSI2_VFIFO_CFG0_DMAMODE_POS)) /**< VFIFO_CFG0_DMAMODE Mask */ 859 #define MXC_V_CSI2_VFIFO_CFG0_DMAMODE_NO_DMA ((uint32_t)0x0UL) /**< VFIFO_CFG0_DMAMODE_NO_DMA Value */ 860 #define MXC_S_CSI2_VFIFO_CFG0_DMAMODE_NO_DMA (MXC_V_CSI2_VFIFO_CFG0_DMAMODE_NO_DMA << MXC_F_CSI2_VFIFO_CFG0_DMAMODE_POS) /**< VFIFO_CFG0_DMAMODE_NO_DMA Setting */ 861 #define MXC_V_CSI2_VFIFO_CFG0_DMAMODE_DMA_REQ ((uint32_t)0x1UL) /**< VFIFO_CFG0_DMAMODE_DMA_REQ Value */ 862 #define MXC_S_CSI2_VFIFO_CFG0_DMAMODE_DMA_REQ (MXC_V_CSI2_VFIFO_CFG0_DMAMODE_DMA_REQ << MXC_F_CSI2_VFIFO_CFG0_DMAMODE_POS) /**< VFIFO_CFG0_DMAMODE_DMA_REQ Setting */ 863 #define MXC_V_CSI2_VFIFO_CFG0_DMAMODE_FIFO_THD ((uint32_t)0x2UL) /**< VFIFO_CFG0_DMAMODE_FIFO_THD Value */ 864 #define MXC_S_CSI2_VFIFO_CFG0_DMAMODE_FIFO_THD (MXC_V_CSI2_VFIFO_CFG0_DMAMODE_FIFO_THD << MXC_F_CSI2_VFIFO_CFG0_DMAMODE_POS) /**< VFIFO_CFG0_DMAMODE_FIFO_THD Setting */ 865 #define MXC_V_CSI2_VFIFO_CFG0_DMAMODE_FIFO_FULL ((uint32_t)0x3UL) /**< VFIFO_CFG0_DMAMODE_FIFO_FULL Value */ 866 #define MXC_S_CSI2_VFIFO_CFG0_DMAMODE_FIFO_FULL (MXC_V_CSI2_VFIFO_CFG0_DMAMODE_FIFO_FULL << MXC_F_CSI2_VFIFO_CFG0_DMAMODE_POS) /**< VFIFO_CFG0_DMAMODE_FIFO_FULL Setting */ 867 868 #define MXC_F_CSI2_VFIFO_CFG0_AHBWAIT_POS 8 /**< VFIFO_CFG0_AHBWAIT Position */ 869 #define MXC_F_CSI2_VFIFO_CFG0_AHBWAIT ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_CFG0_AHBWAIT_POS)) /**< VFIFO_CFG0_AHBWAIT Mask */ 870 871 #define MXC_F_CSI2_VFIFO_CFG0_FIFORM_POS 9 /**< VFIFO_CFG0_FIFORM Position */ 872 #define MXC_F_CSI2_VFIFO_CFG0_FIFORM ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_CFG0_FIFORM_POS)) /**< VFIFO_CFG0_FIFORM Mask */ 873 874 #define MXC_F_CSI2_VFIFO_CFG0_ERRDE_POS 10 /**< VFIFO_CFG0_ERRDE Position */ 875 #define MXC_F_CSI2_VFIFO_CFG0_ERRDE ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_CFG0_ERRDE_POS)) /**< VFIFO_CFG0_ERRDE Mask */ 876 877 #define MXC_F_CSI2_VFIFO_CFG0_FBWM_POS 11 /**< VFIFO_CFG0_FBWM Position */ 878 #define MXC_F_CSI2_VFIFO_CFG0_FBWM ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_CFG0_FBWM_POS)) /**< VFIFO_CFG0_FBWM Mask */ 879 880 /**@} end of group CSI2_VFIFO_CFG0_Register */ 881 882 /** 883 * @ingroup csi2_registers 884 * @defgroup CSI2_VFIFO_CFG1 CSI2_VFIFO_CFG1 885 * @brief Video FIFO Configuration Register 1. 886 * @{ 887 */ 888 #define MXC_F_CSI2_VFIFO_CFG1_AHBWCYC_POS 0 /**< VFIFO_CFG1_AHBWCYC Position */ 889 #define MXC_F_CSI2_VFIFO_CFG1_AHBWCYC ((uint32_t)(0xFFFFUL << MXC_F_CSI2_VFIFO_CFG1_AHBWCYC_POS)) /**< VFIFO_CFG1_AHBWCYC Mask */ 890 891 #define MXC_F_CSI2_VFIFO_CFG1_WAIT_FIRST_FS_POS 16 /**< VFIFO_CFG1_WAIT_FIRST_FS Position */ 892 #define MXC_F_CSI2_VFIFO_CFG1_WAIT_FIRST_FS ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_CFG1_WAIT_FIRST_FS_POS)) /**< VFIFO_CFG1_WAIT_FIRST_FS Mask */ 893 894 #define MXC_F_CSI2_VFIFO_CFG1_ACCU_FRAME_CTRL_POS 17 /**< VFIFO_CFG1_ACCU_FRAME_CTRL Position */ 895 #define MXC_F_CSI2_VFIFO_CFG1_ACCU_FRAME_CTRL ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_CFG1_ACCU_FRAME_CTRL_POS)) /**< VFIFO_CFG1_ACCU_FRAME_CTRL Mask */ 896 897 #define MXC_F_CSI2_VFIFO_CFG1_ACCU_LINE_CTRL_POS 18 /**< VFIFO_CFG1_ACCU_LINE_CTRL Position */ 898 #define MXC_F_CSI2_VFIFO_CFG1_ACCU_LINE_CTRL ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_CFG1_ACCU_LINE_CTRL_POS)) /**< VFIFO_CFG1_ACCU_LINE_CTRL Mask */ 899 900 #define MXC_F_CSI2_VFIFO_CFG1_ACCU_LINE_CNT_POS 19 /**< VFIFO_CFG1_ACCU_LINE_CNT Position */ 901 #define MXC_F_CSI2_VFIFO_CFG1_ACCU_LINE_CNT ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_CFG1_ACCU_LINE_CNT_POS)) /**< VFIFO_CFG1_ACCU_LINE_CNT Mask */ 902 903 #define MXC_F_CSI2_VFIFO_CFG1_ACCU_PIXEL_CNT_POS 20 /**< VFIFO_CFG1_ACCU_PIXEL_CNT Position */ 904 #define MXC_F_CSI2_VFIFO_CFG1_ACCU_PIXEL_CNT ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_CFG1_ACCU_PIXEL_CNT_POS)) /**< VFIFO_CFG1_ACCU_PIXEL_CNT Mask */ 905 906 #define MXC_F_CSI2_VFIFO_CFG1_ACCU_PIXEL_ZERO_POS 21 /**< VFIFO_CFG1_ACCU_PIXEL_ZERO Position */ 907 #define MXC_F_CSI2_VFIFO_CFG1_ACCU_PIXEL_ZERO ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_CFG1_ACCU_PIXEL_ZERO_POS)) /**< VFIFO_CFG1_ACCU_PIXEL_ZERO Mask */ 908 909 /**@} end of group CSI2_VFIFO_CFG1_Register */ 910 911 /** 912 * @ingroup csi2_registers 913 * @defgroup CSI2_VFIFO_CTRL CSI2_VFIFO_CTRL 914 * @brief Video FIFO Control Register. 915 * @{ 916 */ 917 #define MXC_F_CSI2_VFIFO_CTRL_FIFOEN_POS 0 /**< VFIFO_CTRL_FIFOEN Position */ 918 #define MXC_F_CSI2_VFIFO_CTRL_FIFOEN ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_CTRL_FIFOEN_POS)) /**< VFIFO_CTRL_FIFOEN Mask */ 919 920 #define MXC_F_CSI2_VFIFO_CTRL_FLUSH_POS 4 /**< VFIFO_CTRL_FLUSH Position */ 921 #define MXC_F_CSI2_VFIFO_CTRL_FLUSH ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_CTRL_FLUSH_POS)) /**< VFIFO_CTRL_FLUSH Mask */ 922 923 #define MXC_F_CSI2_VFIFO_CTRL_THD_POS 8 /**< VFIFO_CTRL_THD Position */ 924 #define MXC_F_CSI2_VFIFO_CTRL_THD ((uint32_t)(0x7FUL << MXC_F_CSI2_VFIFO_CTRL_THD_POS)) /**< VFIFO_CTRL_THD Mask */ 925 926 /**@} end of group CSI2_VFIFO_CTRL_Register */ 927 928 /** 929 * @ingroup csi2_registers 930 * @defgroup CSI2_VFIFO_STS CSI2_VFIFO_STS 931 * @brief Video FIFO Status Register. 932 * @{ 933 */ 934 #define MXC_F_CSI2_VFIFO_STS_FEMPTY_POS 0 /**< VFIFO_STS_FEMPTY Position */ 935 #define MXC_F_CSI2_VFIFO_STS_FEMPTY ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_STS_FEMPTY_POS)) /**< VFIFO_STS_FEMPTY Mask */ 936 937 #define MXC_F_CSI2_VFIFO_STS_FTHD_POS 1 /**< VFIFO_STS_FTHD Position */ 938 #define MXC_F_CSI2_VFIFO_STS_FTHD ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_STS_FTHD_POS)) /**< VFIFO_STS_FTHD Mask */ 939 940 #define MXC_F_CSI2_VFIFO_STS_FFULL_POS 2 /**< VFIFO_STS_FFULL Position */ 941 #define MXC_F_CSI2_VFIFO_STS_FFULL ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_STS_FFULL_POS)) /**< VFIFO_STS_FFULL Mask */ 942 943 #define MXC_F_CSI2_VFIFO_STS_UNDERRUN_POS 3 /**< VFIFO_STS_UNDERRUN Position */ 944 #define MXC_F_CSI2_VFIFO_STS_UNDERRUN ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_STS_UNDERRUN_POS)) /**< VFIFO_STS_UNDERRUN Mask */ 945 946 #define MXC_F_CSI2_VFIFO_STS_OVERRUN_POS 4 /**< VFIFO_STS_OVERRUN Position */ 947 #define MXC_F_CSI2_VFIFO_STS_OVERRUN ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_STS_OVERRUN_POS)) /**< VFIFO_STS_OVERRUN Mask */ 948 949 #define MXC_F_CSI2_VFIFO_STS_OUTSYNC_POS 5 /**< VFIFO_STS_OUTSYNC Position */ 950 #define MXC_F_CSI2_VFIFO_STS_OUTSYNC ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_STS_OUTSYNC_POS)) /**< VFIFO_STS_OUTSYNC Mask */ 951 952 #define MXC_F_CSI2_VFIFO_STS_FMTERR_POS 6 /**< VFIFO_STS_FMTERR Position */ 953 #define MXC_F_CSI2_VFIFO_STS_FMTERR ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_STS_FMTERR_POS)) /**< VFIFO_STS_FMTERR Mask */ 954 955 #define MXC_F_CSI2_VFIFO_STS_AHBWTO_POS 7 /**< VFIFO_STS_AHBWTO Position */ 956 #define MXC_F_CSI2_VFIFO_STS_AHBWTO ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_STS_AHBWTO_POS)) /**< VFIFO_STS_AHBWTO Mask */ 957 958 #define MXC_F_CSI2_VFIFO_STS_FS_POS 8 /**< VFIFO_STS_FS Position */ 959 #define MXC_F_CSI2_VFIFO_STS_FS ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_STS_FS_POS)) /**< VFIFO_STS_FS Mask */ 960 961 #define MXC_F_CSI2_VFIFO_STS_FE_POS 9 /**< VFIFO_STS_FE Position */ 962 #define MXC_F_CSI2_VFIFO_STS_FE ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_STS_FE_POS)) /**< VFIFO_STS_FE Mask */ 963 964 #define MXC_F_CSI2_VFIFO_STS_LS_POS 10 /**< VFIFO_STS_LS Position */ 965 #define MXC_F_CSI2_VFIFO_STS_LS ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_STS_LS_POS)) /**< VFIFO_STS_LS Mask */ 966 967 #define MXC_F_CSI2_VFIFO_STS_LE_POS 11 /**< VFIFO_STS_LE Position */ 968 #define MXC_F_CSI2_VFIFO_STS_LE ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_STS_LE_POS)) /**< VFIFO_STS_LE Mask */ 969 970 #define MXC_F_CSI2_VFIFO_STS_FELT_POS 16 /**< VFIFO_STS_FELT Position */ 971 #define MXC_F_CSI2_VFIFO_STS_FELT ((uint32_t)(0x7FUL << MXC_F_CSI2_VFIFO_STS_FELT_POS)) /**< VFIFO_STS_FELT Mask */ 972 973 #define MXC_F_CSI2_VFIFO_STS_FMT_POS 24 /**< VFIFO_STS_FMT Position */ 974 #define MXC_F_CSI2_VFIFO_STS_FMT ((uint32_t)(0x3FUL << MXC_F_CSI2_VFIFO_STS_FMT_POS)) /**< VFIFO_STS_FMT Mask */ 975 976 /**@} end of group CSI2_VFIFO_STS_Register */ 977 978 /** 979 * @ingroup csi2_registers 980 * @defgroup CSI2_VFIFO_LINE_NUM CSI2_VFIFO_LINE_NUM 981 * @brief Video FIFO CSI Line Number Per Frame. 982 * @{ 983 */ 984 #define MXC_F_CSI2_VFIFO_LINE_NUM_LINE_NUM_POS 0 /**< VFIFO_LINE_NUM_LINE_NUM Position */ 985 #define MXC_F_CSI2_VFIFO_LINE_NUM_LINE_NUM ((uint32_t)(0x1FFFUL << MXC_F_CSI2_VFIFO_LINE_NUM_LINE_NUM_POS)) /**< VFIFO_LINE_NUM_LINE_NUM Mask */ 986 987 /**@} end of group CSI2_VFIFO_LINE_NUM_Register */ 988 989 /** 990 * @ingroup csi2_registers 991 * @defgroup CSI2_VFIFO_PIXEL_NUM CSI2_VFIFO_PIXEL_NUM 992 * @brief Video FIFO CSI Pixel Number Per Line. 993 * @{ 994 */ 995 #define MXC_F_CSI2_VFIFO_PIXEL_NUM_PIXEL_NUM_POS 0 /**< VFIFO_PIXEL_NUM_PIXEL_NUM Position */ 996 #define MXC_F_CSI2_VFIFO_PIXEL_NUM_PIXEL_NUM ((uint32_t)(0x3FFFUL << MXC_F_CSI2_VFIFO_PIXEL_NUM_PIXEL_NUM_POS)) /**< VFIFO_PIXEL_NUM_PIXEL_NUM Mask */ 997 998 /**@} end of group CSI2_VFIFO_PIXEL_NUM_Register */ 999 1000 /** 1001 * @ingroup csi2_registers 1002 * @defgroup CSI2_VFIFO_LINE_CNT CSI2_VFIFO_LINE_CNT 1003 * @brief Video FIFO CSI Line Count. 1004 * @{ 1005 */ 1006 #define MXC_F_CSI2_VFIFO_LINE_CNT_LINE_CNT_POS 0 /**< VFIFO_LINE_CNT_LINE_CNT Position */ 1007 #define MXC_F_CSI2_VFIFO_LINE_CNT_LINE_CNT ((uint32_t)(0xFFFUL << MXC_F_CSI2_VFIFO_LINE_CNT_LINE_CNT_POS)) /**< VFIFO_LINE_CNT_LINE_CNT Mask */ 1008 1009 /**@} end of group CSI2_VFIFO_LINE_CNT_Register */ 1010 1011 /** 1012 * @ingroup csi2_registers 1013 * @defgroup CSI2_VFIFO_PIXEL_CNT CSI2_VFIFO_PIXEL_CNT 1014 * @brief Video FIFO CSI Pixel Count. 1015 * @{ 1016 */ 1017 #define MXC_F_CSI2_VFIFO_PIXEL_CNT_PIXEL_CNT_POS 0 /**< VFIFO_PIXEL_CNT_PIXEL_CNT Position */ 1018 #define MXC_F_CSI2_VFIFO_PIXEL_CNT_PIXEL_CNT ((uint32_t)(0x1FFFUL << MXC_F_CSI2_VFIFO_PIXEL_CNT_PIXEL_CNT_POS)) /**< VFIFO_PIXEL_CNT_PIXEL_CNT Mask */ 1019 1020 /**@} end of group CSI2_VFIFO_PIXEL_CNT_Register */ 1021 1022 /** 1023 * @ingroup csi2_registers 1024 * @defgroup CSI2_VFIFO_FRAME_STS CSI2_VFIFO_FRAME_STS 1025 * @brief Video FIFO Frame Status Register. 1026 * @{ 1027 */ 1028 #define MXC_F_CSI2_VFIFO_FRAME_STS_FRAME_STATE_POS 0 /**< VFIFO_FRAME_STS_FRAME_STATE Position */ 1029 #define MXC_F_CSI2_VFIFO_FRAME_STS_FRAME_STATE ((uint32_t)(0x7UL << MXC_F_CSI2_VFIFO_FRAME_STS_FRAME_STATE_POS)) /**< VFIFO_FRAME_STS_FRAME_STATE Mask */ 1030 1031 #define MXC_F_CSI2_VFIFO_FRAME_STS_ERROR_CODE_POS 3 /**< VFIFO_FRAME_STS_ERROR_CODE Position */ 1032 #define MXC_F_CSI2_VFIFO_FRAME_STS_ERROR_CODE ((uint32_t)(0x7UL << MXC_F_CSI2_VFIFO_FRAME_STS_ERROR_CODE_POS)) /**< VFIFO_FRAME_STS_ERROR_CODE Mask */ 1033 1034 /**@} end of group CSI2_VFIFO_FRAME_STS_Register */ 1035 1036 /** 1037 * @ingroup csi2_registers 1038 * @defgroup CSI2_VFIFO_RAW_CTRL CSI2_VFIFO_RAW_CTRL 1039 * @brief Video FIFO RAW-to-RGB Control Register. 1040 * @{ 1041 */ 1042 #define MXC_F_CSI2_VFIFO_RAW_CTRL_RAW_CEN_POS 0 /**< VFIFO_RAW_CTRL_RAW_CEN Position */ 1043 #define MXC_F_CSI2_VFIFO_RAW_CTRL_RAW_CEN ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_RAW_CTRL_RAW_CEN_POS)) /**< VFIFO_RAW_CTRL_RAW_CEN Mask */ 1044 1045 #define MXC_F_CSI2_VFIFO_RAW_CTRL_RAW_FF_AFO_POS 1 /**< VFIFO_RAW_CTRL_RAW_FF_AFO Position */ 1046 #define MXC_F_CSI2_VFIFO_RAW_CTRL_RAW_FF_AFO ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_RAW_CTRL_RAW_FF_AFO_POS)) /**< VFIFO_RAW_CTRL_RAW_FF_AFO Mask */ 1047 1048 #define MXC_F_CSI2_VFIFO_RAW_CTRL_RAW_FF_FO_POS 4 /**< VFIFO_RAW_CTRL_RAW_FF_FO Position */ 1049 #define MXC_F_CSI2_VFIFO_RAW_CTRL_RAW_FF_FO ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_RAW_CTRL_RAW_FF_FO_POS)) /**< VFIFO_RAW_CTRL_RAW_FF_FO Mask */ 1050 1051 #define MXC_F_CSI2_VFIFO_RAW_CTRL_RAW_FMT_POS 8 /**< VFIFO_RAW_CTRL_RAW_FMT Position */ 1052 #define MXC_F_CSI2_VFIFO_RAW_CTRL_RAW_FMT ((uint32_t)(0x3UL << MXC_F_CSI2_VFIFO_RAW_CTRL_RAW_FMT_POS)) /**< VFIFO_RAW_CTRL_RAW_FMT Mask */ 1053 #define MXC_V_CSI2_VFIFO_RAW_CTRL_RAW_FMT_RGRG_GBGB ((uint32_t)0x0UL) /**< VFIFO_RAW_CTRL_RAW_FMT_RGRG_GBGB Value */ 1054 #define MXC_S_CSI2_VFIFO_RAW_CTRL_RAW_FMT_RGRG_GBGB (MXC_V_CSI2_VFIFO_RAW_CTRL_RAW_FMT_RGRG_GBGB << MXC_F_CSI2_VFIFO_RAW_CTRL_RAW_FMT_POS) /**< VFIFO_RAW_CTRL_RAW_FMT_RGRG_GBGB Setting */ 1055 #define MXC_V_CSI2_VFIFO_RAW_CTRL_RAW_FMT_GRGR_BGBG ((uint32_t)0x1UL) /**< VFIFO_RAW_CTRL_RAW_FMT_GRGR_BGBG Value */ 1056 #define MXC_S_CSI2_VFIFO_RAW_CTRL_RAW_FMT_GRGR_BGBG (MXC_V_CSI2_VFIFO_RAW_CTRL_RAW_FMT_GRGR_BGBG << MXC_F_CSI2_VFIFO_RAW_CTRL_RAW_FMT_POS) /**< VFIFO_RAW_CTRL_RAW_FMT_GRGR_BGBG Setting */ 1057 #define MXC_V_CSI2_VFIFO_RAW_CTRL_RAW_FMT_GBGB_RGRG ((uint32_t)0x2UL) /**< VFIFO_RAW_CTRL_RAW_FMT_GBGB_RGRG Value */ 1058 #define MXC_S_CSI2_VFIFO_RAW_CTRL_RAW_FMT_GBGB_RGRG (MXC_V_CSI2_VFIFO_RAW_CTRL_RAW_FMT_GBGB_RGRG << MXC_F_CSI2_VFIFO_RAW_CTRL_RAW_FMT_POS) /**< VFIFO_RAW_CTRL_RAW_FMT_GBGB_RGRG Setting */ 1059 #define MXC_V_CSI2_VFIFO_RAW_CTRL_RAW_FMT_BGBG_GRGR ((uint32_t)0x3UL) /**< VFIFO_RAW_CTRL_RAW_FMT_BGBG_GRGR Value */ 1060 #define MXC_S_CSI2_VFIFO_RAW_CTRL_RAW_FMT_BGBG_GRGR (MXC_V_CSI2_VFIFO_RAW_CTRL_RAW_FMT_BGBG_GRGR << MXC_F_CSI2_VFIFO_RAW_CTRL_RAW_FMT_POS) /**< VFIFO_RAW_CTRL_RAW_FMT_BGBG_GRGR Setting */ 1061 1062 #define MXC_F_CSI2_VFIFO_RAW_CTRL_RGB_TYP_POS 12 /**< VFIFO_RAW_CTRL_RGB_TYP Position */ 1063 #define MXC_F_CSI2_VFIFO_RAW_CTRL_RGB_TYP ((uint32_t)(0x7UL << MXC_F_CSI2_VFIFO_RAW_CTRL_RGB_TYP_POS)) /**< VFIFO_RAW_CTRL_RGB_TYP Mask */ 1064 #define MXC_V_CSI2_VFIFO_RAW_CTRL_RGB_TYP_RGB444 ((uint32_t)0x0UL) /**< VFIFO_RAW_CTRL_RGB_TYP_RGB444 Value */ 1065 #define MXC_S_CSI2_VFIFO_RAW_CTRL_RGB_TYP_RGB444 (MXC_V_CSI2_VFIFO_RAW_CTRL_RGB_TYP_RGB444 << MXC_F_CSI2_VFIFO_RAW_CTRL_RGB_TYP_POS) /**< VFIFO_RAW_CTRL_RGB_TYP_RGB444 Setting */ 1066 #define MXC_V_CSI2_VFIFO_RAW_CTRL_RGB_TYP_RGB555 ((uint32_t)0x1UL) /**< VFIFO_RAW_CTRL_RGB_TYP_RGB555 Value */ 1067 #define MXC_S_CSI2_VFIFO_RAW_CTRL_RGB_TYP_RGB555 (MXC_V_CSI2_VFIFO_RAW_CTRL_RGB_TYP_RGB555 << MXC_F_CSI2_VFIFO_RAW_CTRL_RGB_TYP_POS) /**< VFIFO_RAW_CTRL_RGB_TYP_RGB555 Setting */ 1068 #define MXC_V_CSI2_VFIFO_RAW_CTRL_RGB_TYP_RGB565 ((uint32_t)0x2UL) /**< VFIFO_RAW_CTRL_RGB_TYP_RGB565 Value */ 1069 #define MXC_S_CSI2_VFIFO_RAW_CTRL_RGB_TYP_RGB565 (MXC_V_CSI2_VFIFO_RAW_CTRL_RGB_TYP_RGB565 << MXC_F_CSI2_VFIFO_RAW_CTRL_RGB_TYP_POS) /**< VFIFO_RAW_CTRL_RGB_TYP_RGB565 Setting */ 1070 #define MXC_V_CSI2_VFIFO_RAW_CTRL_RGB_TYP_RGB666 ((uint32_t)0x3UL) /**< VFIFO_RAW_CTRL_RGB_TYP_RGB666 Value */ 1071 #define MXC_S_CSI2_VFIFO_RAW_CTRL_RGB_TYP_RGB666 (MXC_V_CSI2_VFIFO_RAW_CTRL_RGB_TYP_RGB666 << MXC_F_CSI2_VFIFO_RAW_CTRL_RGB_TYP_POS) /**< VFIFO_RAW_CTRL_RGB_TYP_RGB666 Setting */ 1072 #define MXC_V_CSI2_VFIFO_RAW_CTRL_RGB_TYP_RGG888 ((uint32_t)0x4UL) /**< VFIFO_RAW_CTRL_RGB_TYP_RGG888 Value */ 1073 #define MXC_S_CSI2_VFIFO_RAW_CTRL_RGB_TYP_RGG888 (MXC_V_CSI2_VFIFO_RAW_CTRL_RGB_TYP_RGG888 << MXC_F_CSI2_VFIFO_RAW_CTRL_RGB_TYP_POS) /**< VFIFO_RAW_CTRL_RGB_TYP_RGG888 Setting */ 1074 1075 /**@} end of group CSI2_VFIFO_RAW_CTRL_Register */ 1076 1077 /** 1078 * @ingroup csi2_registers 1079 * @defgroup CSI2_VFIFO_RAW_BUF0_ADDR CSI2_VFIFO_RAW_BUF0_ADDR 1080 * @brief Video FIFO RAW-to-RGB Line Buffer0 Address. 1081 * @{ 1082 */ 1083 #define MXC_F_CSI2_VFIFO_RAW_BUF0_ADDR_ADDR_POS 2 /**< VFIFO_RAW_BUF0_ADDR_ADDR Position */ 1084 #define MXC_F_CSI2_VFIFO_RAW_BUF0_ADDR_ADDR ((uint32_t)(0x3FFFFFFFUL << MXC_F_CSI2_VFIFO_RAW_BUF0_ADDR_ADDR_POS)) /**< VFIFO_RAW_BUF0_ADDR_ADDR Mask */ 1085 1086 /**@} end of group CSI2_VFIFO_RAW_BUF0_ADDR_Register */ 1087 1088 /** 1089 * @ingroup csi2_registers 1090 * @defgroup CSI2_VFIFO_RAW_BUF1_ADDR CSI2_VFIFO_RAW_BUF1_ADDR 1091 * @brief Video FIFO RAW-to-RGB Line Buffer1 Address. 1092 * @{ 1093 */ 1094 #define MXC_F_CSI2_VFIFO_RAW_BUF1_ADDR_ADDR_POS 2 /**< VFIFO_RAW_BUF1_ADDR_ADDR Position */ 1095 #define MXC_F_CSI2_VFIFO_RAW_BUF1_ADDR_ADDR ((uint32_t)(0x3FFFFFFFUL << MXC_F_CSI2_VFIFO_RAW_BUF1_ADDR_ADDR_POS)) /**< VFIFO_RAW_BUF1_ADDR_ADDR Mask */ 1096 1097 /**@} end of group CSI2_VFIFO_RAW_BUF1_ADDR_Register */ 1098 1099 /** 1100 * @ingroup csi2_registers 1101 * @defgroup CSI2_VFIFO_AHBM_CTRL CSI2_VFIFO_AHBM_CTRL 1102 * @brief Video FIFO AHB Master Control Register. 1103 * @{ 1104 */ 1105 #define MXC_F_CSI2_VFIFO_AHBM_CTRL_AHBMEN_POS 0 /**< VFIFO_AHBM_CTRL_AHBMEN Position */ 1106 #define MXC_F_CSI2_VFIFO_AHBM_CTRL_AHBMEN ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_AHBM_CTRL_AHBMEN_POS)) /**< VFIFO_AHBM_CTRL_AHBMEN Mask */ 1107 1108 #define MXC_F_CSI2_VFIFO_AHBM_CTRL_AHBMCLR_POS 1 /**< VFIFO_AHBM_CTRL_AHBMCLR Position */ 1109 #define MXC_F_CSI2_VFIFO_AHBM_CTRL_AHBMCLR ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_AHBM_CTRL_AHBMCLR_POS)) /**< VFIFO_AHBM_CTRL_AHBMCLR Mask */ 1110 1111 #define MXC_F_CSI2_VFIFO_AHBM_CTRL_BSTLEN_POS 4 /**< VFIFO_AHBM_CTRL_BSTLEN Position */ 1112 #define MXC_F_CSI2_VFIFO_AHBM_CTRL_BSTLEN ((uint32_t)(0x3UL << MXC_F_CSI2_VFIFO_AHBM_CTRL_BSTLEN_POS)) /**< VFIFO_AHBM_CTRL_BSTLEN Mask */ 1113 #define MXC_V_CSI2_VFIFO_AHBM_CTRL_BSTLEN_VFIFO_THD ((uint32_t)0x0UL) /**< VFIFO_AHBM_CTRL_BSTLEN_VFIFO_THD Value */ 1114 #define MXC_S_CSI2_VFIFO_AHBM_CTRL_BSTLEN_VFIFO_THD (MXC_V_CSI2_VFIFO_AHBM_CTRL_BSTLEN_VFIFO_THD << MXC_F_CSI2_VFIFO_AHBM_CTRL_BSTLEN_POS) /**< VFIFO_AHBM_CTRL_BSTLEN_VFIFO_THD Setting */ 1115 #define MXC_V_CSI2_VFIFO_AHBM_CTRL_BSTLEN_ONE_WORD ((uint32_t)0x1UL) /**< VFIFO_AHBM_CTRL_BSTLEN_ONE_WORD Value */ 1116 #define MXC_S_CSI2_VFIFO_AHBM_CTRL_BSTLEN_ONE_WORD (MXC_V_CSI2_VFIFO_AHBM_CTRL_BSTLEN_ONE_WORD << MXC_F_CSI2_VFIFO_AHBM_CTRL_BSTLEN_POS) /**< VFIFO_AHBM_CTRL_BSTLEN_ONE_WORD Setting */ 1117 #define MXC_V_CSI2_VFIFO_AHBM_CTRL_BSTLEN_FOUR_WORDS ((uint32_t)0x2UL) /**< VFIFO_AHBM_CTRL_BSTLEN_FOUR_WORDS Value */ 1118 #define MXC_S_CSI2_VFIFO_AHBM_CTRL_BSTLEN_FOUR_WORDS (MXC_V_CSI2_VFIFO_AHBM_CTRL_BSTLEN_FOUR_WORDS << MXC_F_CSI2_VFIFO_AHBM_CTRL_BSTLEN_POS) /**< VFIFO_AHBM_CTRL_BSTLEN_FOUR_WORDS Setting */ 1119 #define MXC_V_CSI2_VFIFO_AHBM_CTRL_BSTLEN_EIGHT_WORDS ((uint32_t)0x3UL) /**< VFIFO_AHBM_CTRL_BSTLEN_EIGHT_WORDS Value */ 1120 #define MXC_S_CSI2_VFIFO_AHBM_CTRL_BSTLEN_EIGHT_WORDS (MXC_V_CSI2_VFIFO_AHBM_CTRL_BSTLEN_EIGHT_WORDS << MXC_F_CSI2_VFIFO_AHBM_CTRL_BSTLEN_POS) /**< VFIFO_AHBM_CTRL_BSTLEN_EIGHT_WORDS Setting */ 1121 1122 /**@} end of group CSI2_VFIFO_AHBM_CTRL_Register */ 1123 1124 /** 1125 * @ingroup csi2_registers 1126 * @defgroup CSI2_VFIFO_AHBM_STS CSI2_VFIFO_AHBM_STS 1127 * @brief Video FIFO AHB Master Status Register. 1128 * @{ 1129 */ 1130 #define MXC_F_CSI2_VFIFO_AHBM_STS_HRDY_TO_POS 0 /**< VFIFO_AHBM_STS_HRDY_TO Position */ 1131 #define MXC_F_CSI2_VFIFO_AHBM_STS_HRDY_TO ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_AHBM_STS_HRDY_TO_POS)) /**< VFIFO_AHBM_STS_HRDY_TO Mask */ 1132 1133 #define MXC_F_CSI2_VFIFO_AHBM_STS_IDLE_TO_POS 1 /**< VFIFO_AHBM_STS_IDLE_TO Position */ 1134 #define MXC_F_CSI2_VFIFO_AHBM_STS_IDLE_TO ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_AHBM_STS_IDLE_TO_POS)) /**< VFIFO_AHBM_STS_IDLE_TO Mask */ 1135 1136 #define MXC_F_CSI2_VFIFO_AHBM_STS_TRANS_MAX_POS 2 /**< VFIFO_AHBM_STS_TRANS_MAX Position */ 1137 #define MXC_F_CSI2_VFIFO_AHBM_STS_TRANS_MAX ((uint32_t)(0x1UL << MXC_F_CSI2_VFIFO_AHBM_STS_TRANS_MAX_POS)) /**< VFIFO_AHBM_STS_TRANS_MAX Mask */ 1138 1139 /**@} end of group CSI2_VFIFO_AHBM_STS_Register */ 1140 1141 /** 1142 * @ingroup csi2_registers 1143 * @defgroup CSI2_VFIFO_AHBM_START_ADDR CSI2_VFIFO_AHBM_START_ADDR 1144 * @brief Video FIFO AHB Master Start Address Register. 1145 * @{ 1146 */ 1147 #define MXC_F_CSI2_VFIFO_AHBM_START_ADDR_AHBM_START_ADDR_POS 2 /**< VFIFO_AHBM_START_ADDR_AHBM_START_ADDR Position */ 1148 #define MXC_F_CSI2_VFIFO_AHBM_START_ADDR_AHBM_START_ADDR ((uint32_t)(0x3FFFFFFFUL << MXC_F_CSI2_VFIFO_AHBM_START_ADDR_AHBM_START_ADDR_POS)) /**< VFIFO_AHBM_START_ADDR_AHBM_START_ADDR Mask */ 1149 1150 /**@} end of group CSI2_VFIFO_AHBM_START_ADDR_Register */ 1151 1152 /** 1153 * @ingroup csi2_registers 1154 * @defgroup CSI2_VFIFO_AHBM_ADDR_RANGE CSI2_VFIFO_AHBM_ADDR_RANGE 1155 * @brief Video FIFO AHB Master Address Range Register. 1156 * @{ 1157 */ 1158 #define MXC_F_CSI2_VFIFO_AHBM_ADDR_RANGE_AHBM_ADDR_RANGE_POS 2 /**< VFIFO_AHBM_ADDR_RANGE_AHBM_ADDR_RANGE Position */ 1159 #define MXC_F_CSI2_VFIFO_AHBM_ADDR_RANGE_AHBM_ADDR_RANGE ((uint32_t)(0x3FFFUL << MXC_F_CSI2_VFIFO_AHBM_ADDR_RANGE_AHBM_ADDR_RANGE_POS)) /**< VFIFO_AHBM_ADDR_RANGE_AHBM_ADDR_RANGE Mask */ 1160 1161 /**@} end of group CSI2_VFIFO_AHBM_ADDR_RANGE_Register */ 1162 1163 /** 1164 * @ingroup csi2_registers 1165 * @defgroup CSI2_VFIFO_AHBM_MAX_TRANS CSI2_VFIFO_AHBM_MAX_TRANS 1166 * @brief Video FIFO AHB Master Maximal Transfer Number Register. 1167 * @{ 1168 */ 1169 #define MXC_F_CSI2_VFIFO_AHBM_MAX_TRANS_AHBM_MAX_TRANS_POS 0 /**< VFIFO_AHBM_MAX_TRANS_AHBM_MAX_TRANS Position */ 1170 #define MXC_F_CSI2_VFIFO_AHBM_MAX_TRANS_AHBM_MAX_TRANS ((uint32_t)(0xFFFFFFFFUL << MXC_F_CSI2_VFIFO_AHBM_MAX_TRANS_AHBM_MAX_TRANS_POS)) /**< VFIFO_AHBM_MAX_TRANS_AHBM_MAX_TRANS Mask */ 1171 1172 /**@} end of group CSI2_VFIFO_AHBM_MAX_TRANS_Register */ 1173 1174 /** 1175 * @ingroup csi2_registers 1176 * @defgroup CSI2_VFIFO_AHBM_TRANS_CNT CSI2_VFIFO_AHBM_TRANS_CNT 1177 * @brief Video FIFO AHB Master Transfer Count Register. 1178 * @{ 1179 */ 1180 #define MXC_F_CSI2_VFIFO_AHBM_TRANS_CNT_AHBM_TRANS_CNT_POS 0 /**< VFIFO_AHBM_TRANS_CNT_AHBM_TRANS_CNT Position */ 1181 #define MXC_F_CSI2_VFIFO_AHBM_TRANS_CNT_AHBM_TRANS_CNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_CSI2_VFIFO_AHBM_TRANS_CNT_AHBM_TRANS_CNT_POS)) /**< VFIFO_AHBM_TRANS_CNT_AHBM_TRANS_CNT Mask */ 1182 1183 /**@} end of group CSI2_VFIFO_AHBM_TRANS_CNT_Register */ 1184 1185 /** 1186 * @ingroup csi2_registers 1187 * @defgroup CSI2_RX_EINT_VFF_IE CSI2_RX_EINT_VFF_IE 1188 * @brief RX Video FIFO Interrupt Enable Register. 1189 * @{ 1190 */ 1191 #define MXC_F_CSI2_RX_EINT_VFF_IE_FNEMPTY_POS 0 /**< RX_EINT_VFF_IE_FNEMPTY Position */ 1192 #define MXC_F_CSI2_RX_EINT_VFF_IE_FNEMPTY ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IE_FNEMPTY_POS)) /**< RX_EINT_VFF_IE_FNEMPTY Mask */ 1193 1194 #define MXC_F_CSI2_RX_EINT_VFF_IE_FTHD_POS 1 /**< RX_EINT_VFF_IE_FTHD Position */ 1195 #define MXC_F_CSI2_RX_EINT_VFF_IE_FTHD ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IE_FTHD_POS)) /**< RX_EINT_VFF_IE_FTHD Mask */ 1196 1197 #define MXC_F_CSI2_RX_EINT_VFF_IE_FFULL_POS 2 /**< RX_EINT_VFF_IE_FFULL Position */ 1198 #define MXC_F_CSI2_RX_EINT_VFF_IE_FFULL ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IE_FFULL_POS)) /**< RX_EINT_VFF_IE_FFULL Mask */ 1199 1200 #define MXC_F_CSI2_RX_EINT_VFF_IE_UNDERRUN_POS 3 /**< RX_EINT_VFF_IE_UNDERRUN Position */ 1201 #define MXC_F_CSI2_RX_EINT_VFF_IE_UNDERRUN ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IE_UNDERRUN_POS)) /**< RX_EINT_VFF_IE_UNDERRUN Mask */ 1202 1203 #define MXC_F_CSI2_RX_EINT_VFF_IE_OVERRUN_POS 4 /**< RX_EINT_VFF_IE_OVERRUN Position */ 1204 #define MXC_F_CSI2_RX_EINT_VFF_IE_OVERRUN ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IE_OVERRUN_POS)) /**< RX_EINT_VFF_IE_OVERRUN Mask */ 1205 1206 #define MXC_F_CSI2_RX_EINT_VFF_IE_OUTSYNC_POS 5 /**< RX_EINT_VFF_IE_OUTSYNC Position */ 1207 #define MXC_F_CSI2_RX_EINT_VFF_IE_OUTSYNC ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IE_OUTSYNC_POS)) /**< RX_EINT_VFF_IE_OUTSYNC Mask */ 1208 1209 #define MXC_F_CSI2_RX_EINT_VFF_IE_FMTERR_POS 6 /**< RX_EINT_VFF_IE_FMTERR Position */ 1210 #define MXC_F_CSI2_RX_EINT_VFF_IE_FMTERR ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IE_FMTERR_POS)) /**< RX_EINT_VFF_IE_FMTERR Mask */ 1211 1212 #define MXC_F_CSI2_RX_EINT_VFF_IE_AHBWTO_POS 7 /**< RX_EINT_VFF_IE_AHBWTO Position */ 1213 #define MXC_F_CSI2_RX_EINT_VFF_IE_AHBWTO ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IE_AHBWTO_POS)) /**< RX_EINT_VFF_IE_AHBWTO Mask */ 1214 1215 #define MXC_F_CSI2_RX_EINT_VFF_IE_FS_POS 8 /**< RX_EINT_VFF_IE_FS Position */ 1216 #define MXC_F_CSI2_RX_EINT_VFF_IE_FS ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IE_FS_POS)) /**< RX_EINT_VFF_IE_FS Mask */ 1217 1218 #define MXC_F_CSI2_RX_EINT_VFF_IE_FE_POS 9 /**< RX_EINT_VFF_IE_FE Position */ 1219 #define MXC_F_CSI2_RX_EINT_VFF_IE_FE ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IE_FE_POS)) /**< RX_EINT_VFF_IE_FE Mask */ 1220 1221 #define MXC_F_CSI2_RX_EINT_VFF_IE_LS_POS 10 /**< RX_EINT_VFF_IE_LS Position */ 1222 #define MXC_F_CSI2_RX_EINT_VFF_IE_LS ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IE_LS_POS)) /**< RX_EINT_VFF_IE_LS Mask */ 1223 1224 #define MXC_F_CSI2_RX_EINT_VFF_IE_LE_POS 11 /**< RX_EINT_VFF_IE_LE Position */ 1225 #define MXC_F_CSI2_RX_EINT_VFF_IE_LE ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IE_LE_POS)) /**< RX_EINT_VFF_IE_LE Mask */ 1226 1227 #define MXC_F_CSI2_RX_EINT_VFF_IE_RAW_OVR_POS 12 /**< RX_EINT_VFF_IE_RAW_OVR Position */ 1228 #define MXC_F_CSI2_RX_EINT_VFF_IE_RAW_OVR ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IE_RAW_OVR_POS)) /**< RX_EINT_VFF_IE_RAW_OVR Mask */ 1229 1230 #define MXC_F_CSI2_RX_EINT_VFF_IE_RAW_AHBERR_POS 13 /**< RX_EINT_VFF_IE_RAW_AHBERR Position */ 1231 #define MXC_F_CSI2_RX_EINT_VFF_IE_RAW_AHBERR ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IE_RAW_AHBERR_POS)) /**< RX_EINT_VFF_IE_RAW_AHBERR Mask */ 1232 1233 #define MXC_F_CSI2_RX_EINT_VFF_IE_FNEMP_MD_POS 16 /**< RX_EINT_VFF_IE_FNEMP_MD Position */ 1234 #define MXC_F_CSI2_RX_EINT_VFF_IE_FNEMP_MD ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IE_FNEMP_MD_POS)) /**< RX_EINT_VFF_IE_FNEMP_MD Mask */ 1235 1236 #define MXC_F_CSI2_RX_EINT_VFF_IE_FTHD_MD_POS 17 /**< RX_EINT_VFF_IE_FTHD_MD Position */ 1237 #define MXC_F_CSI2_RX_EINT_VFF_IE_FTHD_MD ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IE_FTHD_MD_POS)) /**< RX_EINT_VFF_IE_FTHD_MD Mask */ 1238 1239 #define MXC_F_CSI2_RX_EINT_VFF_IE_FFUL_MD_POS 18 /**< RX_EINT_VFF_IE_FFUL_MD Position */ 1240 #define MXC_F_CSI2_RX_EINT_VFF_IE_FFUL_MD ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IE_FFUL_MD_POS)) /**< RX_EINT_VFF_IE_FFUL_MD Mask */ 1241 1242 #define MXC_F_CSI2_RX_EINT_VFF_IE_AHBM_RDTO_POS 24 /**< RX_EINT_VFF_IE_AHBM_RDTO Position */ 1243 #define MXC_F_CSI2_RX_EINT_VFF_IE_AHBM_RDTO ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IE_AHBM_RDTO_POS)) /**< RX_EINT_VFF_IE_AHBM_RDTO Mask */ 1244 1245 #define MXC_F_CSI2_RX_EINT_VFF_IE_AHBM_IDTO_POS 25 /**< RX_EINT_VFF_IE_AHBM_IDTO Position */ 1246 #define MXC_F_CSI2_RX_EINT_VFF_IE_AHBM_IDTO ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IE_AHBM_IDTO_POS)) /**< RX_EINT_VFF_IE_AHBM_IDTO Mask */ 1247 1248 #define MXC_F_CSI2_RX_EINT_VFF_IE_AHBM_MAX_POS 26 /**< RX_EINT_VFF_IE_AHBM_MAX Position */ 1249 #define MXC_F_CSI2_RX_EINT_VFF_IE_AHBM_MAX ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IE_AHBM_MAX_POS)) /**< RX_EINT_VFF_IE_AHBM_MAX Mask */ 1250 1251 /**@} end of group CSI2_RX_EINT_VFF_IE_Register */ 1252 1253 /** 1254 * @ingroup csi2_registers 1255 * @defgroup CSI2_RX_EINT_VFF_IF CSI2_RX_EINT_VFF_IF 1256 * @brief RX Video FIFO Interrupt Flag Register. 1257 * @{ 1258 */ 1259 #define MXC_F_CSI2_RX_EINT_VFF_IF_FNEMPTY_POS 0 /**< RX_EINT_VFF_IF_FNEMPTY Position */ 1260 #define MXC_F_CSI2_RX_EINT_VFF_IF_FNEMPTY ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IF_FNEMPTY_POS)) /**< RX_EINT_VFF_IF_FNEMPTY Mask */ 1261 1262 #define MXC_F_CSI2_RX_EINT_VFF_IF_FTHD_POS 1 /**< RX_EINT_VFF_IF_FTHD Position */ 1263 #define MXC_F_CSI2_RX_EINT_VFF_IF_FTHD ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IF_FTHD_POS)) /**< RX_EINT_VFF_IF_FTHD Mask */ 1264 1265 #define MXC_F_CSI2_RX_EINT_VFF_IF_FFULL_POS 2 /**< RX_EINT_VFF_IF_FFULL Position */ 1266 #define MXC_F_CSI2_RX_EINT_VFF_IF_FFULL ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IF_FFULL_POS)) /**< RX_EINT_VFF_IF_FFULL Mask */ 1267 1268 #define MXC_F_CSI2_RX_EINT_VFF_IF_UNDERRUN_POS 3 /**< RX_EINT_VFF_IF_UNDERRUN Position */ 1269 #define MXC_F_CSI2_RX_EINT_VFF_IF_UNDERRUN ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IF_UNDERRUN_POS)) /**< RX_EINT_VFF_IF_UNDERRUN Mask */ 1270 1271 #define MXC_F_CSI2_RX_EINT_VFF_IF_OVERRUN_POS 4 /**< RX_EINT_VFF_IF_OVERRUN Position */ 1272 #define MXC_F_CSI2_RX_EINT_VFF_IF_OVERRUN ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IF_OVERRUN_POS)) /**< RX_EINT_VFF_IF_OVERRUN Mask */ 1273 1274 #define MXC_F_CSI2_RX_EINT_VFF_IF_OUTSYNC_POS 5 /**< RX_EINT_VFF_IF_OUTSYNC Position */ 1275 #define MXC_F_CSI2_RX_EINT_VFF_IF_OUTSYNC ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IF_OUTSYNC_POS)) /**< RX_EINT_VFF_IF_OUTSYNC Mask */ 1276 1277 #define MXC_F_CSI2_RX_EINT_VFF_IF_FMTERR_POS 6 /**< RX_EINT_VFF_IF_FMTERR Position */ 1278 #define MXC_F_CSI2_RX_EINT_VFF_IF_FMTERR ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IF_FMTERR_POS)) /**< RX_EINT_VFF_IF_FMTERR Mask */ 1279 1280 #define MXC_F_CSI2_RX_EINT_VFF_IF_AHBWTO_POS 7 /**< RX_EINT_VFF_IF_AHBWTO Position */ 1281 #define MXC_F_CSI2_RX_EINT_VFF_IF_AHBWTO ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IF_AHBWTO_POS)) /**< RX_EINT_VFF_IF_AHBWTO Mask */ 1282 1283 #define MXC_F_CSI2_RX_EINT_VFF_IF_FS_POS 8 /**< RX_EINT_VFF_IF_FS Position */ 1284 #define MXC_F_CSI2_RX_EINT_VFF_IF_FS ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IF_FS_POS)) /**< RX_EINT_VFF_IF_FS Mask */ 1285 1286 #define MXC_F_CSI2_RX_EINT_VFF_IF_FE_POS 9 /**< RX_EINT_VFF_IF_FE Position */ 1287 #define MXC_F_CSI2_RX_EINT_VFF_IF_FE ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IF_FE_POS)) /**< RX_EINT_VFF_IF_FE Mask */ 1288 1289 #define MXC_F_CSI2_RX_EINT_VFF_IF_LS_POS 10 /**< RX_EINT_VFF_IF_LS Position */ 1290 #define MXC_F_CSI2_RX_EINT_VFF_IF_LS ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IF_LS_POS)) /**< RX_EINT_VFF_IF_LS Mask */ 1291 1292 #define MXC_F_CSI2_RX_EINT_VFF_IF_LE_POS 11 /**< RX_EINT_VFF_IF_LE Position */ 1293 #define MXC_F_CSI2_RX_EINT_VFF_IF_LE ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IF_LE_POS)) /**< RX_EINT_VFF_IF_LE Mask */ 1294 1295 #define MXC_F_CSI2_RX_EINT_VFF_IF_RAW_OVR_POS 12 /**< RX_EINT_VFF_IF_RAW_OVR Position */ 1296 #define MXC_F_CSI2_RX_EINT_VFF_IF_RAW_OVR ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IF_RAW_OVR_POS)) /**< RX_EINT_VFF_IF_RAW_OVR Mask */ 1297 1298 #define MXC_F_CSI2_RX_EINT_VFF_IF_RAW_AHBERR_POS 13 /**< RX_EINT_VFF_IF_RAW_AHBERR Position */ 1299 #define MXC_F_CSI2_RX_EINT_VFF_IF_RAW_AHBERR ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IF_RAW_AHBERR_POS)) /**< RX_EINT_VFF_IF_RAW_AHBERR Mask */ 1300 1301 #define MXC_F_CSI2_RX_EINT_VFF_IF_AHBM_RDTO_POS 24 /**< RX_EINT_VFF_IF_AHBM_RDTO Position */ 1302 #define MXC_F_CSI2_RX_EINT_VFF_IF_AHBM_RDTO ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IF_AHBM_RDTO_POS)) /**< RX_EINT_VFF_IF_AHBM_RDTO Mask */ 1303 1304 #define MXC_F_CSI2_RX_EINT_VFF_IF_AHBM_IDTO_POS 25 /**< RX_EINT_VFF_IF_AHBM_IDTO Position */ 1305 #define MXC_F_CSI2_RX_EINT_VFF_IF_AHBM_IDTO ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IF_AHBM_IDTO_POS)) /**< RX_EINT_VFF_IF_AHBM_IDTO Mask */ 1306 1307 #define MXC_F_CSI2_RX_EINT_VFF_IF_AHBM_MAX_POS 26 /**< RX_EINT_VFF_IF_AHBM_MAX Position */ 1308 #define MXC_F_CSI2_RX_EINT_VFF_IF_AHBM_MAX ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_VFF_IF_AHBM_MAX_POS)) /**< RX_EINT_VFF_IF_AHBM_MAX Mask */ 1309 1310 /**@} end of group CSI2_RX_EINT_VFF_IF_Register */ 1311 1312 /** 1313 * @ingroup csi2_registers 1314 * @defgroup CSI2_RX_EINT_PPI_IE CSI2_RX_EINT_PPI_IE 1315 * @brief RX D-PHY Interrupt Enable Register. 1316 * @{ 1317 */ 1318 #define MXC_F_CSI2_RX_EINT_PPI_IE_DL0STOP_POS 0 /**< RX_EINT_PPI_IE_DL0STOP Position */ 1319 #define MXC_F_CSI2_RX_EINT_PPI_IE_DL0STOP ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IE_DL0STOP_POS)) /**< RX_EINT_PPI_IE_DL0STOP Mask */ 1320 1321 #define MXC_F_CSI2_RX_EINT_PPI_IE_DL1STOP_POS 1 /**< RX_EINT_PPI_IE_DL1STOP Position */ 1322 #define MXC_F_CSI2_RX_EINT_PPI_IE_DL1STOP ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IE_DL1STOP_POS)) /**< RX_EINT_PPI_IE_DL1STOP Mask */ 1323 1324 #define MXC_F_CSI2_RX_EINT_PPI_IE_CL0STOP_POS 4 /**< RX_EINT_PPI_IE_CL0STOP Position */ 1325 #define MXC_F_CSI2_RX_EINT_PPI_IE_CL0STOP ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IE_CL0STOP_POS)) /**< RX_EINT_PPI_IE_CL0STOP Mask */ 1326 1327 #define MXC_F_CSI2_RX_EINT_PPI_IE_DL0ECONT0_POS 6 /**< RX_EINT_PPI_IE_DL0ECONT0 Position */ 1328 #define MXC_F_CSI2_RX_EINT_PPI_IE_DL0ECONT0 ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IE_DL0ECONT0_POS)) /**< RX_EINT_PPI_IE_DL0ECONT0 Mask */ 1329 1330 #define MXC_F_CSI2_RX_EINT_PPI_IE_DL0ECONT1_POS 7 /**< RX_EINT_PPI_IE_DL0ECONT1 Position */ 1331 #define MXC_F_CSI2_RX_EINT_PPI_IE_DL0ECONT1 ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IE_DL0ECONT1_POS)) /**< RX_EINT_PPI_IE_DL0ECONT1 Mask */ 1332 1333 #define MXC_F_CSI2_RX_EINT_PPI_IE_DL0ESOT_POS 8 /**< RX_EINT_PPI_IE_DL0ESOT Position */ 1334 #define MXC_F_CSI2_RX_EINT_PPI_IE_DL0ESOT ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IE_DL0ESOT_POS)) /**< RX_EINT_PPI_IE_DL0ESOT Mask */ 1335 1336 #define MXC_F_CSI2_RX_EINT_PPI_IE_DL1ESOT_POS 9 /**< RX_EINT_PPI_IE_DL1ESOT Position */ 1337 #define MXC_F_CSI2_RX_EINT_PPI_IE_DL1ESOT ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IE_DL1ESOT_POS)) /**< RX_EINT_PPI_IE_DL1ESOT Mask */ 1338 1339 #define MXC_F_CSI2_RX_EINT_PPI_IE_DL0ESOTS_POS 12 /**< RX_EINT_PPI_IE_DL0ESOTS Position */ 1340 #define MXC_F_CSI2_RX_EINT_PPI_IE_DL0ESOTS ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IE_DL0ESOTS_POS)) /**< RX_EINT_PPI_IE_DL0ESOTS Mask */ 1341 1342 #define MXC_F_CSI2_RX_EINT_PPI_IE_DL1ESOTS_POS 13 /**< RX_EINT_PPI_IE_DL1ESOTS Position */ 1343 #define MXC_F_CSI2_RX_EINT_PPI_IE_DL1ESOTS ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IE_DL1ESOTS_POS)) /**< RX_EINT_PPI_IE_DL1ESOTS Mask */ 1344 1345 #define MXC_F_CSI2_RX_EINT_PPI_IE_DL0EESC_POS 16 /**< RX_EINT_PPI_IE_DL0EESC Position */ 1346 #define MXC_F_CSI2_RX_EINT_PPI_IE_DL0EESC ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IE_DL0EESC_POS)) /**< RX_EINT_PPI_IE_DL0EESC Mask */ 1347 1348 #define MXC_F_CSI2_RX_EINT_PPI_IE_DL1EESC_POS 17 /**< RX_EINT_PPI_IE_DL1EESC Position */ 1349 #define MXC_F_CSI2_RX_EINT_PPI_IE_DL1EESC ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IE_DL1EESC_POS)) /**< RX_EINT_PPI_IE_DL1EESC Mask */ 1350 1351 #define MXC_F_CSI2_RX_EINT_PPI_IE_DL0ESESC_POS 20 /**< RX_EINT_PPI_IE_DL0ESESC Position */ 1352 #define MXC_F_CSI2_RX_EINT_PPI_IE_DL0ESESC ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IE_DL0ESESC_POS)) /**< RX_EINT_PPI_IE_DL0ESESC Mask */ 1353 1354 #define MXC_F_CSI2_RX_EINT_PPI_IE_DL1ESESC_POS 21 /**< RX_EINT_PPI_IE_DL1ESESC Position */ 1355 #define MXC_F_CSI2_RX_EINT_PPI_IE_DL1ESESC ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IE_DL1ESESC_POS)) /**< RX_EINT_PPI_IE_DL1ESESC Mask */ 1356 1357 #define MXC_F_CSI2_RX_EINT_PPI_IE_DL0ECTL_POS 24 /**< RX_EINT_PPI_IE_DL0ECTL Position */ 1358 #define MXC_F_CSI2_RX_EINT_PPI_IE_DL0ECTL ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IE_DL0ECTL_POS)) /**< RX_EINT_PPI_IE_DL0ECTL Mask */ 1359 1360 #define MXC_F_CSI2_RX_EINT_PPI_IE_DL1ECTL_POS 25 /**< RX_EINT_PPI_IE_DL1ECTL Position */ 1361 #define MXC_F_CSI2_RX_EINT_PPI_IE_DL1ECTL ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IE_DL1ECTL_POS)) /**< RX_EINT_PPI_IE_DL1ECTL Mask */ 1362 1363 /**@} end of group CSI2_RX_EINT_PPI_IE_Register */ 1364 1365 /** 1366 * @ingroup csi2_registers 1367 * @defgroup CSI2_RX_EINT_PPI_IF CSI2_RX_EINT_PPI_IF 1368 * @brief RX D-PHY Interrupt Flag Register. 1369 * @{ 1370 */ 1371 #define MXC_F_CSI2_RX_EINT_PPI_IF_DL0STOP_POS 0 /**< RX_EINT_PPI_IF_DL0STOP Position */ 1372 #define MXC_F_CSI2_RX_EINT_PPI_IF_DL0STOP ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IF_DL0STOP_POS)) /**< RX_EINT_PPI_IF_DL0STOP Mask */ 1373 1374 #define MXC_F_CSI2_RX_EINT_PPI_IF_DL1STOP_POS 1 /**< RX_EINT_PPI_IF_DL1STOP Position */ 1375 #define MXC_F_CSI2_RX_EINT_PPI_IF_DL1STOP ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IF_DL1STOP_POS)) /**< RX_EINT_PPI_IF_DL1STOP Mask */ 1376 1377 #define MXC_F_CSI2_RX_EINT_PPI_IF_CL0STOP_POS 4 /**< RX_EINT_PPI_IF_CL0STOP Position */ 1378 #define MXC_F_CSI2_RX_EINT_PPI_IF_CL0STOP ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IF_CL0STOP_POS)) /**< RX_EINT_PPI_IF_CL0STOP Mask */ 1379 1380 #define MXC_F_CSI2_RX_EINT_PPI_IF_DL0ECONT0_POS 6 /**< RX_EINT_PPI_IF_DL0ECONT0 Position */ 1381 #define MXC_F_CSI2_RX_EINT_PPI_IF_DL0ECONT0 ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IF_DL0ECONT0_POS)) /**< RX_EINT_PPI_IF_DL0ECONT0 Mask */ 1382 1383 #define MXC_F_CSI2_RX_EINT_PPI_IF_DL0ECONT1_POS 7 /**< RX_EINT_PPI_IF_DL0ECONT1 Position */ 1384 #define MXC_F_CSI2_RX_EINT_PPI_IF_DL0ECONT1 ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IF_DL0ECONT1_POS)) /**< RX_EINT_PPI_IF_DL0ECONT1 Mask */ 1385 1386 #define MXC_F_CSI2_RX_EINT_PPI_IF_DL0ESOT_POS 8 /**< RX_EINT_PPI_IF_DL0ESOT Position */ 1387 #define MXC_F_CSI2_RX_EINT_PPI_IF_DL0ESOT ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IF_DL0ESOT_POS)) /**< RX_EINT_PPI_IF_DL0ESOT Mask */ 1388 1389 #define MXC_F_CSI2_RX_EINT_PPI_IF_DL1ESOT_POS 9 /**< RX_EINT_PPI_IF_DL1ESOT Position */ 1390 #define MXC_F_CSI2_RX_EINT_PPI_IF_DL1ESOT ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IF_DL1ESOT_POS)) /**< RX_EINT_PPI_IF_DL1ESOT Mask */ 1391 1392 #define MXC_F_CSI2_RX_EINT_PPI_IF_DL0ESOTS_POS 12 /**< RX_EINT_PPI_IF_DL0ESOTS Position */ 1393 #define MXC_F_CSI2_RX_EINT_PPI_IF_DL0ESOTS ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IF_DL0ESOTS_POS)) /**< RX_EINT_PPI_IF_DL0ESOTS Mask */ 1394 1395 #define MXC_F_CSI2_RX_EINT_PPI_IF_DL1ESOTS_POS 13 /**< RX_EINT_PPI_IF_DL1ESOTS Position */ 1396 #define MXC_F_CSI2_RX_EINT_PPI_IF_DL1ESOTS ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IF_DL1ESOTS_POS)) /**< RX_EINT_PPI_IF_DL1ESOTS Mask */ 1397 1398 #define MXC_F_CSI2_RX_EINT_PPI_IF_DL0EESC_POS 16 /**< RX_EINT_PPI_IF_DL0EESC Position */ 1399 #define MXC_F_CSI2_RX_EINT_PPI_IF_DL0EESC ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IF_DL0EESC_POS)) /**< RX_EINT_PPI_IF_DL0EESC Mask */ 1400 1401 #define MXC_F_CSI2_RX_EINT_PPI_IF_DL1EESC_POS 17 /**< RX_EINT_PPI_IF_DL1EESC Position */ 1402 #define MXC_F_CSI2_RX_EINT_PPI_IF_DL1EESC ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IF_DL1EESC_POS)) /**< RX_EINT_PPI_IF_DL1EESC Mask */ 1403 1404 #define MXC_F_CSI2_RX_EINT_PPI_IF_DL0ESESC_POS 20 /**< RX_EINT_PPI_IF_DL0ESESC Position */ 1405 #define MXC_F_CSI2_RX_EINT_PPI_IF_DL0ESESC ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IF_DL0ESESC_POS)) /**< RX_EINT_PPI_IF_DL0ESESC Mask */ 1406 1407 #define MXC_F_CSI2_RX_EINT_PPI_IF_DL1ESESC_POS 21 /**< RX_EINT_PPI_IF_DL1ESESC Position */ 1408 #define MXC_F_CSI2_RX_EINT_PPI_IF_DL1ESESC ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IF_DL1ESESC_POS)) /**< RX_EINT_PPI_IF_DL1ESESC Mask */ 1409 1410 #define MXC_F_CSI2_RX_EINT_PPI_IF_DL0ECTL_POS 24 /**< RX_EINT_PPI_IF_DL0ECTL Position */ 1411 #define MXC_F_CSI2_RX_EINT_PPI_IF_DL0ECTL ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IF_DL0ECTL_POS)) /**< RX_EINT_PPI_IF_DL0ECTL Mask */ 1412 1413 #define MXC_F_CSI2_RX_EINT_PPI_IF_DL1ECTL_POS 25 /**< RX_EINT_PPI_IF_DL1ECTL Position */ 1414 #define MXC_F_CSI2_RX_EINT_PPI_IF_DL1ECTL ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_PPI_IF_DL1ECTL_POS)) /**< RX_EINT_PPI_IF_DL1ECTL Mask */ 1415 1416 /**@} end of group CSI2_RX_EINT_PPI_IF_Register */ 1417 1418 /** 1419 * @ingroup csi2_registers 1420 * @defgroup CSI2_RX_EINT_CTRL_IE CSI2_RX_EINT_CTRL_IE 1421 * @brief RX Controller Interrupt Enable Register. 1422 * @{ 1423 */ 1424 #define MXC_F_CSI2_RX_EINT_CTRL_IE_EECC2_POS 0 /**< RX_EINT_CTRL_IE_EECC2 Position */ 1425 #define MXC_F_CSI2_RX_EINT_CTRL_IE_EECC2 ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IE_EECC2_POS)) /**< RX_EINT_CTRL_IE_EECC2 Mask */ 1426 1427 #define MXC_F_CSI2_RX_EINT_CTRL_IE_EECC1_POS 1 /**< RX_EINT_CTRL_IE_EECC1 Position */ 1428 #define MXC_F_CSI2_RX_EINT_CTRL_IE_EECC1 ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IE_EECC1_POS)) /**< RX_EINT_CTRL_IE_EECC1 Mask */ 1429 1430 #define MXC_F_CSI2_RX_EINT_CTRL_IE_ECRC_POS 2 /**< RX_EINT_CTRL_IE_ECRC Position */ 1431 #define MXC_F_CSI2_RX_EINT_CTRL_IE_ECRC ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IE_ECRC_POS)) /**< RX_EINT_CTRL_IE_ECRC Mask */ 1432 1433 #define MXC_F_CSI2_RX_EINT_CTRL_IE_EID_POS 3 /**< RX_EINT_CTRL_IE_EID Position */ 1434 #define MXC_F_CSI2_RX_EINT_CTRL_IE_EID ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IE_EID_POS)) /**< RX_EINT_CTRL_IE_EID Mask */ 1435 1436 #define MXC_F_CSI2_RX_EINT_CTRL_IE_PKTFFOV_POS 4 /**< RX_EINT_CTRL_IE_PKTFFOV Position */ 1437 #define MXC_F_CSI2_RX_EINT_CTRL_IE_PKTFFOV ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IE_PKTFFOV_POS)) /**< RX_EINT_CTRL_IE_PKTFFOV Mask */ 1438 1439 #define MXC_F_CSI2_RX_EINT_CTRL_IE_DL0ULPSA_POS 8 /**< RX_EINT_CTRL_IE_DL0ULPSA Position */ 1440 #define MXC_F_CSI2_RX_EINT_CTRL_IE_DL0ULPSA ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IE_DL0ULPSA_POS)) /**< RX_EINT_CTRL_IE_DL0ULPSA Mask */ 1441 1442 #define MXC_F_CSI2_RX_EINT_CTRL_IE_DL1ULPSA_POS 9 /**< RX_EINT_CTRL_IE_DL1ULPSA Position */ 1443 #define MXC_F_CSI2_RX_EINT_CTRL_IE_DL1ULPSA ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IE_DL1ULPSA_POS)) /**< RX_EINT_CTRL_IE_DL1ULPSA Mask */ 1444 1445 #define MXC_F_CSI2_RX_EINT_CTRL_IE_DL0ULPSM_POS 12 /**< RX_EINT_CTRL_IE_DL0ULPSM Position */ 1446 #define MXC_F_CSI2_RX_EINT_CTRL_IE_DL0ULPSM ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IE_DL0ULPSM_POS)) /**< RX_EINT_CTRL_IE_DL0ULPSM Mask */ 1447 1448 #define MXC_F_CSI2_RX_EINT_CTRL_IE_DL1ULPSM_POS 13 /**< RX_EINT_CTRL_IE_DL1ULPSM Position */ 1449 #define MXC_F_CSI2_RX_EINT_CTRL_IE_DL1ULPSM ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IE_DL1ULPSM_POS)) /**< RX_EINT_CTRL_IE_DL1ULPSM Mask */ 1450 1451 #define MXC_F_CSI2_RX_EINT_CTRL_IE_CL0ULPSA_POS 16 /**< RX_EINT_CTRL_IE_CL0ULPSA Position */ 1452 #define MXC_F_CSI2_RX_EINT_CTRL_IE_CL0ULPSA ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IE_CL0ULPSA_POS)) /**< RX_EINT_CTRL_IE_CL0ULPSA Mask */ 1453 1454 #define MXC_F_CSI2_RX_EINT_CTRL_IE_CL0ULPSM_POS 17 /**< RX_EINT_CTRL_IE_CL0ULPSM Position */ 1455 #define MXC_F_CSI2_RX_EINT_CTRL_IE_CL0ULPSM ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IE_CL0ULPSM_POS)) /**< RX_EINT_CTRL_IE_CL0ULPSM Mask */ 1456 1457 /**@} end of group CSI2_RX_EINT_CTRL_IE_Register */ 1458 1459 /** 1460 * @ingroup csi2_registers 1461 * @defgroup CSI2_RX_EINT_CTRL_IF CSI2_RX_EINT_CTRL_IF 1462 * @brief RX Controller Interrupt Flag Register. 1463 * @{ 1464 */ 1465 #define MXC_F_CSI2_RX_EINT_CTRL_IF_EECC2_POS 0 /**< RX_EINT_CTRL_IF_EECC2 Position */ 1466 #define MXC_F_CSI2_RX_EINT_CTRL_IF_EECC2 ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IF_EECC2_POS)) /**< RX_EINT_CTRL_IF_EECC2 Mask */ 1467 1468 #define MXC_F_CSI2_RX_EINT_CTRL_IF_EECC1_POS 1 /**< RX_EINT_CTRL_IF_EECC1 Position */ 1469 #define MXC_F_CSI2_RX_EINT_CTRL_IF_EECC1 ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IF_EECC1_POS)) /**< RX_EINT_CTRL_IF_EECC1 Mask */ 1470 1471 #define MXC_F_CSI2_RX_EINT_CTRL_IF_ECRC_POS 2 /**< RX_EINT_CTRL_IF_ECRC Position */ 1472 #define MXC_F_CSI2_RX_EINT_CTRL_IF_ECRC ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IF_ECRC_POS)) /**< RX_EINT_CTRL_IF_ECRC Mask */ 1473 1474 #define MXC_F_CSI2_RX_EINT_CTRL_IF_EID_POS 3 /**< RX_EINT_CTRL_IF_EID Position */ 1475 #define MXC_F_CSI2_RX_EINT_CTRL_IF_EID ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IF_EID_POS)) /**< RX_EINT_CTRL_IF_EID Mask */ 1476 1477 #define MXC_F_CSI2_RX_EINT_CTRL_IF_PKTFFOV_POS 4 /**< RX_EINT_CTRL_IF_PKTFFOV Position */ 1478 #define MXC_F_CSI2_RX_EINT_CTRL_IF_PKTFFOV ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IF_PKTFFOV_POS)) /**< RX_EINT_CTRL_IF_PKTFFOV Mask */ 1479 1480 #define MXC_F_CSI2_RX_EINT_CTRL_IF_DL0ULPSA_POS 8 /**< RX_EINT_CTRL_IF_DL0ULPSA Position */ 1481 #define MXC_F_CSI2_RX_EINT_CTRL_IF_DL0ULPSA ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IF_DL0ULPSA_POS)) /**< RX_EINT_CTRL_IF_DL0ULPSA Mask */ 1482 1483 #define MXC_F_CSI2_RX_EINT_CTRL_IF_DL1ULPSA_POS 9 /**< RX_EINT_CTRL_IF_DL1ULPSA Position */ 1484 #define MXC_F_CSI2_RX_EINT_CTRL_IF_DL1ULPSA ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IF_DL1ULPSA_POS)) /**< RX_EINT_CTRL_IF_DL1ULPSA Mask */ 1485 1486 #define MXC_F_CSI2_RX_EINT_CTRL_IF_DL0ULPSM_POS 12 /**< RX_EINT_CTRL_IF_DL0ULPSM Position */ 1487 #define MXC_F_CSI2_RX_EINT_CTRL_IF_DL0ULPSM ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IF_DL0ULPSM_POS)) /**< RX_EINT_CTRL_IF_DL0ULPSM Mask */ 1488 1489 #define MXC_F_CSI2_RX_EINT_CTRL_IF_DL1ULPSM_POS 13 /**< RX_EINT_CTRL_IF_DL1ULPSM Position */ 1490 #define MXC_F_CSI2_RX_EINT_CTRL_IF_DL1ULPSM ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IF_DL1ULPSM_POS)) /**< RX_EINT_CTRL_IF_DL1ULPSM Mask */ 1491 1492 #define MXC_F_CSI2_RX_EINT_CTRL_IF_CL0ULPSA_POS 16 /**< RX_EINT_CTRL_IF_CL0ULPSA Position */ 1493 #define MXC_F_CSI2_RX_EINT_CTRL_IF_CL0ULPSA ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IF_CL0ULPSA_POS)) /**< RX_EINT_CTRL_IF_CL0ULPSA Mask */ 1494 1495 #define MXC_F_CSI2_RX_EINT_CTRL_IF_CL0ULPSM_POS 17 /**< RX_EINT_CTRL_IF_CL0ULPSM Position */ 1496 #define MXC_F_CSI2_RX_EINT_CTRL_IF_CL0ULPSM ((uint32_t)(0x1UL << MXC_F_CSI2_RX_EINT_CTRL_IF_CL0ULPSM_POS)) /**< RX_EINT_CTRL_IF_CL0ULPSM Mask */ 1497 1498 /**@} end of group CSI2_RX_EINT_CTRL_IF_Register */ 1499 1500 /** 1501 * @ingroup csi2_registers 1502 * @defgroup CSI2_PPI_STOPSTATE CSI2_PPI_STOPSTATE 1503 * @brief DPHY PPI Stop State Register. 1504 * @{ 1505 */ 1506 #define MXC_F_CSI2_PPI_STOPSTATE_DL0STOP_POS 0 /**< PPI_STOPSTATE_DL0STOP Position */ 1507 #define MXC_F_CSI2_PPI_STOPSTATE_DL0STOP ((uint32_t)(0x1UL << MXC_F_CSI2_PPI_STOPSTATE_DL0STOP_POS)) /**< PPI_STOPSTATE_DL0STOP Mask */ 1508 1509 #define MXC_F_CSI2_PPI_STOPSTATE_DL1STOP_POS 1 /**< PPI_STOPSTATE_DL1STOP Position */ 1510 #define MXC_F_CSI2_PPI_STOPSTATE_DL1STOP ((uint32_t)(0x1UL << MXC_F_CSI2_PPI_STOPSTATE_DL1STOP_POS)) /**< PPI_STOPSTATE_DL1STOP Mask */ 1511 1512 #define MXC_F_CSI2_PPI_STOPSTATE_CL0STOP_POS 2 /**< PPI_STOPSTATE_CL0STOP Position */ 1513 #define MXC_F_CSI2_PPI_STOPSTATE_CL0STOP ((uint32_t)(0x1UL << MXC_F_CSI2_PPI_STOPSTATE_CL0STOP_POS)) /**< PPI_STOPSTATE_CL0STOP Mask */ 1514 1515 /**@} end of group CSI2_PPI_STOPSTATE_Register */ 1516 1517 /** 1518 * @ingroup csi2_registers 1519 * @defgroup CSI2_PPI_TURNAROUND_CFG CSI2_PPI_TURNAROUND_CFG 1520 * @brief DPHY PPI Turn-Around Configuration Register. 1521 * @{ 1522 */ 1523 #define MXC_F_CSI2_PPI_TURNAROUND_CFG_DL0TAREQ_POS 0 /**< PPI_TURNAROUND_CFG_DL0TAREQ Position */ 1524 #define MXC_F_CSI2_PPI_TURNAROUND_CFG_DL0TAREQ ((uint32_t)(0x1UL << MXC_F_CSI2_PPI_TURNAROUND_CFG_DL0TAREQ_POS)) /**< PPI_TURNAROUND_CFG_DL0TAREQ Mask */ 1525 1526 #define MXC_F_CSI2_PPI_TURNAROUND_CFG_DL0TADIS_POS 1 /**< PPI_TURNAROUND_CFG_DL0TADIS Position */ 1527 #define MXC_F_CSI2_PPI_TURNAROUND_CFG_DL0TADIS ((uint32_t)(0x1UL << MXC_F_CSI2_PPI_TURNAROUND_CFG_DL0TADIS_POS)) /**< PPI_TURNAROUND_CFG_DL0TADIS Mask */ 1528 1529 #define MXC_F_CSI2_PPI_TURNAROUND_CFG_DL0FRCRX_POS 2 /**< PPI_TURNAROUND_CFG_DL0FRCRX Position */ 1530 #define MXC_F_CSI2_PPI_TURNAROUND_CFG_DL0FRCRX ((uint32_t)(0x1UL << MXC_F_CSI2_PPI_TURNAROUND_CFG_DL0FRCRX_POS)) /**< PPI_TURNAROUND_CFG_DL0FRCRX Mask */ 1531 1532 /**@} end of group CSI2_PPI_TURNAROUND_CFG_Register */ 1533 1534 #ifdef __cplusplus 1535 } 1536 #endif 1537 1538 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78002_INCLUDE_CSI2_REGS_H_ 1539
