1 /** 2 * @file adc_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the ADC Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup adc_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78002_INCLUDE_ADC_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78002_INCLUDE_ADC_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup adc 67 * @defgroup adc_registers ADC_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the ADC Peripheral Module. 69 * @details Inter-Integrated Circuit. 70 */ 71 72 /** 73 * @ingroup adc_registers 74 * Structure type to access the ADC Registers. 75 */ 76 typedef struct { 77 __IO uint32_t ctrl0; /**< <tt>\b 0x00:</tt> ADC CTRL0 Register */ 78 __IO uint32_t ctrl1; /**< <tt>\b 0x04:</tt> ADC CTRL1 Register */ 79 __IO uint32_t clkctrl; /**< <tt>\b 0x08:</tt> ADC CLKCTRL Register */ 80 __IO uint32_t sampclkctrl; /**< <tt>\b 0x0C:</tt> ADC SAMPCLKCTRL Register */ 81 __IO uint32_t chsel0; /**< <tt>\b 0x10:</tt> ADC CHSEL0 Register */ 82 __IO uint32_t chsel1; /**< <tt>\b 0x14:</tt> ADC CHSEL1 Register */ 83 __IO uint32_t chsel2; /**< <tt>\b 0x18:</tt> ADC CHSEL2 Register */ 84 __IO uint32_t chsel3; /**< <tt>\b 0x1C:</tt> ADC CHSEL3 Register */ 85 __IO uint32_t chsel4; /**< <tt>\b 0x20:</tt> ADC CHSEL4 Register */ 86 __IO uint32_t chsel5; /**< <tt>\b 0x24:</tt> ADC CHSEL5 Register */ 87 __IO uint32_t chsel6; /**< <tt>\b 0x28:</tt> ADC CHSEL6 Register */ 88 __IO uint32_t chsel7; /**< <tt>\b 0x2C:</tt> ADC CHSEL7 Register */ 89 __IO uint32_t restart; /**< <tt>\b 0x30:</tt> ADC RESTART Register */ 90 __R uint32_t rsv_0x34_0x3b[2]; 91 __IO uint32_t datafmt; /**< <tt>\b 0x3C:</tt> ADC DATAFMT Register */ 92 __IO uint32_t fifodmactrl; /**< <tt>\b 0x40:</tt> ADC FIFODMACTRL Register */ 93 __IO uint32_t data; /**< <tt>\b 0x44:</tt> ADC DATA Register */ 94 __IO uint32_t status; /**< <tt>\b 0x48:</tt> ADC STATUS Register */ 95 __IO uint32_t chstatus; /**< <tt>\b 0x4C:</tt> ADC CHSTATUS Register */ 96 __IO uint32_t inten; /**< <tt>\b 0x50:</tt> ADC INTEN Register */ 97 __IO uint32_t intfl; /**< <tt>\b 0x54:</tt> ADC INTFL Register */ 98 __R uint32_t rsv_0x58_0x5f[2]; 99 __IO uint32_t sfraddroffset; /**< <tt>\b 0x60:</tt> ADC SFRADDROFFSET Register */ 100 __IO uint32_t sfraddr; /**< <tt>\b 0x64:</tt> ADC SFRADDR Register */ 101 __IO uint32_t sfrwrdata; /**< <tt>\b 0x68:</tt> ADC SFRWRDATA Register */ 102 __IO uint32_t sfrrddata; /**< <tt>\b 0x6C:</tt> ADC SFRRDDATA Register */ 103 __IO uint32_t sfrstatus; /**< <tt>\b 0x70:</tt> ADC SFRSTATUS Register */ 104 } mxc_adc_regs_t; 105 106 /* Register offsets for module ADC */ 107 /** 108 * @ingroup adc_registers 109 * @defgroup ADC_Register_Offsets Register Offsets 110 * @brief ADC Peripheral Register Offsets from the ADC Base Peripheral Address. 111 * @{ 112 */ 113 #define MXC_R_ADC_CTRL0 ((uint32_t)0x00000000UL) /**< Offset from ADC Base Address: <tt> 0x0000</tt> */ 114 #define MXC_R_ADC_CTRL1 ((uint32_t)0x00000004UL) /**< Offset from ADC Base Address: <tt> 0x0004</tt> */ 115 #define MXC_R_ADC_CLKCTRL ((uint32_t)0x00000008UL) /**< Offset from ADC Base Address: <tt> 0x0008</tt> */ 116 #define MXC_R_ADC_SAMPCLKCTRL ((uint32_t)0x0000000CUL) /**< Offset from ADC Base Address: <tt> 0x000C</tt> */ 117 #define MXC_R_ADC_CHSEL0 ((uint32_t)0x00000010UL) /**< Offset from ADC Base Address: <tt> 0x0010</tt> */ 118 #define MXC_R_ADC_CHSEL1 ((uint32_t)0x00000014UL) /**< Offset from ADC Base Address: <tt> 0x0014</tt> */ 119 #define MXC_R_ADC_CHSEL2 ((uint32_t)0x00000018UL) /**< Offset from ADC Base Address: <tt> 0x0018</tt> */ 120 #define MXC_R_ADC_CHSEL3 ((uint32_t)0x0000001CUL) /**< Offset from ADC Base Address: <tt> 0x001C</tt> */ 121 #define MXC_R_ADC_CHSEL4 ((uint32_t)0x00000020UL) /**< Offset from ADC Base Address: <tt> 0x0020</tt> */ 122 #define MXC_R_ADC_CHSEL5 ((uint32_t)0x00000024UL) /**< Offset from ADC Base Address: <tt> 0x0024</tt> */ 123 #define MXC_R_ADC_CHSEL6 ((uint32_t)0x00000028UL) /**< Offset from ADC Base Address: <tt> 0x0028</tt> */ 124 #define MXC_R_ADC_CHSEL7 ((uint32_t)0x0000002CUL) /**< Offset from ADC Base Address: <tt> 0x002C</tt> */ 125 #define MXC_R_ADC_RESTART ((uint32_t)0x00000030UL) /**< Offset from ADC Base Address: <tt> 0x0030</tt> */ 126 #define MXC_R_ADC_DATAFMT ((uint32_t)0x0000003CUL) /**< Offset from ADC Base Address: <tt> 0x003C</tt> */ 127 #define MXC_R_ADC_FIFODMACTRL ((uint32_t)0x00000040UL) /**< Offset from ADC Base Address: <tt> 0x0040</tt> */ 128 #define MXC_R_ADC_DATA ((uint32_t)0x00000044UL) /**< Offset from ADC Base Address: <tt> 0x0044</tt> */ 129 #define MXC_R_ADC_STATUS ((uint32_t)0x00000048UL) /**< Offset from ADC Base Address: <tt> 0x0048</tt> */ 130 #define MXC_R_ADC_CHSTATUS ((uint32_t)0x0000004CUL) /**< Offset from ADC Base Address: <tt> 0x004C</tt> */ 131 #define MXC_R_ADC_INTEN ((uint32_t)0x00000050UL) /**< Offset from ADC Base Address: <tt> 0x0050</tt> */ 132 #define MXC_R_ADC_INTFL ((uint32_t)0x00000054UL) /**< Offset from ADC Base Address: <tt> 0x0054</tt> */ 133 #define MXC_R_ADC_SFRADDROFFSET ((uint32_t)0x00000060UL) /**< Offset from ADC Base Address: <tt> 0x0060</tt> */ 134 #define MXC_R_ADC_SFRADDR ((uint32_t)0x00000064UL) /**< Offset from ADC Base Address: <tt> 0x0064</tt> */ 135 #define MXC_R_ADC_SFRWRDATA ((uint32_t)0x00000068UL) /**< Offset from ADC Base Address: <tt> 0x0068</tt> */ 136 #define MXC_R_ADC_SFRRDDATA ((uint32_t)0x0000006CUL) /**< Offset from ADC Base Address: <tt> 0x006C</tt> */ 137 #define MXC_R_ADC_SFRSTATUS ((uint32_t)0x00000070UL) /**< Offset from ADC Base Address: <tt> 0x0070</tt> */ 138 /**@} end of group adc_registers */ 139 140 /** 141 * @ingroup adc_registers 142 * @defgroup ADC_CTRL0 ADC_CTRL0 143 * @brief Control Register 0. 144 * @{ 145 */ 146 #define MXC_F_ADC_CTRL0_ADC_EN_POS 0 /**< CTRL0_ADC_EN Position */ 147 #define MXC_F_ADC_CTRL0_ADC_EN ((uint32_t)(0x1UL << MXC_F_ADC_CTRL0_ADC_EN_POS)) /**< CTRL0_ADC_EN Mask */ 148 149 #define MXC_F_ADC_CTRL0_BIAS_EN_POS 1 /**< CTRL0_BIAS_EN Position */ 150 #define MXC_F_ADC_CTRL0_BIAS_EN ((uint32_t)(0x1UL << MXC_F_ADC_CTRL0_BIAS_EN_POS)) /**< CTRL0_BIAS_EN Mask */ 151 152 #define MXC_F_ADC_CTRL0_SKIP_CAL_POS 2 /**< CTRL0_SKIP_CAL Position */ 153 #define MXC_F_ADC_CTRL0_SKIP_CAL ((uint32_t)(0x1UL << MXC_F_ADC_CTRL0_SKIP_CAL_POS)) /**< CTRL0_SKIP_CAL Mask */ 154 155 #define MXC_F_ADC_CTRL0_CHOP_FORCE_POS 3 /**< CTRL0_CHOP_FORCE Position */ 156 #define MXC_F_ADC_CTRL0_CHOP_FORCE ((uint32_t)(0x1UL << MXC_F_ADC_CTRL0_CHOP_FORCE_POS)) /**< CTRL0_CHOP_FORCE Mask */ 157 158 #define MXC_F_ADC_CTRL0_RESETB_POS 4 /**< CTRL0_RESETB Position */ 159 #define MXC_F_ADC_CTRL0_RESETB ((uint32_t)(0x1UL << MXC_F_ADC_CTRL0_RESETB_POS)) /**< CTRL0_RESETB Mask */ 160 161 /**@} end of group ADC_CTRL0_Register */ 162 163 /** 164 * @ingroup adc_registers 165 * @defgroup ADC_CTRL1 ADC_CTRL1 166 * @brief Control Register 1. 167 * @{ 168 */ 169 #define MXC_F_ADC_CTRL1_START_POS 0 /**< CTRL1_START Position */ 170 #define MXC_F_ADC_CTRL1_START ((uint32_t)(0x1UL << MXC_F_ADC_CTRL1_START_POS)) /**< CTRL1_START Mask */ 171 172 #define MXC_F_ADC_CTRL1_TRIG_MODE_POS 1 /**< CTRL1_TRIG_MODE Position */ 173 #define MXC_F_ADC_CTRL1_TRIG_MODE ((uint32_t)(0x1UL << MXC_F_ADC_CTRL1_TRIG_MODE_POS)) /**< CTRL1_TRIG_MODE Mask */ 174 175 #define MXC_F_ADC_CTRL1_CNV_MODE_POS 2 /**< CTRL1_CNV_MODE Position */ 176 #define MXC_F_ADC_CTRL1_CNV_MODE ((uint32_t)(0x1UL << MXC_F_ADC_CTRL1_CNV_MODE_POS)) /**< CTRL1_CNV_MODE Mask */ 177 178 #define MXC_F_ADC_CTRL1_SAMP_CK_OFF_POS 3 /**< CTRL1_SAMP_CK_OFF Position */ 179 #define MXC_F_ADC_CTRL1_SAMP_CK_OFF ((uint32_t)(0x1UL << MXC_F_ADC_CTRL1_SAMP_CK_OFF_POS)) /**< CTRL1_SAMP_CK_OFF Mask */ 180 181 #define MXC_F_ADC_CTRL1_TRIG_SEL_POS 4 /**< CTRL1_TRIG_SEL Position */ 182 #define MXC_F_ADC_CTRL1_TRIG_SEL ((uint32_t)(0x7UL << MXC_F_ADC_CTRL1_TRIG_SEL_POS)) /**< CTRL1_TRIG_SEL Mask */ 183 184 #define MXC_F_ADC_CTRL1_TS_SEL_POS 7 /**< CTRL1_TS_SEL Position */ 185 #define MXC_F_ADC_CTRL1_TS_SEL ((uint32_t)(0x1UL << MXC_F_ADC_CTRL1_TS_SEL_POS)) /**< CTRL1_TS_SEL Mask */ 186 187 #define MXC_F_ADC_CTRL1_AVG_POS 8 /**< CTRL1_AVG Position */ 188 #define MXC_F_ADC_CTRL1_AVG ((uint32_t)(0x7UL << MXC_F_ADC_CTRL1_AVG_POS)) /**< CTRL1_AVG Mask */ 189 #define MXC_V_ADC_CTRL1_AVG_AVG1 ((uint32_t)0x0UL) /**< CTRL1_AVG_AVG1 Value */ 190 #define MXC_S_ADC_CTRL1_AVG_AVG1 (MXC_V_ADC_CTRL1_AVG_AVG1 << MXC_F_ADC_CTRL1_AVG_POS) /**< CTRL1_AVG_AVG1 Setting */ 191 #define MXC_V_ADC_CTRL1_AVG_AVG2 ((uint32_t)0x1UL) /**< CTRL1_AVG_AVG2 Value */ 192 #define MXC_S_ADC_CTRL1_AVG_AVG2 (MXC_V_ADC_CTRL1_AVG_AVG2 << MXC_F_ADC_CTRL1_AVG_POS) /**< CTRL1_AVG_AVG2 Setting */ 193 #define MXC_V_ADC_CTRL1_AVG_AVG4 ((uint32_t)0x2UL) /**< CTRL1_AVG_AVG4 Value */ 194 #define MXC_S_ADC_CTRL1_AVG_AVG4 (MXC_V_ADC_CTRL1_AVG_AVG4 << MXC_F_ADC_CTRL1_AVG_POS) /**< CTRL1_AVG_AVG4 Setting */ 195 #define MXC_V_ADC_CTRL1_AVG_AVG8 ((uint32_t)0x3UL) /**< CTRL1_AVG_AVG8 Value */ 196 #define MXC_S_ADC_CTRL1_AVG_AVG8 (MXC_V_ADC_CTRL1_AVG_AVG8 << MXC_F_ADC_CTRL1_AVG_POS) /**< CTRL1_AVG_AVG8 Setting */ 197 #define MXC_V_ADC_CTRL1_AVG_AVG16 ((uint32_t)0x4UL) /**< CTRL1_AVG_AVG16 Value */ 198 #define MXC_S_ADC_CTRL1_AVG_AVG16 (MXC_V_ADC_CTRL1_AVG_AVG16 << MXC_F_ADC_CTRL1_AVG_POS) /**< CTRL1_AVG_AVG16 Setting */ 199 #define MXC_V_ADC_CTRL1_AVG_AVG32 ((uint32_t)0x5UL) /**< CTRL1_AVG_AVG32 Value */ 200 #define MXC_S_ADC_CTRL1_AVG_AVG32 (MXC_V_ADC_CTRL1_AVG_AVG32 << MXC_F_ADC_CTRL1_AVG_POS) /**< CTRL1_AVG_AVG32 Setting */ 201 202 #define MXC_F_ADC_CTRL1_NUM_SLOTS_POS 16 /**< CTRL1_NUM_SLOTS Position */ 203 #define MXC_F_ADC_CTRL1_NUM_SLOTS ((uint32_t)(0x1FUL << MXC_F_ADC_CTRL1_NUM_SLOTS_POS)) /**< CTRL1_NUM_SLOTS Mask */ 204 205 /**@} end of group ADC_CTRL1_Register */ 206 207 /** 208 * @ingroup adc_registers 209 * @defgroup ADC_CLKCTRL ADC_CLKCTRL 210 * @brief Clock Control Register. 211 * @{ 212 */ 213 #define MXC_F_ADC_CLKCTRL_CLKSEL_POS 0 /**< CLKCTRL_CLKSEL Position */ 214 #define MXC_F_ADC_CLKCTRL_CLKSEL ((uint32_t)(0x3UL << MXC_F_ADC_CLKCTRL_CLKSEL_POS)) /**< CLKCTRL_CLKSEL Mask */ 215 #define MXC_V_ADC_CLKCTRL_CLKSEL_HCLK ((uint32_t)0x0UL) /**< CLKCTRL_CLKSEL_HCLK Value */ 216 #define MXC_S_ADC_CLKCTRL_CLKSEL_HCLK (MXC_V_ADC_CLKCTRL_CLKSEL_HCLK << MXC_F_ADC_CLKCTRL_CLKSEL_POS) /**< CLKCTRL_CLKSEL_HCLK Setting */ 217 #define MXC_V_ADC_CLKCTRL_CLKSEL_CLK_ADC0 ((uint32_t)0x1UL) /**< CLKCTRL_CLKSEL_CLK_ADC0 Value */ 218 #define MXC_S_ADC_CLKCTRL_CLKSEL_CLK_ADC0 (MXC_V_ADC_CLKCTRL_CLKSEL_CLK_ADC0 << MXC_F_ADC_CLKCTRL_CLKSEL_POS) /**< CLKCTRL_CLKSEL_CLK_ADC0 Setting */ 219 #define MXC_V_ADC_CLKCTRL_CLKSEL_CLK_ADC1 ((uint32_t)0x2UL) /**< CLKCTRL_CLKSEL_CLK_ADC1 Value */ 220 #define MXC_S_ADC_CLKCTRL_CLKSEL_CLK_ADC1 (MXC_V_ADC_CLKCTRL_CLKSEL_CLK_ADC1 << MXC_F_ADC_CLKCTRL_CLKSEL_POS) /**< CLKCTRL_CLKSEL_CLK_ADC1 Setting */ 221 #define MXC_V_ADC_CLKCTRL_CLKSEL_CLK_ADC2 ((uint32_t)0x3UL) /**< CLKCTRL_CLKSEL_CLK_ADC2 Value */ 222 #define MXC_S_ADC_CLKCTRL_CLKSEL_CLK_ADC2 (MXC_V_ADC_CLKCTRL_CLKSEL_CLK_ADC2 << MXC_F_ADC_CLKCTRL_CLKSEL_POS) /**< CLKCTRL_CLKSEL_CLK_ADC2 Setting */ 223 224 #define MXC_F_ADC_CLKCTRL_CLKDIV_POS 4 /**< CLKCTRL_CLKDIV Position */ 225 #define MXC_F_ADC_CLKCTRL_CLKDIV ((uint32_t)(0x7UL << MXC_F_ADC_CLKCTRL_CLKDIV_POS)) /**< CLKCTRL_CLKDIV Mask */ 226 #define MXC_V_ADC_CLKCTRL_CLKDIV_DIV2 ((uint32_t)0x0UL) /**< CLKCTRL_CLKDIV_DIV2 Value */ 227 #define MXC_S_ADC_CLKCTRL_CLKDIV_DIV2 (MXC_V_ADC_CLKCTRL_CLKDIV_DIV2 << MXC_F_ADC_CLKCTRL_CLKDIV_POS) /**< CLKCTRL_CLKDIV_DIV2 Setting */ 228 #define MXC_V_ADC_CLKCTRL_CLKDIV_DIV4 ((uint32_t)0x1UL) /**< CLKCTRL_CLKDIV_DIV4 Value */ 229 #define MXC_S_ADC_CLKCTRL_CLKDIV_DIV4 (MXC_V_ADC_CLKCTRL_CLKDIV_DIV4 << MXC_F_ADC_CLKCTRL_CLKDIV_POS) /**< CLKCTRL_CLKDIV_DIV4 Setting */ 230 #define MXC_V_ADC_CLKCTRL_CLKDIV_DIV8 ((uint32_t)0x2UL) /**< CLKCTRL_CLKDIV_DIV8 Value */ 231 #define MXC_S_ADC_CLKCTRL_CLKDIV_DIV8 (MXC_V_ADC_CLKCTRL_CLKDIV_DIV8 << MXC_F_ADC_CLKCTRL_CLKDIV_POS) /**< CLKCTRL_CLKDIV_DIV8 Setting */ 232 #define MXC_V_ADC_CLKCTRL_CLKDIV_DIV16 ((uint32_t)0x3UL) /**< CLKCTRL_CLKDIV_DIV16 Value */ 233 #define MXC_S_ADC_CLKCTRL_CLKDIV_DIV16 (MXC_V_ADC_CLKCTRL_CLKDIV_DIV16 << MXC_F_ADC_CLKCTRL_CLKDIV_POS) /**< CLKCTRL_CLKDIV_DIV16 Setting */ 234 #define MXC_V_ADC_CLKCTRL_CLKDIV_DIV1 ((uint32_t)0x4UL) /**< CLKCTRL_CLKDIV_DIV1 Value */ 235 #define MXC_S_ADC_CLKCTRL_CLKDIV_DIV1 (MXC_V_ADC_CLKCTRL_CLKDIV_DIV1 << MXC_F_ADC_CLKCTRL_CLKDIV_POS) /**< CLKCTRL_CLKDIV_DIV1 Setting */ 236 237 /**@} end of group ADC_CLKCTRL_Register */ 238 239 /** 240 * @ingroup adc_registers 241 * @defgroup ADC_SAMPCLKCTRL ADC_SAMPCLKCTRL 242 * @brief Sample Clock Control Register. 243 * @{ 244 */ 245 #define MXC_F_ADC_SAMPCLKCTRL_TRACK_CNT_POS 0 /**< SAMPCLKCTRL_TRACK_CNT Position */ 246 #define MXC_F_ADC_SAMPCLKCTRL_TRACK_CNT ((uint32_t)(0xFFUL << MXC_F_ADC_SAMPCLKCTRL_TRACK_CNT_POS)) /**< SAMPCLKCTRL_TRACK_CNT Mask */ 247 248 #define MXC_F_ADC_SAMPCLKCTRL_IDLE_CNT_POS 16 /**< SAMPCLKCTRL_IDLE_CNT Position */ 249 #define MXC_F_ADC_SAMPCLKCTRL_IDLE_CNT ((uint32_t)(0xFFFFUL << MXC_F_ADC_SAMPCLKCTRL_IDLE_CNT_POS)) /**< SAMPCLKCTRL_IDLE_CNT Mask */ 250 251 /**@} end of group ADC_SAMPCLKCTRL_Register */ 252 253 /** 254 * @ingroup adc_registers 255 * @defgroup ADC_CHSEL0 ADC_CHSEL0 256 * @brief Channel Select Register 0. 257 * @{ 258 */ 259 #define MXC_F_ADC_CHSEL0_SLOT0_ID_POS 0 /**< CHSEL0_SLOT0_ID Position */ 260 #define MXC_F_ADC_CHSEL0_SLOT0_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL0_SLOT0_ID_POS)) /**< CHSEL0_SLOT0_ID Mask */ 261 262 #define MXC_F_ADC_CHSEL0_SLOT1_ID_POS 8 /**< CHSEL0_SLOT1_ID Position */ 263 #define MXC_F_ADC_CHSEL0_SLOT1_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL0_SLOT1_ID_POS)) /**< CHSEL0_SLOT1_ID Mask */ 264 265 #define MXC_F_ADC_CHSEL0_SLOT2_ID_POS 16 /**< CHSEL0_SLOT2_ID Position */ 266 #define MXC_F_ADC_CHSEL0_SLOT2_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL0_SLOT2_ID_POS)) /**< CHSEL0_SLOT2_ID Mask */ 267 268 #define MXC_F_ADC_CHSEL0_SLOT3_ID_POS 24 /**< CHSEL0_SLOT3_ID Position */ 269 #define MXC_F_ADC_CHSEL0_SLOT3_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL0_SLOT3_ID_POS)) /**< CHSEL0_SLOT3_ID Mask */ 270 271 /**@} end of group ADC_CHSEL0_Register */ 272 273 /** 274 * @ingroup adc_registers 275 * @defgroup ADC_CHSEL1 ADC_CHSEL1 276 * @brief Channel Select Register 1. 277 * @{ 278 */ 279 #define MXC_F_ADC_CHSEL1_SLOT4_ID_POS 0 /**< CHSEL1_SLOT4_ID Position */ 280 #define MXC_F_ADC_CHSEL1_SLOT4_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL1_SLOT4_ID_POS)) /**< CHSEL1_SLOT4_ID Mask */ 281 282 #define MXC_F_ADC_CHSEL1_SLOT5_ID_POS 8 /**< CHSEL1_SLOT5_ID Position */ 283 #define MXC_F_ADC_CHSEL1_SLOT5_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL1_SLOT5_ID_POS)) /**< CHSEL1_SLOT5_ID Mask */ 284 285 #define MXC_F_ADC_CHSEL1_SLOT6_ID_POS 16 /**< CHSEL1_SLOT6_ID Position */ 286 #define MXC_F_ADC_CHSEL1_SLOT6_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL1_SLOT6_ID_POS)) /**< CHSEL1_SLOT6_ID Mask */ 287 288 #define MXC_F_ADC_CHSEL1_SLOT7_ID_POS 24 /**< CHSEL1_SLOT7_ID Position */ 289 #define MXC_F_ADC_CHSEL1_SLOT7_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL1_SLOT7_ID_POS)) /**< CHSEL1_SLOT7_ID Mask */ 290 291 /**@} end of group ADC_CHSEL1_Register */ 292 293 /** 294 * @ingroup adc_registers 295 * @defgroup ADC_CHSEL2 ADC_CHSEL2 296 * @brief Channel Select Register 2. 297 * @{ 298 */ 299 #define MXC_F_ADC_CHSEL2_SLOT8_ID_POS 0 /**< CHSEL2_SLOT8_ID Position */ 300 #define MXC_F_ADC_CHSEL2_SLOT8_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL2_SLOT8_ID_POS)) /**< CHSEL2_SLOT8_ID Mask */ 301 302 #define MXC_F_ADC_CHSEL2_SLOT9_ID_POS 8 /**< CHSEL2_SLOT9_ID Position */ 303 #define MXC_F_ADC_CHSEL2_SLOT9_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL2_SLOT9_ID_POS)) /**< CHSEL2_SLOT9_ID Mask */ 304 305 #define MXC_F_ADC_CHSEL2_SLOT10_ID_POS 16 /**< CHSEL2_SLOT10_ID Position */ 306 #define MXC_F_ADC_CHSEL2_SLOT10_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL2_SLOT10_ID_POS)) /**< CHSEL2_SLOT10_ID Mask */ 307 308 #define MXC_F_ADC_CHSEL2_SLOT11_ID_POS 24 /**< CHSEL2_SLOT11_ID Position */ 309 #define MXC_F_ADC_CHSEL2_SLOT11_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL2_SLOT11_ID_POS)) /**< CHSEL2_SLOT11_ID Mask */ 310 311 /**@} end of group ADC_CHSEL2_Register */ 312 313 /** 314 * @ingroup adc_registers 315 * @defgroup ADC_CHSEL3 ADC_CHSEL3 316 * @brief Channel Select Register 3. 317 * @{ 318 */ 319 #define MXC_F_ADC_CHSEL3_SLOT12_ID_POS 0 /**< CHSEL3_SLOT12_ID Position */ 320 #define MXC_F_ADC_CHSEL3_SLOT12_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL3_SLOT12_ID_POS)) /**< CHSEL3_SLOT12_ID Mask */ 321 322 #define MXC_F_ADC_CHSEL3_SLOT13_ID_POS 8 /**< CHSEL3_SLOT13_ID Position */ 323 #define MXC_F_ADC_CHSEL3_SLOT13_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL3_SLOT13_ID_POS)) /**< CHSEL3_SLOT13_ID Mask */ 324 325 #define MXC_F_ADC_CHSEL3_SLOT14_ID_POS 16 /**< CHSEL3_SLOT14_ID Position */ 326 #define MXC_F_ADC_CHSEL3_SLOT14_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL3_SLOT14_ID_POS)) /**< CHSEL3_SLOT14_ID Mask */ 327 328 #define MXC_F_ADC_CHSEL3_SLOT15_ID_POS 24 /**< CHSEL3_SLOT15_ID Position */ 329 #define MXC_F_ADC_CHSEL3_SLOT15_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL3_SLOT15_ID_POS)) /**< CHSEL3_SLOT15_ID Mask */ 330 331 /**@} end of group ADC_CHSEL3_Register */ 332 333 /** 334 * @ingroup adc_registers 335 * @defgroup ADC_CHSEL4 ADC_CHSEL4 336 * @brief Channel Select Register 4. 337 * @{ 338 */ 339 #define MXC_F_ADC_CHSEL4_SLOT16_ID_POS 0 /**< CHSEL4_SLOT16_ID Position */ 340 #define MXC_F_ADC_CHSEL4_SLOT16_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL4_SLOT16_ID_POS)) /**< CHSEL4_SLOT16_ID Mask */ 341 342 #define MXC_F_ADC_CHSEL4_SLOT17_ID_POS 8 /**< CHSEL4_SLOT17_ID Position */ 343 #define MXC_F_ADC_CHSEL4_SLOT17_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL4_SLOT17_ID_POS)) /**< CHSEL4_SLOT17_ID Mask */ 344 345 #define MXC_F_ADC_CHSEL4_SLOT18_ID_POS 16 /**< CHSEL4_SLOT18_ID Position */ 346 #define MXC_F_ADC_CHSEL4_SLOT18_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL4_SLOT18_ID_POS)) /**< CHSEL4_SLOT18_ID Mask */ 347 348 #define MXC_F_ADC_CHSEL4_SLOT19_ID_POS 24 /**< CHSEL4_SLOT19_ID Position */ 349 #define MXC_F_ADC_CHSEL4_SLOT19_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL4_SLOT19_ID_POS)) /**< CHSEL4_SLOT19_ID Mask */ 350 351 /**@} end of group ADC_CHSEL4_Register */ 352 353 /** 354 * @ingroup adc_registers 355 * @defgroup ADC_CHSEL5 ADC_CHSEL5 356 * @brief Channel Select Register 5. 357 * @{ 358 */ 359 #define MXC_F_ADC_CHSEL5_SLOT20_ID_POS 0 /**< CHSEL5_SLOT20_ID Position */ 360 #define MXC_F_ADC_CHSEL5_SLOT20_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL5_SLOT20_ID_POS)) /**< CHSEL5_SLOT20_ID Mask */ 361 362 #define MXC_F_ADC_CHSEL5_SLOT21_ID_POS 8 /**< CHSEL5_SLOT21_ID Position */ 363 #define MXC_F_ADC_CHSEL5_SLOT21_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL5_SLOT21_ID_POS)) /**< CHSEL5_SLOT21_ID Mask */ 364 365 #define MXC_F_ADC_CHSEL5_SLOT22_ID_POS 16 /**< CHSEL5_SLOT22_ID Position */ 366 #define MXC_F_ADC_CHSEL5_SLOT22_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL5_SLOT22_ID_POS)) /**< CHSEL5_SLOT22_ID Mask */ 367 368 #define MXC_F_ADC_CHSEL5_SLOT23_ID_POS 24 /**< CHSEL5_SLOT23_ID Position */ 369 #define MXC_F_ADC_CHSEL5_SLOT23_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL5_SLOT23_ID_POS)) /**< CHSEL5_SLOT23_ID Mask */ 370 371 /**@} end of group ADC_CHSEL5_Register */ 372 373 /** 374 * @ingroup adc_registers 375 * @defgroup ADC_CHSEL6 ADC_CHSEL6 376 * @brief Channel Select Register 6. 377 * @{ 378 */ 379 #define MXC_F_ADC_CHSEL6_SLOT24_ID_POS 0 /**< CHSEL6_SLOT24_ID Position */ 380 #define MXC_F_ADC_CHSEL6_SLOT24_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL6_SLOT24_ID_POS)) /**< CHSEL6_SLOT24_ID Mask */ 381 382 #define MXC_F_ADC_CHSEL6_SLOT25_ID_POS 8 /**< CHSEL6_SLOT25_ID Position */ 383 #define MXC_F_ADC_CHSEL6_SLOT25_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL6_SLOT25_ID_POS)) /**< CHSEL6_SLOT25_ID Mask */ 384 385 #define MXC_F_ADC_CHSEL6_SLOT26_ID_POS 16 /**< CHSEL6_SLOT26_ID Position */ 386 #define MXC_F_ADC_CHSEL6_SLOT26_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL6_SLOT26_ID_POS)) /**< CHSEL6_SLOT26_ID Mask */ 387 388 #define MXC_F_ADC_CHSEL6_SLOT27_ID_POS 24 /**< CHSEL6_SLOT27_ID Position */ 389 #define MXC_F_ADC_CHSEL6_SLOT27_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL6_SLOT27_ID_POS)) /**< CHSEL6_SLOT27_ID Mask */ 390 391 /**@} end of group ADC_CHSEL6_Register */ 392 393 /** 394 * @ingroup adc_registers 395 * @defgroup ADC_CHSEL7 ADC_CHSEL7 396 * @brief Channel Select Register 7. 397 * @{ 398 */ 399 #define MXC_F_ADC_CHSEL7_SLOT28_ID_POS 0 /**< CHSEL7_SLOT28_ID Position */ 400 #define MXC_F_ADC_CHSEL7_SLOT28_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL7_SLOT28_ID_POS)) /**< CHSEL7_SLOT28_ID Mask */ 401 402 #define MXC_F_ADC_CHSEL7_SLOT29_ID_POS 8 /**< CHSEL7_SLOT29_ID Position */ 403 #define MXC_F_ADC_CHSEL7_SLOT29_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL7_SLOT29_ID_POS)) /**< CHSEL7_SLOT29_ID Mask */ 404 405 #define MXC_F_ADC_CHSEL7_SLOT30_ID_POS 16 /**< CHSEL7_SLOT30_ID Position */ 406 #define MXC_F_ADC_CHSEL7_SLOT30_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL7_SLOT30_ID_POS)) /**< CHSEL7_SLOT30_ID Mask */ 407 408 #define MXC_F_ADC_CHSEL7_SLOT31_ID_POS 24 /**< CHSEL7_SLOT31_ID Position */ 409 #define MXC_F_ADC_CHSEL7_SLOT31_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL7_SLOT31_ID_POS)) /**< CHSEL7_SLOT31_ID Mask */ 410 411 /**@} end of group ADC_CHSEL7_Register */ 412 413 /** 414 * @ingroup adc_registers 415 * @defgroup ADC_RESTART ADC_RESTART 416 * @brief Restart Count Control Register 417 * @{ 418 */ 419 #define MXC_F_ADC_RESTART_CNT_POS 0 /**< RESTART_CNT Position */ 420 #define MXC_F_ADC_RESTART_CNT ((uint32_t)(0xFFFFUL << MXC_F_ADC_RESTART_CNT_POS)) /**< RESTART_CNT Mask */ 421 422 /**@} end of group ADC_RESTART_Register */ 423 424 /** 425 * @ingroup adc_registers 426 * @defgroup ADC_DATAFMT ADC_DATAFMT 427 * @brief Channel Data Format Register 428 * @{ 429 */ 430 #define MXC_F_ADC_DATAFMT_MODE_POS 0 /**< DATAFMT_MODE Position */ 431 #define MXC_F_ADC_DATAFMT_MODE ((uint32_t)(0xFFFFFFFFUL << MXC_F_ADC_DATAFMT_MODE_POS)) /**< DATAFMT_MODE Mask */ 432 433 /**@} end of group ADC_DATAFMT_Register */ 434 435 /** 436 * @ingroup adc_registers 437 * @defgroup ADC_FIFODMACTRL ADC_FIFODMACTRL 438 * @brief FIFO and DMA control 439 * @{ 440 */ 441 #define MXC_F_ADC_FIFODMACTRL_DMA_EN_POS 0 /**< FIFODMACTRL_DMA_EN Position */ 442 #define MXC_F_ADC_FIFODMACTRL_DMA_EN ((uint32_t)(0x1UL << MXC_F_ADC_FIFODMACTRL_DMA_EN_POS)) /**< FIFODMACTRL_DMA_EN Mask */ 443 444 #define MXC_F_ADC_FIFODMACTRL_FLUSH_POS 1 /**< FIFODMACTRL_FLUSH Position */ 445 #define MXC_F_ADC_FIFODMACTRL_FLUSH ((uint32_t)(0x1UL << MXC_F_ADC_FIFODMACTRL_FLUSH_POS)) /**< FIFODMACTRL_FLUSH Mask */ 446 447 #define MXC_F_ADC_FIFODMACTRL_DATA_FORMAT_POS 2 /**< FIFODMACTRL_DATA_FORMAT Position */ 448 #define MXC_F_ADC_FIFODMACTRL_DATA_FORMAT ((uint32_t)(0x3UL << MXC_F_ADC_FIFODMACTRL_DATA_FORMAT_POS)) /**< FIFODMACTRL_DATA_FORMAT Mask */ 449 #define MXC_V_ADC_FIFODMACTRL_DATA_FORMAT_DATA_STATUS ((uint32_t)0x0UL) /**< FIFODMACTRL_DATA_FORMAT_DATA_STATUS Value */ 450 #define MXC_S_ADC_FIFODMACTRL_DATA_FORMAT_DATA_STATUS (MXC_V_ADC_FIFODMACTRL_DATA_FORMAT_DATA_STATUS << MXC_F_ADC_FIFODMACTRL_DATA_FORMAT_POS) /**< FIFODMACTRL_DATA_FORMAT_DATA_STATUS Setting */ 451 #define MXC_V_ADC_FIFODMACTRL_DATA_FORMAT_DATA_ONLY ((uint32_t)0x1UL) /**< FIFODMACTRL_DATA_FORMAT_DATA_ONLY Value */ 452 #define MXC_S_ADC_FIFODMACTRL_DATA_FORMAT_DATA_ONLY (MXC_V_ADC_FIFODMACTRL_DATA_FORMAT_DATA_ONLY << MXC_F_ADC_FIFODMACTRL_DATA_FORMAT_POS) /**< FIFODMACTRL_DATA_FORMAT_DATA_ONLY Setting */ 453 #define MXC_V_ADC_FIFODMACTRL_DATA_FORMAT_RAW_DATA_ONLY ((uint32_t)0x2UL) /**< FIFODMACTRL_DATA_FORMAT_RAW_DATA_ONLY Value */ 454 #define MXC_S_ADC_FIFODMACTRL_DATA_FORMAT_RAW_DATA_ONLY (MXC_V_ADC_FIFODMACTRL_DATA_FORMAT_RAW_DATA_ONLY << MXC_F_ADC_FIFODMACTRL_DATA_FORMAT_POS) /**< FIFODMACTRL_DATA_FORMAT_RAW_DATA_ONLY Setting */ 455 456 #define MXC_F_ADC_FIFODMACTRL_THRESH_POS 8 /**< FIFODMACTRL_THRESH Position */ 457 #define MXC_F_ADC_FIFODMACTRL_THRESH ((uint32_t)(0xFFUL << MXC_F_ADC_FIFODMACTRL_THRESH_POS)) /**< FIFODMACTRL_THRESH Mask */ 458 459 /**@} end of group ADC_FIFODMACTRL_Register */ 460 461 /** 462 * @ingroup adc_registers 463 * @defgroup ADC_DATA ADC_DATA 464 * @brief Data Register (FIFO). 465 * @{ 466 */ 467 #define MXC_F_ADC_DATA_DATA_POS 0 /**< DATA_DATA Position */ 468 #define MXC_F_ADC_DATA_DATA ((uint32_t)(0xFFFFUL << MXC_F_ADC_DATA_DATA_POS)) /**< DATA_DATA Mask */ 469 470 #define MXC_F_ADC_DATA_CHAN_POS 16 /**< DATA_CHAN Position */ 471 #define MXC_F_ADC_DATA_CHAN ((uint32_t)(0x1FUL << MXC_F_ADC_DATA_CHAN_POS)) /**< DATA_CHAN Mask */ 472 473 #define MXC_F_ADC_DATA_INVALID_POS 24 /**< DATA_INVALID Position */ 474 #define MXC_F_ADC_DATA_INVALID ((uint32_t)(0x1UL << MXC_F_ADC_DATA_INVALID_POS)) /**< DATA_INVALID Mask */ 475 476 #define MXC_F_ADC_DATA_CLIPPED_POS 31 /**< DATA_CLIPPED Position */ 477 #define MXC_F_ADC_DATA_CLIPPED ((uint32_t)(0x1UL << MXC_F_ADC_DATA_CLIPPED_POS)) /**< DATA_CLIPPED Mask */ 478 479 /**@} end of group ADC_DATA_Register */ 480 481 /** 482 * @ingroup adc_registers 483 * @defgroup ADC_STATUS ADC_STATUS 484 * @brief Status Register 485 * @{ 486 */ 487 #define MXC_F_ADC_STATUS_READY_POS 0 /**< STATUS_READY Position */ 488 #define MXC_F_ADC_STATUS_READY ((uint32_t)(0x1UL << MXC_F_ADC_STATUS_READY_POS)) /**< STATUS_READY Mask */ 489 490 #define MXC_F_ADC_STATUS_EMPTY_POS 1 /**< STATUS_EMPTY Position */ 491 #define MXC_F_ADC_STATUS_EMPTY ((uint32_t)(0x1UL << MXC_F_ADC_STATUS_EMPTY_POS)) /**< STATUS_EMPTY Mask */ 492 493 #define MXC_F_ADC_STATUS_FULL_POS 2 /**< STATUS_FULL Position */ 494 #define MXC_F_ADC_STATUS_FULL ((uint32_t)(0x1UL << MXC_F_ADC_STATUS_FULL_POS)) /**< STATUS_FULL Mask */ 495 496 #define MXC_F_ADC_STATUS_FIFO_LEVEL_POS 8 /**< STATUS_FIFO_LEVEL Position */ 497 #define MXC_F_ADC_STATUS_FIFO_LEVEL ((uint32_t)(0xFFUL << MXC_F_ADC_STATUS_FIFO_LEVEL_POS)) /**< STATUS_FIFO_LEVEL Mask */ 498 499 /**@} end of group ADC_STATUS_Register */ 500 501 /** 502 * @ingroup adc_registers 503 * @defgroup ADC_CHSTATUS ADC_CHSTATUS 504 * @brief Channel Status 505 * @{ 506 */ 507 #define MXC_F_ADC_CHSTATUS_CLIPPED_POS 0 /**< CHSTATUS_CLIPPED Position */ 508 #define MXC_F_ADC_CHSTATUS_CLIPPED ((uint32_t)(0xFFFFFFFFUL << MXC_F_ADC_CHSTATUS_CLIPPED_POS)) /**< CHSTATUS_CLIPPED Mask */ 509 510 /**@} end of group ADC_CHSTATUS_Register */ 511 512 /** 513 * @ingroup adc_registers 514 * @defgroup ADC_INTEN ADC_INTEN 515 * @brief Interrupt Enable Register. 516 * @{ 517 */ 518 #define MXC_F_ADC_INTEN_READY_POS 0 /**< INTEN_READY Position */ 519 #define MXC_F_ADC_INTEN_READY ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_READY_POS)) /**< INTEN_READY Mask */ 520 521 #define MXC_F_ADC_INTEN_ABORT_POS 2 /**< INTEN_ABORT Position */ 522 #define MXC_F_ADC_INTEN_ABORT ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_ABORT_POS)) /**< INTEN_ABORT Mask */ 523 524 #define MXC_F_ADC_INTEN_START_DET_POS 3 /**< INTEN_START_DET Position */ 525 #define MXC_F_ADC_INTEN_START_DET ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_START_DET_POS)) /**< INTEN_START_DET Mask */ 526 527 #define MXC_F_ADC_INTEN_SEQ_STARTED_POS 4 /**< INTEN_SEQ_STARTED Position */ 528 #define MXC_F_ADC_INTEN_SEQ_STARTED ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_SEQ_STARTED_POS)) /**< INTEN_SEQ_STARTED Mask */ 529 530 #define MXC_F_ADC_INTEN_SEQ_DONE_POS 5 /**< INTEN_SEQ_DONE Position */ 531 #define MXC_F_ADC_INTEN_SEQ_DONE ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_SEQ_DONE_POS)) /**< INTEN_SEQ_DONE Mask */ 532 533 #define MXC_F_ADC_INTEN_CONV_DONE_POS 6 /**< INTEN_CONV_DONE Position */ 534 #define MXC_F_ADC_INTEN_CONV_DONE ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_CONV_DONE_POS)) /**< INTEN_CONV_DONE Mask */ 535 536 #define MXC_F_ADC_INTEN_CLIPPED_POS 7 /**< INTEN_CLIPPED Position */ 537 #define MXC_F_ADC_INTEN_CLIPPED ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_CLIPPED_POS)) /**< INTEN_CLIPPED Mask */ 538 539 #define MXC_F_ADC_INTEN_FIFO_LVL_POS 8 /**< INTEN_FIFO_LVL Position */ 540 #define MXC_F_ADC_INTEN_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_FIFO_LVL_POS)) /**< INTEN_FIFO_LVL Mask */ 541 542 #define MXC_F_ADC_INTEN_FIFO_UFL_POS 9 /**< INTEN_FIFO_UFL Position */ 543 #define MXC_F_ADC_INTEN_FIFO_UFL ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_FIFO_UFL_POS)) /**< INTEN_FIFO_UFL Mask */ 544 545 #define MXC_F_ADC_INTEN_FIFO_OFL_POS 10 /**< INTEN_FIFO_OFL Position */ 546 #define MXC_F_ADC_INTEN_FIFO_OFL ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_FIFO_OFL_POS)) /**< INTEN_FIFO_OFL Mask */ 547 548 /**@} end of group ADC_INTEN_Register */ 549 550 /** 551 * @ingroup adc_registers 552 * @defgroup ADC_INTFL ADC_INTFL 553 * @brief Interrupt Flags Register. 554 * @{ 555 */ 556 #define MXC_F_ADC_INTFL_READY_POS 0 /**< INTFL_READY Position */ 557 #define MXC_F_ADC_INTFL_READY ((uint32_t)(0x1UL << MXC_F_ADC_INTFL_READY_POS)) /**< INTFL_READY Mask */ 558 559 #define MXC_F_ADC_INTFL_ABORT_POS 2 /**< INTFL_ABORT Position */ 560 #define MXC_F_ADC_INTFL_ABORT ((uint32_t)(0x1UL << MXC_F_ADC_INTFL_ABORT_POS)) /**< INTFL_ABORT Mask */ 561 562 #define MXC_F_ADC_INTFL_START_DET_POS 3 /**< INTFL_START_DET Position */ 563 #define MXC_F_ADC_INTFL_START_DET ((uint32_t)(0x1UL << MXC_F_ADC_INTFL_START_DET_POS)) /**< INTFL_START_DET Mask */ 564 565 #define MXC_F_ADC_INTFL_SEQ_STARTED_POS 4 /**< INTFL_SEQ_STARTED Position */ 566 #define MXC_F_ADC_INTFL_SEQ_STARTED ((uint32_t)(0x1UL << MXC_F_ADC_INTFL_SEQ_STARTED_POS)) /**< INTFL_SEQ_STARTED Mask */ 567 568 #define MXC_F_ADC_INTFL_SEQ_DONE_POS 5 /**< INTFL_SEQ_DONE Position */ 569 #define MXC_F_ADC_INTFL_SEQ_DONE ((uint32_t)(0x1UL << MXC_F_ADC_INTFL_SEQ_DONE_POS)) /**< INTFL_SEQ_DONE Mask */ 570 571 #define MXC_F_ADC_INTFL_CONV_DONE_POS 6 /**< INTFL_CONV_DONE Position */ 572 #define MXC_F_ADC_INTFL_CONV_DONE ((uint32_t)(0x1UL << MXC_F_ADC_INTFL_CONV_DONE_POS)) /**< INTFL_CONV_DONE Mask */ 573 574 #define MXC_F_ADC_INTFL_CLIPPED_POS 7 /**< INTFL_CLIPPED Position */ 575 #define MXC_F_ADC_INTFL_CLIPPED ((uint32_t)(0x1UL << MXC_F_ADC_INTFL_CLIPPED_POS)) /**< INTFL_CLIPPED Mask */ 576 577 #define MXC_F_ADC_INTFL_FIFO_LVL_POS 8 /**< INTFL_FIFO_LVL Position */ 578 #define MXC_F_ADC_INTFL_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_ADC_INTFL_FIFO_LVL_POS)) /**< INTFL_FIFO_LVL Mask */ 579 580 #define MXC_F_ADC_INTFL_FIFO_UFL_POS 9 /**< INTFL_FIFO_UFL Position */ 581 #define MXC_F_ADC_INTFL_FIFO_UFL ((uint32_t)(0x1UL << MXC_F_ADC_INTFL_FIFO_UFL_POS)) /**< INTFL_FIFO_UFL Mask */ 582 583 #define MXC_F_ADC_INTFL_FIFO_OFL_POS 10 /**< INTFL_FIFO_OFL Position */ 584 #define MXC_F_ADC_INTFL_FIFO_OFL ((uint32_t)(0x1UL << MXC_F_ADC_INTFL_FIFO_OFL_POS)) /**< INTFL_FIFO_OFL Mask */ 585 586 /**@} end of group ADC_INTFL_Register */ 587 588 /** 589 * @ingroup adc_registers 590 * @defgroup ADC_SFRADDROFFSET ADC_SFRADDROFFSET 591 * @brief SFR Address Offset Register 592 * @{ 593 */ 594 #define MXC_F_ADC_SFRADDROFFSET_OFFSET_POS 0 /**< SFRADDROFFSET_OFFSET Position */ 595 #define MXC_F_ADC_SFRADDROFFSET_OFFSET ((uint32_t)(0xFFUL << MXC_F_ADC_SFRADDROFFSET_OFFSET_POS)) /**< SFRADDROFFSET_OFFSET Mask */ 596 597 /**@} end of group ADC_SFRADDROFFSET_Register */ 598 599 /** 600 * @ingroup adc_registers 601 * @defgroup ADC_SFRADDR ADC_SFRADDR 602 * @brief SFR Address Register 603 * @{ 604 */ 605 #define MXC_F_ADC_SFRADDR_ADDR_POS 0 /**< SFRADDR_ADDR Position */ 606 #define MXC_F_ADC_SFRADDR_ADDR ((uint32_t)(0xFFUL << MXC_F_ADC_SFRADDR_ADDR_POS)) /**< SFRADDR_ADDR Mask */ 607 608 /**@} end of group ADC_SFRADDR_Register */ 609 610 /** 611 * @ingroup adc_registers 612 * @defgroup ADC_SFRWRDATA ADC_SFRWRDATA 613 * @brief SFR Write Data Register 614 * @{ 615 */ 616 #define MXC_F_ADC_SFRWRDATA_DATA_POS 0 /**< SFRWRDATA_DATA Position */ 617 #define MXC_F_ADC_SFRWRDATA_DATA ((uint32_t)(0xFFUL << MXC_F_ADC_SFRWRDATA_DATA_POS)) /**< SFRWRDATA_DATA Mask */ 618 619 /**@} end of group ADC_SFRWRDATA_Register */ 620 621 /** 622 * @ingroup adc_registers 623 * @defgroup ADC_SFRRDDATA ADC_SFRRDDATA 624 * @brief SFR Read Data Register 625 * @{ 626 */ 627 #define MXC_F_ADC_SFRRDDATA_DATA_POS 0 /**< SFRRDDATA_DATA Position */ 628 #define MXC_F_ADC_SFRRDDATA_DATA ((uint32_t)(0xFFUL << MXC_F_ADC_SFRRDDATA_DATA_POS)) /**< SFRRDDATA_DATA Mask */ 629 630 /**@} end of group ADC_SFRRDDATA_Register */ 631 632 /** 633 * @ingroup adc_registers 634 * @defgroup ADC_SFRSTATUS ADC_SFRSTATUS 635 * @brief SFR Status Register 636 * @{ 637 */ 638 #define MXC_F_ADC_SFRSTATUS_NACK_POS 0 /**< SFRSTATUS_NACK Position */ 639 #define MXC_F_ADC_SFRSTATUS_NACK ((uint32_t)(0x1UL << MXC_F_ADC_SFRSTATUS_NACK_POS)) /**< SFRSTATUS_NACK Mask */ 640 641 /**@} end of group ADC_SFRSTATUS_Register */ 642 643 #ifdef __cplusplus 644 } 645 #endif 646 647 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78002_INCLUDE_ADC_REGS_H_ 648
