1 /** 2 * @file uart_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup uart_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78000_INCLUDE_UART_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78000_INCLUDE_UART_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup uart 67 * @defgroup uart_registers UART_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module. 69 * @details UART Low Power Registers 70 */ 71 72 /** 73 * @ingroup uart_registers 74 * Structure type to access the UART Registers. 75 */ 76 typedef struct { 77 __IO uint32_t ctrl; /**< <tt>\b 0x0000:</tt> UART CTRL Register */ 78 __I uint32_t status; /**< <tt>\b 0x0004:</tt> UART STATUS Register */ 79 __IO uint32_t int_en; /**< <tt>\b 0x0008:</tt> UART INT_EN Register */ 80 __IO uint32_t int_fl; /**< <tt>\b 0x000C:</tt> UART INT_FL Register */ 81 __IO uint32_t clkdiv; /**< <tt>\b 0x0010:</tt> UART CLKDIV Register */ 82 __IO uint32_t osr; /**< <tt>\b 0x0014:</tt> UART OSR Register */ 83 __IO uint32_t txpeek; /**< <tt>\b 0x0018:</tt> UART TXPEEK Register */ 84 __IO uint32_t pnr; /**< <tt>\b 0x001C:</tt> UART PNR Register */ 85 __IO uint32_t fifo; /**< <tt>\b 0x0020:</tt> UART FIFO Register */ 86 __R uint32_t rsv_0x24_0x2f[3]; 87 __IO uint32_t dma; /**< <tt>\b 0x0030:</tt> UART DMA Register */ 88 __IO uint32_t wken; /**< <tt>\b 0x0034:</tt> UART WKEN Register */ 89 __IO uint32_t wkfl; /**< <tt>\b 0x0038:</tt> UART WKFL Register */ 90 } mxc_uart_regs_t; 91 92 /* Register offsets for module UART */ 93 /** 94 * @ingroup uart_registers 95 * @defgroup UART_Register_Offsets Register Offsets 96 * @brief UART Peripheral Register Offsets from the UART Base Peripheral Address. 97 * @{ 98 */ 99 #define MXC_R_UART_CTRL ((uint32_t)0x00000000UL) /**< Offset from UART Base Address: <tt> 0x0000</tt> */ 100 #define MXC_R_UART_STATUS ((uint32_t)0x00000004UL) /**< Offset from UART Base Address: <tt> 0x0004</tt> */ 101 #define MXC_R_UART_INT_EN ((uint32_t)0x00000008UL) /**< Offset from UART Base Address: <tt> 0x0008</tt> */ 102 #define MXC_R_UART_INT_FL ((uint32_t)0x0000000CUL) /**< Offset from UART Base Address: <tt> 0x000C</tt> */ 103 #define MXC_R_UART_CLKDIV ((uint32_t)0x00000010UL) /**< Offset from UART Base Address: <tt> 0x0010</tt> */ 104 #define MXC_R_UART_OSR ((uint32_t)0x00000014UL) /**< Offset from UART Base Address: <tt> 0x0014</tt> */ 105 #define MXC_R_UART_TXPEEK ((uint32_t)0x00000018UL) /**< Offset from UART Base Address: <tt> 0x0018</tt> */ 106 #define MXC_R_UART_PNR ((uint32_t)0x0000001CUL) /**< Offset from UART Base Address: <tt> 0x001C</tt> */ 107 #define MXC_R_UART_FIFO ((uint32_t)0x00000020UL) /**< Offset from UART Base Address: <tt> 0x0020</tt> */ 108 #define MXC_R_UART_DMA ((uint32_t)0x00000030UL) /**< Offset from UART Base Address: <tt> 0x0030</tt> */ 109 #define MXC_R_UART_WKEN ((uint32_t)0x00000034UL) /**< Offset from UART Base Address: <tt> 0x0034</tt> */ 110 #define MXC_R_UART_WKFL ((uint32_t)0x00000038UL) /**< Offset from UART Base Address: <tt> 0x0038</tt> */ 111 /**@} end of group uart_registers */ 112 113 /** 114 * @ingroup uart_registers 115 * @defgroup UART_CTRL UART_CTRL 116 * @brief Control register 117 * @{ 118 */ 119 #define MXC_F_UART_CTRL_RX_THD_VAL_POS 0 /**< CTRL_RX_THD_VAL Position */ 120 #define MXC_F_UART_CTRL_RX_THD_VAL ((uint32_t)(0xFUL << MXC_F_UART_CTRL_RX_THD_VAL_POS)) /**< CTRL_RX_THD_VAL Mask */ 121 122 #define MXC_F_UART_CTRL_PAR_EN_POS 4 /**< CTRL_PAR_EN Position */ 123 #define MXC_F_UART_CTRL_PAR_EN ((uint32_t)(0x1UL << MXC_F_UART_CTRL_PAR_EN_POS)) /**< CTRL_PAR_EN Mask */ 124 125 #define MXC_F_UART_CTRL_PAR_EO_POS 5 /**< CTRL_PAR_EO Position */ 126 #define MXC_F_UART_CTRL_PAR_EO ((uint32_t)(0x1UL << MXC_F_UART_CTRL_PAR_EO_POS)) /**< CTRL_PAR_EO Mask */ 127 128 #define MXC_F_UART_CTRL_PAR_MD_POS 6 /**< CTRL_PAR_MD Position */ 129 #define MXC_F_UART_CTRL_PAR_MD ((uint32_t)(0x1UL << MXC_F_UART_CTRL_PAR_MD_POS)) /**< CTRL_PAR_MD Mask */ 130 131 #define MXC_F_UART_CTRL_CTS_DIS_POS 7 /**< CTRL_CTS_DIS Position */ 132 #define MXC_F_UART_CTRL_CTS_DIS ((uint32_t)(0x1UL << MXC_F_UART_CTRL_CTS_DIS_POS)) /**< CTRL_CTS_DIS Mask */ 133 134 #define MXC_F_UART_CTRL_TX_FLUSH_POS 8 /**< CTRL_TX_FLUSH Position */ 135 #define MXC_F_UART_CTRL_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_UART_CTRL_TX_FLUSH_POS)) /**< CTRL_TX_FLUSH Mask */ 136 137 #define MXC_F_UART_CTRL_RX_FLUSH_POS 9 /**< CTRL_RX_FLUSH Position */ 138 #define MXC_F_UART_CTRL_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_UART_CTRL_RX_FLUSH_POS)) /**< CTRL_RX_FLUSH Mask */ 139 140 #define MXC_F_UART_CTRL_CHAR_SIZE_POS 10 /**< CTRL_CHAR_SIZE Position */ 141 #define MXC_F_UART_CTRL_CHAR_SIZE ((uint32_t)(0x3UL << MXC_F_UART_CTRL_CHAR_SIZE_POS)) /**< CTRL_CHAR_SIZE Mask */ 142 #define MXC_V_UART_CTRL_CHAR_SIZE_5BITS ((uint32_t)0x0UL) /**< CTRL_CHAR_SIZE_5BITS Value */ 143 #define MXC_S_UART_CTRL_CHAR_SIZE_5BITS (MXC_V_UART_CTRL_CHAR_SIZE_5BITS << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_5BITS Setting */ 144 #define MXC_V_UART_CTRL_CHAR_SIZE_6BITS ((uint32_t)0x1UL) /**< CTRL_CHAR_SIZE_6BITS Value */ 145 #define MXC_S_UART_CTRL_CHAR_SIZE_6BITS (MXC_V_UART_CTRL_CHAR_SIZE_6BITS << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_6BITS Setting */ 146 #define MXC_V_UART_CTRL_CHAR_SIZE_7BITS ((uint32_t)0x2UL) /**< CTRL_CHAR_SIZE_7BITS Value */ 147 #define MXC_S_UART_CTRL_CHAR_SIZE_7BITS (MXC_V_UART_CTRL_CHAR_SIZE_7BITS << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_7BITS Setting */ 148 #define MXC_V_UART_CTRL_CHAR_SIZE_8BITS ((uint32_t)0x3UL) /**< CTRL_CHAR_SIZE_8BITS Value */ 149 #define MXC_S_UART_CTRL_CHAR_SIZE_8BITS (MXC_V_UART_CTRL_CHAR_SIZE_8BITS << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_8BITS Setting */ 150 151 #define MXC_F_UART_CTRL_STOPBITS_POS 12 /**< CTRL_STOPBITS Position */ 152 #define MXC_F_UART_CTRL_STOPBITS ((uint32_t)(0x1UL << MXC_F_UART_CTRL_STOPBITS_POS)) /**< CTRL_STOPBITS Mask */ 153 154 #define MXC_F_UART_CTRL_HFC_EN_POS 13 /**< CTRL_HFC_EN Position */ 155 #define MXC_F_UART_CTRL_HFC_EN ((uint32_t)(0x1UL << MXC_F_UART_CTRL_HFC_EN_POS)) /**< CTRL_HFC_EN Mask */ 156 157 #define MXC_F_UART_CTRL_RTSDC_POS 14 /**< CTRL_RTSDC Position */ 158 #define MXC_F_UART_CTRL_RTSDC ((uint32_t)(0x1UL << MXC_F_UART_CTRL_RTSDC_POS)) /**< CTRL_RTSDC Mask */ 159 160 #define MXC_F_UART_CTRL_BCLKEN_POS 15 /**< CTRL_BCLKEN Position */ 161 #define MXC_F_UART_CTRL_BCLKEN ((uint32_t)(0x1UL << MXC_F_UART_CTRL_BCLKEN_POS)) /**< CTRL_BCLKEN Mask */ 162 163 #define MXC_F_UART_CTRL_BCLKSRC_POS 16 /**< CTRL_BCLKSRC Position */ 164 #define MXC_F_UART_CTRL_BCLKSRC ((uint32_t)(0x3UL << MXC_F_UART_CTRL_BCLKSRC_POS)) /**< CTRL_BCLKSRC Mask */ 165 #define MXC_V_UART_CTRL_BCLKSRC_PERIPHERAL_CLOCK ((uint32_t)0x0UL) /**< CTRL_BCLKSRC_PERIPHERAL_CLOCK Value */ 166 #define MXC_S_UART_CTRL_BCLKSRC_PERIPHERAL_CLOCK (MXC_V_UART_CTRL_BCLKSRC_PERIPHERAL_CLOCK << MXC_F_UART_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_PERIPHERAL_CLOCK Setting */ 167 #define MXC_V_UART_CTRL_BCLKSRC_EXTERNAL_CLOCK ((uint32_t)0x1UL) /**< CTRL_BCLKSRC_EXTERNAL_CLOCK Value */ 168 #define MXC_S_UART_CTRL_BCLKSRC_EXTERNAL_CLOCK (MXC_V_UART_CTRL_BCLKSRC_EXTERNAL_CLOCK << MXC_F_UART_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_EXTERNAL_CLOCK Setting */ 169 #define MXC_V_UART_CTRL_BCLKSRC_CLK2 ((uint32_t)0x2UL) /**< CTRL_BCLKSRC_CLK2 Value */ 170 #define MXC_S_UART_CTRL_BCLKSRC_CLK2 (MXC_V_UART_CTRL_BCLKSRC_CLK2 << MXC_F_UART_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_CLK2 Setting */ 171 #define MXC_V_UART_CTRL_BCLKSRC_CLK3 ((uint32_t)0x3UL) /**< CTRL_BCLKSRC_CLK3 Value */ 172 #define MXC_S_UART_CTRL_BCLKSRC_CLK3 (MXC_V_UART_CTRL_BCLKSRC_CLK3 << MXC_F_UART_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_CLK3 Setting */ 173 174 #define MXC_F_UART_CTRL_DPFE_EN_POS 18 /**< CTRL_DPFE_EN Position */ 175 #define MXC_F_UART_CTRL_DPFE_EN ((uint32_t)(0x1UL << MXC_F_UART_CTRL_DPFE_EN_POS)) /**< CTRL_DPFE_EN Mask */ 176 177 #define MXC_F_UART_CTRL_BCLKRDY_POS 19 /**< CTRL_BCLKRDY Position */ 178 #define MXC_F_UART_CTRL_BCLKRDY ((uint32_t)(0x1UL << MXC_F_UART_CTRL_BCLKRDY_POS)) /**< CTRL_BCLKRDY Mask */ 179 180 #define MXC_F_UART_CTRL_UCAGM_POS 20 /**< CTRL_UCAGM Position */ 181 #define MXC_F_UART_CTRL_UCAGM ((uint32_t)(0x1UL << MXC_F_UART_CTRL_UCAGM_POS)) /**< CTRL_UCAGM Mask */ 182 183 #define MXC_F_UART_CTRL_FDM_POS 21 /**< CTRL_FDM Position */ 184 #define MXC_F_UART_CTRL_FDM ((uint32_t)(0x1UL << MXC_F_UART_CTRL_FDM_POS)) /**< CTRL_FDM Mask */ 185 186 #define MXC_F_UART_CTRL_DESM_POS 22 /**< CTRL_DESM Position */ 187 #define MXC_F_UART_CTRL_DESM ((uint32_t)(0x1UL << MXC_F_UART_CTRL_DESM_POS)) /**< CTRL_DESM Mask */ 188 189 /**@} end of group UART_CTRL_Register */ 190 191 /** 192 * @ingroup uart_registers 193 * @defgroup UART_STATUS UART_STATUS 194 * @brief Status register 195 * @{ 196 */ 197 #define MXC_F_UART_STATUS_TX_BUSY_POS 0 /**< STATUS_TX_BUSY Position */ 198 #define MXC_F_UART_STATUS_TX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_BUSY_POS)) /**< STATUS_TX_BUSY Mask */ 199 200 #define MXC_F_UART_STATUS_RX_BUSY_POS 1 /**< STATUS_RX_BUSY Position */ 201 #define MXC_F_UART_STATUS_RX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_BUSY_POS)) /**< STATUS_RX_BUSY Mask */ 202 203 #define MXC_F_UART_STATUS_RX_EM_POS 4 /**< STATUS_RX_EM Position */ 204 #define MXC_F_UART_STATUS_RX_EM ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_EM_POS)) /**< STATUS_RX_EM Mask */ 205 206 #define MXC_F_UART_STATUS_RX_FULL_POS 5 /**< STATUS_RX_FULL Position */ 207 #define MXC_F_UART_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */ 208 209 #define MXC_F_UART_STATUS_TX_EM_POS 6 /**< STATUS_TX_EM Position */ 210 #define MXC_F_UART_STATUS_TX_EM ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_EM_POS)) /**< STATUS_TX_EM Mask */ 211 212 #define MXC_F_UART_STATUS_TX_FULL_POS 7 /**< STATUS_TX_FULL Position */ 213 #define MXC_F_UART_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */ 214 215 #define MXC_F_UART_STATUS_RX_LVL_POS 8 /**< STATUS_RX_LVL Position */ 216 #define MXC_F_UART_STATUS_RX_LVL ((uint32_t)(0xFUL << MXC_F_UART_STATUS_RX_LVL_POS)) /**< STATUS_RX_LVL Mask */ 217 218 #define MXC_F_UART_STATUS_TX_LVL_POS 12 /**< STATUS_TX_LVL Position */ 219 #define MXC_F_UART_STATUS_TX_LVL ((uint32_t)(0xFUL << MXC_F_UART_STATUS_TX_LVL_POS)) /**< STATUS_TX_LVL Mask */ 220 221 /**@} end of group UART_STATUS_Register */ 222 223 /** 224 * @ingroup uart_registers 225 * @defgroup UART_INT_EN UART_INT_EN 226 * @brief Interrupt Enable control register 227 * @{ 228 */ 229 #define MXC_F_UART_INT_EN_RX_FERR_POS 0 /**< INT_EN_RX_FERR Position */ 230 #define MXC_F_UART_INT_EN_RX_FERR ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_FERR_POS)) /**< INT_EN_RX_FERR Mask */ 231 232 #define MXC_F_UART_INT_EN_RX_PAR_POS 1 /**< INT_EN_RX_PAR Position */ 233 #define MXC_F_UART_INT_EN_RX_PAR ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_PAR_POS)) /**< INT_EN_RX_PAR Mask */ 234 235 #define MXC_F_UART_INT_EN_CTS_EV_POS 2 /**< INT_EN_CTS_EV Position */ 236 #define MXC_F_UART_INT_EN_CTS_EV ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_CTS_EV_POS)) /**< INT_EN_CTS_EV Mask */ 237 238 #define MXC_F_UART_INT_EN_RX_OV_POS 3 /**< INT_EN_RX_OV Position */ 239 #define MXC_F_UART_INT_EN_RX_OV ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_OV_POS)) /**< INT_EN_RX_OV Mask */ 240 241 #define MXC_F_UART_INT_EN_RX_THD_POS 4 /**< INT_EN_RX_THD Position */ 242 #define MXC_F_UART_INT_EN_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_RX_THD_POS)) /**< INT_EN_RX_THD Mask */ 243 244 #define MXC_F_UART_INT_EN_TX_OB_POS 5 /**< INT_EN_TX_OB Position */ 245 #define MXC_F_UART_INT_EN_TX_OB ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_TX_OB_POS)) /**< INT_EN_TX_OB Mask */ 246 247 #define MXC_F_UART_INT_EN_TX_HE_POS 6 /**< INT_EN_TX_HE Position */ 248 #define MXC_F_UART_INT_EN_TX_HE ((uint32_t)(0x1UL << MXC_F_UART_INT_EN_TX_HE_POS)) /**< INT_EN_TX_HE Mask */ 249 250 /**@} end of group UART_INT_EN_Register */ 251 252 /** 253 * @ingroup uart_registers 254 * @defgroup UART_INT_FL UART_INT_FL 255 * @brief Interrupt status flags Control register 256 * @{ 257 */ 258 #define MXC_F_UART_INT_FL_RX_FERR_POS 0 /**< INT_FL_RX_FERR Position */ 259 #define MXC_F_UART_INT_FL_RX_FERR ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_FERR_POS)) /**< INT_FL_RX_FERR Mask */ 260 261 #define MXC_F_UART_INT_FL_RX_PAR_POS 1 /**< INT_FL_RX_PAR Position */ 262 #define MXC_F_UART_INT_FL_RX_PAR ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_PAR_POS)) /**< INT_FL_RX_PAR Mask */ 263 264 #define MXC_F_UART_INT_FL_CTS_EV_POS 2 /**< INT_FL_CTS_EV Position */ 265 #define MXC_F_UART_INT_FL_CTS_EV ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_CTS_EV_POS)) /**< INT_FL_CTS_EV Mask */ 266 267 #define MXC_F_UART_INT_FL_RX_OV_POS 3 /**< INT_FL_RX_OV Position */ 268 #define MXC_F_UART_INT_FL_RX_OV ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_OV_POS)) /**< INT_FL_RX_OV Mask */ 269 270 #define MXC_F_UART_INT_FL_RX_THD_POS 4 /**< INT_FL_RX_THD Position */ 271 #define MXC_F_UART_INT_FL_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_RX_THD_POS)) /**< INT_FL_RX_THD Mask */ 272 273 #define MXC_F_UART_INT_FL_TX_OB_POS 5 /**< INT_FL_TX_OB Position */ 274 #define MXC_F_UART_INT_FL_TX_OB ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_TX_OB_POS)) /**< INT_FL_TX_OB Mask */ 275 276 #define MXC_F_UART_INT_FL_TX_HE_POS 6 /**< INT_FL_TX_HE Position */ 277 #define MXC_F_UART_INT_FL_TX_HE ((uint32_t)(0x1UL << MXC_F_UART_INT_FL_TX_HE_POS)) /**< INT_FL_TX_HE Mask */ 278 279 /**@} end of group UART_INT_FL_Register */ 280 281 /** 282 * @ingroup uart_registers 283 * @defgroup UART_CLKDIV UART_CLKDIV 284 * @brief Clock Divider register 285 * @{ 286 */ 287 #define MXC_F_UART_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */ 288 #define MXC_F_UART_CLKDIV_CLKDIV ((uint32_t)(0xFFFFFUL << MXC_F_UART_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */ 289 290 /**@} end of group UART_CLKDIV_Register */ 291 292 /** 293 * @ingroup uart_registers 294 * @defgroup UART_OSR UART_OSR 295 * @brief Over Sampling Rate register 296 * @{ 297 */ 298 #define MXC_F_UART_OSR_OSR_POS 0 /**< OSR_OSR Position */ 299 #define MXC_F_UART_OSR_OSR ((uint32_t)(0x7UL << MXC_F_UART_OSR_OSR_POS)) /**< OSR_OSR Mask */ 300 301 /**@} end of group UART_OSR_Register */ 302 303 /** 304 * @ingroup uart_registers 305 * @defgroup UART_TXPEEK UART_TXPEEK 306 * @brief TX FIFO Output Peek register 307 * @{ 308 */ 309 #define MXC_F_UART_TXPEEK_DATA_POS 0 /**< TXPEEK_DATA Position */ 310 #define MXC_F_UART_TXPEEK_DATA ((uint32_t)(0xFFUL << MXC_F_UART_TXPEEK_DATA_POS)) /**< TXPEEK_DATA Mask */ 311 312 /**@} end of group UART_TXPEEK_Register */ 313 314 /** 315 * @ingroup uart_registers 316 * @defgroup UART_PNR UART_PNR 317 * @brief Pin register 318 * @{ 319 */ 320 #define MXC_F_UART_PNR_CTS_POS 0 /**< PNR_CTS Position */ 321 #define MXC_F_UART_PNR_CTS ((uint32_t)(0x1UL << MXC_F_UART_PNR_CTS_POS)) /**< PNR_CTS Mask */ 322 323 #define MXC_F_UART_PNR_RTS_POS 1 /**< PNR_RTS Position */ 324 #define MXC_F_UART_PNR_RTS ((uint32_t)(0x1UL << MXC_F_UART_PNR_RTS_POS)) /**< PNR_RTS Mask */ 325 326 /**@} end of group UART_PNR_Register */ 327 328 /** 329 * @ingroup uart_registers 330 * @defgroup UART_FIFO UART_FIFO 331 * @brief FIFO Read/Write register 332 * @{ 333 */ 334 #define MXC_F_UART_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ 335 #define MXC_F_UART_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_UART_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ 336 337 #define MXC_F_UART_FIFO_RX_PAR_POS 8 /**< FIFO_RX_PAR Position */ 338 #define MXC_F_UART_FIFO_RX_PAR ((uint32_t)(0x1UL << MXC_F_UART_FIFO_RX_PAR_POS)) /**< FIFO_RX_PAR Mask */ 339 340 /**@} end of group UART_FIFO_Register */ 341 342 /** 343 * @ingroup uart_registers 344 * @defgroup UART_DMA UART_DMA 345 * @brief DMA Configuration register 346 * @{ 347 */ 348 #define MXC_F_UART_DMA_TX_THD_VAL_POS 0 /**< DMA_TX_THD_VAL Position */ 349 #define MXC_F_UART_DMA_TX_THD_VAL ((uint32_t)(0xFUL << MXC_F_UART_DMA_TX_THD_VAL_POS)) /**< DMA_TX_THD_VAL Mask */ 350 351 #define MXC_F_UART_DMA_TX_EN_POS 4 /**< DMA_TX_EN Position */ 352 #define MXC_F_UART_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_UART_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */ 353 354 #define MXC_F_UART_DMA_RX_THD_VAL_POS 5 /**< DMA_RX_THD_VAL Position */ 355 #define MXC_F_UART_DMA_RX_THD_VAL ((uint32_t)(0xFUL << MXC_F_UART_DMA_RX_THD_VAL_POS)) /**< DMA_RX_THD_VAL Mask */ 356 357 #define MXC_F_UART_DMA_RX_EN_POS 9 /**< DMA_RX_EN Position */ 358 #define MXC_F_UART_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_UART_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */ 359 360 /**@} end of group UART_DMA_Register */ 361 362 /** 363 * @ingroup uart_registers 364 * @defgroup UART_WKEN UART_WKEN 365 * @brief Wake up enable Control register 366 * @{ 367 */ 368 #define MXC_F_UART_WKEN_RX_NE_POS 0 /**< WKEN_RX_NE Position */ 369 #define MXC_F_UART_WKEN_RX_NE ((uint32_t)(0x1UL << MXC_F_UART_WKEN_RX_NE_POS)) /**< WKEN_RX_NE Mask */ 370 371 #define MXC_F_UART_WKEN_RX_FULL_POS 1 /**< WKEN_RX_FULL Position */ 372 #define MXC_F_UART_WKEN_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_WKEN_RX_FULL_POS)) /**< WKEN_RX_FULL Mask */ 373 374 #define MXC_F_UART_WKEN_RX_THD_POS 2 /**< WKEN_RX_THD Position */ 375 #define MXC_F_UART_WKEN_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_WKEN_RX_THD_POS)) /**< WKEN_RX_THD Mask */ 376 377 /**@} end of group UART_WKEN_Register */ 378 379 /** 380 * @ingroup uart_registers 381 * @defgroup UART_WKFL UART_WKFL 382 * @brief Wake up Flags register 383 * @{ 384 */ 385 #define MXC_F_UART_WKFL_RX_NE_POS 0 /**< WKFL_RX_NE Position */ 386 #define MXC_F_UART_WKFL_RX_NE ((uint32_t)(0x1UL << MXC_F_UART_WKFL_RX_NE_POS)) /**< WKFL_RX_NE Mask */ 387 388 #define MXC_F_UART_WKFL_RX_FULL_POS 1 /**< WKFL_RX_FULL Position */ 389 #define MXC_F_UART_WKFL_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_WKFL_RX_FULL_POS)) /**< WKFL_RX_FULL Mask */ 390 391 #define MXC_F_UART_WKFL_RX_THD_POS 2 /**< WKFL_RX_THD Position */ 392 #define MXC_F_UART_WKFL_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_WKFL_RX_THD_POS)) /**< WKFL_RX_THD Mask */ 393 394 /**@} end of group UART_WKFL_Register */ 395 396 #ifdef __cplusplus 397 } 398 #endif 399 400 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78000_INCLUDE_UART_REGS_H_ 401
