1 /** 2 * @file sir_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SIR Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup sir_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78000_INCLUDE_SIR_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78000_INCLUDE_SIR_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup sir 67 * @defgroup sir_registers SIR_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the SIR Peripheral Module. 69 * @details System Initialization Registers. 70 */ 71 72 /** 73 * @ingroup sir_registers 74 * Structure type to access the SIR Registers. 75 */ 76 typedef struct { 77 __I uint32_t sistat; /**< <tt>\b 0x00:</tt> SIR SISTAT Register */ 78 __I uint32_t addr; /**< <tt>\b 0x04:</tt> SIR ADDR Register */ 79 __R uint32_t rsv_0x8_0xff[62]; 80 __I uint32_t fstat; /**< <tt>\b 0x100:</tt> SIR FSTAT Register */ 81 __I uint32_t sfstat; /**< <tt>\b 0x104:</tt> SIR SFSTAT Register */ 82 } mxc_sir_regs_t; 83 84 /* Register offsets for module SIR */ 85 /** 86 * @ingroup sir_registers 87 * @defgroup SIR_Register_Offsets Register Offsets 88 * @brief SIR Peripheral Register Offsets from the SIR Base Peripheral Address. 89 * @{ 90 */ 91 #define MXC_R_SIR_SISTAT ((uint32_t)0x00000000UL) /**< Offset from SIR Base Address: <tt> 0x0000</tt> */ 92 #define MXC_R_SIR_ADDR ((uint32_t)0x00000004UL) /**< Offset from SIR Base Address: <tt> 0x0004</tt> */ 93 #define MXC_R_SIR_FSTAT ((uint32_t)0x00000100UL) /**< Offset from SIR Base Address: <tt> 0x0100</tt> */ 94 #define MXC_R_SIR_SFSTAT ((uint32_t)0x00000104UL) /**< Offset from SIR Base Address: <tt> 0x0104</tt> */ 95 /**@} end of group sir_registers */ 96 97 /** 98 * @ingroup sir_registers 99 * @defgroup SIR_SISTAT SIR_SISTAT 100 * @brief System Initialization Status Register. 101 * @{ 102 */ 103 #define MXC_F_SIR_SISTAT_MAGIC_POS 0 /**< SISTAT_MAGIC Position */ 104 #define MXC_F_SIR_SISTAT_MAGIC ((uint32_t)(0x1UL << MXC_F_SIR_SISTAT_MAGIC_POS)) /**< SISTAT_MAGIC Mask */ 105 106 #define MXC_F_SIR_SISTAT_CRCERR_POS 1 /**< SISTAT_CRCERR Position */ 107 #define MXC_F_SIR_SISTAT_CRCERR ((uint32_t)(0x1UL << MXC_F_SIR_SISTAT_CRCERR_POS)) /**< SISTAT_CRCERR Mask */ 108 109 /**@} end of group SIR_SISTAT_Register */ 110 111 /** 112 * @ingroup sir_registers 113 * @defgroup SIR_ADDR SIR_ADDR 114 * @brief Read-only field set by the SIB block if a CRC error occurs during the read of 115 * the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 116 * 1). 117 * @{ 118 */ 119 #define MXC_F_SIR_ADDR_ERRADDR_POS 0 /**< ADDR_ERRADDR Position */ 120 #define MXC_F_SIR_ADDR_ERRADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_SIR_ADDR_ERRADDR_POS)) /**< ADDR_ERRADDR Mask */ 121 122 /**@} end of group SIR_ADDR_Register */ 123 124 /** 125 * @ingroup sir_registers 126 * @defgroup SIR_FSTAT SIR_FSTAT 127 * @brief funcstat register. 128 * @{ 129 */ 130 #define MXC_F_SIR_FSTAT_FPU_POS 0 /**< FSTAT_FPU Position */ 131 #define MXC_F_SIR_FSTAT_FPU ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_FPU_POS)) /**< FSTAT_FPU Mask */ 132 133 #define MXC_F_SIR_FSTAT_ADC_POS 2 /**< FSTAT_ADC Position */ 134 #define MXC_F_SIR_FSTAT_ADC ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_ADC_POS)) /**< FSTAT_ADC Mask */ 135 136 #define MXC_F_SIR_FSTAT_SMPHR_POS 7 /**< FSTAT_SMPHR Position */ 137 #define MXC_F_SIR_FSTAT_SMPHR ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_SMPHR_POS)) /**< FSTAT_SMPHR Mask */ 138 139 /**@} end of group SIR_FSTAT_Register */ 140 141 /** 142 * @ingroup sir_registers 143 * @defgroup SIR_SFSTAT SIR_SFSTAT 144 * @brief Security function status register. 145 * @{ 146 */ 147 #define MXC_F_SIR_SFSTAT_TRNG_POS 0 /**< SFSTAT_TRNG Position */ 148 #define MXC_F_SIR_SFSTAT_TRNG ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_TRNG_POS)) /**< SFSTAT_TRNG Mask */ 149 150 #define MXC_F_SIR_SFSTAT_AES_POS 2 /**< SFSTAT_AES Position */ 151 #define MXC_F_SIR_SFSTAT_AES ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_AES_POS)) /**< SFSTAT_AES Mask */ 152 153 /**@} end of group SIR_SFSTAT_Register */ 154 155 #ifdef __cplusplus 156 } 157 #endif 158 159 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78000_INCLUDE_SIR_REGS_H_ 160
