1 /** 2 * @file ptg_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the PTG Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup ptg_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78000_INCLUDE_PTG_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78000_INCLUDE_PTG_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup ptg 67 * @defgroup ptg_registers PTG_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the PTG Peripheral Module. 69 * @details Pulse Train Generation 70 */ 71 72 /** 73 * @ingroup ptg_registers 74 * Structure type to access the PTG Registers. 75 */ 76 typedef struct { 77 __IO uint32_t enable; /**< <tt>\b 0x0000:</tt> PTG ENABLE Register */ 78 __IO uint32_t resync; /**< <tt>\b 0x0004:</tt> PTG RESYNC Register */ 79 __IO uint32_t intfl; /**< <tt>\b 0x0008:</tt> PTG INTFL Register */ 80 __IO uint32_t inten; /**< <tt>\b 0x000C:</tt> PTG INTEN Register */ 81 __O uint32_t safe_en; /**< <tt>\b 0x0010:</tt> PTG SAFE_EN Register */ 82 __O uint32_t safe_dis; /**< <tt>\b 0x0014:</tt> PTG SAFE_DIS Register */ 83 } mxc_ptg_regs_t; 84 85 /* Register offsets for module PTG */ 86 /** 87 * @ingroup ptg_registers 88 * @defgroup PTG_Register_Offsets Register Offsets 89 * @brief PTG Peripheral Register Offsets from the PTG Base Peripheral Address. 90 * @{ 91 */ 92 #define MXC_R_PTG_ENABLE ((uint32_t)0x00000000UL) /**< Offset from PTG Base Address: <tt> 0x0000</tt> */ 93 #define MXC_R_PTG_RESYNC ((uint32_t)0x00000004UL) /**< Offset from PTG Base Address: <tt> 0x0004</tt> */ 94 #define MXC_R_PTG_INTFL ((uint32_t)0x00000008UL) /**< Offset from PTG Base Address: <tt> 0x0008</tt> */ 95 #define MXC_R_PTG_INTEN ((uint32_t)0x0000000CUL) /**< Offset from PTG Base Address: <tt> 0x000C</tt> */ 96 #define MXC_R_PTG_SAFE_EN ((uint32_t)0x00000010UL) /**< Offset from PTG Base Address: <tt> 0x0010</tt> */ 97 #define MXC_R_PTG_SAFE_DIS ((uint32_t)0x00000014UL) /**< Offset from PTG Base Address: <tt> 0x0014</tt> */ 98 /**@} end of group ptg_registers */ 99 100 /** 101 * @ingroup ptg_registers 102 * @defgroup PTG_ENABLE PTG_ENABLE 103 * @brief Global Enable/Disable Controls for All Pulse Trains 104 * @{ 105 */ 106 #define MXC_F_PTG_ENABLE_PT0_POS 0 /**< ENABLE_PT0 Position */ 107 #define MXC_F_PTG_ENABLE_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT0_POS)) /**< ENABLE_PT0 Mask */ 108 109 #define MXC_F_PTG_ENABLE_PT1_POS 1 /**< ENABLE_PT1 Position */ 110 #define MXC_F_PTG_ENABLE_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT1_POS)) /**< ENABLE_PT1 Mask */ 111 112 #define MXC_F_PTG_ENABLE_PT2_POS 2 /**< ENABLE_PT2 Position */ 113 #define MXC_F_PTG_ENABLE_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT2_POS)) /**< ENABLE_PT2 Mask */ 114 115 #define MXC_F_PTG_ENABLE_PT3_POS 3 /**< ENABLE_PT3 Position */ 116 #define MXC_F_PTG_ENABLE_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT3_POS)) /**< ENABLE_PT3 Mask */ 117 118 /**@} end of group PTG_ENABLE_Register */ 119 120 /** 121 * @ingroup ptg_registers 122 * @defgroup PTG_RESYNC PTG_RESYNC 123 * @brief Global Resync (All Pulse Trains) Control 124 * @{ 125 */ 126 #define MXC_F_PTG_RESYNC_PT0_POS 0 /**< RESYNC_PT0 Position */ 127 #define MXC_F_PTG_RESYNC_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT0_POS)) /**< RESYNC_PT0 Mask */ 128 129 #define MXC_F_PTG_RESYNC_PT1_POS 1 /**< RESYNC_PT1 Position */ 130 #define MXC_F_PTG_RESYNC_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT1_POS)) /**< RESYNC_PT1 Mask */ 131 132 #define MXC_F_PTG_RESYNC_PT2_POS 2 /**< RESYNC_PT2 Position */ 133 #define MXC_F_PTG_RESYNC_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT2_POS)) /**< RESYNC_PT2 Mask */ 134 135 #define MXC_F_PTG_RESYNC_PT3_POS 3 /**< RESYNC_PT3 Position */ 136 #define MXC_F_PTG_RESYNC_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT3_POS)) /**< RESYNC_PT3 Mask */ 137 138 /**@} end of group PTG_RESYNC_Register */ 139 140 /** 141 * @ingroup ptg_registers 142 * @defgroup PTG_INTFL PTG_INTFL 143 * @brief Pulse Train Interrupt Flags 144 * @{ 145 */ 146 #define MXC_F_PTG_INTFL_PT0_POS 0 /**< INTFL_PT0 Position */ 147 #define MXC_F_PTG_INTFL_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_INTFL_PT0_POS)) /**< INTFL_PT0 Mask */ 148 149 #define MXC_F_PTG_INTFL_PT1_POS 1 /**< INTFL_PT1 Position */ 150 #define MXC_F_PTG_INTFL_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_INTFL_PT1_POS)) /**< INTFL_PT1 Mask */ 151 152 #define MXC_F_PTG_INTFL_PT2_POS 2 /**< INTFL_PT2 Position */ 153 #define MXC_F_PTG_INTFL_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_INTFL_PT2_POS)) /**< INTFL_PT2 Mask */ 154 155 #define MXC_F_PTG_INTFL_PT3_POS 3 /**< INTFL_PT3 Position */ 156 #define MXC_F_PTG_INTFL_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_INTFL_PT3_POS)) /**< INTFL_PT3 Mask */ 157 158 /**@} end of group PTG_INTFL_Register */ 159 160 /** 161 * @ingroup ptg_registers 162 * @defgroup PTG_INTEN PTG_INTEN 163 * @brief Pulse Train Interrupt Enable/Disable 164 * @{ 165 */ 166 #define MXC_F_PTG_INTEN_PT0_POS 0 /**< INTEN_PT0 Position */ 167 #define MXC_F_PTG_INTEN_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_INTEN_PT0_POS)) /**< INTEN_PT0 Mask */ 168 169 #define MXC_F_PTG_INTEN_PT1_POS 1 /**< INTEN_PT1 Position */ 170 #define MXC_F_PTG_INTEN_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_INTEN_PT1_POS)) /**< INTEN_PT1 Mask */ 171 172 #define MXC_F_PTG_INTEN_PT2_POS 2 /**< INTEN_PT2 Position */ 173 #define MXC_F_PTG_INTEN_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_INTEN_PT2_POS)) /**< INTEN_PT2 Mask */ 174 175 #define MXC_F_PTG_INTEN_PT3_POS 3 /**< INTEN_PT3 Position */ 176 #define MXC_F_PTG_INTEN_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_INTEN_PT3_POS)) /**< INTEN_PT3 Mask */ 177 178 /**@} end of group PTG_INTEN_Register */ 179 180 /** 181 * @ingroup ptg_registers 182 * @defgroup PTG_SAFE_EN PTG_SAFE_EN 183 * @brief Pulse Train Global Safe Enable. 184 * @{ 185 */ 186 #define MXC_F_PTG_SAFE_EN_PT0_POS 0 /**< SAFE_EN_PT0 Position */ 187 #define MXC_F_PTG_SAFE_EN_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT0_POS)) /**< SAFE_EN_PT0 Mask */ 188 189 #define MXC_F_PTG_SAFE_EN_PT1_POS 1 /**< SAFE_EN_PT1 Position */ 190 #define MXC_F_PTG_SAFE_EN_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT1_POS)) /**< SAFE_EN_PT1 Mask */ 191 192 #define MXC_F_PTG_SAFE_EN_PT2_POS 2 /**< SAFE_EN_PT2 Position */ 193 #define MXC_F_PTG_SAFE_EN_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT2_POS)) /**< SAFE_EN_PT2 Mask */ 194 195 #define MXC_F_PTG_SAFE_EN_PT3_POS 3 /**< SAFE_EN_PT3 Position */ 196 #define MXC_F_PTG_SAFE_EN_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT3_POS)) /**< SAFE_EN_PT3 Mask */ 197 198 /**@} end of group PTG_SAFE_EN_Register */ 199 200 /** 201 * @ingroup ptg_registers 202 * @defgroup PTG_SAFE_DIS PTG_SAFE_DIS 203 * @brief Pulse Train Global Safe Disable. 204 * @{ 205 */ 206 #define MXC_F_PTG_SAFE_DIS_PT0_POS 0 /**< SAFE_DIS_PT0 Position */ 207 #define MXC_F_PTG_SAFE_DIS_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT0_POS)) /**< SAFE_DIS_PT0 Mask */ 208 209 #define MXC_F_PTG_SAFE_DIS_PT1_POS 1 /**< SAFE_DIS_PT1 Position */ 210 #define MXC_F_PTG_SAFE_DIS_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT1_POS)) /**< SAFE_DIS_PT1 Mask */ 211 212 #define MXC_F_PTG_SAFE_DIS_PT2_POS 2 /**< SAFE_DIS_PT2 Position */ 213 #define MXC_F_PTG_SAFE_DIS_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT2_POS)) /**< SAFE_DIS_PT2 Mask */ 214 215 #define MXC_F_PTG_SAFE_DIS_PT3_POS 3 /**< SAFE_DIS_PT3 Position */ 216 #define MXC_F_PTG_SAFE_DIS_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT3_POS)) /**< SAFE_DIS_PT3 Mask */ 217 218 /**@} end of group PTG_SAFE_DIS_Register */ 219 220 #ifdef __cplusplus 221 } 222 #endif 223 224 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78000_INCLUDE_PTG_REGS_H_ 225
