1 /** 2 * @file owm_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the OWM Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup owm_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78000_INCLUDE_OWM_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78000_INCLUDE_OWM_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup owm 67 * @defgroup owm_registers OWM_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the OWM Peripheral Module. 69 * @details 1-Wire Master Interface. 70 */ 71 72 /** 73 * @ingroup owm_registers 74 * Structure type to access the OWM Registers. 75 */ 76 typedef struct { 77 __IO uint32_t cfg; /**< <tt>\b 0x0000:</tt> OWM CFG Register */ 78 __IO uint32_t clk_div_1us; /**< <tt>\b 0x0004:</tt> OWM CLK_DIV_1US Register */ 79 __IO uint32_t ctrl_stat; /**< <tt>\b 0x0008:</tt> OWM CTRL_STAT Register */ 80 __IO uint32_t data; /**< <tt>\b 0x000C:</tt> OWM DATA Register */ 81 __IO uint32_t intfl; /**< <tt>\b 0x0010:</tt> OWM INTFL Register */ 82 __IO uint32_t inten; /**< <tt>\b 0x0014:</tt> OWM INTEN Register */ 83 } mxc_owm_regs_t; 84 85 /* Register offsets for module OWM */ 86 /** 87 * @ingroup owm_registers 88 * @defgroup OWM_Register_Offsets Register Offsets 89 * @brief OWM Peripheral Register Offsets from the OWM Base Peripheral Address. 90 * @{ 91 */ 92 #define MXC_R_OWM_CFG ((uint32_t)0x00000000UL) /**< Offset from OWM Base Address: <tt> 0x0000</tt> */ 93 #define MXC_R_OWM_CLK_DIV_1US ((uint32_t)0x00000004UL) /**< Offset from OWM Base Address: <tt> 0x0004</tt> */ 94 #define MXC_R_OWM_CTRL_STAT ((uint32_t)0x00000008UL) /**< Offset from OWM Base Address: <tt> 0x0008</tt> */ 95 #define MXC_R_OWM_DATA ((uint32_t)0x0000000CUL) /**< Offset from OWM Base Address: <tt> 0x000C</tt> */ 96 #define MXC_R_OWM_INTFL ((uint32_t)0x00000010UL) /**< Offset from OWM Base Address: <tt> 0x0010</tt> */ 97 #define MXC_R_OWM_INTEN ((uint32_t)0x00000014UL) /**< Offset from OWM Base Address: <tt> 0x0014</tt> */ 98 /**@} end of group owm_registers */ 99 100 /** 101 * @ingroup owm_registers 102 * @defgroup OWM_CFG OWM_CFG 103 * @brief 1-Wire Master Configuration. 104 * @{ 105 */ 106 #define MXC_F_OWM_CFG_LONG_LINE_MODE_POS 0 /**< CFG_LONG_LINE_MODE Position */ 107 #define MXC_F_OWM_CFG_LONG_LINE_MODE ((uint32_t)(0x1UL << MXC_F_OWM_CFG_LONG_LINE_MODE_POS)) /**< CFG_LONG_LINE_MODE Mask */ 108 109 #define MXC_F_OWM_CFG_FORCE_PRES_DET_POS 1 /**< CFG_FORCE_PRES_DET Position */ 110 #define MXC_F_OWM_CFG_FORCE_PRES_DET ((uint32_t)(0x1UL << MXC_F_OWM_CFG_FORCE_PRES_DET_POS)) /**< CFG_FORCE_PRES_DET Mask */ 111 112 #define MXC_F_OWM_CFG_BIT_BANG_EN_POS 2 /**< CFG_BIT_BANG_EN Position */ 113 #define MXC_F_OWM_CFG_BIT_BANG_EN ((uint32_t)(0x1UL << MXC_F_OWM_CFG_BIT_BANG_EN_POS)) /**< CFG_BIT_BANG_EN Mask */ 114 115 #define MXC_F_OWM_CFG_EXT_PULLUP_MODE_POS 3 /**< CFG_EXT_PULLUP_MODE Position */ 116 #define MXC_F_OWM_CFG_EXT_PULLUP_MODE ((uint32_t)(0x1UL << MXC_F_OWM_CFG_EXT_PULLUP_MODE_POS)) /**< CFG_EXT_PULLUP_MODE Mask */ 117 118 #define MXC_F_OWM_CFG_EXT_PULLUP_ENABLE_POS 4 /**< CFG_EXT_PULLUP_ENABLE Position */ 119 #define MXC_F_OWM_CFG_EXT_PULLUP_ENABLE ((uint32_t)(0x1UL << MXC_F_OWM_CFG_EXT_PULLUP_ENABLE_POS)) /**< CFG_EXT_PULLUP_ENABLE Mask */ 120 121 #define MXC_F_OWM_CFG_SINGLE_BIT_MODE_POS 5 /**< CFG_SINGLE_BIT_MODE Position */ 122 #define MXC_F_OWM_CFG_SINGLE_BIT_MODE ((uint32_t)(0x1UL << MXC_F_OWM_CFG_SINGLE_BIT_MODE_POS)) /**< CFG_SINGLE_BIT_MODE Mask */ 123 124 #define MXC_F_OWM_CFG_OVERDRIVE_POS 6 /**< CFG_OVERDRIVE Position */ 125 #define MXC_F_OWM_CFG_OVERDRIVE ((uint32_t)(0x1UL << MXC_F_OWM_CFG_OVERDRIVE_POS)) /**< CFG_OVERDRIVE Mask */ 126 127 #define MXC_F_OWM_CFG_INT_PULLUP_ENABLE_POS 7 /**< CFG_INT_PULLUP_ENABLE Position */ 128 #define MXC_F_OWM_CFG_INT_PULLUP_ENABLE ((uint32_t)(0x1UL << MXC_F_OWM_CFG_INT_PULLUP_ENABLE_POS)) /**< CFG_INT_PULLUP_ENABLE Mask */ 129 130 /**@} end of group OWM_CFG_Register */ 131 132 /** 133 * @ingroup owm_registers 134 * @defgroup OWM_CLK_DIV_1US OWM_CLK_DIV_1US 135 * @brief 1-Wire Master Clock Divisor. 136 * @{ 137 */ 138 #define MXC_F_OWM_CLK_DIV_1US_DIVISOR_POS 0 /**< CLK_DIV_1US_DIVISOR Position */ 139 #define MXC_F_OWM_CLK_DIV_1US_DIVISOR ((uint32_t)(0xFFUL << MXC_F_OWM_CLK_DIV_1US_DIVISOR_POS)) /**< CLK_DIV_1US_DIVISOR Mask */ 140 141 /**@} end of group OWM_CLK_DIV_1US_Register */ 142 143 /** 144 * @ingroup owm_registers 145 * @defgroup OWM_CTRL_STAT OWM_CTRL_STAT 146 * @brief 1-Wire Master Control/Status. 147 * @{ 148 */ 149 #define MXC_F_OWM_CTRL_STAT_START_OW_RESET_POS 0 /**< CTRL_STAT_START_OW_RESET Position */ 150 #define MXC_F_OWM_CTRL_STAT_START_OW_RESET ((uint32_t)(0x1UL << MXC_F_OWM_CTRL_STAT_START_OW_RESET_POS)) /**< CTRL_STAT_START_OW_RESET Mask */ 151 152 #define MXC_F_OWM_CTRL_STAT_SRA_MODE_POS 1 /**< CTRL_STAT_SRA_MODE Position */ 153 #define MXC_F_OWM_CTRL_STAT_SRA_MODE ((uint32_t)(0x1UL << MXC_F_OWM_CTRL_STAT_SRA_MODE_POS)) /**< CTRL_STAT_SRA_MODE Mask */ 154 155 #define MXC_F_OWM_CTRL_STAT_BIT_BANG_OE_POS 2 /**< CTRL_STAT_BIT_BANG_OE Position */ 156 #define MXC_F_OWM_CTRL_STAT_BIT_BANG_OE ((uint32_t)(0x1UL << MXC_F_OWM_CTRL_STAT_BIT_BANG_OE_POS)) /**< CTRL_STAT_BIT_BANG_OE Mask */ 157 158 #define MXC_F_OWM_CTRL_STAT_OW_INPUT_POS 3 /**< CTRL_STAT_OW_INPUT Position */ 159 #define MXC_F_OWM_CTRL_STAT_OW_INPUT ((uint32_t)(0x1UL << MXC_F_OWM_CTRL_STAT_OW_INPUT_POS)) /**< CTRL_STAT_OW_INPUT Mask */ 160 161 #define MXC_F_OWM_CTRL_STAT_OD_SPEC_MODE_POS 4 /**< CTRL_STAT_OD_SPEC_MODE Position */ 162 #define MXC_F_OWM_CTRL_STAT_OD_SPEC_MODE ((uint32_t)(0x1UL << MXC_F_OWM_CTRL_STAT_OD_SPEC_MODE_POS)) /**< CTRL_STAT_OD_SPEC_MODE Mask */ 163 164 #define MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT_POS 7 /**< CTRL_STAT_PRESENCE_DETECT Position */ 165 #define MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT ((uint32_t)(0x1UL << MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT_POS)) /**< CTRL_STAT_PRESENCE_DETECT Mask */ 166 167 /**@} end of group OWM_CTRL_STAT_Register */ 168 169 /** 170 * @ingroup owm_registers 171 * @defgroup OWM_DATA OWM_DATA 172 * @brief 1-Wire Master Data Buffer. 173 * @{ 174 */ 175 #define MXC_F_OWM_DATA_TX_RX_POS 0 /**< DATA_TX_RX Position */ 176 #define MXC_F_OWM_DATA_TX_RX ((uint32_t)(0xFFUL << MXC_F_OWM_DATA_TX_RX_POS)) /**< DATA_TX_RX Mask */ 177 178 /**@} end of group OWM_DATA_Register */ 179 180 /** 181 * @ingroup owm_registers 182 * @defgroup OWM_INTFL OWM_INTFL 183 * @brief 1-Wire Master Interrupt Flags. 184 * @{ 185 */ 186 #define MXC_F_OWM_INTFL_OW_RESET_DONE_POS 0 /**< INTFL_OW_RESET_DONE Position */ 187 #define MXC_F_OWM_INTFL_OW_RESET_DONE ((uint32_t)(0x1UL << MXC_F_OWM_INTFL_OW_RESET_DONE_POS)) /**< INTFL_OW_RESET_DONE Mask */ 188 189 #define MXC_F_OWM_INTFL_TX_DATA_EMPTY_POS 1 /**< INTFL_TX_DATA_EMPTY Position */ 190 #define MXC_F_OWM_INTFL_TX_DATA_EMPTY ((uint32_t)(0x1UL << MXC_F_OWM_INTFL_TX_DATA_EMPTY_POS)) /**< INTFL_TX_DATA_EMPTY Mask */ 191 192 #define MXC_F_OWM_INTFL_RX_DATA_READY_POS 2 /**< INTFL_RX_DATA_READY Position */ 193 #define MXC_F_OWM_INTFL_RX_DATA_READY ((uint32_t)(0x1UL << MXC_F_OWM_INTFL_RX_DATA_READY_POS)) /**< INTFL_RX_DATA_READY Mask */ 194 195 #define MXC_F_OWM_INTFL_LINE_SHORT_POS 3 /**< INTFL_LINE_SHORT Position */ 196 #define MXC_F_OWM_INTFL_LINE_SHORT ((uint32_t)(0x1UL << MXC_F_OWM_INTFL_LINE_SHORT_POS)) /**< INTFL_LINE_SHORT Mask */ 197 198 #define MXC_F_OWM_INTFL_LINE_LOW_POS 4 /**< INTFL_LINE_LOW Position */ 199 #define MXC_F_OWM_INTFL_LINE_LOW ((uint32_t)(0x1UL << MXC_F_OWM_INTFL_LINE_LOW_POS)) /**< INTFL_LINE_LOW Mask */ 200 201 /**@} end of group OWM_INTFL_Register */ 202 203 /** 204 * @ingroup owm_registers 205 * @defgroup OWM_INTEN OWM_INTEN 206 * @brief 1-Wire Master Interrupt Enables. 207 * @{ 208 */ 209 #define MXC_F_OWM_INTEN_OW_RESET_DONE_POS 0 /**< INTEN_OW_RESET_DONE Position */ 210 #define MXC_F_OWM_INTEN_OW_RESET_DONE ((uint32_t)(0x1UL << MXC_F_OWM_INTEN_OW_RESET_DONE_POS)) /**< INTEN_OW_RESET_DONE Mask */ 211 212 #define MXC_F_OWM_INTEN_TX_DATA_EMPTY_POS 1 /**< INTEN_TX_DATA_EMPTY Position */ 213 #define MXC_F_OWM_INTEN_TX_DATA_EMPTY ((uint32_t)(0x1UL << MXC_F_OWM_INTEN_TX_DATA_EMPTY_POS)) /**< INTEN_TX_DATA_EMPTY Mask */ 214 215 #define MXC_F_OWM_INTEN_RX_DATA_READY_POS 2 /**< INTEN_RX_DATA_READY Position */ 216 #define MXC_F_OWM_INTEN_RX_DATA_READY ((uint32_t)(0x1UL << MXC_F_OWM_INTEN_RX_DATA_READY_POS)) /**< INTEN_RX_DATA_READY Mask */ 217 218 #define MXC_F_OWM_INTEN_LINE_SHORT_POS 3 /**< INTEN_LINE_SHORT Position */ 219 #define MXC_F_OWM_INTEN_LINE_SHORT ((uint32_t)(0x1UL << MXC_F_OWM_INTEN_LINE_SHORT_POS)) /**< INTEN_LINE_SHORT Mask */ 220 221 #define MXC_F_OWM_INTEN_LINE_LOW_POS 4 /**< INTEN_LINE_LOW Position */ 222 #define MXC_F_OWM_INTEN_LINE_LOW ((uint32_t)(0x1UL << MXC_F_OWM_INTEN_LINE_LOW_POS)) /**< INTEN_LINE_LOW Mask */ 223 224 /**@} end of group OWM_INTEN_Register */ 225 226 #ifdef __cplusplus 227 } 228 #endif 229 230 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78000_INCLUDE_OWM_REGS_H_ 231
