1 /** 2 * @file gcr_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup gcr_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78000_INCLUDE_GCR_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78000_INCLUDE_GCR_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup gcr 67 * @defgroup gcr_registers GCR_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module. 69 * @details Global Control Registers. 70 */ 71 72 /** 73 * @ingroup gcr_registers 74 * Structure type to access the GCR Registers. 75 */ 76 typedef struct { 77 __IO uint32_t sysctrl; /**< <tt>\b 0x00:</tt> GCR SYSCTRL Register */ 78 __IO uint32_t rst0; /**< <tt>\b 0x04:</tt> GCR RST0 Register */ 79 __IO uint32_t clkctrl; /**< <tt>\b 0x08:</tt> GCR CLKCTRL Register */ 80 __IO uint32_t pm; /**< <tt>\b 0x0C:</tt> GCR PM Register */ 81 __R uint32_t rsv_0x10_0x17[2]; 82 __IO uint32_t pclkdiv; /**< <tt>\b 0x18:</tt> GCR PCLKDIV Register */ 83 __R uint32_t rsv_0x1c_0x23[2]; 84 __IO uint32_t pclkdis0; /**< <tt>\b 0x24:</tt> GCR PCLKDIS0 Register */ 85 __IO uint32_t memctrl; /**< <tt>\b 0x28:</tt> GCR MEMCTRL Register */ 86 __IO uint32_t memz; /**< <tt>\b 0x2C:</tt> GCR MEMZ Register */ 87 __R uint32_t rsv_0x30_0x3f[4]; 88 __IO uint32_t sysst; /**< <tt>\b 0x40:</tt> GCR SYSST Register */ 89 __IO uint32_t rst1; /**< <tt>\b 0x44:</tt> GCR RST1 Register */ 90 __IO uint32_t pclkdis1; /**< <tt>\b 0x48:</tt> GCR PCLKDIS1 Register */ 91 __IO uint32_t eventen; /**< <tt>\b 0x4C:</tt> GCR EVENTEN Register */ 92 __I uint32_t revision; /**< <tt>\b 0x50:</tt> GCR REVISION Register */ 93 __IO uint32_t sysie; /**< <tt>\b 0x54:</tt> GCR SYSIE Register */ 94 __R uint32_t rsv_0x58_0x63[3]; 95 __IO uint32_t eccerr; /**< <tt>\b 0x64:</tt> GCR ECCERR Register */ 96 __IO uint32_t eccced; /**< <tt>\b 0x68:</tt> GCR ECCCED Register */ 97 __IO uint32_t eccie; /**< <tt>\b 0x6C:</tt> GCR ECCIE Register */ 98 __IO uint32_t eccaddr; /**< <tt>\b 0x70:</tt> GCR ECCADDR Register */ 99 __R uint32_t rsv_0x74_0x7f[3]; 100 __IO uint32_t gpr; /**< <tt>\b 0x80:</tt> GCR GPR Register */ 101 } mxc_gcr_regs_t; 102 103 /* Register offsets for module GCR */ 104 /** 105 * @ingroup gcr_registers 106 * @defgroup GCR_Register_Offsets Register Offsets 107 * @brief GCR Peripheral Register Offsets from the GCR Base Peripheral Address. 108 * @{ 109 */ 110 #define MXC_R_GCR_SYSCTRL ((uint32_t)0x00000000UL) /**< Offset from GCR Base Address: <tt> 0x0000</tt> */ 111 #define MXC_R_GCR_RST0 ((uint32_t)0x00000004UL) /**< Offset from GCR Base Address: <tt> 0x0004</tt> */ 112 #define MXC_R_GCR_CLKCTRL ((uint32_t)0x00000008UL) /**< Offset from GCR Base Address: <tt> 0x0008</tt> */ 113 #define MXC_R_GCR_PM ((uint32_t)0x0000000CUL) /**< Offset from GCR Base Address: <tt> 0x000C</tt> */ 114 #define MXC_R_GCR_PCLKDIV ((uint32_t)0x00000018UL) /**< Offset from GCR Base Address: <tt> 0x0018</tt> */ 115 #define MXC_R_GCR_PCLKDIS0 ((uint32_t)0x00000024UL) /**< Offset from GCR Base Address: <tt> 0x0024</tt> */ 116 #define MXC_R_GCR_MEMCTRL ((uint32_t)0x00000028UL) /**< Offset from GCR Base Address: <tt> 0x0028</tt> */ 117 #define MXC_R_GCR_MEMZ ((uint32_t)0x0000002CUL) /**< Offset from GCR Base Address: <tt> 0x002C</tt> */ 118 #define MXC_R_GCR_SYSST ((uint32_t)0x00000040UL) /**< Offset from GCR Base Address: <tt> 0x0040</tt> */ 119 #define MXC_R_GCR_RST1 ((uint32_t)0x00000044UL) /**< Offset from GCR Base Address: <tt> 0x0044</tt> */ 120 #define MXC_R_GCR_PCLKDIS1 ((uint32_t)0x00000048UL) /**< Offset from GCR Base Address: <tt> 0x0048</tt> */ 121 #define MXC_R_GCR_EVENTEN ((uint32_t)0x0000004CUL) /**< Offset from GCR Base Address: <tt> 0x004C</tt> */ 122 #define MXC_R_GCR_REVISION ((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: <tt> 0x0050</tt> */ 123 #define MXC_R_GCR_SYSIE ((uint32_t)0x00000054UL) /**< Offset from GCR Base Address: <tt> 0x0054</tt> */ 124 #define MXC_R_GCR_ECCERR ((uint32_t)0x00000064UL) /**< Offset from GCR Base Address: <tt> 0x0064</tt> */ 125 #define MXC_R_GCR_ECCCED ((uint32_t)0x00000068UL) /**< Offset from GCR Base Address: <tt> 0x0068</tt> */ 126 #define MXC_R_GCR_ECCIE ((uint32_t)0x0000006CUL) /**< Offset from GCR Base Address: <tt> 0x006C</tt> */ 127 #define MXC_R_GCR_ECCADDR ((uint32_t)0x00000070UL) /**< Offset from GCR Base Address: <tt> 0x0070</tt> */ 128 #define MXC_R_GCR_GPR ((uint32_t)0x00000080UL) /**< Offset from GCR Base Address: <tt> 0x0080</tt> */ 129 /**@} end of group gcr_registers */ 130 131 /** 132 * @ingroup gcr_registers 133 * @defgroup GCR_SYSCTRL GCR_SYSCTRL 134 * @brief System Control. 135 * @{ 136 */ 137 #define MXC_F_GCR_SYSCTRL_BSTAPEN_POS 1 /**< SYSCTRL_BSTAPEN Position */ 138 #define MXC_F_GCR_SYSCTRL_BSTAPEN ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_BSTAPEN_POS)) /**< SYSCTRL_BSTAPEN Mask */ 139 140 #define MXC_F_GCR_SYSCTRL_FLASH_PAGE_FLIP_POS 4 /**< SYSCTRL_FLASH_PAGE_FLIP Position */ 141 #define MXC_F_GCR_SYSCTRL_FLASH_PAGE_FLIP ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_FLASH_PAGE_FLIP_POS)) /**< SYSCTRL_FLASH_PAGE_FLIP Mask */ 142 143 #define MXC_F_GCR_SYSCTRL_ICC0_FLUSH_POS 6 /**< SYSCTRL_ICC0_FLUSH Position */ 144 #define MXC_F_GCR_SYSCTRL_ICC0_FLUSH ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_ICC0_FLUSH_POS)) /**< SYSCTRL_ICC0_FLUSH Mask */ 145 146 #define MXC_F_GCR_SYSCTRL_ROMDONE_POS 12 /**< SYSCTRL_ROMDONE Position */ 147 #define MXC_F_GCR_SYSCTRL_ROMDONE ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_ROMDONE_POS)) /**< SYSCTRL_ROMDONE Mask */ 148 149 #define MXC_F_GCR_SYSCTRL_CCHK_POS 13 /**< SYSCTRL_CCHK Position */ 150 #define MXC_F_GCR_SYSCTRL_CCHK ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CCHK_POS)) /**< SYSCTRL_CCHK Mask */ 151 152 #define MXC_F_GCR_SYSCTRL_SWD_DIS_POS 14 /**< SYSCTRL_SWD_DIS Position */ 153 #define MXC_F_GCR_SYSCTRL_SWD_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_SWD_DIS_POS)) /**< SYSCTRL_SWD_DIS Mask */ 154 155 #define MXC_F_GCR_SYSCTRL_CHKRES_POS 15 /**< SYSCTRL_CHKRES Position */ 156 #define MXC_F_GCR_SYSCTRL_CHKRES ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CHKRES_POS)) /**< SYSCTRL_CHKRES Mask */ 157 158 #define MXC_F_GCR_SYSCTRL_OVR_POS 16 /**< SYSCTRL_OVR Position */ 159 #define MXC_F_GCR_SYSCTRL_OVR ((uint32_t)(0x3UL << MXC_F_GCR_SYSCTRL_OVR_POS)) /**< SYSCTRL_OVR Mask */ 160 161 /**@} end of group GCR_SYSCTRL_Register */ 162 163 /** 164 * @ingroup gcr_registers 165 * @defgroup GCR_RST0 GCR_RST0 166 * @brief Reset. 167 * @{ 168 */ 169 #define MXC_F_GCR_RST0_DMA_POS 0 /**< RST0_DMA Position */ 170 #define MXC_F_GCR_RST0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_RST0_DMA_POS)) /**< RST0_DMA Mask */ 171 172 #define MXC_F_GCR_RST0_WDT0_POS 1 /**< RST0_WDT0 Position */ 173 #define MXC_F_GCR_RST0_WDT0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_WDT0_POS)) /**< RST0_WDT0 Mask */ 174 175 #define MXC_F_GCR_RST0_GPIO0_POS 2 /**< RST0_GPIO0 Position */ 176 #define MXC_F_GCR_RST0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO0_POS)) /**< RST0_GPIO0 Mask */ 177 178 #define MXC_F_GCR_RST0_GPIO1_POS 3 /**< RST0_GPIO1 Position */ 179 #define MXC_F_GCR_RST0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO1_POS)) /**< RST0_GPIO1 Mask */ 180 181 #define MXC_F_GCR_RST0_TMR0_POS 5 /**< RST0_TMR0 Position */ 182 #define MXC_F_GCR_RST0_TMR0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR0_POS)) /**< RST0_TMR0 Mask */ 183 184 #define MXC_F_GCR_RST0_TMR1_POS 6 /**< RST0_TMR1 Position */ 185 #define MXC_F_GCR_RST0_TMR1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR1_POS)) /**< RST0_TMR1 Mask */ 186 187 #define MXC_F_GCR_RST0_TMR2_POS 7 /**< RST0_TMR2 Position */ 188 #define MXC_F_GCR_RST0_TMR2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR2_POS)) /**< RST0_TMR2 Mask */ 189 190 #define MXC_F_GCR_RST0_TMR3_POS 8 /**< RST0_TMR3 Position */ 191 #define MXC_F_GCR_RST0_TMR3 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR3_POS)) /**< RST0_TMR3 Mask */ 192 193 #define MXC_F_GCR_RST0_UART0_POS 11 /**< RST0_UART0 Position */ 194 #define MXC_F_GCR_RST0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART0_POS)) /**< RST0_UART0 Mask */ 195 196 #define MXC_F_GCR_RST0_UART1_POS 12 /**< RST0_UART1 Position */ 197 #define MXC_F_GCR_RST0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART1_POS)) /**< RST0_UART1 Mask */ 198 199 #define MXC_F_GCR_RST0_SPI1_POS 13 /**< RST0_SPI1 Position */ 200 #define MXC_F_GCR_RST0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI1_POS)) /**< RST0_SPI1 Mask */ 201 202 #define MXC_F_GCR_RST0_I2C0_POS 16 /**< RST0_I2C0 Position */ 203 #define MXC_F_GCR_RST0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_I2C0_POS)) /**< RST0_I2C0 Mask */ 204 205 #define MXC_F_GCR_RST0_RTC_POS 17 /**< RST0_RTC Position */ 206 #define MXC_F_GCR_RST0_RTC ((uint32_t)(0x1UL << MXC_F_GCR_RST0_RTC_POS)) /**< RST0_RTC Mask */ 207 208 #define MXC_F_GCR_RST0_SMPHR_POS 22 /**< RST0_SMPHR Position */ 209 #define MXC_F_GCR_RST0_SMPHR ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SMPHR_POS)) /**< RST0_SMPHR Mask */ 210 211 #define MXC_F_GCR_RST0_TRNG_POS 24 /**< RST0_TRNG Position */ 212 #define MXC_F_GCR_RST0_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TRNG_POS)) /**< RST0_TRNG Mask */ 213 214 #define MXC_F_GCR_RST0_CNN_POS 25 /**< RST0_CNN Position */ 215 #define MXC_F_GCR_RST0_CNN ((uint32_t)(0x1UL << MXC_F_GCR_RST0_CNN_POS)) /**< RST0_CNN Mask */ 216 217 #define MXC_F_GCR_RST0_ADC_POS 26 /**< RST0_ADC Position */ 218 #define MXC_F_GCR_RST0_ADC ((uint32_t)(0x1UL << MXC_F_GCR_RST0_ADC_POS)) /**< RST0_ADC Mask */ 219 220 #define MXC_F_GCR_RST0_UART2_POS 28 /**< RST0_UART2 Position */ 221 #define MXC_F_GCR_RST0_UART2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART2_POS)) /**< RST0_UART2 Mask */ 222 223 #define MXC_F_GCR_RST0_SOFT_POS 29 /**< RST0_SOFT Position */ 224 #define MXC_F_GCR_RST0_SOFT ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SOFT_POS)) /**< RST0_SOFT Mask */ 225 226 #define MXC_F_GCR_RST0_PERIPH_POS 30 /**< RST0_PERIPH Position */ 227 #define MXC_F_GCR_RST0_PERIPH ((uint32_t)(0x1UL << MXC_F_GCR_RST0_PERIPH_POS)) /**< RST0_PERIPH Mask */ 228 229 #define MXC_F_GCR_RST0_SYS_POS 31 /**< RST0_SYS Position */ 230 #define MXC_F_GCR_RST0_SYS ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SYS_POS)) /**< RST0_SYS Mask */ 231 232 /**@} end of group GCR_RST0_Register */ 233 234 /** 235 * @ingroup gcr_registers 236 * @defgroup GCR_CLKCTRL GCR_CLKCTRL 237 * @brief Clock Control. 238 * @{ 239 */ 240 #define MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS 6 /**< CLKCTRL_SYSCLK_DIV Position */ 241 #define MXC_F_GCR_CLKCTRL_SYSCLK_DIV ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS)) /**< CLKCTRL_SYSCLK_DIV Mask */ 242 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV1 ((uint32_t)0x0UL) /**< CLKCTRL_SYSCLK_DIV_DIV1 Value */ 243 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV1 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV1 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV1 Setting */ 244 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV2 ((uint32_t)0x1UL) /**< CLKCTRL_SYSCLK_DIV_DIV2 Value */ 245 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV2 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV2 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV2 Setting */ 246 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV4 ((uint32_t)0x2UL) /**< CLKCTRL_SYSCLK_DIV_DIV4 Value */ 247 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV4 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV4 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV4 Setting */ 248 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV8 ((uint32_t)0x3UL) /**< CLKCTRL_SYSCLK_DIV_DIV8 Value */ 249 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV8 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV8 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV8 Setting */ 250 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV16 ((uint32_t)0x4UL) /**< CLKCTRL_SYSCLK_DIV_DIV16 Value */ 251 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV16 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV16 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV16 Setting */ 252 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV32 ((uint32_t)0x5UL) /**< CLKCTRL_SYSCLK_DIV_DIV32 Value */ 253 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV32 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV32 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV32 Setting */ 254 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV64 ((uint32_t)0x6UL) /**< CLKCTRL_SYSCLK_DIV_DIV64 Value */ 255 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV64 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV64 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV64 Setting */ 256 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV128 ((uint32_t)0x7UL) /**< CLKCTRL_SYSCLK_DIV_DIV128 Value */ 257 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV128 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV128 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV128 Setting */ 258 259 #define MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS 9 /**< CLKCTRL_SYSCLK_SEL Position */ 260 #define MXC_F_GCR_CLKCTRL_SYSCLK_SEL ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS)) /**< CLKCTRL_SYSCLK_SEL Mask */ 261 #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ISO ((uint32_t)0x0UL) /**< CLKCTRL_SYSCLK_SEL_ISO Value */ 262 #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ISO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ISO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_ISO Setting */ 263 #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO ((uint32_t)0x3UL) /**< CLKCTRL_SYSCLK_SEL_INRO Value */ 264 #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_INRO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_INRO Setting */ 265 #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO ((uint32_t)0x4UL) /**< CLKCTRL_SYSCLK_SEL_IPO Value */ 266 #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_IPO Setting */ 267 #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO ((uint32_t)0x5UL) /**< CLKCTRL_SYSCLK_SEL_IBRO Value */ 268 #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IBRO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_IBRO Setting */ 269 #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO ((uint32_t)0x6UL) /**< CLKCTRL_SYSCLK_SEL_ERTCO Value */ 270 #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERTCO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_ERTCO Setting */ 271 #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK ((uint32_t)0x7UL) /**< CLKCTRL_SYSCLK_SEL_EXTCLK Value */ 272 #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_EXTCLK Setting */ 273 274 #define MXC_F_GCR_CLKCTRL_SYSCLK_RDY_POS 13 /**< CLKCTRL_SYSCLK_RDY Position */ 275 #define MXC_F_GCR_CLKCTRL_SYSCLK_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_SYSCLK_RDY_POS)) /**< CLKCTRL_SYSCLK_RDY Mask */ 276 277 #define MXC_F_GCR_CLKCTRL_ERTCO_EN_POS 17 /**< CLKCTRL_ERTCO_EN Position */ 278 #define MXC_F_GCR_CLKCTRL_ERTCO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERTCO_EN_POS)) /**< CLKCTRL_ERTCO_EN Mask */ 279 280 #define MXC_F_GCR_CLKCTRL_ISO_EN_POS 18 /**< CLKCTRL_ISO_EN Position */ 281 #define MXC_F_GCR_CLKCTRL_ISO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ISO_EN_POS)) /**< CLKCTRL_ISO_EN Mask */ 282 283 #define MXC_F_GCR_CLKCTRL_IPO_EN_POS 19 /**< CLKCTRL_IPO_EN Position */ 284 #define MXC_F_GCR_CLKCTRL_IPO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IPO_EN_POS)) /**< CLKCTRL_IPO_EN Mask */ 285 286 #define MXC_F_GCR_CLKCTRL_IBRO_EN_POS 20 /**< CLKCTRL_IBRO_EN Position */ 287 #define MXC_F_GCR_CLKCTRL_IBRO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_EN_POS)) /**< CLKCTRL_IBRO_EN Mask */ 288 289 #define MXC_F_GCR_CLKCTRL_IBRO_VS_POS 21 /**< CLKCTRL_IBRO_VS Position */ 290 #define MXC_F_GCR_CLKCTRL_IBRO_VS ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_VS_POS)) /**< CLKCTRL_IBRO_VS Mask */ 291 292 #define MXC_F_GCR_CLKCTRL_ERTCO_RDY_POS 25 /**< CLKCTRL_ERTCO_RDY Position */ 293 #define MXC_F_GCR_CLKCTRL_ERTCO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERTCO_RDY_POS)) /**< CLKCTRL_ERTCO_RDY Mask */ 294 295 #define MXC_F_GCR_CLKCTRL_ISO_RDY_POS 26 /**< CLKCTRL_ISO_RDY Position */ 296 #define MXC_F_GCR_CLKCTRL_ISO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ISO_RDY_POS)) /**< CLKCTRL_ISO_RDY Mask */ 297 298 #define MXC_F_GCR_CLKCTRL_IPO_RDY_POS 27 /**< CLKCTRL_IPO_RDY Position */ 299 #define MXC_F_GCR_CLKCTRL_IPO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IPO_RDY_POS)) /**< CLKCTRL_IPO_RDY Mask */ 300 301 #define MXC_F_GCR_CLKCTRL_IBRO_RDY_POS 28 /**< CLKCTRL_IBRO_RDY Position */ 302 #define MXC_F_GCR_CLKCTRL_IBRO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_RDY_POS)) /**< CLKCTRL_IBRO_RDY Mask */ 303 304 #define MXC_F_GCR_CLKCTRL_INRO_RDY_POS 29 /**< CLKCTRL_INRO_RDY Position */ 305 #define MXC_F_GCR_CLKCTRL_INRO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_INRO_RDY_POS)) /**< CLKCTRL_INRO_RDY Mask */ 306 307 /**@} end of group GCR_CLKCTRL_Register */ 308 309 /** 310 * @ingroup gcr_registers 311 * @defgroup GCR_PM GCR_PM 312 * @brief Power Management. 313 * @{ 314 */ 315 #define MXC_F_GCR_PM_MODE_POS 0 /**< PM_MODE Position */ 316 #define MXC_F_GCR_PM_MODE ((uint32_t)(0xFUL << MXC_F_GCR_PM_MODE_POS)) /**< PM_MODE Mask */ 317 #define MXC_V_GCR_PM_MODE_ACTIVE ((uint32_t)0x0UL) /**< PM_MODE_ACTIVE Value */ 318 #define MXC_S_GCR_PM_MODE_ACTIVE (MXC_V_GCR_PM_MODE_ACTIVE << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_ACTIVE Setting */ 319 #define MXC_V_GCR_PM_MODE_SLEEP ((uint32_t)0x1UL) /**< PM_MODE_SLEEP Value */ 320 #define MXC_S_GCR_PM_MODE_SLEEP (MXC_V_GCR_PM_MODE_SLEEP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_SLEEP Setting */ 321 #define MXC_V_GCR_PM_MODE_STANDBY ((uint32_t)0x2UL) /**< PM_MODE_STANDBY Value */ 322 #define MXC_S_GCR_PM_MODE_STANDBY (MXC_V_GCR_PM_MODE_STANDBY << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_STANDBY Setting */ 323 #define MXC_V_GCR_PM_MODE_BACKUP ((uint32_t)0x4UL) /**< PM_MODE_BACKUP Value */ 324 #define MXC_S_GCR_PM_MODE_BACKUP (MXC_V_GCR_PM_MODE_BACKUP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_BACKUP Setting */ 325 #define MXC_V_GCR_PM_MODE_LPM ((uint32_t)0x8UL) /**< PM_MODE_LPM Value */ 326 #define MXC_S_GCR_PM_MODE_LPM (MXC_V_GCR_PM_MODE_LPM << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_LPM Setting */ 327 #define MXC_V_GCR_PM_MODE_UPM ((uint32_t)0x9UL) /**< PM_MODE_UPM Value */ 328 #define MXC_S_GCR_PM_MODE_UPM (MXC_V_GCR_PM_MODE_UPM << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_UPM Setting */ 329 #define MXC_V_GCR_PM_MODE_POWERDOWN ((uint32_t)0xAUL) /**< PM_MODE_POWERDOWN Value */ 330 #define MXC_S_GCR_PM_MODE_POWERDOWN (MXC_V_GCR_PM_MODE_POWERDOWN << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_POWERDOWN Setting */ 331 332 #define MXC_F_GCR_PM_GPIO_WE_POS 4 /**< PM_GPIO_WE Position */ 333 #define MXC_F_GCR_PM_GPIO_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_GPIO_WE_POS)) /**< PM_GPIO_WE Mask */ 334 335 #define MXC_F_GCR_PM_RTC_WE_POS 5 /**< PM_RTC_WE Position */ 336 #define MXC_F_GCR_PM_RTC_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_RTC_WE_POS)) /**< PM_RTC_WE Mask */ 337 338 #define MXC_F_GCR_PM_WUT_WE_POS 7 /**< PM_WUT_WE Position */ 339 #define MXC_F_GCR_PM_WUT_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_WUT_WE_POS)) /**< PM_WUT_WE Mask */ 340 341 #define MXC_F_GCR_PM_AINCOMP_WE_POS 9 /**< PM_AINCOMP_WE Position */ 342 #define MXC_F_GCR_PM_AINCOMP_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_AINCOMP_WE_POS)) /**< PM_AINCOMP_WE Mask */ 343 344 #define MXC_F_GCR_PM_ISO_PD_POS 15 /**< PM_ISO_PD Position */ 345 #define MXC_F_GCR_PM_ISO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_ISO_PD_POS)) /**< PM_ISO_PD Mask */ 346 347 #define MXC_F_GCR_PM_IPO_PD_POS 16 /**< PM_IPO_PD Position */ 348 #define MXC_F_GCR_PM_IPO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_IPO_PD_POS)) /**< PM_IPO_PD Mask */ 349 350 #define MXC_F_GCR_PM_IBRO_PD_POS 17 /**< PM_IBRO_PD Position */ 351 #define MXC_F_GCR_PM_IBRO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_IBRO_PD_POS)) /**< PM_IBRO_PD Mask */ 352 353 /**@} end of group GCR_PM_Register */ 354 355 /** 356 * @ingroup gcr_registers 357 * @defgroup GCR_PCLKDIV GCR_PCLKDIV 358 * @brief Peripheral Clock Divider. 359 * @{ 360 */ 361 #define MXC_F_GCR_PCLKDIV_ADCFRQ_POS 10 /**< PCLKDIV_ADCFRQ Position */ 362 #define MXC_F_GCR_PCLKDIV_ADCFRQ ((uint32_t)(0xFUL << MXC_F_GCR_PCLKDIV_ADCFRQ_POS)) /**< PCLKDIV_ADCFRQ Mask */ 363 364 #define MXC_F_GCR_PCLKDIV_CNNCLKDIV_POS 14 /**< PCLKDIV_CNNCLKDIV Position */ 365 #define MXC_F_GCR_PCLKDIV_CNNCLKDIV ((uint32_t)(0x7UL << MXC_F_GCR_PCLKDIV_CNNCLKDIV_POS)) /**< PCLKDIV_CNNCLKDIV Mask */ 366 #define MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV2 ((uint32_t)0x0UL) /**< PCLKDIV_CNNCLKDIV_DIV2 Value */ 367 #define MXC_S_GCR_PCLKDIV_CNNCLKDIV_DIV2 (MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV2 << MXC_F_GCR_PCLKDIV_CNNCLKDIV_POS) /**< PCLKDIV_CNNCLKDIV_DIV2 Setting */ 368 #define MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV4 ((uint32_t)0x1UL) /**< PCLKDIV_CNNCLKDIV_DIV4 Value */ 369 #define MXC_S_GCR_PCLKDIV_CNNCLKDIV_DIV4 (MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV4 << MXC_F_GCR_PCLKDIV_CNNCLKDIV_POS) /**< PCLKDIV_CNNCLKDIV_DIV4 Setting */ 370 #define MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV8 ((uint32_t)0x2UL) /**< PCLKDIV_CNNCLKDIV_DIV8 Value */ 371 #define MXC_S_GCR_PCLKDIV_CNNCLKDIV_DIV8 (MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV8 << MXC_F_GCR_PCLKDIV_CNNCLKDIV_POS) /**< PCLKDIV_CNNCLKDIV_DIV8 Setting */ 372 #define MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV16 ((uint32_t)0x3UL) /**< PCLKDIV_CNNCLKDIV_DIV16 Value */ 373 #define MXC_S_GCR_PCLKDIV_CNNCLKDIV_DIV16 (MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV16 << MXC_F_GCR_PCLKDIV_CNNCLKDIV_POS) /**< PCLKDIV_CNNCLKDIV_DIV16 Setting */ 374 #define MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV1 ((uint32_t)0x4UL) /**< PCLKDIV_CNNCLKDIV_DIV1 Value */ 375 #define MXC_S_GCR_PCLKDIV_CNNCLKDIV_DIV1 (MXC_V_GCR_PCLKDIV_CNNCLKDIV_DIV1 << MXC_F_GCR_PCLKDIV_CNNCLKDIV_POS) /**< PCLKDIV_CNNCLKDIV_DIV1 Setting */ 376 377 #define MXC_F_GCR_PCLKDIV_CNNCLKSEL_POS 17 /**< PCLKDIV_CNNCLKSEL Position */ 378 #define MXC_F_GCR_PCLKDIV_CNNCLKSEL ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIV_CNNCLKSEL_POS)) /**< PCLKDIV_CNNCLKSEL Mask */ 379 380 /**@} end of group GCR_PCLKDIV_Register */ 381 382 /** 383 * @ingroup gcr_registers 384 * @defgroup GCR_PCLKDIS0 GCR_PCLKDIS0 385 * @brief Peripheral Clock Disable. 386 * @{ 387 */ 388 #define MXC_F_GCR_PCLKDIS0_GPIO0_POS 0 /**< PCLKDIS0_GPIO0 Position */ 389 #define MXC_F_GCR_PCLKDIS0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_GPIO0_POS)) /**< PCLKDIS0_GPIO0 Mask */ 390 391 #define MXC_F_GCR_PCLKDIS0_GPIO1_POS 1 /**< PCLKDIS0_GPIO1 Position */ 392 #define MXC_F_GCR_PCLKDIS0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_GPIO1_POS)) /**< PCLKDIS0_GPIO1 Mask */ 393 394 #define MXC_F_GCR_PCLKDIS0_DMA_POS 5 /**< PCLKDIS0_DMA Position */ 395 #define MXC_F_GCR_PCLKDIS0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_DMA_POS)) /**< PCLKDIS0_DMA Mask */ 396 397 #define MXC_F_GCR_PCLKDIS0_SPI1_POS 6 /**< PCLKDIS0_SPI1 Position */ 398 #define MXC_F_GCR_PCLKDIS0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI1_POS)) /**< PCLKDIS0_SPI1 Mask */ 399 400 #define MXC_F_GCR_PCLKDIS0_UART0_POS 9 /**< PCLKDIS0_UART0 Position */ 401 #define MXC_F_GCR_PCLKDIS0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_UART0_POS)) /**< PCLKDIS0_UART0 Mask */ 402 403 #define MXC_F_GCR_PCLKDIS0_UART1_POS 10 /**< PCLKDIS0_UART1 Position */ 404 #define MXC_F_GCR_PCLKDIS0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_UART1_POS)) /**< PCLKDIS0_UART1 Mask */ 405 406 #define MXC_F_GCR_PCLKDIS0_I2C0_POS 13 /**< PCLKDIS0_I2C0 Position */ 407 #define MXC_F_GCR_PCLKDIS0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_I2C0_POS)) /**< PCLKDIS0_I2C0 Mask */ 408 409 #define MXC_F_GCR_PCLKDIS0_TMR0_POS 15 /**< PCLKDIS0_TMR0 Position */ 410 #define MXC_F_GCR_PCLKDIS0_TMR0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR0_POS)) /**< PCLKDIS0_TMR0 Mask */ 411 412 #define MXC_F_GCR_PCLKDIS0_TMR1_POS 16 /**< PCLKDIS0_TMR1 Position */ 413 #define MXC_F_GCR_PCLKDIS0_TMR1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR1_POS)) /**< PCLKDIS0_TMR1 Mask */ 414 415 #define MXC_F_GCR_PCLKDIS0_TMR2_POS 17 /**< PCLKDIS0_TMR2 Position */ 416 #define MXC_F_GCR_PCLKDIS0_TMR2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR2_POS)) /**< PCLKDIS0_TMR2 Mask */ 417 418 #define MXC_F_GCR_PCLKDIS0_TMR3_POS 18 /**< PCLKDIS0_TMR3 Position */ 419 #define MXC_F_GCR_PCLKDIS0_TMR3 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR3_POS)) /**< PCLKDIS0_TMR3 Mask */ 420 421 #define MXC_F_GCR_PCLKDIS0_ADC_POS 23 /**< PCLKDIS0_ADC Position */ 422 #define MXC_F_GCR_PCLKDIS0_ADC ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_ADC_POS)) /**< PCLKDIS0_ADC Mask */ 423 424 #define MXC_F_GCR_PCLKDIS0_CNN_POS 25 /**< PCLKDIS0_CNN Position */ 425 #define MXC_F_GCR_PCLKDIS0_CNN ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_CNN_POS)) /**< PCLKDIS0_CNN Mask */ 426 427 #define MXC_F_GCR_PCLKDIS0_I2C1_POS 28 /**< PCLKDIS0_I2C1 Position */ 428 #define MXC_F_GCR_PCLKDIS0_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_I2C1_POS)) /**< PCLKDIS0_I2C1 Mask */ 429 430 #define MXC_F_GCR_PCLKDIS0_PT_POS 29 /**< PCLKDIS0_PT Position */ 431 #define MXC_F_GCR_PCLKDIS0_PT ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_PT_POS)) /**< PCLKDIS0_PT Mask */ 432 433 /**@} end of group GCR_PCLKDIS0_Register */ 434 435 /** 436 * @ingroup gcr_registers 437 * @defgroup GCR_MEMCTRL GCR_MEMCTRL 438 * @brief Memory Clock Control Register. 439 * @{ 440 */ 441 #define MXC_F_GCR_MEMCTRL_FWS_POS 0 /**< MEMCTRL_FWS Position */ 442 #define MXC_F_GCR_MEMCTRL_FWS ((uint32_t)(0x7UL << MXC_F_GCR_MEMCTRL_FWS_POS)) /**< MEMCTRL_FWS Mask */ 443 444 #define MXC_F_GCR_MEMCTRL_SYSRAM0ECC_POS 16 /**< MEMCTRL_SYSRAM0ECC Position */ 445 #define MXC_F_GCR_MEMCTRL_SYSRAM0ECC ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_SYSRAM0ECC_POS)) /**< MEMCTRL_SYSRAM0ECC Mask */ 446 447 /**@} end of group GCR_MEMCTRL_Register */ 448 449 /** 450 * @ingroup gcr_registers 451 * @defgroup GCR_MEMZ GCR_MEMZ 452 * @brief Memory Zeroize Control. 453 * @{ 454 */ 455 #define MXC_F_GCR_MEMZ_RAM0_POS 0 /**< MEMZ_RAM0 Position */ 456 #define MXC_F_GCR_MEMZ_RAM0 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM0_POS)) /**< MEMZ_RAM0 Mask */ 457 458 #define MXC_F_GCR_MEMZ_RAM1_POS 1 /**< MEMZ_RAM1 Position */ 459 #define MXC_F_GCR_MEMZ_RAM1 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM1_POS)) /**< MEMZ_RAM1 Mask */ 460 461 #define MXC_F_GCR_MEMZ_RAM2_POS 2 /**< MEMZ_RAM2 Position */ 462 #define MXC_F_GCR_MEMZ_RAM2 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM2_POS)) /**< MEMZ_RAM2 Mask */ 463 464 #define MXC_F_GCR_MEMZ_RAM3_POS 3 /**< MEMZ_RAM3 Position */ 465 #define MXC_F_GCR_MEMZ_RAM3 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM3_POS)) /**< MEMZ_RAM3 Mask */ 466 467 #define MXC_F_GCR_MEMZ_SYSRAM0ECC_POS 4 /**< MEMZ_SYSRAM0ECC Position */ 468 #define MXC_F_GCR_MEMZ_SYSRAM0ECC ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_SYSRAM0ECC_POS)) /**< MEMZ_SYSRAM0ECC Mask */ 469 470 #define MXC_F_GCR_MEMZ_ICC0_POS 5 /**< MEMZ_ICC0 Position */ 471 #define MXC_F_GCR_MEMZ_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_ICC0_POS)) /**< MEMZ_ICC0 Mask */ 472 473 #define MXC_F_GCR_MEMZ_ICC1_POS 6 /**< MEMZ_ICC1 Position */ 474 #define MXC_F_GCR_MEMZ_ICC1 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_ICC1_POS)) /**< MEMZ_ICC1 Mask */ 475 476 /**@} end of group GCR_MEMZ_Register */ 477 478 /** 479 * @ingroup gcr_registers 480 * @defgroup GCR_SYSST GCR_SYSST 481 * @brief System Status Register. 482 * @{ 483 */ 484 #define MXC_F_GCR_SYSST_ICELOCK_POS 0 /**< SYSST_ICELOCK Position */ 485 #define MXC_F_GCR_SYSST_ICELOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_ICELOCK_POS)) /**< SYSST_ICELOCK Mask */ 486 487 /**@} end of group GCR_SYSST_Register */ 488 489 /** 490 * @ingroup gcr_registers 491 * @defgroup GCR_RST1 GCR_RST1 492 * @brief Reset 1. 493 * @{ 494 */ 495 #define MXC_F_GCR_RST1_I2C1_POS 0 /**< RST1_I2C1 Position */ 496 #define MXC_F_GCR_RST1_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C1_POS)) /**< RST1_I2C1 Mask */ 497 498 #define MXC_F_GCR_RST1_PT_POS 1 /**< RST1_PT Position */ 499 #define MXC_F_GCR_RST1_PT ((uint32_t)(0x1UL << MXC_F_GCR_RST1_PT_POS)) /**< RST1_PT Mask */ 500 501 #define MXC_F_GCR_RST1_OWM_POS 7 /**< RST1_OWM Position */ 502 #define MXC_F_GCR_RST1_OWM ((uint32_t)(0x1UL << MXC_F_GCR_RST1_OWM_POS)) /**< RST1_OWM Mask */ 503 504 #define MXC_F_GCR_RST1_CRC_POS 9 /**< RST1_CRC Position */ 505 #define MXC_F_GCR_RST1_CRC ((uint32_t)(0x1UL << MXC_F_GCR_RST1_CRC_POS)) /**< RST1_CRC Mask */ 506 507 #define MXC_F_GCR_RST1_AES_POS 10 /**< RST1_AES Position */ 508 #define MXC_F_GCR_RST1_AES ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AES_POS)) /**< RST1_AES Mask */ 509 510 #define MXC_F_GCR_RST1_SPI0_POS 11 /**< RST1_SPI0 Position */ 511 #define MXC_F_GCR_RST1_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SPI0_POS)) /**< RST1_SPI0 Mask */ 512 513 #define MXC_F_GCR_RST1_SMPHR_POS 16 /**< RST1_SMPHR Position */ 514 #define MXC_F_GCR_RST1_SMPHR ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SMPHR_POS)) /**< RST1_SMPHR Mask */ 515 516 #define MXC_F_GCR_RST1_I2S_POS 19 /**< RST1_I2S Position */ 517 #define MXC_F_GCR_RST1_I2S ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2S_POS)) /**< RST1_I2S Mask */ 518 519 #define MXC_F_GCR_RST1_I2C2_POS 20 /**< RST1_I2C2 Position */ 520 #define MXC_F_GCR_RST1_I2C2 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C2_POS)) /**< RST1_I2C2 Mask */ 521 522 #define MXC_F_GCR_RST1_DVS_POS 24 /**< RST1_DVS Position */ 523 #define MXC_F_GCR_RST1_DVS ((uint32_t)(0x1UL << MXC_F_GCR_RST1_DVS_POS)) /**< RST1_DVS Mask */ 524 525 #define MXC_F_GCR_RST1_SIMO_POS 25 /**< RST1_SIMO Position */ 526 #define MXC_F_GCR_RST1_SIMO ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SIMO_POS)) /**< RST1_SIMO Mask */ 527 528 #define MXC_F_GCR_RST1_CPU1_POS 31 /**< RST1_CPU1 Position */ 529 #define MXC_F_GCR_RST1_CPU1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_CPU1_POS)) /**< RST1_CPU1 Mask */ 530 531 /**@} end of group GCR_RST1_Register */ 532 533 /** 534 * @ingroup gcr_registers 535 * @defgroup GCR_PCLKDIS1 GCR_PCLKDIS1 536 * @brief Peripheral Clock Disable. 537 * @{ 538 */ 539 #define MXC_F_GCR_PCLKDIS1_UART2_POS 1 /**< PCLKDIS1_UART2 Position */ 540 #define MXC_F_GCR_PCLKDIS1_UART2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_UART2_POS)) /**< PCLKDIS1_UART2 Mask */ 541 542 #define MXC_F_GCR_PCLKDIS1_TRNG_POS 2 /**< PCLKDIS1_TRNG Position */ 543 #define MXC_F_GCR_PCLKDIS1_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_TRNG_POS)) /**< PCLKDIS1_TRNG Mask */ 544 545 #define MXC_F_GCR_PCLKDIS1_SMPHR_POS 9 /**< PCLKDIS1_SMPHR Position */ 546 #define MXC_F_GCR_PCLKDIS1_SMPHR ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_SMPHR_POS)) /**< PCLKDIS1_SMPHR Mask */ 547 548 #define MXC_F_GCR_PCLKDIS1_OWM_POS 13 /**< PCLKDIS1_OWM Position */ 549 #define MXC_F_GCR_PCLKDIS1_OWM ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_OWM_POS)) /**< PCLKDIS1_OWM Mask */ 550 551 #define MXC_F_GCR_PCLKDIS1_CRC_POS 14 /**< PCLKDIS1_CRC Position */ 552 #define MXC_F_GCR_PCLKDIS1_CRC ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_CRC_POS)) /**< PCLKDIS1_CRC Mask */ 553 554 #define MXC_F_GCR_PCLKDIS1_AES_POS 15 /**< PCLKDIS1_AES Position */ 555 #define MXC_F_GCR_PCLKDIS1_AES ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_AES_POS)) /**< PCLKDIS1_AES Mask */ 556 557 #define MXC_F_GCR_PCLKDIS1_SPI0_POS 16 /**< PCLKDIS1_SPI0 Position */ 558 #define MXC_F_GCR_PCLKDIS1_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_SPI0_POS)) /**< PCLKDIS1_SPI0 Mask */ 559 560 #define MXC_F_GCR_PCLKDIS1_PCIF_POS 18 /**< PCLKDIS1_PCIF Position */ 561 #define MXC_F_GCR_PCLKDIS1_PCIF ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_PCIF_POS)) /**< PCLKDIS1_PCIF Mask */ 562 563 #define MXC_F_GCR_PCLKDIS1_I2S_POS 23 /**< PCLKDIS1_I2S Position */ 564 #define MXC_F_GCR_PCLKDIS1_I2S ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_I2S_POS)) /**< PCLKDIS1_I2S Mask */ 565 566 #define MXC_F_GCR_PCLKDIS1_I2C2_POS 24 /**< PCLKDIS1_I2C2 Position */ 567 #define MXC_F_GCR_PCLKDIS1_I2C2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_I2C2_POS)) /**< PCLKDIS1_I2C2 Mask */ 568 569 #define MXC_F_GCR_PCLKDIS1_WDT0_POS 27 /**< PCLKDIS1_WDT0 Position */ 570 #define MXC_F_GCR_PCLKDIS1_WDT0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_WDT0_POS)) /**< PCLKDIS1_WDT0 Mask */ 571 572 #define MXC_F_GCR_PCLKDIS1_CPU1_POS 31 /**< PCLKDIS1_CPU1 Position */ 573 #define MXC_F_GCR_PCLKDIS1_CPU1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_CPU1_POS)) /**< PCLKDIS1_CPU1 Mask */ 574 575 /**@} end of group GCR_PCLKDIS1_Register */ 576 577 /** 578 * @ingroup gcr_registers 579 * @defgroup GCR_EVENTEN GCR_EVENTEN 580 * @brief Event Enable Register. 581 * @{ 582 */ 583 #define MXC_F_GCR_EVENTEN_DMA_POS 0 /**< EVENTEN_DMA Position */ 584 #define MXC_F_GCR_EVENTEN_DMA ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_DMA_POS)) /**< EVENTEN_DMA Mask */ 585 586 #define MXC_F_GCR_EVENTEN_RX_POS 1 /**< EVENTEN_RX Position */ 587 #define MXC_F_GCR_EVENTEN_RX ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_RX_POS)) /**< EVENTEN_RX Mask */ 588 589 #define MXC_F_GCR_EVENTEN_TX_POS 2 /**< EVENTEN_TX Position */ 590 #define MXC_F_GCR_EVENTEN_TX ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_TX_POS)) /**< EVENTEN_TX Mask */ 591 592 /**@} end of group GCR_EVENTEN_Register */ 593 594 /** 595 * @ingroup gcr_registers 596 * @defgroup GCR_REVISION GCR_REVISION 597 * @brief Revision Register. 598 * @{ 599 */ 600 #define MXC_F_GCR_REVISION_REVISION_POS 0 /**< REVISION_REVISION Position */ 601 #define MXC_F_GCR_REVISION_REVISION ((uint32_t)(0xFFFFUL << MXC_F_GCR_REVISION_REVISION_POS)) /**< REVISION_REVISION Mask */ 602 603 /**@} end of group GCR_REVISION_Register */ 604 605 /** 606 * @ingroup gcr_registers 607 * @defgroup GCR_SYSIE GCR_SYSIE 608 * @brief System Status Interrupt Enable Register. 609 * @{ 610 */ 611 #define MXC_F_GCR_SYSIE_ICEUNLOCK_POS 0 /**< SYSIE_ICEUNLOCK Position */ 612 #define MXC_F_GCR_SYSIE_ICEUNLOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYSIE_ICEUNLOCK_POS)) /**< SYSIE_ICEUNLOCK Mask */ 613 614 /**@} end of group GCR_SYSIE_Register */ 615 616 /** 617 * @ingroup gcr_registers 618 * @defgroup GCR_ECCERR GCR_ECCERR 619 * @brief ECC Error Register 620 * @{ 621 */ 622 #define MXC_F_GCR_ECCERR_RAM_POS 0 /**< ECCERR_RAM Position */ 623 #define MXC_F_GCR_ECCERR_RAM ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM_POS)) /**< ECCERR_RAM Mask */ 624 625 /**@} end of group GCR_ECCERR_Register */ 626 627 /** 628 * @ingroup gcr_registers 629 * @defgroup GCR_ECCCED GCR_ECCCED 630 * @brief ECC Not Double Error Detect Register 631 * @{ 632 */ 633 #define MXC_F_GCR_ECCCED_RAM_POS 0 /**< ECCCED_RAM Position */ 634 #define MXC_F_GCR_ECCCED_RAM ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM_POS)) /**< ECCCED_RAM Mask */ 635 636 /**@} end of group GCR_ECCCED_Register */ 637 638 /** 639 * @ingroup gcr_registers 640 * @defgroup GCR_ECCIE GCR_ECCIE 641 * @brief ECC IRQ Enable Register 642 * @{ 643 */ 644 #define MXC_F_GCR_ECCIE_RAM_POS 0 /**< ECCIE_RAM Position */ 645 #define MXC_F_GCR_ECCIE_RAM ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_RAM_POS)) /**< ECCIE_RAM Mask */ 646 647 /**@} end of group GCR_ECCIE_Register */ 648 649 /** 650 * @ingroup gcr_registers 651 * @defgroup GCR_ECCADDR GCR_ECCADDR 652 * @brief ECC Error Address Register 653 * @{ 654 */ 655 #define MXC_F_GCR_ECCADDR_ECCERRAD_POS 0 /**< ECCADDR_ECCERRAD Position */ 656 #define MXC_F_GCR_ECCADDR_ECCERRAD ((uint32_t)(0xFFFFFFFFUL << MXC_F_GCR_ECCADDR_ECCERRAD_POS)) /**< ECCADDR_ECCERRAD Mask */ 657 658 /**@} end of group GCR_ECCADDR_Register */ 659 660 #ifdef __cplusplus 661 } 662 #endif 663 664 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78000_INCLUDE_GCR_REGS_H_ 665
