1 /** 2 * @file fcr_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the FCR Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup fcr_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78000_INCLUDE_FCR_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78000_INCLUDE_FCR_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup fcr 67 * @defgroup fcr_registers FCR_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the FCR Peripheral Module. 69 * @details Function Control Register. 70 */ 71 72 /** 73 * @ingroup fcr_registers 74 * Structure type to access the FCR Registers. 75 */ 76 typedef struct { 77 __IO uint32_t fctrl0; /**< <tt>\b 0x00:</tt> FCR FCTRL0 Register */ 78 __IO uint32_t autocal0; /**< <tt>\b 0x04:</tt> FCR AUTOCAL0 Register */ 79 __IO uint32_t autocal1; /**< <tt>\b 0x08:</tt> FCR AUTOCAL1 Register */ 80 __IO uint32_t autocal2; /**< <tt>\b 0x0C:</tt> FCR AUTOCAL2 Register */ 81 __IO uint32_t urvbootaddr; /**< <tt>\b 0x10:</tt> FCR URVBOOTADDR Register */ 82 __IO uint32_t urvctrl; /**< <tt>\b 0x14:</tt> FCR URVCTRL Register */ 83 } mxc_fcr_regs_t; 84 85 /* Register offsets for module FCR */ 86 /** 87 * @ingroup fcr_registers 88 * @defgroup FCR_Register_Offsets Register Offsets 89 * @brief FCR Peripheral Register Offsets from the FCR Base Peripheral Address. 90 * @{ 91 */ 92 #define MXC_R_FCR_FCTRL0 ((uint32_t)0x00000000UL) /**< Offset from FCR Base Address: <tt> 0x0000</tt> */ 93 #define MXC_R_FCR_AUTOCAL0 ((uint32_t)0x00000004UL) /**< Offset from FCR Base Address: <tt> 0x0004</tt> */ 94 #define MXC_R_FCR_AUTOCAL1 ((uint32_t)0x00000008UL) /**< Offset from FCR Base Address: <tt> 0x0008</tt> */ 95 #define MXC_R_FCR_AUTOCAL2 ((uint32_t)0x0000000CUL) /**< Offset from FCR Base Address: <tt> 0x000C</tt> */ 96 #define MXC_R_FCR_URVBOOTADDR ((uint32_t)0x00000010UL) /**< Offset from FCR Base Address: <tt> 0x0010</tt> */ 97 #define MXC_R_FCR_URVCTRL ((uint32_t)0x00000014UL) /**< Offset from FCR Base Address: <tt> 0x0014</tt> */ 98 /**@} end of group fcr_registers */ 99 100 /** 101 * @ingroup fcr_registers 102 * @defgroup FCR_FCTRL0 FCR_FCTRL0 103 * @brief Function Control 0. 104 * @{ 105 */ 106 #define MXC_F_FCR_FCTRL0_I2C0DGEN0_POS 20 /**< FCTRL0_I2C0DGEN0 Position */ 107 #define MXC_F_FCR_FCTRL0_I2C0DGEN0 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0DGEN0_POS)) /**< FCTRL0_I2C0DGEN0 Mask */ 108 109 #define MXC_F_FCR_FCTRL0_I2C0DGEN1_POS 21 /**< FCTRL0_I2C0DGEN1 Position */ 110 #define MXC_F_FCR_FCTRL0_I2C0DGEN1 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0DGEN1_POS)) /**< FCTRL0_I2C0DGEN1 Mask */ 111 112 #define MXC_F_FCR_FCTRL0_I2C1DGEN0_POS 22 /**< FCTRL0_I2C1DGEN0 Position */ 113 #define MXC_F_FCR_FCTRL0_I2C1DGEN0 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1DGEN0_POS)) /**< FCTRL0_I2C1DGEN0 Mask */ 114 115 #define MXC_F_FCR_FCTRL0_I2C1DGEN1_POS 23 /**< FCTRL0_I2C1DGEN1 Position */ 116 #define MXC_F_FCR_FCTRL0_I2C1DGEN1 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1DGEN1_POS)) /**< FCTRL0_I2C1DGEN1 Mask */ 117 118 #define MXC_F_FCR_FCTRL0_I2C2DGEN0_POS 24 /**< FCTRL0_I2C2DGEN0 Position */ 119 #define MXC_F_FCR_FCTRL0_I2C2DGEN0 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2DGEN0_POS)) /**< FCTRL0_I2C2DGEN0 Mask */ 120 121 #define MXC_F_FCR_FCTRL0_I2C2DGEN1_POS 25 /**< FCTRL0_I2C2DGEN1 Position */ 122 #define MXC_F_FCR_FCTRL0_I2C2DGEN1 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2DGEN1_POS)) /**< FCTRL0_I2C2DGEN1 Mask */ 123 124 /**@} end of group FCR_FCTRL0_Register */ 125 126 /** 127 * @ingroup fcr_registers 128 * @defgroup FCR_AUTOCAL0 FCR_AUTOCAL0 129 * @brief Automatic Calibration 0. 130 * @{ 131 */ 132 #define MXC_F_FCR_AUTOCAL0_ACEN_POS 0 /**< AUTOCAL0_ACEN Position */ 133 #define MXC_F_FCR_AUTOCAL0_ACEN ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_ACEN_POS)) /**< AUTOCAL0_ACEN Mask */ 134 135 #define MXC_F_FCR_AUTOCAL0_ACRUN_POS 1 /**< AUTOCAL0_ACRUN Position */ 136 #define MXC_F_FCR_AUTOCAL0_ACRUN ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_ACRUN_POS)) /**< AUTOCAL0_ACRUN Mask */ 137 138 #define MXC_F_FCR_AUTOCAL0_LDTRM_POS 2 /**< AUTOCAL0_LDTRM Position */ 139 #define MXC_F_FCR_AUTOCAL0_LDTRM ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_LDTRM_POS)) /**< AUTOCAL0_LDTRM Mask */ 140 141 #define MXC_F_FCR_AUTOCAL0_GAININV_POS 3 /**< AUTOCAL0_GAININV Position */ 142 #define MXC_F_FCR_AUTOCAL0_GAININV ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_GAININV_POS)) /**< AUTOCAL0_GAININV Mask */ 143 144 #define MXC_F_FCR_AUTOCAL0_ATOMIC_POS 4 /**< AUTOCAL0_ATOMIC Position */ 145 #define MXC_F_FCR_AUTOCAL0_ATOMIC ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_ATOMIC_POS)) /**< AUTOCAL0_ATOMIC Mask */ 146 147 #define MXC_F_FCR_AUTOCAL0_MU_POS 8 /**< AUTOCAL0_MU Position */ 148 #define MXC_F_FCR_AUTOCAL0_MU ((uint32_t)(0xFFFUL << MXC_F_FCR_AUTOCAL0_MU_POS)) /**< AUTOCAL0_MU Mask */ 149 150 #define MXC_F_FCR_AUTOCAL0_HIRC96MACTMROUT_POS 23 /**< AUTOCAL0_HIRC96MACTMROUT Position */ 151 #define MXC_F_FCR_AUTOCAL0_HIRC96MACTMROUT ((uint32_t)(0x1FFUL << MXC_F_FCR_AUTOCAL0_HIRC96MACTMROUT_POS)) /**< AUTOCAL0_HIRC96MACTMROUT Mask */ 152 153 /**@} end of group FCR_AUTOCAL0_Register */ 154 155 /** 156 * @ingroup fcr_registers 157 * @defgroup FCR_AUTOCAL1 FCR_AUTOCAL1 158 * @brief Automatic Calibration 1. 159 * @{ 160 */ 161 #define MXC_F_FCR_AUTOCAL1_INITTRM_POS 0 /**< AUTOCAL1_INITTRM Position */ 162 #define MXC_F_FCR_AUTOCAL1_INITTRM ((uint32_t)(0x1FFUL << MXC_F_FCR_AUTOCAL1_INITTRM_POS)) /**< AUTOCAL1_INITTRM Mask */ 163 164 /**@} end of group FCR_AUTOCAL1_Register */ 165 166 /** 167 * @ingroup fcr_registers 168 * @defgroup FCR_AUTOCAL2 FCR_AUTOCAL2 169 * @brief Automatic Calibration 2 170 * @{ 171 */ 172 #define MXC_F_FCR_AUTOCAL2_DONECNT_POS 0 /**< AUTOCAL2_DONECNT Position */ 173 #define MXC_F_FCR_AUTOCAL2_DONECNT ((uint32_t)(0xFFUL << MXC_F_FCR_AUTOCAL2_DONECNT_POS)) /**< AUTOCAL2_DONECNT Mask */ 174 175 #define MXC_F_FCR_AUTOCAL2_ACDIV_POS 8 /**< AUTOCAL2_ACDIV Position */ 176 #define MXC_F_FCR_AUTOCAL2_ACDIV ((uint32_t)(0x1FFFUL << MXC_F_FCR_AUTOCAL2_ACDIV_POS)) /**< AUTOCAL2_ACDIV Mask */ 177 178 /**@} end of group FCR_AUTOCAL2_Register */ 179 180 /** 181 * @ingroup fcr_registers 182 * @defgroup FCR_URVCTRL FCR_URVCTRL 183 * @brief RISC-V Control Register. 184 * @{ 185 */ 186 #define MXC_F_FCR_URVCTRL_MEMSEL_POS 0 /**< URVCTRL_MEMSEL Position */ 187 #define MXC_F_FCR_URVCTRL_MEMSEL ((uint32_t)(0x1UL << MXC_F_FCR_URVCTRL_MEMSEL_POS)) /**< URVCTRL_MEMSEL Mask */ 188 189 #define MXC_F_FCR_URVCTRL_IFLUSHEN_POS 1 /**< URVCTRL_IFLUSHEN Position */ 190 #define MXC_F_FCR_URVCTRL_IFLUSHEN ((uint32_t)(0x1UL << MXC_F_FCR_URVCTRL_IFLUSHEN_POS)) /**< URVCTRL_IFLUSHEN Mask */ 191 192 /**@} end of group FCR_URVCTRL_Register */ 193 194 #ifdef __cplusplus 195 } 196 #endif 197 198 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX78000_INCLUDE_FCR_REGS_H_ 199
