1 /** 2 * @file spixr_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SPIXR Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup spixr_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_SPIXR_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_SPIXR_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup spixr 67 * @defgroup spixr_registers SPIXR_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the SPIXR Peripheral Module. 69 * @details SPIXR peripheral. 70 */ 71 72 /** 73 * @ingroup spixr_registers 74 * Structure type to access the SPIXR Registers. 75 */ 76 typedef struct { 77 union { 78 __IO uint32_t data32; /**< <tt>\b 0x00:</tt> SPIXR DATA32 Register */ 79 __IO uint16_t data16[2]; /**< <tt>\b 0x00:</tt> SPIXR DATA16 Register */ 80 __IO uint8_t data8[4]; /**< <tt>\b 0x00:</tt> SPIXR DATA8 Register */ 81 }; 82 __IO uint32_t ctrl0; /**< <tt>\b 0x04:</tt> SPIXR CTRL0 Register */ 83 __IO uint32_t ctrl1; /**< <tt>\b 0x08:</tt> SPIXR CTRL1 Register */ 84 __IO uint32_t ctrl2; /**< <tt>\b 0x0C:</tt> SPIXR CTRL2 Register */ 85 __IO uint32_t ctrl3; /**< <tt>\b 0x10:</tt> SPIXR CTRL3 Register */ 86 __IO uint32_t brgctrl; /**< <tt>\b 0x14:</tt> SPIXR BRGCTRL Register */ 87 __R uint32_t rsv_0x18; 88 __IO uint32_t dma; /**< <tt>\b 0x1C:</tt> SPIXR DMA Register */ 89 __IO uint32_t intfl; /**< <tt>\b 0x20:</tt> SPIXR INTFL Register */ 90 __IO uint32_t inten; /**< <tt>\b 0x24:</tt> SPIXR INTEN Register */ 91 __IO uint32_t wkfl; /**< <tt>\b 0x28:</tt> SPIXR WKFL Register */ 92 __IO uint32_t wken; /**< <tt>\b 0x2C:</tt> SPIXR WKEN Register */ 93 __I uint32_t stat; /**< <tt>\b 0x30:</tt> SPIXR STAT Register */ 94 __IO uint32_t xmemctrl; /**< <tt>\b 0x34:</tt> SPIXR XMEMCTRL Register */ 95 } mxc_spixr_regs_t; 96 97 /* Register offsets for module SPIXR */ 98 /** 99 * @ingroup spixr_registers 100 * @defgroup SPIXR_Register_Offsets Register Offsets 101 * @brief SPIXR Peripheral Register Offsets from the SPIXR Base Peripheral Address. 102 * @{ 103 */ 104 #define MXC_R_SPIXR_DATA32 ((uint32_t)0x00000000UL) /**< Offset from SPIXR Base Address: <tt> 0x0000</tt> */ 105 #define MXC_R_SPIXR_DATA16 ((uint32_t)0x00000000UL) /**< Offset from SPIXR Base Address: <tt> 0x0000</tt> */ 106 #define MXC_R_SPIXR_DATA8 ((uint32_t)0x00000000UL) /**< Offset from SPIXR Base Address: <tt> 0x0000</tt> */ 107 #define MXC_R_SPIXR_CTRL0 ((uint32_t)0x00000004UL) /**< Offset from SPIXR Base Address: <tt> 0x0004</tt> */ 108 #define MXC_R_SPIXR_CTRL1 ((uint32_t)0x00000008UL) /**< Offset from SPIXR Base Address: <tt> 0x0008</tt> */ 109 #define MXC_R_SPIXR_CTRL2 ((uint32_t)0x0000000CUL) /**< Offset from SPIXR Base Address: <tt> 0x000C</tt> */ 110 #define MXC_R_SPIXR_CTRL3 ((uint32_t)0x00000010UL) /**< Offset from SPIXR Base Address: <tt> 0x0010</tt> */ 111 #define MXC_R_SPIXR_BRGCTRL ((uint32_t)0x00000014UL) /**< Offset from SPIXR Base Address: <tt> 0x0014</tt> */ 112 #define MXC_R_SPIXR_DMA ((uint32_t)0x0000001CUL) /**< Offset from SPIXR Base Address: <tt> 0x001C</tt> */ 113 #define MXC_R_SPIXR_INTFL ((uint32_t)0x00000020UL) /**< Offset from SPIXR Base Address: <tt> 0x0020</tt> */ 114 #define MXC_R_SPIXR_INTEN ((uint32_t)0x00000024UL) /**< Offset from SPIXR Base Address: <tt> 0x0024</tt> */ 115 #define MXC_R_SPIXR_WKFL ((uint32_t)0x00000028UL) /**< Offset from SPIXR Base Address: <tt> 0x0028</tt> */ 116 #define MXC_R_SPIXR_WKEN ((uint32_t)0x0000002CUL) /**< Offset from SPIXR Base Address: <tt> 0x002C</tt> */ 117 #define MXC_R_SPIXR_STAT ((uint32_t)0x00000030UL) /**< Offset from SPIXR Base Address: <tt> 0x0030</tt> */ 118 #define MXC_R_SPIXR_XMEMCTRL ((uint32_t)0x00000034UL) /**< Offset from SPIXR Base Address: <tt> 0x0034</tt> */ 119 /**@} end of group spixr_registers */ 120 121 /** 122 * @ingroup spixr_registers 123 * @defgroup SPIXR_DATA32 SPIXR_DATA32 124 * @brief Register for reading and writing the FIFO. 125 * @{ 126 */ 127 #define MXC_F_SPIXR_DATA32_DATA_POS 0 /**< DATA32_DATA Position */ 128 #define MXC_F_SPIXR_DATA32_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_SPIXR_DATA32_DATA_POS)) /**< DATA32_DATA Mask */ 129 130 /**@} end of group SPIXR_DATA32_Register */ 131 132 /** 133 * @ingroup spixr_registers 134 * @defgroup SPIXR_DATA16 SPIXR_DATA16 135 * @brief Register for reading and writing the FIFO. 136 * @{ 137 */ 138 #define MXC_F_SPIXR_DATA16_DATA_POS 0 /**< DATA16_DATA Position */ 139 #define MXC_F_SPIXR_DATA16_DATA ((uint16_t)(0xFFFFUL << MXC_F_SPIXR_DATA16_DATA_POS)) /**< DATA16_DATA Mask */ 140 141 /**@} end of group SPIXR_DATA16_Register */ 142 143 /** 144 * @ingroup spixr_registers 145 * @defgroup SPIXR_DATA8 SPIXR_DATA8 146 * @brief Register for reading and writing the FIFO. 147 * @{ 148 */ 149 #define MXC_F_SPIXR_DATA8_DATA_POS 0 /**< DATA8_DATA Position */ 150 #define MXC_F_SPIXR_DATA8_DATA ((uint8_t)(0xFFUL << MXC_F_SPIXR_DATA8_DATA_POS)) /**< DATA8_DATA Mask */ 151 152 /**@} end of group SPIXR_DATA8_Register */ 153 154 /** 155 * @ingroup spixr_registers 156 * @defgroup SPIXR_CTRL0 SPIXR_CTRL0 157 * @brief Register for controlling SPI peripheral. 158 * @{ 159 */ 160 #define MXC_F_SPIXR_CTRL0_EN_POS 0 /**< CTRL0_EN Position */ 161 #define MXC_F_SPIXR_CTRL0_EN ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL0_EN_POS)) /**< CTRL0_EN Mask */ 162 163 #define MXC_F_SPIXR_CTRL0_MSTR_EN_POS 1 /**< CTRL0_MSTR_EN Position */ 164 #define MXC_F_SPIXR_CTRL0_MSTR_EN ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL0_MSTR_EN_POS)) /**< CTRL0_MSTR_EN Mask */ 165 166 #define MXC_F_SPIXR_CTRL0_SSIO_POS 4 /**< CTRL0_SSIO Position */ 167 #define MXC_F_SPIXR_CTRL0_SSIO ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL0_SSIO_POS)) /**< CTRL0_SSIO Mask */ 168 169 #define MXC_F_SPIXR_CTRL0_TX_START_POS 5 /**< CTRL0_TX_START Position */ 170 #define MXC_F_SPIXR_CTRL0_TX_START ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL0_TX_START_POS)) /**< CTRL0_TX_START Mask */ 171 172 #define MXC_F_SPIXR_CTRL0_SS_CTRL_POS 8 /**< CTRL0_SS_CTRL Position */ 173 #define MXC_F_SPIXR_CTRL0_SS_CTRL ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL0_SS_CTRL_POS)) /**< CTRL0_SS_CTRL Mask */ 174 175 #define MXC_F_SPIXR_CTRL0_SS_POS 16 /**< CTRL0_SS Position */ 176 #define MXC_F_SPIXR_CTRL0_SS ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL0_SS_POS)) /**< CTRL0_SS Mask */ 177 178 /**@} end of group SPIXR_CTRL0_Register */ 179 180 /** 181 * @ingroup spixr_registers 182 * @defgroup SPIXR_CTRL1 SPIXR_CTRL1 183 * @brief Register for controlling SPI peripheral. 184 * @{ 185 */ 186 #define MXC_F_SPIXR_CTRL1_TX_NUM_CHAR_POS 0 /**< CTRL1_TX_NUM_CHAR Position */ 187 #define MXC_F_SPIXR_CTRL1_TX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPIXR_CTRL1_TX_NUM_CHAR_POS)) /**< CTRL1_TX_NUM_CHAR Mask */ 188 189 #define MXC_F_SPIXR_CTRL1_RX_NUM_CHAR_POS 16 /**< CTRL1_RX_NUM_CHAR Position */ 190 #define MXC_F_SPIXR_CTRL1_RX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPIXR_CTRL1_RX_NUM_CHAR_POS)) /**< CTRL1_RX_NUM_CHAR Mask */ 191 192 /**@} end of group SPIXR_CTRL1_Register */ 193 194 /** 195 * @ingroup spixr_registers 196 * @defgroup SPIXR_CTRL2 SPIXR_CTRL2 197 * @brief Register for controlling SPI peripheral. 198 * @{ 199 */ 200 #define MXC_F_SPIXR_CTRL2_CPHA_POS 0 /**< CTRL2_CPHA Position */ 201 #define MXC_F_SPIXR_CTRL2_CPHA ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL2_CPHA_POS)) /**< CTRL2_CPHA Mask */ 202 203 #define MXC_F_SPIXR_CTRL2_CPOL_POS 1 /**< CTRL2_CPOL Position */ 204 #define MXC_F_SPIXR_CTRL2_CPOL ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL2_CPOL_POS)) /**< CTRL2_CPOL Mask */ 205 206 #define MXC_F_SPIXR_CTRL2_SCLK_FB_INV_POS 4 /**< CTRL2_SCLK_FB_INV Position */ 207 #define MXC_F_SPIXR_CTRL2_SCLK_FB_INV ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL2_SCLK_FB_INV_POS)) /**< CTRL2_SCLK_FB_INV Mask */ 208 209 #define MXC_F_SPIXR_CTRL2_NUMBITS_POS 8 /**< CTRL2_NUMBITS Position */ 210 #define MXC_F_SPIXR_CTRL2_NUMBITS ((uint32_t)(0xFUL << MXC_F_SPIXR_CTRL2_NUMBITS_POS)) /**< CTRL2_NUMBITS Mask */ 211 #define MXC_V_SPIXR_CTRL2_NUMBITS_0 ((uint32_t)0x0UL) /**< CTRL2_NUMBITS_0 Value */ 212 #define MXC_S_SPIXR_CTRL2_NUMBITS_0 (MXC_V_SPIXR_CTRL2_NUMBITS_0 << MXC_F_SPIXR_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_0 Setting */ 213 214 #define MXC_F_SPIXR_CTRL2_DATA_WIDTH_POS 12 /**< CTRL2_DATA_WIDTH Position */ 215 #define MXC_F_SPIXR_CTRL2_DATA_WIDTH ((uint32_t)(0x3UL << MXC_F_SPIXR_CTRL2_DATA_WIDTH_POS)) /**< CTRL2_DATA_WIDTH Mask */ 216 #define MXC_V_SPIXR_CTRL2_DATA_WIDTH_MONO ((uint32_t)0x0UL) /**< CTRL2_DATA_WIDTH_MONO Value */ 217 #define MXC_S_SPIXR_CTRL2_DATA_WIDTH_MONO (MXC_V_SPIXR_CTRL2_DATA_WIDTH_MONO << MXC_F_SPIXR_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_MONO Setting */ 218 #define MXC_V_SPIXR_CTRL2_DATA_WIDTH_DUAL ((uint32_t)0x1UL) /**< CTRL2_DATA_WIDTH_DUAL Value */ 219 #define MXC_S_SPIXR_CTRL2_DATA_WIDTH_DUAL (MXC_V_SPIXR_CTRL2_DATA_WIDTH_DUAL << MXC_F_SPIXR_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_DUAL Setting */ 220 #define MXC_V_SPIXR_CTRL2_DATA_WIDTH_QUAD ((uint32_t)0x2UL) /**< CTRL2_DATA_WIDTH_QUAD Value */ 221 #define MXC_S_SPIXR_CTRL2_DATA_WIDTH_QUAD (MXC_V_SPIXR_CTRL2_DATA_WIDTH_QUAD << MXC_F_SPIXR_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_QUAD Setting */ 222 223 #define MXC_F_SPIXR_CTRL2_THREE_WIRE_POS 15 /**< CTRL2_THREE_WIRE Position */ 224 #define MXC_F_SPIXR_CTRL2_THREE_WIRE ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL2_THREE_WIRE_POS)) /**< CTRL2_THREE_WIRE Mask */ 225 226 #define MXC_F_SPIXR_CTRL2_SSPOL_POS 16 /**< CTRL2_SSPOL Position */ 227 #define MXC_F_SPIXR_CTRL2_SSPOL ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL2_SSPOL_POS)) /**< CTRL2_SSPOL Mask */ 228 229 /**@} end of group SPIXR_CTRL2_Register */ 230 231 /** 232 * @ingroup spixr_registers 233 * @defgroup SPIXR_CTRL3 SPIXR_CTRL3 234 * @brief Register for controlling SPI peripheral. 235 * @{ 236 */ 237 #define MXC_F_SPIXR_CTRL3_SSACT1_POS 0 /**< CTRL3_SSACT1 Position */ 238 #define MXC_F_SPIXR_CTRL3_SSACT1 ((uint32_t)(0xFFUL << MXC_F_SPIXR_CTRL3_SSACT1_POS)) /**< CTRL3_SSACT1 Mask */ 239 #define MXC_V_SPIXR_CTRL3_SSACT1_256 ((uint32_t)0x0UL) /**< CTRL3_SSACT1_256 Value */ 240 #define MXC_S_SPIXR_CTRL3_SSACT1_256 (MXC_V_SPIXR_CTRL3_SSACT1_256 << MXC_F_SPIXR_CTRL3_SSACT1_POS) /**< CTRL3_SSACT1_256 Setting */ 241 242 #define MXC_F_SPIXR_CTRL3_SSACT2_POS 8 /**< CTRL3_SSACT2 Position */ 243 #define MXC_F_SPIXR_CTRL3_SSACT2 ((uint32_t)(0xFFUL << MXC_F_SPIXR_CTRL3_SSACT2_POS)) /**< CTRL3_SSACT2 Mask */ 244 #define MXC_V_SPIXR_CTRL3_SSACT2_256 ((uint32_t)0x0UL) /**< CTRL3_SSACT2_256 Value */ 245 #define MXC_S_SPIXR_CTRL3_SSACT2_256 (MXC_V_SPIXR_CTRL3_SSACT2_256 << MXC_F_SPIXR_CTRL3_SSACT2_POS) /**< CTRL3_SSACT2_256 Setting */ 246 247 #define MXC_F_SPIXR_CTRL3_SSIACT_POS 16 /**< CTRL3_SSIACT Position */ 248 #define MXC_F_SPIXR_CTRL3_SSIACT ((uint32_t)(0xFFUL << MXC_F_SPIXR_CTRL3_SSIACT_POS)) /**< CTRL3_SSIACT Mask */ 249 #define MXC_V_SPIXR_CTRL3_SSIACT_256 ((uint32_t)0x0UL) /**< CTRL3_SSIACT_256 Value */ 250 #define MXC_S_SPIXR_CTRL3_SSIACT_256 (MXC_V_SPIXR_CTRL3_SSIACT_256 << MXC_F_SPIXR_CTRL3_SSIACT_POS) /**< CTRL3_SSIACT_256 Setting */ 251 252 /**@} end of group SPIXR_CTRL3_Register */ 253 254 /** 255 * @ingroup spixr_registers 256 * @defgroup SPIXR_BRGCTRL SPIXR_BRGCTRL 257 * @brief Register for controlling SPI clock rate. 258 * @{ 259 */ 260 #define MXC_F_SPIXR_BRGCTRL_LOW_POS 0 /**< BRGCTRL_LOW Position */ 261 #define MXC_F_SPIXR_BRGCTRL_LOW ((uint32_t)(0xFFUL << MXC_F_SPIXR_BRGCTRL_LOW_POS)) /**< BRGCTRL_LOW Mask */ 262 #define MXC_V_SPIXR_BRGCTRL_LOW_DIS ((uint32_t)0x0UL) /**< BRGCTRL_LOW_DIS Value */ 263 #define MXC_S_SPIXR_BRGCTRL_LOW_DIS (MXC_V_SPIXR_BRGCTRL_LOW_DIS << MXC_F_SPIXR_BRGCTRL_LOW_POS) /**< BRGCTRL_LOW_DIS Setting */ 264 265 #define MXC_F_SPIXR_BRGCTRL_HIGH_POS 8 /**< BRGCTRL_HIGH Position */ 266 #define MXC_F_SPIXR_BRGCTRL_HIGH ((uint32_t)(0xFFUL << MXC_F_SPIXR_BRGCTRL_HIGH_POS)) /**< BRGCTRL_HIGH Mask */ 267 #define MXC_V_SPIXR_BRGCTRL_HIGH_DIS ((uint32_t)0x0UL) /**< BRGCTRL_HIGH_DIS Value */ 268 #define MXC_S_SPIXR_BRGCTRL_HIGH_DIS (MXC_V_SPIXR_BRGCTRL_HIGH_DIS << MXC_F_SPIXR_BRGCTRL_HIGH_POS) /**< BRGCTRL_HIGH_DIS Setting */ 269 270 #define MXC_F_SPIXR_BRGCTRL_SCALE_POS 16 /**< BRGCTRL_SCALE Position */ 271 #define MXC_F_SPIXR_BRGCTRL_SCALE ((uint32_t)(0xFUL << MXC_F_SPIXR_BRGCTRL_SCALE_POS)) /**< BRGCTRL_SCALE Mask */ 272 273 /**@} end of group SPIXR_BRGCTRL_Register */ 274 275 /** 276 * @ingroup spixr_registers 277 * @defgroup SPIXR_DMA SPIXR_DMA 278 * @brief Register for controlling DMA. 279 * @{ 280 */ 281 #define MXC_F_SPIXR_DMA_TX_FIFO_LVL_POS 0 /**< DMA_TX_FIFO_LVL Position */ 282 #define MXC_F_SPIXR_DMA_TX_FIFO_LVL ((uint32_t)(0x3FUL << MXC_F_SPIXR_DMA_TX_FIFO_LVL_POS)) /**< DMA_TX_FIFO_LVL Mask */ 283 284 #define MXC_F_SPIXR_DMA_TX_FIFO_EN_POS 6 /**< DMA_TX_FIFO_EN Position */ 285 #define MXC_F_SPIXR_DMA_TX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_TX_FIFO_EN_POS)) /**< DMA_TX_FIFO_EN Mask */ 286 287 #define MXC_F_SPIXR_DMA_TX_FIFO_CLEAR_POS 7 /**< DMA_TX_FIFO_CLEAR Position */ 288 #define MXC_F_SPIXR_DMA_TX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_TX_FIFO_CLEAR_POS)) /**< DMA_TX_FIFO_CLEAR Mask */ 289 290 #define MXC_F_SPIXR_DMA_TX_FIFO_CNT_POS 8 /**< DMA_TX_FIFO_CNT Position */ 291 #define MXC_F_SPIXR_DMA_TX_FIFO_CNT ((uint32_t)(0x1FUL << MXC_F_SPIXR_DMA_TX_FIFO_CNT_POS)) /**< DMA_TX_FIFO_CNT Mask */ 292 293 #define MXC_F_SPIXR_DMA_DMA_TX_EN_POS 15 /**< DMA_DMA_TX_EN Position */ 294 #define MXC_F_SPIXR_DMA_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_DMA_TX_EN_POS)) /**< DMA_DMA_TX_EN Mask */ 295 296 #define MXC_F_SPIXR_DMA_RX_FIFO_LVL_POS 16 /**< DMA_RX_FIFO_LVL Position */ 297 #define MXC_F_SPIXR_DMA_RX_FIFO_LVL ((uint32_t)(0x3FUL << MXC_F_SPIXR_DMA_RX_FIFO_LVL_POS)) /**< DMA_RX_FIFO_LVL Mask */ 298 299 #define MXC_F_SPIXR_DMA_RX_FIFO_EN_POS 22 /**< DMA_RX_FIFO_EN Position */ 300 #define MXC_F_SPIXR_DMA_RX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_RX_FIFO_EN_POS)) /**< DMA_RX_FIFO_EN Mask */ 301 302 #define MXC_F_SPIXR_DMA_RX_FIFO_CLR_POS 23 /**< DMA_RX_FIFO_CLR Position */ 303 #define MXC_F_SPIXR_DMA_RX_FIFO_CLR ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_RX_FIFO_CLR_POS)) /**< DMA_RX_FIFO_CLR Mask */ 304 305 #define MXC_F_SPIXR_DMA_RX_FIFO_CNT_POS 24 /**< DMA_RX_FIFO_CNT Position */ 306 #define MXC_F_SPIXR_DMA_RX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_SPIXR_DMA_RX_FIFO_CNT_POS)) /**< DMA_RX_FIFO_CNT Mask */ 307 308 #define MXC_F_SPIXR_DMA_DMA_RX_EN_POS 31 /**< DMA_DMA_RX_EN Position */ 309 #define MXC_F_SPIXR_DMA_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_DMA_RX_EN_POS)) /**< DMA_DMA_RX_EN Mask */ 310 311 /**@} end of group SPIXR_DMA_Register */ 312 313 /** 314 * @ingroup spixr_registers 315 * @defgroup SPIXR_INTFL SPIXR_INTFL 316 * @brief Register for reading and clearing interrupt flags. All bits are write 1 to 317 * clear. 318 * @{ 319 */ 320 #define MXC_F_SPIXR_INTFL_TX_THRESH_POS 0 /**< INTFL_TX_THRESH Position */ 321 #define MXC_F_SPIXR_INTFL_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPIXR_INTFL_TX_THRESH_POS)) /**< INTFL_TX_THRESH Mask */ 322 323 #define MXC_F_SPIXR_INTFL_TX_EMPTY_POS 1 /**< INTFL_TX_EMPTY Position */ 324 #define MXC_F_SPIXR_INTFL_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPIXR_INTFL_TX_EMPTY_POS)) /**< INTFL_TX_EMPTY Mask */ 325 326 #define MXC_F_SPIXR_INTFL_RX_THRESH_POS 2 /**< INTFL_RX_THRESH Position */ 327 #define MXC_F_SPIXR_INTFL_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPIXR_INTFL_RX_THRESH_POS)) /**< INTFL_RX_THRESH Mask */ 328 329 #define MXC_F_SPIXR_INTFL_RX_FULL_POS 3 /**< INTFL_RX_FULL Position */ 330 #define MXC_F_SPIXR_INTFL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPIXR_INTFL_RX_FULL_POS)) /**< INTFL_RX_FULL Mask */ 331 332 #define MXC_F_SPIXR_INTFL_SSA_POS 4 /**< INTFL_SSA Position */ 333 #define MXC_F_SPIXR_INTFL_SSA ((uint32_t)(0x1UL << MXC_F_SPIXR_INTFL_SSA_POS)) /**< INTFL_SSA Mask */ 334 335 #define MXC_F_SPIXR_INTFL_SSD_POS 5 /**< INTFL_SSD Position */ 336 #define MXC_F_SPIXR_INTFL_SSD ((uint32_t)(0x1UL << MXC_F_SPIXR_INTFL_SSD_POS)) /**< INTFL_SSD Mask */ 337 338 #define MXC_F_SPIXR_INTFL_FAULT_POS 8 /**< INTFL_FAULT Position */ 339 #define MXC_F_SPIXR_INTFL_FAULT ((uint32_t)(0x1UL << MXC_F_SPIXR_INTFL_FAULT_POS)) /**< INTFL_FAULT Mask */ 340 341 #define MXC_F_SPIXR_INTFL_ABORT_POS 9 /**< INTFL_ABORT Position */ 342 #define MXC_F_SPIXR_INTFL_ABORT ((uint32_t)(0x1UL << MXC_F_SPIXR_INTFL_ABORT_POS)) /**< INTFL_ABORT Mask */ 343 344 #define MXC_F_SPIXR_INTFL_M_DONE_POS 11 /**< INTFL_M_DONE Position */ 345 #define MXC_F_SPIXR_INTFL_M_DONE ((uint32_t)(0x1UL << MXC_F_SPIXR_INTFL_M_DONE_POS)) /**< INTFL_M_DONE Mask */ 346 347 #define MXC_F_SPIXR_INTFL_TX_OVR_POS 12 /**< INTFL_TX_OVR Position */ 348 #define MXC_F_SPIXR_INTFL_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPIXR_INTFL_TX_OVR_POS)) /**< INTFL_TX_OVR Mask */ 349 350 #define MXC_F_SPIXR_INTFL_TX_UND_POS 13 /**< INTFL_TX_UND Position */ 351 #define MXC_F_SPIXR_INTFL_TX_UND ((uint32_t)(0x1UL << MXC_F_SPIXR_INTFL_TX_UND_POS)) /**< INTFL_TX_UND Mask */ 352 353 #define MXC_F_SPIXR_INTFL_RX_OVR_POS 14 /**< INTFL_RX_OVR Position */ 354 #define MXC_F_SPIXR_INTFL_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPIXR_INTFL_RX_OVR_POS)) /**< INTFL_RX_OVR Mask */ 355 356 #define MXC_F_SPIXR_INTFL_RX_UND_POS 15 /**< INTFL_RX_UND Position */ 357 #define MXC_F_SPIXR_INTFL_RX_UND ((uint32_t)(0x1UL << MXC_F_SPIXR_INTFL_RX_UND_POS)) /**< INTFL_RX_UND Mask */ 358 359 /**@} end of group SPIXR_INTFL_Register */ 360 361 /** 362 * @ingroup spixr_registers 363 * @defgroup SPIXR_INTEN SPIXR_INTEN 364 * @brief Register for enabling interrupts. 365 * @{ 366 */ 367 #define MXC_F_SPIXR_INTEN_TX_THRESH_POS 0 /**< INTEN_TX_THRESH Position */ 368 #define MXC_F_SPIXR_INTEN_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPIXR_INTEN_TX_THRESH_POS)) /**< INTEN_TX_THRESH Mask */ 369 370 #define MXC_F_SPIXR_INTEN_TX_EMPTY_POS 1 /**< INTEN_TX_EMPTY Position */ 371 #define MXC_F_SPIXR_INTEN_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPIXR_INTEN_TX_EMPTY_POS)) /**< INTEN_TX_EMPTY Mask */ 372 373 #define MXC_F_SPIXR_INTEN_RX_THRESH_POS 2 /**< INTEN_RX_THRESH Position */ 374 #define MXC_F_SPIXR_INTEN_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPIXR_INTEN_RX_THRESH_POS)) /**< INTEN_RX_THRESH Mask */ 375 376 #define MXC_F_SPIXR_INTEN_RX_FULL_POS 3 /**< INTEN_RX_FULL Position */ 377 #define MXC_F_SPIXR_INTEN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPIXR_INTEN_RX_FULL_POS)) /**< INTEN_RX_FULL Mask */ 378 379 #define MXC_F_SPIXR_INTEN_SSA_POS 4 /**< INTEN_SSA Position */ 380 #define MXC_F_SPIXR_INTEN_SSA ((uint32_t)(0x1UL << MXC_F_SPIXR_INTEN_SSA_POS)) /**< INTEN_SSA Mask */ 381 382 #define MXC_F_SPIXR_INTEN_SSD_POS 5 /**< INTEN_SSD Position */ 383 #define MXC_F_SPIXR_INTEN_SSD ((uint32_t)(0x1UL << MXC_F_SPIXR_INTEN_SSD_POS)) /**< INTEN_SSD Mask */ 384 385 #define MXC_F_SPIXR_INTEN_FAULT_POS 8 /**< INTEN_FAULT Position */ 386 #define MXC_F_SPIXR_INTEN_FAULT ((uint32_t)(0x1UL << MXC_F_SPIXR_INTEN_FAULT_POS)) /**< INTEN_FAULT Mask */ 387 388 #define MXC_F_SPIXR_INTEN_ABORT_POS 9 /**< INTEN_ABORT Position */ 389 #define MXC_F_SPIXR_INTEN_ABORT ((uint32_t)(0x1UL << MXC_F_SPIXR_INTEN_ABORT_POS)) /**< INTEN_ABORT Mask */ 390 391 #define MXC_F_SPIXR_INTEN_M_DONE_POS 11 /**< INTEN_M_DONE Position */ 392 #define MXC_F_SPIXR_INTEN_M_DONE ((uint32_t)(0x1UL << MXC_F_SPIXR_INTEN_M_DONE_POS)) /**< INTEN_M_DONE Mask */ 393 394 #define MXC_F_SPIXR_INTEN_TX_OVR_POS 12 /**< INTEN_TX_OVR Position */ 395 #define MXC_F_SPIXR_INTEN_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPIXR_INTEN_TX_OVR_POS)) /**< INTEN_TX_OVR Mask */ 396 397 #define MXC_F_SPIXR_INTEN_TX_UND_POS 13 /**< INTEN_TX_UND Position */ 398 #define MXC_F_SPIXR_INTEN_TX_UND ((uint32_t)(0x1UL << MXC_F_SPIXR_INTEN_TX_UND_POS)) /**< INTEN_TX_UND Mask */ 399 400 #define MXC_F_SPIXR_INTEN_RX_OVR_POS 14 /**< INTEN_RX_OVR Position */ 401 #define MXC_F_SPIXR_INTEN_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPIXR_INTEN_RX_OVR_POS)) /**< INTEN_RX_OVR Mask */ 402 403 #define MXC_F_SPIXR_INTEN_RX_UND_POS 15 /**< INTEN_RX_UND Position */ 404 #define MXC_F_SPIXR_INTEN_RX_UND ((uint32_t)(0x1UL << MXC_F_SPIXR_INTEN_RX_UND_POS)) /**< INTEN_RX_UND Mask */ 405 406 /**@} end of group SPIXR_INTEN_Register */ 407 408 /** 409 * @ingroup spixr_registers 410 * @defgroup SPIXR_WKFL SPIXR_WKFL 411 * @brief Register for wake up flags. All bits in this register are write 1 to clear. 412 * @{ 413 */ 414 #define MXC_F_SPIXR_WKFL_TX_THRESH_POS 0 /**< WKFL_TX_THRESH Position */ 415 #define MXC_F_SPIXR_WKFL_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPIXR_WKFL_TX_THRESH_POS)) /**< WKFL_TX_THRESH Mask */ 416 417 #define MXC_F_SPIXR_WKFL_TX_EM_POS 1 /**< WKFL_TX_EM Position */ 418 #define MXC_F_SPIXR_WKFL_TX_EM ((uint32_t)(0x1UL << MXC_F_SPIXR_WKFL_TX_EM_POS)) /**< WKFL_TX_EM Mask */ 419 420 #define MXC_F_SPIXR_WKFL_RX_THRESH_POS 2 /**< WKFL_RX_THRESH Position */ 421 #define MXC_F_SPIXR_WKFL_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPIXR_WKFL_RX_THRESH_POS)) /**< WKFL_RX_THRESH Mask */ 422 423 #define MXC_F_SPIXR_WKFL_RX_FULL_POS 3 /**< WKFL_RX_FULL Position */ 424 #define MXC_F_SPIXR_WKFL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPIXR_WKFL_RX_FULL_POS)) /**< WKFL_RX_FULL Mask */ 425 426 /**@} end of group SPIXR_WKFL_Register */ 427 428 /** 429 * @ingroup spixr_registers 430 * @defgroup SPIXR_WKEN SPIXR_WKEN 431 * @brief Register for wake up enable. 432 * @{ 433 */ 434 #define MXC_F_SPIXR_WKEN_TX_THRESH_POS 0 /**< WKEN_TX_THRESH Position */ 435 #define MXC_F_SPIXR_WKEN_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPIXR_WKEN_TX_THRESH_POS)) /**< WKEN_TX_THRESH Mask */ 436 437 #define MXC_F_SPIXR_WKEN_TX_EM_POS 1 /**< WKEN_TX_EM Position */ 438 #define MXC_F_SPIXR_WKEN_TX_EM ((uint32_t)(0x1UL << MXC_F_SPIXR_WKEN_TX_EM_POS)) /**< WKEN_TX_EM Mask */ 439 440 #define MXC_F_SPIXR_WKEN_RX_THRESH_POS 2 /**< WKEN_RX_THRESH Position */ 441 #define MXC_F_SPIXR_WKEN_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPIXR_WKEN_RX_THRESH_POS)) /**< WKEN_RX_THRESH Mask */ 442 443 #define MXC_F_SPIXR_WKEN_RX_FULL_POS 3 /**< WKEN_RX_FULL Position */ 444 #define MXC_F_SPIXR_WKEN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPIXR_WKEN_RX_FULL_POS)) /**< WKEN_RX_FULL Mask */ 445 446 /**@} end of group SPIXR_WKEN_Register */ 447 448 /** 449 * @ingroup spixr_registers 450 * @defgroup SPIXR_STAT SPIXR_STAT 451 * @brief SPI Status register. 452 * @{ 453 */ 454 #define MXC_F_SPIXR_STAT_BUSY_POS 0 /**< STAT_BUSY Position */ 455 #define MXC_F_SPIXR_STAT_BUSY ((uint32_t)(0x1UL << MXC_F_SPIXR_STAT_BUSY_POS)) /**< STAT_BUSY Mask */ 456 457 /**@} end of group SPIXR_STAT_Register */ 458 459 /** 460 * @ingroup spixr_registers 461 * @defgroup SPIXR_XMEMCTRL SPIXR_XMEMCTRL 462 * @brief Register to control external memory. 463 * @{ 464 */ 465 #define MXC_F_SPIXR_XMEMCTRL_RD_CMD_POS 0 /**< XMEMCTRL_RD_CMD Position */ 466 #define MXC_F_SPIXR_XMEMCTRL_RD_CMD ((uint32_t)(0xFFUL << MXC_F_SPIXR_XMEMCTRL_RD_CMD_POS)) /**< XMEMCTRL_RD_CMD Mask */ 467 468 #define MXC_F_SPIXR_XMEMCTRL_WR_CMD_POS 8 /**< XMEMCTRL_WR_CMD Position */ 469 #define MXC_F_SPIXR_XMEMCTRL_WR_CMD ((uint32_t)(0xFFUL << MXC_F_SPIXR_XMEMCTRL_WR_CMD_POS)) /**< XMEMCTRL_WR_CMD Mask */ 470 471 #define MXC_F_SPIXR_XMEMCTRL_DUMMY_CLK_POS 16 /**< XMEMCTRL_DUMMY_CLK Position */ 472 #define MXC_F_SPIXR_XMEMCTRL_DUMMY_CLK ((uint32_t)(0xFFUL << MXC_F_SPIXR_XMEMCTRL_DUMMY_CLK_POS)) /**< XMEMCTRL_DUMMY_CLK Mask */ 473 474 #define MXC_F_SPIXR_XMEMCTRL_XMEM_EN_POS 31 /**< XMEMCTRL_XMEM_EN Position */ 475 #define MXC_F_SPIXR_XMEMCTRL_XMEM_EN ((uint32_t)(0x1UL << MXC_F_SPIXR_XMEMCTRL_XMEM_EN_POS)) /**< XMEMCTRL_XMEM_EN Mask */ 476 477 /**@} end of group SPIXR_XMEMCTRL_Register */ 478 479 #ifdef __cplusplus 480 } 481 #endif 482 483 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_SPIXR_REGS_H_ 484
