1 /** 2 * @file spixfm_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SPIXFM Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup spixfm_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_SPIXFM_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_SPIXFM_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup spixfm 67 * @defgroup spixfm_registers SPIXFM_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the SPIXFM Peripheral Module. 69 * @details SPIXF Master 70 */ 71 72 /** 73 * @ingroup spixfm_registers 74 * Structure type to access the SPIXFM Registers. 75 */ 76 typedef struct { 77 __IO uint32_t ctrl; /**< <tt>\b 0x00:</tt> SPIXFM CTRL Register */ 78 __IO uint32_t fetchctrl; /**< <tt>\b 0x04:</tt> SPIXFM FETCHCTRL Register */ 79 __IO uint32_t modectrl; /**< <tt>\b 0x08:</tt> SPIXFM MODECTRL Register */ 80 __IO uint32_t modedata; /**< <tt>\b 0x0C:</tt> SPIXFM MODEDATA Register */ 81 __IO uint32_t fbctrl; /**< <tt>\b 0x10:</tt> SPIXFM FBCTRL Register */ 82 __R uint32_t rsv_0x14_0x1b[2]; 83 __IO uint32_t ioctrl; /**< <tt>\b 0x1C:</tt> SPIXFM IOCTRL Register */ 84 __IO uint32_t memsecctrl; /**< <tt>\b 0x20:</tt> SPIXFM MEMSECCTRL Register */ 85 __IO uint32_t busidle; /**< <tt>\b 0x24:</tt> SPIXFM BUSIDLE Register */ 86 __IO uint32_t authoffset; /**< <tt>\b 0x28:</tt> SPIXFM AUTHOFFSET Register */ 87 } mxc_spixfm_regs_t; 88 89 /* Register offsets for module SPIXFM */ 90 /** 91 * @ingroup spixfm_registers 92 * @defgroup SPIXFM_Register_Offsets Register Offsets 93 * @brief SPIXFM Peripheral Register Offsets from the SPIXFM Base Peripheral Address. 94 * @{ 95 */ 96 #define MXC_R_SPIXFM_CTRL ((uint32_t)0x00000000UL) /**< Offset from SPIXFM Base Address: <tt> 0x0000</tt> */ 97 #define MXC_R_SPIXFM_FETCHCTRL ((uint32_t)0x00000004UL) /**< Offset from SPIXFM Base Address: <tt> 0x0004</tt> */ 98 #define MXC_R_SPIXFM_MODECTRL ((uint32_t)0x00000008UL) /**< Offset from SPIXFM Base Address: <tt> 0x0008</tt> */ 99 #define MXC_R_SPIXFM_MODEDATA ((uint32_t)0x0000000CUL) /**< Offset from SPIXFM Base Address: <tt> 0x000C</tt> */ 100 #define MXC_R_SPIXFM_FBCTRL ((uint32_t)0x00000010UL) /**< Offset from SPIXFM Base Address: <tt> 0x0010</tt> */ 101 #define MXC_R_SPIXFM_IOCTRL ((uint32_t)0x0000001CUL) /**< Offset from SPIXFM Base Address: <tt> 0x001C</tt> */ 102 #define MXC_R_SPIXFM_MEMSECCTRL ((uint32_t)0x00000020UL) /**< Offset from SPIXFM Base Address: <tt> 0x0020</tt> */ 103 #define MXC_R_SPIXFM_BUSIDLE ((uint32_t)0x00000024UL) /**< Offset from SPIXFM Base Address: <tt> 0x0024</tt> */ 104 #define MXC_R_SPIXFM_AUTHOFFSET ((uint32_t)0x00000028UL) /**< Offset from SPIXFM Base Address: <tt> 0x0028</tt> */ 105 /**@} end of group spixfm_registers */ 106 107 /** 108 * @ingroup spixfm_registers 109 * @defgroup SPIXFM_CTRL SPIXFM_CTRL 110 * @brief SPIX Control Register. 111 * @{ 112 */ 113 #define MXC_F_SPIXFM_CTRL_MODE_POS 0 /**< CTRL_MODE Position */ 114 #define MXC_F_SPIXFM_CTRL_MODE ((uint32_t)(0x3UL << MXC_F_SPIXFM_CTRL_MODE_POS)) /**< CTRL_MODE Mask */ 115 #define MXC_V_SPIXFM_CTRL_MODE_SCLK_HI_SAMPLE_RISING ((uint32_t)0x0UL) /**< CTRL_MODE_SCLK_HI_SAMPLE_RISING Value */ 116 #define MXC_S_SPIXFM_CTRL_MODE_SCLK_HI_SAMPLE_RISING (MXC_V_SPIXFM_CTRL_MODE_SCLK_HI_SAMPLE_RISING << MXC_F_SPIXFM_CTRL_MODE_POS) /**< CTRL_MODE_SCLK_HI_SAMPLE_RISING Setting */ 117 #define MXC_V_SPIXFM_CTRL_MODE_SCLK_LO_SAMPLE_FAILLING ((uint32_t)0x3UL) /**< CTRL_MODE_SCLK_LO_SAMPLE_FAILLING Value */ 118 #define MXC_S_SPIXFM_CTRL_MODE_SCLK_LO_SAMPLE_FAILLING (MXC_V_SPIXFM_CTRL_MODE_SCLK_LO_SAMPLE_FAILLING << MXC_F_SPIXFM_CTRL_MODE_POS) /**< CTRL_MODE_SCLK_LO_SAMPLE_FAILLING Setting */ 119 120 #define MXC_F_SPIXFM_CTRL_SSPOL_POS 2 /**< CTRL_SSPOL Position */ 121 #define MXC_F_SPIXFM_CTRL_SSPOL ((uint32_t)(0x1UL << MXC_F_SPIXFM_CTRL_SSPOL_POS)) /**< CTRL_SSPOL Mask */ 122 123 #define MXC_F_SPIXFM_CTRL_SSEL_POS 4 /**< CTRL_SSEL Position */ 124 #define MXC_F_SPIXFM_CTRL_SSEL ((uint32_t)(0x7UL << MXC_F_SPIXFM_CTRL_SSEL_POS)) /**< CTRL_SSEL Mask */ 125 126 #define MXC_F_SPIXFM_CTRL_LOCLK_POS 8 /**< CTRL_LOCLK Position */ 127 #define MXC_F_SPIXFM_CTRL_LOCLK ((uint32_t)(0xFUL << MXC_F_SPIXFM_CTRL_LOCLK_POS)) /**< CTRL_LOCLK Mask */ 128 129 #define MXC_F_SPIXFM_CTRL_HICLK_POS 12 /**< CTRL_HICLK Position */ 130 #define MXC_F_SPIXFM_CTRL_HICLK ((uint32_t)(0xFUL << MXC_F_SPIXFM_CTRL_HICLK_POS)) /**< CTRL_HICLK Mask */ 131 132 #define MXC_F_SPIXFM_CTRL_SSACT_POS 16 /**< CTRL_SSACT Position */ 133 #define MXC_F_SPIXFM_CTRL_SSACT ((uint32_t)(0x3UL << MXC_F_SPIXFM_CTRL_SSACT_POS)) /**< CTRL_SSACT Mask */ 134 #define MXC_V_SPIXFM_CTRL_SSACT_OFF ((uint32_t)0x0UL) /**< CTRL_SSACT_OFF Value */ 135 #define MXC_S_SPIXFM_CTRL_SSACT_OFF (MXC_V_SPIXFM_CTRL_SSACT_OFF << MXC_F_SPIXFM_CTRL_SSACT_POS) /**< CTRL_SSACT_OFF Setting */ 136 #define MXC_V_SPIXFM_CTRL_SSACT_FOR_2_MOD_CLK ((uint32_t)0x1UL) /**< CTRL_SSACT_FOR_2_MOD_CLK Value */ 137 #define MXC_S_SPIXFM_CTRL_SSACT_FOR_2_MOD_CLK (MXC_V_SPIXFM_CTRL_SSACT_FOR_2_MOD_CLK << MXC_F_SPIXFM_CTRL_SSACT_POS) /**< CTRL_SSACT_FOR_2_MOD_CLK Setting */ 138 #define MXC_V_SPIXFM_CTRL_SSACT_FOR_4_MOD_CLK ((uint32_t)0x2UL) /**< CTRL_SSACT_FOR_4_MOD_CLK Value */ 139 #define MXC_S_SPIXFM_CTRL_SSACT_FOR_4_MOD_CLK (MXC_V_SPIXFM_CTRL_SSACT_FOR_4_MOD_CLK << MXC_F_SPIXFM_CTRL_SSACT_POS) /**< CTRL_SSACT_FOR_4_MOD_CLK Setting */ 140 #define MXC_V_SPIXFM_CTRL_SSACT_FOR_8_MOD_CLK ((uint32_t)0x3UL) /**< CTRL_SSACT_FOR_8_MOD_CLK Value */ 141 #define MXC_S_SPIXFM_CTRL_SSACT_FOR_8_MOD_CLK (MXC_V_SPIXFM_CTRL_SSACT_FOR_8_MOD_CLK << MXC_F_SPIXFM_CTRL_SSACT_POS) /**< CTRL_SSACT_FOR_8_MOD_CLK Setting */ 142 143 #define MXC_F_SPIXFM_CTRL_SSIACT_POS 18 /**< CTRL_SSIACT Position */ 144 #define MXC_F_SPIXFM_CTRL_SSIACT ((uint32_t)(0x3UL << MXC_F_SPIXFM_CTRL_SSIACT_POS)) /**< CTRL_SSIACT Mask */ 145 #define MXC_V_SPIXFM_CTRL_SSIACT_FOR_1_MOD_CLK ((uint32_t)0x0UL) /**< CTRL_SSIACT_FOR_1_MOD_CLK Value */ 146 #define MXC_S_SPIXFM_CTRL_SSIACT_FOR_1_MOD_CLK (MXC_V_SPIXFM_CTRL_SSIACT_FOR_1_MOD_CLK << MXC_F_SPIXFM_CTRL_SSIACT_POS) /**< CTRL_SSIACT_FOR_1_MOD_CLK Setting */ 147 #define MXC_V_SPIXFM_CTRL_SSIACT_FOR_3_MOD_CLK ((uint32_t)0x1UL) /**< CTRL_SSIACT_FOR_3_MOD_CLK Value */ 148 #define MXC_S_SPIXFM_CTRL_SSIACT_FOR_3_MOD_CLK (MXC_V_SPIXFM_CTRL_SSIACT_FOR_3_MOD_CLK << MXC_F_SPIXFM_CTRL_SSIACT_POS) /**< CTRL_SSIACT_FOR_3_MOD_CLK Setting */ 149 #define MXC_V_SPIXFM_CTRL_SSIACT_FOR_5_MOD_CLK ((uint32_t)0x2UL) /**< CTRL_SSIACT_FOR_5_MOD_CLK Value */ 150 #define MXC_S_SPIXFM_CTRL_SSIACT_FOR_5_MOD_CLK (MXC_V_SPIXFM_CTRL_SSIACT_FOR_5_MOD_CLK << MXC_F_SPIXFM_CTRL_SSIACT_POS) /**< CTRL_SSIACT_FOR_5_MOD_CLK Setting */ 151 #define MXC_V_SPIXFM_CTRL_SSIACT_FOR_9_MOD_CLK ((uint32_t)0x3UL) /**< CTRL_SSIACT_FOR_9_MOD_CLK Value */ 152 #define MXC_S_SPIXFM_CTRL_SSIACT_FOR_9_MOD_CLK (MXC_V_SPIXFM_CTRL_SSIACT_FOR_9_MOD_CLK << MXC_F_SPIXFM_CTRL_SSIACT_POS) /**< CTRL_SSIACT_FOR_9_MOD_CLK Setting */ 153 154 /**@} end of group SPIXFM_CTRL_Register */ 155 156 /** 157 * @ingroup spixfm_registers 158 * @defgroup SPIXFM_FETCHCTRL SPIXFM_FETCHCTRL 159 * @brief SPIX Fetch Control Register. 160 * @{ 161 */ 162 #define MXC_F_SPIXFM_FETCHCTRL_CMDVAL_POS 0 /**< FETCHCTRL_CMDVAL Position */ 163 #define MXC_F_SPIXFM_FETCHCTRL_CMDVAL ((uint32_t)(0xFFUL << MXC_F_SPIXFM_FETCHCTRL_CMDVAL_POS)) /**< FETCHCTRL_CMDVAL Mask */ 164 165 #define MXC_F_SPIXFM_FETCHCTRL_CMDWTH_POS 8 /**< FETCHCTRL_CMDWTH Position */ 166 #define MXC_F_SPIXFM_FETCHCTRL_CMDWTH ((uint32_t)(0x3UL << MXC_F_SPIXFM_FETCHCTRL_CMDWTH_POS)) /**< FETCHCTRL_CMDWTH Mask */ 167 #define MXC_V_SPIXFM_FETCHCTRL_CMDWTH_SINGLE ((uint32_t)0x0UL) /**< FETCHCTRL_CMDWTH_SINGLE Value */ 168 #define MXC_S_SPIXFM_FETCHCTRL_CMDWTH_SINGLE (MXC_V_SPIXFM_FETCHCTRL_CMDWTH_SINGLE << MXC_F_SPIXFM_FETCHCTRL_CMDWTH_POS) /**< FETCHCTRL_CMDWTH_SINGLE Setting */ 169 #define MXC_V_SPIXFM_FETCHCTRL_CMDWTH_DUAL_IO ((uint32_t)0x1UL) /**< FETCHCTRL_CMDWTH_DUAL_IO Value */ 170 #define MXC_S_SPIXFM_FETCHCTRL_CMDWTH_DUAL_IO (MXC_V_SPIXFM_FETCHCTRL_CMDWTH_DUAL_IO << MXC_F_SPIXFM_FETCHCTRL_CMDWTH_POS) /**< FETCHCTRL_CMDWTH_DUAL_IO Setting */ 171 #define MXC_V_SPIXFM_FETCHCTRL_CMDWTH_QUAD_IO ((uint32_t)0x2UL) /**< FETCHCTRL_CMDWTH_QUAD_IO Value */ 172 #define MXC_S_SPIXFM_FETCHCTRL_CMDWTH_QUAD_IO (MXC_V_SPIXFM_FETCHCTRL_CMDWTH_QUAD_IO << MXC_F_SPIXFM_FETCHCTRL_CMDWTH_POS) /**< FETCHCTRL_CMDWTH_QUAD_IO Setting */ 173 #define MXC_V_SPIXFM_FETCHCTRL_CMDWTH_INVALID ((uint32_t)0x3UL) /**< FETCHCTRL_CMDWTH_INVALID Value */ 174 #define MXC_S_SPIXFM_FETCHCTRL_CMDWTH_INVALID (MXC_V_SPIXFM_FETCHCTRL_CMDWTH_INVALID << MXC_F_SPIXFM_FETCHCTRL_CMDWTH_POS) /**< FETCHCTRL_CMDWTH_INVALID Setting */ 175 176 #define MXC_F_SPIXFM_FETCHCTRL_ADDR_WIDTH_POS 10 /**< FETCHCTRL_ADDR_WIDTH Position */ 177 #define MXC_F_SPIXFM_FETCHCTRL_ADDR_WIDTH ((uint32_t)(0x3UL << MXC_F_SPIXFM_FETCHCTRL_ADDR_WIDTH_POS)) /**< FETCHCTRL_ADDR_WIDTH Mask */ 178 #define MXC_V_SPIXFM_FETCHCTRL_ADDR_WIDTH_SINGLE ((uint32_t)0x0UL) /**< FETCHCTRL_ADDR_WIDTH_SINGLE Value */ 179 #define MXC_S_SPIXFM_FETCHCTRL_ADDR_WIDTH_SINGLE (MXC_V_SPIXFM_FETCHCTRL_ADDR_WIDTH_SINGLE << MXC_F_SPIXFM_FETCHCTRL_ADDR_WIDTH_POS) /**< FETCHCTRL_ADDR_WIDTH_SINGLE Setting */ 180 #define MXC_V_SPIXFM_FETCHCTRL_ADDR_WIDTH_DUAL_IO ((uint32_t)0x1UL) /**< FETCHCTRL_ADDR_WIDTH_DUAL_IO Value */ 181 #define MXC_S_SPIXFM_FETCHCTRL_ADDR_WIDTH_DUAL_IO (MXC_V_SPIXFM_FETCHCTRL_ADDR_WIDTH_DUAL_IO << MXC_F_SPIXFM_FETCHCTRL_ADDR_WIDTH_POS) /**< FETCHCTRL_ADDR_WIDTH_DUAL_IO Setting */ 182 #define MXC_V_SPIXFM_FETCHCTRL_ADDR_WIDTH_QUAD_IO ((uint32_t)0x2UL) /**< FETCHCTRL_ADDR_WIDTH_QUAD_IO Value */ 183 #define MXC_S_SPIXFM_FETCHCTRL_ADDR_WIDTH_QUAD_IO (MXC_V_SPIXFM_FETCHCTRL_ADDR_WIDTH_QUAD_IO << MXC_F_SPIXFM_FETCHCTRL_ADDR_WIDTH_POS) /**< FETCHCTRL_ADDR_WIDTH_QUAD_IO Setting */ 184 #define MXC_V_SPIXFM_FETCHCTRL_ADDR_WIDTH_INVALID ((uint32_t)0x3UL) /**< FETCHCTRL_ADDR_WIDTH_INVALID Value */ 185 #define MXC_S_SPIXFM_FETCHCTRL_ADDR_WIDTH_INVALID (MXC_V_SPIXFM_FETCHCTRL_ADDR_WIDTH_INVALID << MXC_F_SPIXFM_FETCHCTRL_ADDR_WIDTH_POS) /**< FETCHCTRL_ADDR_WIDTH_INVALID Setting */ 186 187 #define MXC_F_SPIXFM_FETCHCTRL_DATA_WIDTH_POS 12 /**< FETCHCTRL_DATA_WIDTH Position */ 188 #define MXC_F_SPIXFM_FETCHCTRL_DATA_WIDTH ((uint32_t)(0x3UL << MXC_F_SPIXFM_FETCHCTRL_DATA_WIDTH_POS)) /**< FETCHCTRL_DATA_WIDTH Mask */ 189 #define MXC_V_SPIXFM_FETCHCTRL_DATA_WIDTH_SINGLE ((uint32_t)0x0UL) /**< FETCHCTRL_DATA_WIDTH_SINGLE Value */ 190 #define MXC_S_SPIXFM_FETCHCTRL_DATA_WIDTH_SINGLE (MXC_V_SPIXFM_FETCHCTRL_DATA_WIDTH_SINGLE << MXC_F_SPIXFM_FETCHCTRL_DATA_WIDTH_POS) /**< FETCHCTRL_DATA_WIDTH_SINGLE Setting */ 191 #define MXC_V_SPIXFM_FETCHCTRL_DATA_WIDTH_DUAL_IO ((uint32_t)0x1UL) /**< FETCHCTRL_DATA_WIDTH_DUAL_IO Value */ 192 #define MXC_S_SPIXFM_FETCHCTRL_DATA_WIDTH_DUAL_IO (MXC_V_SPIXFM_FETCHCTRL_DATA_WIDTH_DUAL_IO << MXC_F_SPIXFM_FETCHCTRL_DATA_WIDTH_POS) /**< FETCHCTRL_DATA_WIDTH_DUAL_IO Setting */ 193 #define MXC_V_SPIXFM_FETCHCTRL_DATA_WIDTH_QUAD_IO ((uint32_t)0x2UL) /**< FETCHCTRL_DATA_WIDTH_QUAD_IO Value */ 194 #define MXC_S_SPIXFM_FETCHCTRL_DATA_WIDTH_QUAD_IO (MXC_V_SPIXFM_FETCHCTRL_DATA_WIDTH_QUAD_IO << MXC_F_SPIXFM_FETCHCTRL_DATA_WIDTH_POS) /**< FETCHCTRL_DATA_WIDTH_QUAD_IO Setting */ 195 #define MXC_V_SPIXFM_FETCHCTRL_DATA_WIDTH_INVALID ((uint32_t)0x3UL) /**< FETCHCTRL_DATA_WIDTH_INVALID Value */ 196 #define MXC_S_SPIXFM_FETCHCTRL_DATA_WIDTH_INVALID (MXC_V_SPIXFM_FETCHCTRL_DATA_WIDTH_INVALID << MXC_F_SPIXFM_FETCHCTRL_DATA_WIDTH_POS) /**< FETCHCTRL_DATA_WIDTH_INVALID Setting */ 197 198 #define MXC_F_SPIXFM_FETCHCTRL_4BADDR_POS 16 /**< FETCHCTRL_4BADDR Position */ 199 #define MXC_F_SPIXFM_FETCHCTRL_4BADDR ((uint32_t)(0x1UL << MXC_F_SPIXFM_FETCHCTRL_4BADDR_POS)) /**< FETCHCTRL_4BADDR Mask */ 200 201 /**@} end of group SPIXFM_FETCHCTRL_Register */ 202 203 /** 204 * @ingroup spixfm_registers 205 * @defgroup SPIXFM_MODECTRL SPIXFM_MODECTRL 206 * @brief SPIX Mode Control Register. 207 * @{ 208 */ 209 #define MXC_F_SPIXFM_MODECTRL_MDCLK_POS 0 /**< MODECTRL_MDCLK Position */ 210 #define MXC_F_SPIXFM_MODECTRL_MDCLK ((uint32_t)(0xFUL << MXC_F_SPIXFM_MODECTRL_MDCLK_POS)) /**< MODECTRL_MDCLK Mask */ 211 212 #define MXC_F_SPIXFM_MODECTRL_NOCMD_POS 8 /**< MODECTRL_NOCMD Position */ 213 #define MXC_F_SPIXFM_MODECTRL_NOCMD ((uint32_t)(0x1UL << MXC_F_SPIXFM_MODECTRL_NOCMD_POS)) /**< MODECTRL_NOCMD Mask */ 214 215 #define MXC_F_SPIXFM_MODECTRL_EXIT_NOCMD_POS 9 /**< MODECTRL_EXIT_NOCMD Position */ 216 #define MXC_F_SPIXFM_MODECTRL_EXIT_NOCMD ((uint32_t)(0x1UL << MXC_F_SPIXFM_MODECTRL_EXIT_NOCMD_POS)) /**< MODECTRL_EXIT_NOCMD Mask */ 217 218 /**@} end of group SPIXFM_MODECTRL_Register */ 219 220 /** 221 * @ingroup spixfm_registers 222 * @defgroup SPIXFM_MODEDATA SPIXFM_MODEDATA 223 * @brief SPIX Mode Data Register. 224 * @{ 225 */ 226 #define MXC_F_SPIXFM_MODEDATA_MDDATA_POS 0 /**< MODEDATA_MDDATA Position */ 227 #define MXC_F_SPIXFM_MODEDATA_MDDATA ((uint32_t)(0xFFFFUL << MXC_F_SPIXFM_MODEDATA_MDDATA_POS)) /**< MODEDATA_MDDATA Mask */ 228 229 #define MXC_F_SPIXFM_MODEDATA_MDOUT_EN_POS 16 /**< MODEDATA_MDOUT_EN Position */ 230 #define MXC_F_SPIXFM_MODEDATA_MDOUT_EN ((uint32_t)(0xFFFFUL << MXC_F_SPIXFM_MODEDATA_MDOUT_EN_POS)) /**< MODEDATA_MDOUT_EN Mask */ 231 232 /**@} end of group SPIXFM_MODEDATA_Register */ 233 234 /** 235 * @ingroup spixfm_registers 236 * @defgroup SPIXFM_FBCTRL SPIXFM_FBCTRL 237 * @brief SPIX Feedback Control Register. 238 * @{ 239 */ 240 #define MXC_F_SPIXFM_FBCTRL_FB_EN_POS 0 /**< FBCTRL_FB_EN Position */ 241 #define MXC_F_SPIXFM_FBCTRL_FB_EN ((uint32_t)(0x1UL << MXC_F_SPIXFM_FBCTRL_FB_EN_POS)) /**< FBCTRL_FB_EN Mask */ 242 243 #define MXC_F_SPIXFM_FBCTRL_INVERT_POS 1 /**< FBCTRL_INVERT Position */ 244 #define MXC_F_SPIXFM_FBCTRL_INVERT ((uint32_t)(0x1UL << MXC_F_SPIXFM_FBCTRL_INVERT_POS)) /**< FBCTRL_INVERT Mask */ 245 246 /**@} end of group SPIXFM_FBCTRL_Register */ 247 248 /** 249 * @ingroup spixfm_registers 250 * @defgroup SPIXFM_IOCTRL SPIXFM_IOCTRL 251 * @brief SPIX IO Control Register. 252 * @{ 253 */ 254 #define MXC_F_SPIXFM_IOCTRL_SCLK_DS_POS 0 /**< IOCTRL_SCLK_DS Position */ 255 #define MXC_F_SPIXFM_IOCTRL_SCLK_DS ((uint32_t)(0x1UL << MXC_F_SPIXFM_IOCTRL_SCLK_DS_POS)) /**< IOCTRL_SCLK_DS Mask */ 256 257 #define MXC_F_SPIXFM_IOCTRL_SS_DS_POS 1 /**< IOCTRL_SS_DS Position */ 258 #define MXC_F_SPIXFM_IOCTRL_SS_DS ((uint32_t)(0x1UL << MXC_F_SPIXFM_IOCTRL_SS_DS_POS)) /**< IOCTRL_SS_DS Mask */ 259 260 #define MXC_F_SPIXFM_IOCTRL_SDIO_DS_POS 2 /**< IOCTRL_SDIO_DS Position */ 261 #define MXC_F_SPIXFM_IOCTRL_SDIO_DS ((uint32_t)(0x1UL << MXC_F_SPIXFM_IOCTRL_SDIO_DS_POS)) /**< IOCTRL_SDIO_DS Mask */ 262 263 #define MXC_F_SPIXFM_IOCTRL_PADCTRL_POS 3 /**< IOCTRL_PADCTRL Position */ 264 #define MXC_F_SPIXFM_IOCTRL_PADCTRL ((uint32_t)(0x3UL << MXC_F_SPIXFM_IOCTRL_PADCTRL_POS)) /**< IOCTRL_PADCTRL Mask */ 265 #define MXC_V_SPIXFM_IOCTRL_PADCTRL_TRI_STATE ((uint32_t)0x0UL) /**< IOCTRL_PADCTRL_TRI_STATE Value */ 266 #define MXC_S_SPIXFM_IOCTRL_PADCTRL_TRI_STATE (MXC_V_SPIXFM_IOCTRL_PADCTRL_TRI_STATE << MXC_F_SPIXFM_IOCTRL_PADCTRL_POS) /**< IOCTRL_PADCTRL_TRI_STATE Setting */ 267 #define MXC_V_SPIXFM_IOCTRL_PADCTRL_PULL_UP ((uint32_t)0x1UL) /**< IOCTRL_PADCTRL_PULL_UP Value */ 268 #define MXC_S_SPIXFM_IOCTRL_PADCTRL_PULL_UP (MXC_V_SPIXFM_IOCTRL_PADCTRL_PULL_UP << MXC_F_SPIXFM_IOCTRL_PADCTRL_POS) /**< IOCTRL_PADCTRL_PULL_UP Setting */ 269 #define MXC_V_SPIXFM_IOCTRL_PADCTRL_PULL_DOWN ((uint32_t)0x2UL) /**< IOCTRL_PADCTRL_PULL_DOWN Value */ 270 #define MXC_S_SPIXFM_IOCTRL_PADCTRL_PULL_DOWN (MXC_V_SPIXFM_IOCTRL_PADCTRL_PULL_DOWN << MXC_F_SPIXFM_IOCTRL_PADCTRL_POS) /**< IOCTRL_PADCTRL_PULL_DOWN Setting */ 271 272 /**@} end of group SPIXFM_IOCTRL_Register */ 273 274 /** 275 * @ingroup spixfm_registers 276 * @defgroup SPIXFM_MEMSECCTRL SPIXFM_MEMSECCTRL 277 * @brief SPIX Memory Security Control Register. 278 * @{ 279 */ 280 #define MXC_F_SPIXFM_MEMSECCTRL_DEC_EN_POS 0 /**< MEMSECCTRL_DEC_EN Position */ 281 #define MXC_F_SPIXFM_MEMSECCTRL_DEC_EN ((uint32_t)(0x1UL << MXC_F_SPIXFM_MEMSECCTRL_DEC_EN_POS)) /**< MEMSECCTRL_DEC_EN Mask */ 282 283 #define MXC_F_SPIXFM_MEMSECCTRL_AUTH_DISABLE_POS 1 /**< MEMSECCTRL_AUTH_DISABLE Position */ 284 #define MXC_F_SPIXFM_MEMSECCTRL_AUTH_DISABLE ((uint32_t)(0x1UL << MXC_F_SPIXFM_MEMSECCTRL_AUTH_DISABLE_POS)) /**< MEMSECCTRL_AUTH_DISABLE Mask */ 285 286 #define MXC_F_SPIXFM_MEMSECCTRL_CNTOPT_EN_POS 2 /**< MEMSECCTRL_CNTOPT_EN Position */ 287 #define MXC_F_SPIXFM_MEMSECCTRL_CNTOPT_EN ((uint32_t)(0x1UL << MXC_F_SPIXFM_MEMSECCTRL_CNTOPT_EN_POS)) /**< MEMSECCTRL_CNTOPT_EN Mask */ 288 289 #define MXC_F_SPIXFM_MEMSECCTRL_INTERL_DIS_POS 3 /**< MEMSECCTRL_INTERL_DIS Position */ 290 #define MXC_F_SPIXFM_MEMSECCTRL_INTERL_DIS ((uint32_t)(0x1UL << MXC_F_SPIXFM_MEMSECCTRL_INTERL_DIS_POS)) /**< MEMSECCTRL_INTERL_DIS Mask */ 291 292 #define MXC_F_SPIXFM_MEMSECCTRL_AUTHERR_FL_POS 4 /**< MEMSECCTRL_AUTHERR_FL Position */ 293 #define MXC_F_SPIXFM_MEMSECCTRL_AUTHERR_FL ((uint32_t)(0x1UL << MXC_F_SPIXFM_MEMSECCTRL_AUTHERR_FL_POS)) /**< MEMSECCTRL_AUTHERR_FL Mask */ 294 295 /**@} end of group SPIXFM_MEMSECCTRL_Register */ 296 297 /** 298 * @ingroup spixfm_registers 299 * @defgroup SPIXFM_BUSIDLE SPIXFM_BUSIDLE 300 * @brief Bus Idle 301 * @{ 302 */ 303 #define MXC_F_SPIXFM_BUSIDLE_BUSIDLE_POS 0 /**< BUSIDLE_BUSIDLE Position */ 304 #define MXC_F_SPIXFM_BUSIDLE_BUSIDLE ((uint32_t)(0xFFFFUL << MXC_F_SPIXFM_BUSIDLE_BUSIDLE_POS)) /**< BUSIDLE_BUSIDLE Mask */ 305 306 /**@} end of group SPIXFM_BUSIDLE_Register */ 307 308 #ifdef __cplusplus 309 } 310 #endif 311 312 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_SPIXFM_REGS_H_ 313
