1 /** 2 * @file spixfc_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SPIXFC Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup spixfc_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_SPIXFC_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_SPIXFC_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup spixfc 67 * @defgroup spixfc_registers SPIXFC_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the SPIXFC Peripheral Module. 69 * @details SPI XiP Flash Configuration Controller 70 */ 71 72 /** 73 * @ingroup spixfc_registers 74 * Structure type to access the SPIXFC Registers. 75 */ 76 typedef struct { 77 __IO uint32_t ctrl0; /**< <tt>\b 0x00:</tt> SPIXFC CTRL0 Register */ 78 __IO uint32_t sspol; /**< <tt>\b 0x04:</tt> SPIXFC SSPOL Register */ 79 __IO uint32_t ctrl1; /**< <tt>\b 0x08:</tt> SPIXFC CTRL1 Register */ 80 __IO uint32_t ctrl2; /**< <tt>\b 0x0C:</tt> SPIXFC CTRL2 Register */ 81 __IO uint32_t ctrl3; /**< <tt>\b 0x10:</tt> SPIXFC CTRL3 Register */ 82 __IO uint32_t intfl; /**< <tt>\b 0x14:</tt> SPIXFC INTFL Register */ 83 __IO uint32_t inten; /**< <tt>\b 0x18:</tt> SPIXFC INTEN Register */ 84 __IO uint32_t simple_header; /**< <tt>\b 0x1C:</tt> SPIXFC SIMPLE_HEADER Register */ 85 } mxc_spixfc_regs_t; 86 87 /* Register offsets for module SPIXFC */ 88 /** 89 * @ingroup spixfc_registers 90 * @defgroup SPIXFC_Register_Offsets Register Offsets 91 * @brief SPIXFC Peripheral Register Offsets from the SPIXFC Base Peripheral Address. 92 * @{ 93 */ 94 #define MXC_R_SPIXFC_CTRL0 ((uint32_t)0x00000000UL) /**< Offset from SPIXFC Base Address: <tt> 0x0000</tt> */ 95 #define MXC_R_SPIXFC_SSPOL ((uint32_t)0x00000004UL) /**< Offset from SPIXFC Base Address: <tt> 0x0004</tt> */ 96 #define MXC_R_SPIXFC_CTRL1 ((uint32_t)0x00000008UL) /**< Offset from SPIXFC Base Address: <tt> 0x0008</tt> */ 97 #define MXC_R_SPIXFC_CTRL2 ((uint32_t)0x0000000CUL) /**< Offset from SPIXFC Base Address: <tt> 0x000C</tt> */ 98 #define MXC_R_SPIXFC_CTRL3 ((uint32_t)0x00000010UL) /**< Offset from SPIXFC Base Address: <tt> 0x0010</tt> */ 99 #define MXC_R_SPIXFC_INTFL ((uint32_t)0x00000014UL) /**< Offset from SPIXFC Base Address: <tt> 0x0014</tt> */ 100 #define MXC_R_SPIXFC_INTEN ((uint32_t)0x00000018UL) /**< Offset from SPIXFC Base Address: <tt> 0x0018</tt> */ 101 #define MXC_R_SPIXFC_SIMPLE_HEADER ((uint32_t)0x0000001CUL) /**< Offset from SPIXFC Base Address: <tt> 0x001C</tt> */ 102 /**@} end of group spixfc_registers */ 103 104 /** 105 * @ingroup spixfc_registers 106 * @defgroup SPIXFC_CTRL0 SPIXFC_CTRL0 107 * @brief Control Register. 108 * @{ 109 */ 110 #define MXC_F_SPIXFC_CTRL0_SSEL_POS 0 /**< CTRL0_SSEL Position */ 111 #define MXC_F_SPIXFC_CTRL0_SSEL ((uint32_t)(0x7UL << MXC_F_SPIXFC_CTRL0_SSEL_POS)) /**< CTRL0_SSEL Mask */ 112 #define MXC_V_SPIXFC_CTRL0_SSEL_SLAVE_0 ((uint32_t)0x0UL) /**< CTRL0_SSEL_SLAVE_0 Value */ 113 #define MXC_S_SPIXFC_CTRL0_SSEL_SLAVE_0 (MXC_V_SPIXFC_CTRL0_SSEL_SLAVE_0 << MXC_F_SPIXFC_CTRL0_SSEL_POS) /**< CTRL0_SSEL_SLAVE_0 Setting */ 114 #define MXC_V_SPIXFC_CTRL0_SSEL_SLAVE_1 ((uint32_t)0x1UL) /**< CTRL0_SSEL_SLAVE_1 Value */ 115 #define MXC_S_SPIXFC_CTRL0_SSEL_SLAVE_1 (MXC_V_SPIXFC_CTRL0_SSEL_SLAVE_1 << MXC_F_SPIXFC_CTRL0_SSEL_POS) /**< CTRL0_SSEL_SLAVE_1 Setting */ 116 117 #define MXC_F_SPIXFC_CTRL0_THREE_WIRE_POS 3 /**< CTRL0_THREE_WIRE Position */ 118 #define MXC_F_SPIXFC_CTRL0_THREE_WIRE ((uint32_t)(0x1UL << MXC_F_SPIXFC_CTRL0_THREE_WIRE_POS)) /**< CTRL0_THREE_WIRE Mask */ 119 120 #define MXC_F_SPIXFC_CTRL0_MODE_POS 4 /**< CTRL0_MODE Position */ 121 #define MXC_F_SPIXFC_CTRL0_MODE ((uint32_t)(0x3UL << MXC_F_SPIXFC_CTRL0_MODE_POS)) /**< CTRL0_MODE Mask */ 122 #define MXC_V_SPIXFC_CTRL0_MODE_SPI_MODE_0 ((uint32_t)0x0UL) /**< CTRL0_MODE_SPI_MODE_0 Value */ 123 #define MXC_S_SPIXFC_CTRL0_MODE_SPI_MODE_0 (MXC_V_SPIXFC_CTRL0_MODE_SPI_MODE_0 << MXC_F_SPIXFC_CTRL0_MODE_POS) /**< CTRL0_MODE_SPI_MODE_0 Setting */ 124 #define MXC_V_SPIXFC_CTRL0_MODE_SPI_MODE_3 ((uint32_t)0x3UL) /**< CTRL0_MODE_SPI_MODE_3 Value */ 125 #define MXC_S_SPIXFC_CTRL0_MODE_SPI_MODE_3 (MXC_V_SPIXFC_CTRL0_MODE_SPI_MODE_3 << MXC_F_SPIXFC_CTRL0_MODE_POS) /**< CTRL0_MODE_SPI_MODE_3 Setting */ 126 127 #define MXC_F_SPIXFC_CTRL0_PGSZ_POS 6 /**< CTRL0_PGSZ Position */ 128 #define MXC_F_SPIXFC_CTRL0_PGSZ ((uint32_t)(0x3UL << MXC_F_SPIXFC_CTRL0_PGSZ_POS)) /**< CTRL0_PGSZ Mask */ 129 #define MXC_V_SPIXFC_CTRL0_PGSZ_4_BYTES ((uint32_t)0x0UL) /**< CTRL0_PGSZ_4_BYTES Value */ 130 #define MXC_S_SPIXFC_CTRL0_PGSZ_4_BYTES (MXC_V_SPIXFC_CTRL0_PGSZ_4_BYTES << MXC_F_SPIXFC_CTRL0_PGSZ_POS) /**< CTRL0_PGSZ_4_BYTES Setting */ 131 #define MXC_V_SPIXFC_CTRL0_PGSZ_8_BYTES ((uint32_t)0x1UL) /**< CTRL0_PGSZ_8_BYTES Value */ 132 #define MXC_S_SPIXFC_CTRL0_PGSZ_8_BYTES (MXC_V_SPIXFC_CTRL0_PGSZ_8_BYTES << MXC_F_SPIXFC_CTRL0_PGSZ_POS) /**< CTRL0_PGSZ_8_BYTES Setting */ 133 #define MXC_V_SPIXFC_CTRL0_PGSZ_16_BYTES ((uint32_t)0x2UL) /**< CTRL0_PGSZ_16_BYTES Value */ 134 #define MXC_S_SPIXFC_CTRL0_PGSZ_16_BYTES (MXC_V_SPIXFC_CTRL0_PGSZ_16_BYTES << MXC_F_SPIXFC_CTRL0_PGSZ_POS) /**< CTRL0_PGSZ_16_BYTES Setting */ 135 #define MXC_V_SPIXFC_CTRL0_PGSZ_32_BYTES ((uint32_t)0x3UL) /**< CTRL0_PGSZ_32_BYTES Value */ 136 #define MXC_S_SPIXFC_CTRL0_PGSZ_32_BYTES (MXC_V_SPIXFC_CTRL0_PGSZ_32_BYTES << MXC_F_SPIXFC_CTRL0_PGSZ_POS) /**< CTRL0_PGSZ_32_BYTES Setting */ 137 138 #define MXC_F_SPIXFC_CTRL0_HICLK_POS 8 /**< CTRL0_HICLK Position */ 139 #define MXC_F_SPIXFC_CTRL0_HICLK ((uint32_t)(0xFUL << MXC_F_SPIXFC_CTRL0_HICLK_POS)) /**< CTRL0_HICLK Mask */ 140 #define MXC_V_SPIXFC_CTRL0_HICLK_16_SCLK ((uint32_t)0x0UL) /**< CTRL0_HICLK_16_SCLK Value */ 141 #define MXC_S_SPIXFC_CTRL0_HICLK_16_SCLK (MXC_V_SPIXFC_CTRL0_HICLK_16_SCLK << MXC_F_SPIXFC_CTRL0_HICLK_POS) /**< CTRL0_HICLK_16_SCLK Setting */ 142 143 #define MXC_F_SPIXFC_CTRL0_LOCLK_POS 12 /**< CTRL0_LOCLK Position */ 144 #define MXC_F_SPIXFC_CTRL0_LOCLK ((uint32_t)(0xFUL << MXC_F_SPIXFC_CTRL0_LOCLK_POS)) /**< CTRL0_LOCLK Mask */ 145 #define MXC_V_SPIXFC_CTRL0_LOCLK_16_SCLK ((uint32_t)0x0UL) /**< CTRL0_LOCLK_16_SCLK Value */ 146 #define MXC_S_SPIXFC_CTRL0_LOCLK_16_SCLK (MXC_V_SPIXFC_CTRL0_LOCLK_16_SCLK << MXC_F_SPIXFC_CTRL0_LOCLK_POS) /**< CTRL0_LOCLK_16_SCLK Setting */ 147 148 #define MXC_F_SPIXFC_CTRL0_SSACT_POS 16 /**< CTRL0_SSACT Position */ 149 #define MXC_F_SPIXFC_CTRL0_SSACT ((uint32_t)(0x3UL << MXC_F_SPIXFC_CTRL0_SSACT_POS)) /**< CTRL0_SSACT Mask */ 150 #define MXC_V_SPIXFC_CTRL0_SSACT_0_CLKS ((uint32_t)0x0UL) /**< CTRL0_SSACT_0_CLKS Value */ 151 #define MXC_S_SPIXFC_CTRL0_SSACT_0_CLKS (MXC_V_SPIXFC_CTRL0_SSACT_0_CLKS << MXC_F_SPIXFC_CTRL0_SSACT_POS) /**< CTRL0_SSACT_0_CLKS Setting */ 152 #define MXC_V_SPIXFC_CTRL0_SSACT_2_CLKS ((uint32_t)0x1UL) /**< CTRL0_SSACT_2_CLKS Value */ 153 #define MXC_S_SPIXFC_CTRL0_SSACT_2_CLKS (MXC_V_SPIXFC_CTRL0_SSACT_2_CLKS << MXC_F_SPIXFC_CTRL0_SSACT_POS) /**< CTRL0_SSACT_2_CLKS Setting */ 154 #define MXC_V_SPIXFC_CTRL0_SSACT_4_CLKS ((uint32_t)0x2UL) /**< CTRL0_SSACT_4_CLKS Value */ 155 #define MXC_S_SPIXFC_CTRL0_SSACT_4_CLKS (MXC_V_SPIXFC_CTRL0_SSACT_4_CLKS << MXC_F_SPIXFC_CTRL0_SSACT_POS) /**< CTRL0_SSACT_4_CLKS Setting */ 156 #define MXC_V_SPIXFC_CTRL0_SSACT_8_CLKS ((uint32_t)0x3UL) /**< CTRL0_SSACT_8_CLKS Value */ 157 #define MXC_S_SPIXFC_CTRL0_SSACT_8_CLKS (MXC_V_SPIXFC_CTRL0_SSACT_8_CLKS << MXC_F_SPIXFC_CTRL0_SSACT_POS) /**< CTRL0_SSACT_8_CLKS Setting */ 158 159 #define MXC_F_SPIXFC_CTRL0_SSIACT_POS 18 /**< CTRL0_SSIACT Position */ 160 #define MXC_F_SPIXFC_CTRL0_SSIACT ((uint32_t)(0x3UL << MXC_F_SPIXFC_CTRL0_SSIACT_POS)) /**< CTRL0_SSIACT Mask */ 161 #define MXC_V_SPIXFC_CTRL0_SSIACT_4_CLKS ((uint32_t)0x0UL) /**< CTRL0_SSIACT_4_CLKS Value */ 162 #define MXC_S_SPIXFC_CTRL0_SSIACT_4_CLKS (MXC_V_SPIXFC_CTRL0_SSIACT_4_CLKS << MXC_F_SPIXFC_CTRL0_SSIACT_POS) /**< CTRL0_SSIACT_4_CLKS Setting */ 163 #define MXC_V_SPIXFC_CTRL0_SSIACT_6_CLKS ((uint32_t)0x1UL) /**< CTRL0_SSIACT_6_CLKS Value */ 164 #define MXC_S_SPIXFC_CTRL0_SSIACT_6_CLKS (MXC_V_SPIXFC_CTRL0_SSIACT_6_CLKS << MXC_F_SPIXFC_CTRL0_SSIACT_POS) /**< CTRL0_SSIACT_6_CLKS Setting */ 165 #define MXC_V_SPIXFC_CTRL0_SSIACT_8_CLKS ((uint32_t)0x2UL) /**< CTRL0_SSIACT_8_CLKS Value */ 166 #define MXC_S_SPIXFC_CTRL0_SSIACT_8_CLKS (MXC_V_SPIXFC_CTRL0_SSIACT_8_CLKS << MXC_F_SPIXFC_CTRL0_SSIACT_POS) /**< CTRL0_SSIACT_8_CLKS Setting */ 167 #define MXC_V_SPIXFC_CTRL0_SSIACT_12_CLKS ((uint32_t)0x3UL) /**< CTRL0_SSIACT_12_CLKS Value */ 168 #define MXC_S_SPIXFC_CTRL0_SSIACT_12_CLKS (MXC_V_SPIXFC_CTRL0_SSIACT_12_CLKS << MXC_F_SPIXFC_CTRL0_SSIACT_POS) /**< CTRL0_SSIACT_12_CLKS Setting */ 169 170 #define MXC_F_SPIXFC_CTRL0_IOSMPL_POS 20 /**< CTRL0_IOSMPL Position */ 171 #define MXC_F_SPIXFC_CTRL0_IOSMPL ((uint32_t)(0xFUL << MXC_F_SPIXFC_CTRL0_IOSMPL_POS)) /**< CTRL0_IOSMPL Mask */ 172 173 /**@} end of group SPIXFC_CTRL0_Register */ 174 175 /** 176 * @ingroup spixfc_registers 177 * @defgroup SPIXFC_SSPOL SPIXFC_SSPOL 178 * @brief SPIX Controller Slave Select Polarity Register. 179 * @{ 180 */ 181 #define MXC_F_SPIXFC_SSPOL_SS_POL_POS 0 /**< SSPOL_SS_POL Position */ 182 #define MXC_F_SPIXFC_SSPOL_SS_POL ((uint32_t)(0x1UL << MXC_F_SPIXFC_SSPOL_SS_POL_POS)) /**< SSPOL_SS_POL Mask */ 183 184 #define MXC_F_SPIXFC_SSPOL_FC_POL_POS 8 /**< SSPOL_FC_POL Position */ 185 #define MXC_F_SPIXFC_SSPOL_FC_POL ((uint32_t)(0x1UL << MXC_F_SPIXFC_SSPOL_FC_POL_POS)) /**< SSPOL_FC_POL Mask */ 186 187 /**@} end of group SPIXFC_SSPOL_Register */ 188 189 /** 190 * @ingroup spixfc_registers 191 * @defgroup SPIXFC_CTRL1 SPIXFC_CTRL1 192 * @brief SPIX Controller General Controller Register. 193 * @{ 194 */ 195 #define MXC_F_SPIXFC_CTRL1_EN_POS 0 /**< CTRL1_EN Position */ 196 #define MXC_F_SPIXFC_CTRL1_EN ((uint32_t)(0x1UL << MXC_F_SPIXFC_CTRL1_EN_POS)) /**< CTRL1_EN Mask */ 197 198 #define MXC_F_SPIXFC_CTRL1_TX_FIFO_EN_POS 1 /**< CTRL1_TX_FIFO_EN Position */ 199 #define MXC_F_SPIXFC_CTRL1_TX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPIXFC_CTRL1_TX_FIFO_EN_POS)) /**< CTRL1_TX_FIFO_EN Mask */ 200 201 #define MXC_F_SPIXFC_CTRL1_RX_FIFO_EN_POS 2 /**< CTRL1_RX_FIFO_EN Position */ 202 #define MXC_F_SPIXFC_CTRL1_RX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPIXFC_CTRL1_RX_FIFO_EN_POS)) /**< CTRL1_RX_FIFO_EN Mask */ 203 204 #define MXC_F_SPIXFC_CTRL1_BBMODE_POS 3 /**< CTRL1_BBMODE Position */ 205 #define MXC_F_SPIXFC_CTRL1_BBMODE ((uint32_t)(0x1UL << MXC_F_SPIXFC_CTRL1_BBMODE_POS)) /**< CTRL1_BBMODE Mask */ 206 207 #define MXC_F_SPIXFC_CTRL1_SSDR_POS 4 /**< CTRL1_SSDR Position */ 208 #define MXC_F_SPIXFC_CTRL1_SSDR ((uint32_t)(0x1UL << MXC_F_SPIXFC_CTRL1_SSDR_POS)) /**< CTRL1_SSDR Mask */ 209 210 #define MXC_F_SPIXFC_CTRL1_FCDR_POS 5 /**< CTRL1_FCDR Position */ 211 #define MXC_F_SPIXFC_CTRL1_FCDR ((uint32_t)(0x1UL << MXC_F_SPIXFC_CTRL1_FCDR_POS)) /**< CTRL1_FCDR Mask */ 212 213 #define MXC_F_SPIXFC_CTRL1_SCLKDR_POS 6 /**< CTRL1_SCLKDR Position */ 214 #define MXC_F_SPIXFC_CTRL1_SCLKDR ((uint32_t)(0x1UL << MXC_F_SPIXFC_CTRL1_SCLKDR_POS)) /**< CTRL1_SCLKDR Mask */ 215 216 #define MXC_F_SPIXFC_CTRL1_SDIO_DATA_IN_POS 8 /**< CTRL1_SDIO_DATA_IN Position */ 217 #define MXC_F_SPIXFC_CTRL1_SDIO_DATA_IN ((uint32_t)(0xFUL << MXC_F_SPIXFC_CTRL1_SDIO_DATA_IN_POS)) /**< CTRL1_SDIO_DATA_IN Mask */ 218 #define MXC_V_SPIXFC_CTRL1_SDIO_DATA_IN_SDIO0 ((uint32_t)0x0UL) /**< CTRL1_SDIO_DATA_IN_SDIO0 Value */ 219 #define MXC_S_SPIXFC_CTRL1_SDIO_DATA_IN_SDIO0 (MXC_V_SPIXFC_CTRL1_SDIO_DATA_IN_SDIO0 << MXC_F_SPIXFC_CTRL1_SDIO_DATA_IN_POS) /**< CTRL1_SDIO_DATA_IN_SDIO0 Setting */ 220 #define MXC_V_SPIXFC_CTRL1_SDIO_DATA_IN_SDIO1 ((uint32_t)0x1UL) /**< CTRL1_SDIO_DATA_IN_SDIO1 Value */ 221 #define MXC_S_SPIXFC_CTRL1_SDIO_DATA_IN_SDIO1 (MXC_V_SPIXFC_CTRL1_SDIO_DATA_IN_SDIO1 << MXC_F_SPIXFC_CTRL1_SDIO_DATA_IN_POS) /**< CTRL1_SDIO_DATA_IN_SDIO1 Setting */ 222 #define MXC_V_SPIXFC_CTRL1_SDIO_DATA_IN_SDIO2 ((uint32_t)0x2UL) /**< CTRL1_SDIO_DATA_IN_SDIO2 Value */ 223 #define MXC_S_SPIXFC_CTRL1_SDIO_DATA_IN_SDIO2 (MXC_V_SPIXFC_CTRL1_SDIO_DATA_IN_SDIO2 << MXC_F_SPIXFC_CTRL1_SDIO_DATA_IN_POS) /**< CTRL1_SDIO_DATA_IN_SDIO2 Setting */ 224 #define MXC_V_SPIXFC_CTRL1_SDIO_DATA_IN_SDIO3 ((uint32_t)0x3UL) /**< CTRL1_SDIO_DATA_IN_SDIO3 Value */ 225 #define MXC_S_SPIXFC_CTRL1_SDIO_DATA_IN_SDIO3 (MXC_V_SPIXFC_CTRL1_SDIO_DATA_IN_SDIO3 << MXC_F_SPIXFC_CTRL1_SDIO_DATA_IN_POS) /**< CTRL1_SDIO_DATA_IN_SDIO3 Setting */ 226 227 #define MXC_F_SPIXFC_CTRL1_BB_DATA_OUT_POS 12 /**< CTRL1_BB_DATA_OUT Position */ 228 #define MXC_F_SPIXFC_CTRL1_BB_DATA_OUT ((uint32_t)(0xFUL << MXC_F_SPIXFC_CTRL1_BB_DATA_OUT_POS)) /**< CTRL1_BB_DATA_OUT Mask */ 229 #define MXC_V_SPIXFC_CTRL1_BB_DATA_OUT_SDIO0 ((uint32_t)0x0UL) /**< CTRL1_BB_DATA_OUT_SDIO0 Value */ 230 #define MXC_S_SPIXFC_CTRL1_BB_DATA_OUT_SDIO0 (MXC_V_SPIXFC_CTRL1_BB_DATA_OUT_SDIO0 << MXC_F_SPIXFC_CTRL1_BB_DATA_OUT_POS) /**< CTRL1_BB_DATA_OUT_SDIO0 Setting */ 231 #define MXC_V_SPIXFC_CTRL1_BB_DATA_OUT_SDIO1 ((uint32_t)0x1UL) /**< CTRL1_BB_DATA_OUT_SDIO1 Value */ 232 #define MXC_S_SPIXFC_CTRL1_BB_DATA_OUT_SDIO1 (MXC_V_SPIXFC_CTRL1_BB_DATA_OUT_SDIO1 << MXC_F_SPIXFC_CTRL1_BB_DATA_OUT_POS) /**< CTRL1_BB_DATA_OUT_SDIO1 Setting */ 233 #define MXC_V_SPIXFC_CTRL1_BB_DATA_OUT_SDIO2 ((uint32_t)0x2UL) /**< CTRL1_BB_DATA_OUT_SDIO2 Value */ 234 #define MXC_S_SPIXFC_CTRL1_BB_DATA_OUT_SDIO2 (MXC_V_SPIXFC_CTRL1_BB_DATA_OUT_SDIO2 << MXC_F_SPIXFC_CTRL1_BB_DATA_OUT_POS) /**< CTRL1_BB_DATA_OUT_SDIO2 Setting */ 235 #define MXC_V_SPIXFC_CTRL1_BB_DATA_OUT_SDIO3 ((uint32_t)0x3UL) /**< CTRL1_BB_DATA_OUT_SDIO3 Value */ 236 #define MXC_S_SPIXFC_CTRL1_BB_DATA_OUT_SDIO3 (MXC_V_SPIXFC_CTRL1_BB_DATA_OUT_SDIO3 << MXC_F_SPIXFC_CTRL1_BB_DATA_OUT_POS) /**< CTRL1_BB_DATA_OUT_SDIO3 Setting */ 237 238 #define MXC_F_SPIXFC_CTRL1_BB_DATA_OUT_EN_POS 16 /**< CTRL1_BB_DATA_OUT_EN Position */ 239 #define MXC_F_SPIXFC_CTRL1_BB_DATA_OUT_EN ((uint32_t)(0xFUL << MXC_F_SPIXFC_CTRL1_BB_DATA_OUT_EN_POS)) /**< CTRL1_BB_DATA_OUT_EN Mask */ 240 #define MXC_V_SPIXFC_CTRL1_BB_DATA_OUT_EN_SDIO0 ((uint32_t)0x0UL) /**< CTRL1_BB_DATA_OUT_EN_SDIO0 Value */ 241 #define MXC_S_SPIXFC_CTRL1_BB_DATA_OUT_EN_SDIO0 (MXC_V_SPIXFC_CTRL1_BB_DATA_OUT_EN_SDIO0 << MXC_F_SPIXFC_CTRL1_BB_DATA_OUT_EN_POS) /**< CTRL1_BB_DATA_OUT_EN_SDIO0 Setting */ 242 #define MXC_V_SPIXFC_CTRL1_BB_DATA_OUT_EN_SDIO1 ((uint32_t)0x1UL) /**< CTRL1_BB_DATA_OUT_EN_SDIO1 Value */ 243 #define MXC_S_SPIXFC_CTRL1_BB_DATA_OUT_EN_SDIO1 (MXC_V_SPIXFC_CTRL1_BB_DATA_OUT_EN_SDIO1 << MXC_F_SPIXFC_CTRL1_BB_DATA_OUT_EN_POS) /**< CTRL1_BB_DATA_OUT_EN_SDIO1 Setting */ 244 #define MXC_V_SPIXFC_CTRL1_BB_DATA_OUT_EN_SDIO2 ((uint32_t)0x2UL) /**< CTRL1_BB_DATA_OUT_EN_SDIO2 Value */ 245 #define MXC_S_SPIXFC_CTRL1_BB_DATA_OUT_EN_SDIO2 (MXC_V_SPIXFC_CTRL1_BB_DATA_OUT_EN_SDIO2 << MXC_F_SPIXFC_CTRL1_BB_DATA_OUT_EN_POS) /**< CTRL1_BB_DATA_OUT_EN_SDIO2 Setting */ 246 #define MXC_V_SPIXFC_CTRL1_BB_DATA_OUT_EN_SDIO3 ((uint32_t)0x3UL) /**< CTRL1_BB_DATA_OUT_EN_SDIO3 Value */ 247 #define MXC_S_SPIXFC_CTRL1_BB_DATA_OUT_EN_SDIO3 (MXC_V_SPIXFC_CTRL1_BB_DATA_OUT_EN_SDIO3 << MXC_F_SPIXFC_CTRL1_BB_DATA_OUT_EN_POS) /**< CTRL1_BB_DATA_OUT_EN_SDIO3 Setting */ 248 249 #define MXC_F_SPIXFC_CTRL1_SIMPLE_POS 20 /**< CTRL1_SIMPLE Position */ 250 #define MXC_F_SPIXFC_CTRL1_SIMPLE ((uint32_t)(0x1UL << MXC_F_SPIXFC_CTRL1_SIMPLE_POS)) /**< CTRL1_SIMPLE Mask */ 251 252 #define MXC_F_SPIXFC_CTRL1_SIMPLE_RX_POS 21 /**< CTRL1_SIMPLE_RX Position */ 253 #define MXC_F_SPIXFC_CTRL1_SIMPLE_RX ((uint32_t)(0x1UL << MXC_F_SPIXFC_CTRL1_SIMPLE_RX_POS)) /**< CTRL1_SIMPLE_RX Mask */ 254 255 #define MXC_F_SPIXFC_CTRL1_SIMPLE_SS_POS 22 /**< CTRL1_SIMPLE_SS Position */ 256 #define MXC_F_SPIXFC_CTRL1_SIMPLE_SS ((uint32_t)(0x1UL << MXC_F_SPIXFC_CTRL1_SIMPLE_SS_POS)) /**< CTRL1_SIMPLE_SS Mask */ 257 258 #define MXC_F_SPIXFC_CTRL1_SCLK_FB_POS 24 /**< CTRL1_SCLK_FB Position */ 259 #define MXC_F_SPIXFC_CTRL1_SCLK_FB ((uint32_t)(0x1UL << MXC_F_SPIXFC_CTRL1_SCLK_FB_POS)) /**< CTRL1_SCLK_FB Mask */ 260 261 #define MXC_F_SPIXFC_CTRL1_SCLK_FB_INV_POS 25 /**< CTRL1_SCLK_FB_INV Position */ 262 #define MXC_F_SPIXFC_CTRL1_SCLK_FB_INV ((uint32_t)(0x1UL << MXC_F_SPIXFC_CTRL1_SCLK_FB_INV_POS)) /**< CTRL1_SCLK_FB_INV Mask */ 263 264 /**@} end of group SPIXFC_CTRL1_Register */ 265 266 /** 267 * @ingroup spixfc_registers 268 * @defgroup SPIXFC_CTRL2 SPIXFC_CTRL2 269 * @brief SPIX Controller FIFO Control and Status Register. 270 * @{ 271 */ 272 #define MXC_F_SPIXFC_CTRL2_TX_AE_LVL_POS 0 /**< CTRL2_TX_AE_LVL Position */ 273 #define MXC_F_SPIXFC_CTRL2_TX_AE_LVL ((uint32_t)(0xFUL << MXC_F_SPIXFC_CTRL2_TX_AE_LVL_POS)) /**< CTRL2_TX_AE_LVL Mask */ 274 275 #define MXC_F_SPIXFC_CTRL2_TX_CNT_POS 8 /**< CTRL2_TX_CNT Position */ 276 #define MXC_F_SPIXFC_CTRL2_TX_CNT ((uint32_t)(0x1FUL << MXC_F_SPIXFC_CTRL2_TX_CNT_POS)) /**< CTRL2_TX_CNT Mask */ 277 278 #define MXC_F_SPIXFC_CTRL2_RX_AF_LVL_POS 16 /**< CTRL2_RX_AF_LVL Position */ 279 #define MXC_F_SPIXFC_CTRL2_RX_AF_LVL ((uint32_t)(0x1FUL << MXC_F_SPIXFC_CTRL2_RX_AF_LVL_POS)) /**< CTRL2_RX_AF_LVL Mask */ 280 281 #define MXC_F_SPIXFC_CTRL2_RX_CNT_POS 24 /**< CTRL2_RX_CNT Position */ 282 #define MXC_F_SPIXFC_CTRL2_RX_CNT ((uint32_t)(0x3FUL << MXC_F_SPIXFC_CTRL2_RX_CNT_POS)) /**< CTRL2_RX_CNT Mask */ 283 284 /**@} end of group SPIXFC_CTRL2_Register */ 285 286 /** 287 * @ingroup spixfc_registers 288 * @defgroup SPIXFC_CTRL3 SPIXFC_CTRL3 289 * @brief SPIX Controller Special Control Register. 290 * @{ 291 */ 292 #define MXC_F_SPIXFC_CTRL3_SAMPLE_POS 0 /**< CTRL3_SAMPLE Position */ 293 #define MXC_F_SPIXFC_CTRL3_SAMPLE ((uint32_t)(0x1UL << MXC_F_SPIXFC_CTRL3_SAMPLE_POS)) /**< CTRL3_SAMPLE Mask */ 294 295 #define MXC_F_SPIXFC_CTRL3_MISO_FC_EN_POS 1 /**< CTRL3_MISO_FC_EN Position */ 296 #define MXC_F_SPIXFC_CTRL3_MISO_FC_EN ((uint32_t)(0x1UL << MXC_F_SPIXFC_CTRL3_MISO_FC_EN_POS)) /**< CTRL3_MISO_FC_EN Mask */ 297 298 #define MXC_F_SPIXFC_CTRL3_SDIO_OUT_POS 4 /**< CTRL3_SDIO_OUT Position */ 299 #define MXC_F_SPIXFC_CTRL3_SDIO_OUT ((uint32_t)(0xFUL << MXC_F_SPIXFC_CTRL3_SDIO_OUT_POS)) /**< CTRL3_SDIO_OUT Mask */ 300 301 #define MXC_F_SPIXFC_CTRL3_SDIO_OUT_EN_POS 8 /**< CTRL3_SDIO_OUT_EN Position */ 302 #define MXC_F_SPIXFC_CTRL3_SDIO_OUT_EN ((uint32_t)(0xFUL << MXC_F_SPIXFC_CTRL3_SDIO_OUT_EN_POS)) /**< CTRL3_SDIO_OUT_EN Mask */ 303 304 #define MXC_F_SPIXFC_CTRL3_SCLKINH3_POS 16 /**< CTRL3_SCLKINH3 Position */ 305 #define MXC_F_SPIXFC_CTRL3_SCLKINH3 ((uint32_t)(0x1UL << MXC_F_SPIXFC_CTRL3_SCLKINH3_POS)) /**< CTRL3_SCLKINH3 Mask */ 306 307 /**@} end of group SPIXFC_CTRL3_Register */ 308 309 /** 310 * @ingroup spixfc_registers 311 * @defgroup SPIXFC_INTFL SPIXFC_INTFL 312 * @brief SPIX Controller Interrupt Status Register. 313 * @{ 314 */ 315 #define MXC_F_SPIXFC_INTFL_TX_STALLED_POS 0 /**< INTFL_TX_STALLED Position */ 316 #define MXC_F_SPIXFC_INTFL_TX_STALLED ((uint32_t)(0x1UL << MXC_F_SPIXFC_INTFL_TX_STALLED_POS)) /**< INTFL_TX_STALLED Mask */ 317 318 #define MXC_F_SPIXFC_INTFL_RX_STALLED_POS 1 /**< INTFL_RX_STALLED Position */ 319 #define MXC_F_SPIXFC_INTFL_RX_STALLED ((uint32_t)(0x1UL << MXC_F_SPIXFC_INTFL_RX_STALLED_POS)) /**< INTFL_RX_STALLED Mask */ 320 321 #define MXC_F_SPIXFC_INTFL_TX_RDY_POS 2 /**< INTFL_TX_RDY Position */ 322 #define MXC_F_SPIXFC_INTFL_TX_RDY ((uint32_t)(0x1UL << MXC_F_SPIXFC_INTFL_TX_RDY_POS)) /**< INTFL_TX_RDY Mask */ 323 324 #define MXC_F_SPIXFC_INTFL_RX_DONE_POS 3 /**< INTFL_RX_DONE Position */ 325 #define MXC_F_SPIXFC_INTFL_RX_DONE ((uint32_t)(0x1UL << MXC_F_SPIXFC_INTFL_RX_DONE_POS)) /**< INTFL_RX_DONE Mask */ 326 327 #define MXC_F_SPIXFC_INTFL_TX_FIFO_AE_POS 4 /**< INTFL_TX_FIFO_AE Position */ 328 #define MXC_F_SPIXFC_INTFL_TX_FIFO_AE ((uint32_t)(0x1UL << MXC_F_SPIXFC_INTFL_TX_FIFO_AE_POS)) /**< INTFL_TX_FIFO_AE Mask */ 329 330 #define MXC_F_SPIXFC_INTFL_RX_FIFO_AF_POS 5 /**< INTFL_RX_FIFO_AF Position */ 331 #define MXC_F_SPIXFC_INTFL_RX_FIFO_AF ((uint32_t)(0x1UL << MXC_F_SPIXFC_INTFL_RX_FIFO_AF_POS)) /**< INTFL_RX_FIFO_AF Mask */ 332 333 /**@} end of group SPIXFC_INTFL_Register */ 334 335 /** 336 * @ingroup spixfc_registers 337 * @defgroup SPIXFC_INTEN SPIXFC_INTEN 338 * @brief SPIX Controller Interrupt Enable Register. 339 * @{ 340 */ 341 #define MXC_F_SPIXFC_INTEN_TX_STALLED_POS 0 /**< INTEN_TX_STALLED Position */ 342 #define MXC_F_SPIXFC_INTEN_TX_STALLED ((uint32_t)(0x1UL << MXC_F_SPIXFC_INTEN_TX_STALLED_POS)) /**< INTEN_TX_STALLED Mask */ 343 344 #define MXC_F_SPIXFC_INTEN_RX_STALLED_POS 1 /**< INTEN_RX_STALLED Position */ 345 #define MXC_F_SPIXFC_INTEN_RX_STALLED ((uint32_t)(0x1UL << MXC_F_SPIXFC_INTEN_RX_STALLED_POS)) /**< INTEN_RX_STALLED Mask */ 346 347 #define MXC_F_SPIXFC_INTEN_TX_RDY_POS 2 /**< INTEN_TX_RDY Position */ 348 #define MXC_F_SPIXFC_INTEN_TX_RDY ((uint32_t)(0x1UL << MXC_F_SPIXFC_INTEN_TX_RDY_POS)) /**< INTEN_TX_RDY Mask */ 349 350 #define MXC_F_SPIXFC_INTEN_RX_DONE_POS 3 /**< INTEN_RX_DONE Position */ 351 #define MXC_F_SPIXFC_INTEN_RX_DONE ((uint32_t)(0x1UL << MXC_F_SPIXFC_INTEN_RX_DONE_POS)) /**< INTEN_RX_DONE Mask */ 352 353 #define MXC_F_SPIXFC_INTEN_TX_FIFO_AE_POS 4 /**< INTEN_TX_FIFO_AE Position */ 354 #define MXC_F_SPIXFC_INTEN_TX_FIFO_AE ((uint32_t)(0x1UL << MXC_F_SPIXFC_INTEN_TX_FIFO_AE_POS)) /**< INTEN_TX_FIFO_AE Mask */ 355 356 #define MXC_F_SPIXFC_INTEN_RX_FIFO_AF_POS 5 /**< INTEN_RX_FIFO_AF Position */ 357 #define MXC_F_SPIXFC_INTEN_RX_FIFO_AF ((uint32_t)(0x1UL << MXC_F_SPIXFC_INTEN_RX_FIFO_AF_POS)) /**< INTEN_RX_FIFO_AF Mask */ 358 359 /**@} end of group SPIXFC_INTEN_Register */ 360 361 /** 362 * @ingroup spixfc_registers 363 * @defgroup SPIXFC_SIMPLE_HEADER SPIXFC_SIMPLE_HEADER 364 * @brief Simple Header 365 * @{ 366 */ 367 #define MXC_F_SPIXFC_SIMPLE_HEADER_TX_BIDIR_POS 0 /**< SIMPLE_HEADER_TX_BIDIR Position */ 368 #define MXC_F_SPIXFC_SIMPLE_HEADER_TX_BIDIR ((uint32_t)(0x3FFFUL << MXC_F_SPIXFC_SIMPLE_HEADER_TX_BIDIR_POS)) /**< SIMPLE_HEADER_TX_BIDIR Mask */ 369 370 #define MXC_F_SPIXFC_SIMPLE_HEADER_RX_ONLY_POS 16 /**< SIMPLE_HEADER_RX_ONLY Position */ 371 #define MXC_F_SPIXFC_SIMPLE_HEADER_RX_ONLY ((uint32_t)(0x3FFFUL << MXC_F_SPIXFC_SIMPLE_HEADER_RX_ONLY_POS)) /**< SIMPLE_HEADER_RX_ONLY Mask */ 372 373 /**@} end of group SPIXFC_SIMPLE_HEADER_Register */ 374 375 #ifdef __cplusplus 376 } 377 #endif 378 379 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_SPIXFC_REGS_H_ 380
