1 /** 2 * @file sema_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SEMA Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup sema_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_SEMA_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_SEMA_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup sema 67 * @defgroup sema_registers SEMA_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the SEMA Peripheral Module. 69 * @details The Semaphore peripheral allows multiple cores in a system to cooperate when accessing shred resources. 70 The peripheral contains eight semaphores that can be atomically set and cleared. It is left to the discretion of the software 71 architect to decide how and when the semaphores are used and how they are allocated. Existing hardware does not have to be 72 73 modified for this type of cooperative sharing, and the use of semaphores is exclusively within the software domain. 74 */ 75 76 /** 77 * @ingroup sema_registers 78 * Structure type to access the SEMA Registers. 79 */ 80 typedef struct { 81 __IO uint32_t semaphores[8]; /**< <tt>\b 0x00:</tt> SEMA SEMAPHORES Register */ 82 __R uint32_t rsv_0x20_0x3f[8]; 83 __IO uint32_t irq0; /**< <tt>\b 0x40:</tt> SEMA IRQ0 Register */ 84 __IO uint32_t mail0; /**< <tt>\b 0x44:</tt> SEMA MAIL0 Register */ 85 __IO uint32_t irq1; /**< <tt>\b 0x48:</tt> SEMA IRQ1 Register */ 86 __IO uint32_t mail1; /**< <tt>\b 0x4C:</tt> SEMA MAIL1 Register */ 87 __R uint32_t rsv_0x50_0xff[44]; 88 __IO uint32_t status; /**< <tt>\b 0x100:</tt> SEMA STATUS Register */ 89 } mxc_sema_regs_t; 90 91 /* Register offsets for module SEMA */ 92 /** 93 * @ingroup sema_registers 94 * @defgroup SEMA_Register_Offsets Register Offsets 95 * @brief SEMA Peripheral Register Offsets from the SEMA Base Peripheral Address. 96 * @{ 97 */ 98 #define MXC_R_SEMA_SEMAPHORES ((uint32_t)0x00000000UL) /**< Offset from SEMA Base Address: <tt> 0x0000</tt> */ 99 #define MXC_R_SEMA_IRQ0 ((uint32_t)0x00000040UL) /**< Offset from SEMA Base Address: <tt> 0x0040</tt> */ 100 #define MXC_R_SEMA_MAIL0 ((uint32_t)0x00000044UL) /**< Offset from SEMA Base Address: <tt> 0x0044</tt> */ 101 #define MXC_R_SEMA_IRQ1 ((uint32_t)0x00000048UL) /**< Offset from SEMA Base Address: <tt> 0x0048</tt> */ 102 #define MXC_R_SEMA_MAIL1 ((uint32_t)0x0000004CUL) /**< Offset from SEMA Base Address: <tt> 0x004C</tt> */ 103 #define MXC_R_SEMA_STATUS ((uint32_t)0x00000100UL) /**< Offset from SEMA Base Address: <tt> 0x0100</tt> */ 104 /**@} end of group sema_registers */ 105 106 /** 107 * @ingroup sema_registers 108 * @defgroup SEMA_SEMAPHORES SEMA_SEMAPHORES 109 * @brief Read to test and set, returns prior value. Write 0 to clear semaphore. 110 * @{ 111 */ 112 #define MXC_F_SEMA_SEMAPHORES_SEMA_POS 0 /**< SEMAPHORES_SEMA Position */ 113 #define MXC_F_SEMA_SEMAPHORES_SEMA ((uint32_t)(0x1UL << MXC_F_SEMA_SEMAPHORES_SEMA_POS)) /**< SEMAPHORES_SEMA Mask */ 114 115 /**@} end of group SEMA_SEMAPHORES_Register */ 116 117 /** 118 * @ingroup sema_registers 119 * @defgroup SEMA_IRQ0 SEMA_IRQ0 120 * @brief Semaphore IRQ0 register. 121 * @{ 122 */ 123 #define MXC_F_SEMA_IRQ0_EN_POS 0 /**< IRQ0_EN Position */ 124 #define MXC_F_SEMA_IRQ0_EN ((uint32_t)(0x1UL << MXC_F_SEMA_IRQ0_EN_POS)) /**< IRQ0_EN Mask */ 125 126 #define MXC_F_SEMA_IRQ0_CM4_IRQ_POS 16 /**< IRQ0_CM4_IRQ Position */ 127 #define MXC_F_SEMA_IRQ0_CM4_IRQ ((uint32_t)(0x1UL << MXC_F_SEMA_IRQ0_CM4_IRQ_POS)) /**< IRQ0_CM4_IRQ Mask */ 128 129 /**@} end of group SEMA_IRQ0_Register */ 130 131 /** 132 * @ingroup sema_registers 133 * @defgroup SEMA_MAIL0 SEMA_MAIL0 134 * @brief Semaphore Mailbox 0 register. 135 * @{ 136 */ 137 #define MXC_F_SEMA_MAIL0_DATA_POS 0 /**< MAIL0_DATA Position */ 138 #define MXC_F_SEMA_MAIL0_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_SEMA_MAIL0_DATA_POS)) /**< MAIL0_DATA Mask */ 139 140 /**@} end of group SEMA_MAIL0_Register */ 141 142 /** 143 * @ingroup sema_registers 144 * @defgroup SEMA_IRQ1 SEMA_IRQ1 145 * @brief Semaphore IRQ1 register. 146 * @{ 147 */ 148 #define MXC_F_SEMA_IRQ1_EN_POS 0 /**< IRQ1_EN Position */ 149 #define MXC_F_SEMA_IRQ1_EN ((uint32_t)(0x1UL << MXC_F_SEMA_IRQ1_EN_POS)) /**< IRQ1_EN Mask */ 150 151 #define MXC_F_SEMA_IRQ1_RV32_IRQ_POS 16 /**< IRQ1_RV32_IRQ Position */ 152 #define MXC_F_SEMA_IRQ1_RV32_IRQ ((uint32_t)(0x1UL << MXC_F_SEMA_IRQ1_RV32_IRQ_POS)) /**< IRQ1_RV32_IRQ Mask */ 153 154 /**@} end of group SEMA_IRQ1_Register */ 155 156 /** 157 * @ingroup sema_registers 158 * @defgroup SEMA_MAIL1 SEMA_MAIL1 159 * @brief Semaphore Mailbox 1 register. 160 * @{ 161 */ 162 #define MXC_F_SEMA_MAIL1_DATA_POS 0 /**< MAIL1_DATA Position */ 163 #define MXC_F_SEMA_MAIL1_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_SEMA_MAIL1_DATA_POS)) /**< MAIL1_DATA Mask */ 164 165 /**@} end of group SEMA_MAIL1_Register */ 166 167 /** 168 * @ingroup sema_registers 169 * @defgroup SEMA_STATUS SEMA_STATUS 170 * @brief Semaphore status bits. 0 indicates the semaphore is free, 1 indicates taken. 171 * @{ 172 */ 173 #define MXC_F_SEMA_STATUS_STATUS0_POS 0 /**< STATUS_STATUS0 Position */ 174 #define MXC_F_SEMA_STATUS_STATUS0 ((uint32_t)(0x1UL << MXC_F_SEMA_STATUS_STATUS0_POS)) /**< STATUS_STATUS0 Mask */ 175 176 #define MXC_F_SEMA_STATUS_STATUS1_POS 1 /**< STATUS_STATUS1 Position */ 177 #define MXC_F_SEMA_STATUS_STATUS1 ((uint32_t)(0x1UL << MXC_F_SEMA_STATUS_STATUS1_POS)) /**< STATUS_STATUS1 Mask */ 178 179 #define MXC_F_SEMA_STATUS_STATUS2_POS 2 /**< STATUS_STATUS2 Position */ 180 #define MXC_F_SEMA_STATUS_STATUS2 ((uint32_t)(0x1UL << MXC_F_SEMA_STATUS_STATUS2_POS)) /**< STATUS_STATUS2 Mask */ 181 182 #define MXC_F_SEMA_STATUS_STATUS3_POS 3 /**< STATUS_STATUS3 Position */ 183 #define MXC_F_SEMA_STATUS_STATUS3 ((uint32_t)(0x1UL << MXC_F_SEMA_STATUS_STATUS3_POS)) /**< STATUS_STATUS3 Mask */ 184 185 #define MXC_F_SEMA_STATUS_STATUS4_POS 4 /**< STATUS_STATUS4 Position */ 186 #define MXC_F_SEMA_STATUS_STATUS4 ((uint32_t)(0x1UL << MXC_F_SEMA_STATUS_STATUS4_POS)) /**< STATUS_STATUS4 Mask */ 187 188 #define MXC_F_SEMA_STATUS_STATUS5_POS 5 /**< STATUS_STATUS5 Position */ 189 #define MXC_F_SEMA_STATUS_STATUS5 ((uint32_t)(0x1UL << MXC_F_SEMA_STATUS_STATUS5_POS)) /**< STATUS_STATUS5 Mask */ 190 191 #define MXC_F_SEMA_STATUS_STATUS6_POS 6 /**< STATUS_STATUS6 Position */ 192 #define MXC_F_SEMA_STATUS_STATUS6 ((uint32_t)(0x1UL << MXC_F_SEMA_STATUS_STATUS6_POS)) /**< STATUS_STATUS6 Mask */ 193 194 #define MXC_F_SEMA_STATUS_STATUS7_POS 7 /**< STATUS_STATUS7 Position */ 195 #define MXC_F_SEMA_STATUS_STATUS7 ((uint32_t)(0x1UL << MXC_F_SEMA_STATUS_STATUS7_POS)) /**< STATUS_STATUS7 Mask */ 196 197 /**@} end of group SEMA_STATUS_Register */ 198 199 #ifdef __cplusplus 200 } 201 #endif 202 203 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_SEMA_REGS_H_ 204
