1 /** 2 * @file ptg_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the PTG Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup ptg_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_PTG_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_PTG_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup ptg 67 * @defgroup ptg_registers PTG_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the PTG Peripheral Module. 69 * @details Pulse Train Generation 70 */ 71 72 /** 73 * @ingroup ptg_registers 74 * Structure type to access the PTG Registers. 75 */ 76 typedef struct { 77 __IO uint32_t enable; /**< <tt>\b 0x0000:</tt> PTG ENABLE Register */ 78 __IO uint32_t resync; /**< <tt>\b 0x0004:</tt> PTG RESYNC Register */ 79 __IO uint32_t stop_intfl; /**< <tt>\b 0x0008:</tt> PTG STOP_INTFL Register */ 80 __IO uint32_t stop_inten; /**< <tt>\b 0x000C:</tt> PTG STOP_INTEN Register */ 81 __O uint32_t safe_en; /**< <tt>\b 0x0010:</tt> PTG SAFE_EN Register */ 82 __O uint32_t safe_dis; /**< <tt>\b 0x0014:</tt> PTG SAFE_DIS Register */ 83 __IO uint32_t ready_intfl; /**< <tt>\b 0x0018:</tt> PTG READY_INTFL Register */ 84 __IO uint32_t ready_inten; /**< <tt>\b 0x001C:</tt> PTG READY_INTEN Register */ 85 } mxc_ptg_regs_t; 86 87 /* Register offsets for module PTG */ 88 /** 89 * @ingroup ptg_registers 90 * @defgroup PTG_Register_Offsets Register Offsets 91 * @brief PTG Peripheral Register Offsets from the PTG Base Peripheral Address. 92 * @{ 93 */ 94 #define MXC_R_PTG_ENABLE ((uint32_t)0x00000000UL) /**< Offset from PTG Base Address: <tt> 0x0000</tt> */ 95 #define MXC_R_PTG_RESYNC ((uint32_t)0x00000004UL) /**< Offset from PTG Base Address: <tt> 0x0004</tt> */ 96 #define MXC_R_PTG_STOP_INTFL ((uint32_t)0x00000008UL) /**< Offset from PTG Base Address: <tt> 0x0008</tt> */ 97 #define MXC_R_PTG_STOP_INTEN ((uint32_t)0x0000000CUL) /**< Offset from PTG Base Address: <tt> 0x000C</tt> */ 98 #define MXC_R_PTG_SAFE_EN ((uint32_t)0x00000010UL) /**< Offset from PTG Base Address: <tt> 0x0010</tt> */ 99 #define MXC_R_PTG_SAFE_DIS ((uint32_t)0x00000014UL) /**< Offset from PTG Base Address: <tt> 0x0014</tt> */ 100 #define MXC_R_PTG_READY_INTFL ((uint32_t)0x00000018UL) /**< Offset from PTG Base Address: <tt> 0x0018</tt> */ 101 #define MXC_R_PTG_READY_INTEN ((uint32_t)0x0000001CUL) /**< Offset from PTG Base Address: <tt> 0x001C</tt> */ 102 /**@} end of group ptg_registers */ 103 104 /** 105 * @ingroup ptg_registers 106 * @defgroup PTG_ENABLE PTG_ENABLE 107 * @brief Global Enable/Disable Controls for All Pulse Trains 108 * @{ 109 */ 110 #define MXC_F_PTG_ENABLE_PT0_POS 0 /**< ENABLE_PT0 Position */ 111 #define MXC_F_PTG_ENABLE_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT0_POS)) /**< ENABLE_PT0 Mask */ 112 113 #define MXC_F_PTG_ENABLE_PT1_POS 1 /**< ENABLE_PT1 Position */ 114 #define MXC_F_PTG_ENABLE_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT1_POS)) /**< ENABLE_PT1 Mask */ 115 116 #define MXC_F_PTG_ENABLE_PT2_POS 2 /**< ENABLE_PT2 Position */ 117 #define MXC_F_PTG_ENABLE_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT2_POS)) /**< ENABLE_PT2 Mask */ 118 119 #define MXC_F_PTG_ENABLE_PT3_POS 3 /**< ENABLE_PT3 Position */ 120 #define MXC_F_PTG_ENABLE_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT3_POS)) /**< ENABLE_PT3 Mask */ 121 122 #define MXC_F_PTG_ENABLE_PT4_POS 4 /**< ENABLE_PT4 Position */ 123 #define MXC_F_PTG_ENABLE_PT4 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT4_POS)) /**< ENABLE_PT4 Mask */ 124 125 #define MXC_F_PTG_ENABLE_PT5_POS 5 /**< ENABLE_PT5 Position */ 126 #define MXC_F_PTG_ENABLE_PT5 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT5_POS)) /**< ENABLE_PT5 Mask */ 127 128 #define MXC_F_PTG_ENABLE_PT6_POS 6 /**< ENABLE_PT6 Position */ 129 #define MXC_F_PTG_ENABLE_PT6 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT6_POS)) /**< ENABLE_PT6 Mask */ 130 131 #define MXC_F_PTG_ENABLE_PT7_POS 7 /**< ENABLE_PT7 Position */ 132 #define MXC_F_PTG_ENABLE_PT7 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT7_POS)) /**< ENABLE_PT7 Mask */ 133 134 #define MXC_F_PTG_ENABLE_PT8_POS 8 /**< ENABLE_PT8 Position */ 135 #define MXC_F_PTG_ENABLE_PT8 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT8_POS)) /**< ENABLE_PT8 Mask */ 136 137 #define MXC_F_PTG_ENABLE_PT9_POS 9 /**< ENABLE_PT9 Position */ 138 #define MXC_F_PTG_ENABLE_PT9 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT9_POS)) /**< ENABLE_PT9 Mask */ 139 140 #define MXC_F_PTG_ENABLE_PT10_POS 10 /**< ENABLE_PT10 Position */ 141 #define MXC_F_PTG_ENABLE_PT10 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT10_POS)) /**< ENABLE_PT10 Mask */ 142 143 #define MXC_F_PTG_ENABLE_PT11_POS 11 /**< ENABLE_PT11 Position */ 144 #define MXC_F_PTG_ENABLE_PT11 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT11_POS)) /**< ENABLE_PT11 Mask */ 145 146 #define MXC_F_PTG_ENABLE_PT12_POS 12 /**< ENABLE_PT12 Position */ 147 #define MXC_F_PTG_ENABLE_PT12 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT12_POS)) /**< ENABLE_PT12 Mask */ 148 149 #define MXC_F_PTG_ENABLE_PT13_POS 13 /**< ENABLE_PT13 Position */ 150 #define MXC_F_PTG_ENABLE_PT13 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT13_POS)) /**< ENABLE_PT13 Mask */ 151 152 #define MXC_F_PTG_ENABLE_PT14_POS 14 /**< ENABLE_PT14 Position */ 153 #define MXC_F_PTG_ENABLE_PT14 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT14_POS)) /**< ENABLE_PT14 Mask */ 154 155 #define MXC_F_PTG_ENABLE_PT15_POS 15 /**< ENABLE_PT15 Position */ 156 #define MXC_F_PTG_ENABLE_PT15 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT15_POS)) /**< ENABLE_PT15 Mask */ 157 158 /**@} end of group PTG_ENABLE_Register */ 159 160 /** 161 * @ingroup ptg_registers 162 * @defgroup PTG_RESYNC PTG_RESYNC 163 * @brief Global Resync (All Pulse Trains) Control 164 * @{ 165 */ 166 #define MXC_F_PTG_RESYNC_PT0_POS 0 /**< RESYNC_PT0 Position */ 167 #define MXC_F_PTG_RESYNC_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT0_POS)) /**< RESYNC_PT0 Mask */ 168 169 #define MXC_F_PTG_RESYNC_PT1_POS 1 /**< RESYNC_PT1 Position */ 170 #define MXC_F_PTG_RESYNC_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT1_POS)) /**< RESYNC_PT1 Mask */ 171 172 #define MXC_F_PTG_RESYNC_PT2_POS 2 /**< RESYNC_PT2 Position */ 173 #define MXC_F_PTG_RESYNC_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT2_POS)) /**< RESYNC_PT2 Mask */ 174 175 #define MXC_F_PTG_RESYNC_PT3_POS 3 /**< RESYNC_PT3 Position */ 176 #define MXC_F_PTG_RESYNC_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT3_POS)) /**< RESYNC_PT3 Mask */ 177 178 #define MXC_F_PTG_RESYNC_PT4_POS 4 /**< RESYNC_PT4 Position */ 179 #define MXC_F_PTG_RESYNC_PT4 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT4_POS)) /**< RESYNC_PT4 Mask */ 180 181 #define MXC_F_PTG_RESYNC_PT5_POS 5 /**< RESYNC_PT5 Position */ 182 #define MXC_F_PTG_RESYNC_PT5 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT5_POS)) /**< RESYNC_PT5 Mask */ 183 184 #define MXC_F_PTG_RESYNC_PT6_POS 6 /**< RESYNC_PT6 Position */ 185 #define MXC_F_PTG_RESYNC_PT6 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT6_POS)) /**< RESYNC_PT6 Mask */ 186 187 #define MXC_F_PTG_RESYNC_PT7_POS 7 /**< RESYNC_PT7 Position */ 188 #define MXC_F_PTG_RESYNC_PT7 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT7_POS)) /**< RESYNC_PT7 Mask */ 189 190 #define MXC_F_PTG_RESYNC_PT8_POS 8 /**< RESYNC_PT8 Position */ 191 #define MXC_F_PTG_RESYNC_PT8 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT8_POS)) /**< RESYNC_PT8 Mask */ 192 193 #define MXC_F_PTG_RESYNC_PT9_POS 9 /**< RESYNC_PT9 Position */ 194 #define MXC_F_PTG_RESYNC_PT9 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT9_POS)) /**< RESYNC_PT9 Mask */ 195 196 #define MXC_F_PTG_RESYNC_PT10_POS 10 /**< RESYNC_PT10 Position */ 197 #define MXC_F_PTG_RESYNC_PT10 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT10_POS)) /**< RESYNC_PT10 Mask */ 198 199 #define MXC_F_PTG_RESYNC_PT11_POS 11 /**< RESYNC_PT11 Position */ 200 #define MXC_F_PTG_RESYNC_PT11 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT11_POS)) /**< RESYNC_PT11 Mask */ 201 202 #define MXC_F_PTG_RESYNC_PT12_POS 12 /**< RESYNC_PT12 Position */ 203 #define MXC_F_PTG_RESYNC_PT12 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT12_POS)) /**< RESYNC_PT12 Mask */ 204 205 #define MXC_F_PTG_RESYNC_PT13_POS 13 /**< RESYNC_PT13 Position */ 206 #define MXC_F_PTG_RESYNC_PT13 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT13_POS)) /**< RESYNC_PT13 Mask */ 207 208 #define MXC_F_PTG_RESYNC_PT14_POS 14 /**< RESYNC_PT14 Position */ 209 #define MXC_F_PTG_RESYNC_PT14 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT14_POS)) /**< RESYNC_PT14 Mask */ 210 211 #define MXC_F_PTG_RESYNC_PT15_POS 15 /**< RESYNC_PT15 Position */ 212 #define MXC_F_PTG_RESYNC_PT15 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT15_POS)) /**< RESYNC_PT15 Mask */ 213 214 /**@} end of group PTG_RESYNC_Register */ 215 216 /** 217 * @ingroup ptg_registers 218 * @defgroup PTG_STOP_INTFL PTG_STOP_INTFL 219 * @brief Pulse Train Interrupt Flags 220 * @{ 221 */ 222 #define MXC_F_PTG_STOP_INTFL_PT0_POS 0 /**< STOP_INTFL_PT0 Position */ 223 #define MXC_F_PTG_STOP_INTFL_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTFL_PT0_POS)) /**< STOP_INTFL_PT0 Mask */ 224 225 #define MXC_F_PTG_STOP_INTFL_PT1_POS 1 /**< STOP_INTFL_PT1 Position */ 226 #define MXC_F_PTG_STOP_INTFL_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTFL_PT1_POS)) /**< STOP_INTFL_PT1 Mask */ 227 228 #define MXC_F_PTG_STOP_INTFL_PT2_POS 2 /**< STOP_INTFL_PT2 Position */ 229 #define MXC_F_PTG_STOP_INTFL_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTFL_PT2_POS)) /**< STOP_INTFL_PT2 Mask */ 230 231 #define MXC_F_PTG_STOP_INTFL_PT3_POS 3 /**< STOP_INTFL_PT3 Position */ 232 #define MXC_F_PTG_STOP_INTFL_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTFL_PT3_POS)) /**< STOP_INTFL_PT3 Mask */ 233 234 #define MXC_F_PTG_STOP_INTFL_PT4_POS 4 /**< STOP_INTFL_PT4 Position */ 235 #define MXC_F_PTG_STOP_INTFL_PT4 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTFL_PT4_POS)) /**< STOP_INTFL_PT4 Mask */ 236 237 #define MXC_F_PTG_STOP_INTFL_PT5_POS 5 /**< STOP_INTFL_PT5 Position */ 238 #define MXC_F_PTG_STOP_INTFL_PT5 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTFL_PT5_POS)) /**< STOP_INTFL_PT5 Mask */ 239 240 #define MXC_F_PTG_STOP_INTFL_PT6_POS 6 /**< STOP_INTFL_PT6 Position */ 241 #define MXC_F_PTG_STOP_INTFL_PT6 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTFL_PT6_POS)) /**< STOP_INTFL_PT6 Mask */ 242 243 #define MXC_F_PTG_STOP_INTFL_PT7_POS 7 /**< STOP_INTFL_PT7 Position */ 244 #define MXC_F_PTG_STOP_INTFL_PT7 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTFL_PT7_POS)) /**< STOP_INTFL_PT7 Mask */ 245 246 #define MXC_F_PTG_STOP_INTFL_PT8_POS 8 /**< STOP_INTFL_PT8 Position */ 247 #define MXC_F_PTG_STOP_INTFL_PT8 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTFL_PT8_POS)) /**< STOP_INTFL_PT8 Mask */ 248 249 #define MXC_F_PTG_STOP_INTFL_PT9_POS 9 /**< STOP_INTFL_PT9 Position */ 250 #define MXC_F_PTG_STOP_INTFL_PT9 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTFL_PT9_POS)) /**< STOP_INTFL_PT9 Mask */ 251 252 #define MXC_F_PTG_STOP_INTFL_PT10_POS 10 /**< STOP_INTFL_PT10 Position */ 253 #define MXC_F_PTG_STOP_INTFL_PT10 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTFL_PT10_POS)) /**< STOP_INTFL_PT10 Mask */ 254 255 #define MXC_F_PTG_STOP_INTFL_PT11_POS 11 /**< STOP_INTFL_PT11 Position */ 256 #define MXC_F_PTG_STOP_INTFL_PT11 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTFL_PT11_POS)) /**< STOP_INTFL_PT11 Mask */ 257 258 #define MXC_F_PTG_STOP_INTFL_PT12_POS 12 /**< STOP_INTFL_PT12 Position */ 259 #define MXC_F_PTG_STOP_INTFL_PT12 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTFL_PT12_POS)) /**< STOP_INTFL_PT12 Mask */ 260 261 #define MXC_F_PTG_STOP_INTFL_PT13_POS 13 /**< STOP_INTFL_PT13 Position */ 262 #define MXC_F_PTG_STOP_INTFL_PT13 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTFL_PT13_POS)) /**< STOP_INTFL_PT13 Mask */ 263 264 #define MXC_F_PTG_STOP_INTFL_PT14_POS 14 /**< STOP_INTFL_PT14 Position */ 265 #define MXC_F_PTG_STOP_INTFL_PT14 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTFL_PT14_POS)) /**< STOP_INTFL_PT14 Mask */ 266 267 #define MXC_F_PTG_STOP_INTFL_PT15_POS 15 /**< STOP_INTFL_PT15 Position */ 268 #define MXC_F_PTG_STOP_INTFL_PT15 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTFL_PT15_POS)) /**< STOP_INTFL_PT15 Mask */ 269 270 /**@} end of group PTG_STOP_INTFL_Register */ 271 272 /** 273 * @ingroup ptg_registers 274 * @defgroup PTG_STOP_INTEN PTG_STOP_INTEN 275 * @brief Pulse Train Interrupt Enable/Disable 276 * @{ 277 */ 278 #define MXC_F_PTG_STOP_INTEN_PT0_POS 0 /**< STOP_INTEN_PT0 Position */ 279 #define MXC_F_PTG_STOP_INTEN_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTEN_PT0_POS)) /**< STOP_INTEN_PT0 Mask */ 280 281 #define MXC_F_PTG_STOP_INTEN_PT1_POS 1 /**< STOP_INTEN_PT1 Position */ 282 #define MXC_F_PTG_STOP_INTEN_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTEN_PT1_POS)) /**< STOP_INTEN_PT1 Mask */ 283 284 #define MXC_F_PTG_STOP_INTEN_PT2_POS 2 /**< STOP_INTEN_PT2 Position */ 285 #define MXC_F_PTG_STOP_INTEN_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTEN_PT2_POS)) /**< STOP_INTEN_PT2 Mask */ 286 287 #define MXC_F_PTG_STOP_INTEN_PT3_POS 3 /**< STOP_INTEN_PT3 Position */ 288 #define MXC_F_PTG_STOP_INTEN_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTEN_PT3_POS)) /**< STOP_INTEN_PT3 Mask */ 289 290 #define MXC_F_PTG_STOP_INTEN_PT4_POS 4 /**< STOP_INTEN_PT4 Position */ 291 #define MXC_F_PTG_STOP_INTEN_PT4 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTEN_PT4_POS)) /**< STOP_INTEN_PT4 Mask */ 292 293 #define MXC_F_PTG_STOP_INTEN_PT5_POS 5 /**< STOP_INTEN_PT5 Position */ 294 #define MXC_F_PTG_STOP_INTEN_PT5 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTEN_PT5_POS)) /**< STOP_INTEN_PT5 Mask */ 295 296 #define MXC_F_PTG_STOP_INTEN_PT6_POS 6 /**< STOP_INTEN_PT6 Position */ 297 #define MXC_F_PTG_STOP_INTEN_PT6 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTEN_PT6_POS)) /**< STOP_INTEN_PT6 Mask */ 298 299 #define MXC_F_PTG_STOP_INTEN_PT7_POS 7 /**< STOP_INTEN_PT7 Position */ 300 #define MXC_F_PTG_STOP_INTEN_PT7 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTEN_PT7_POS)) /**< STOP_INTEN_PT7 Mask */ 301 302 #define MXC_F_PTG_STOP_INTEN_PT8_POS 8 /**< STOP_INTEN_PT8 Position */ 303 #define MXC_F_PTG_STOP_INTEN_PT8 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTEN_PT8_POS)) /**< STOP_INTEN_PT8 Mask */ 304 305 #define MXC_F_PTG_STOP_INTEN_PT9_POS 9 /**< STOP_INTEN_PT9 Position */ 306 #define MXC_F_PTG_STOP_INTEN_PT9 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTEN_PT9_POS)) /**< STOP_INTEN_PT9 Mask */ 307 308 #define MXC_F_PTG_STOP_INTEN_PT10_POS 10 /**< STOP_INTEN_PT10 Position */ 309 #define MXC_F_PTG_STOP_INTEN_PT10 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTEN_PT10_POS)) /**< STOP_INTEN_PT10 Mask */ 310 311 #define MXC_F_PTG_STOP_INTEN_PT11_POS 11 /**< STOP_INTEN_PT11 Position */ 312 #define MXC_F_PTG_STOP_INTEN_PT11 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTEN_PT11_POS)) /**< STOP_INTEN_PT11 Mask */ 313 314 #define MXC_F_PTG_STOP_INTEN_PT12_POS 12 /**< STOP_INTEN_PT12 Position */ 315 #define MXC_F_PTG_STOP_INTEN_PT12 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTEN_PT12_POS)) /**< STOP_INTEN_PT12 Mask */ 316 317 #define MXC_F_PTG_STOP_INTEN_PT13_POS 13 /**< STOP_INTEN_PT13 Position */ 318 #define MXC_F_PTG_STOP_INTEN_PT13 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTEN_PT13_POS)) /**< STOP_INTEN_PT13 Mask */ 319 320 #define MXC_F_PTG_STOP_INTEN_PT14_POS 14 /**< STOP_INTEN_PT14 Position */ 321 #define MXC_F_PTG_STOP_INTEN_PT14 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTEN_PT14_POS)) /**< STOP_INTEN_PT14 Mask */ 322 323 #define MXC_F_PTG_STOP_INTEN_PT15_POS 15 /**< STOP_INTEN_PT15 Position */ 324 #define MXC_F_PTG_STOP_INTEN_PT15 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTEN_PT15_POS)) /**< STOP_INTEN_PT15 Mask */ 325 326 /**@} end of group PTG_STOP_INTEN_Register */ 327 328 /** 329 * @ingroup ptg_registers 330 * @defgroup PTG_SAFE_EN PTG_SAFE_EN 331 * @brief Pulse Train Global Safe Enable. 332 * @{ 333 */ 334 #define MXC_F_PTG_SAFE_EN_PT0_POS 0 /**< SAFE_EN_PT0 Position */ 335 #define MXC_F_PTG_SAFE_EN_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT0_POS)) /**< SAFE_EN_PT0 Mask */ 336 337 #define MXC_F_PTG_SAFE_EN_PT1_POS 1 /**< SAFE_EN_PT1 Position */ 338 #define MXC_F_PTG_SAFE_EN_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT1_POS)) /**< SAFE_EN_PT1 Mask */ 339 340 #define MXC_F_PTG_SAFE_EN_PT2_POS 2 /**< SAFE_EN_PT2 Position */ 341 #define MXC_F_PTG_SAFE_EN_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT2_POS)) /**< SAFE_EN_PT2 Mask */ 342 343 #define MXC_F_PTG_SAFE_EN_PT3_POS 3 /**< SAFE_EN_PT3 Position */ 344 #define MXC_F_PTG_SAFE_EN_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT3_POS)) /**< SAFE_EN_PT3 Mask */ 345 346 #define MXC_F_PTG_SAFE_EN_PT4_POS 4 /**< SAFE_EN_PT4 Position */ 347 #define MXC_F_PTG_SAFE_EN_PT4 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT4_POS)) /**< SAFE_EN_PT4 Mask */ 348 349 #define MXC_F_PTG_SAFE_EN_PT5_POS 5 /**< SAFE_EN_PT5 Position */ 350 #define MXC_F_PTG_SAFE_EN_PT5 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT5_POS)) /**< SAFE_EN_PT5 Mask */ 351 352 #define MXC_F_PTG_SAFE_EN_PT6_POS 6 /**< SAFE_EN_PT6 Position */ 353 #define MXC_F_PTG_SAFE_EN_PT6 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT6_POS)) /**< SAFE_EN_PT6 Mask */ 354 355 #define MXC_F_PTG_SAFE_EN_PT7_POS 7 /**< SAFE_EN_PT7 Position */ 356 #define MXC_F_PTG_SAFE_EN_PT7 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT7_POS)) /**< SAFE_EN_PT7 Mask */ 357 358 #define MXC_F_PTG_SAFE_EN_PT8_POS 8 /**< SAFE_EN_PT8 Position */ 359 #define MXC_F_PTG_SAFE_EN_PT8 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT8_POS)) /**< SAFE_EN_PT8 Mask */ 360 361 #define MXC_F_PTG_SAFE_EN_PT9_POS 9 /**< SAFE_EN_PT9 Position */ 362 #define MXC_F_PTG_SAFE_EN_PT9 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT9_POS)) /**< SAFE_EN_PT9 Mask */ 363 364 #define MXC_F_PTG_SAFE_EN_PT10_POS 10 /**< SAFE_EN_PT10 Position */ 365 #define MXC_F_PTG_SAFE_EN_PT10 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT10_POS)) /**< SAFE_EN_PT10 Mask */ 366 367 #define MXC_F_PTG_SAFE_EN_PT11_POS 11 /**< SAFE_EN_PT11 Position */ 368 #define MXC_F_PTG_SAFE_EN_PT11 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT11_POS)) /**< SAFE_EN_PT11 Mask */ 369 370 #define MXC_F_PTG_SAFE_EN_PT12_POS 12 /**< SAFE_EN_PT12 Position */ 371 #define MXC_F_PTG_SAFE_EN_PT12 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT12_POS)) /**< SAFE_EN_PT12 Mask */ 372 373 #define MXC_F_PTG_SAFE_EN_PT13_POS 13 /**< SAFE_EN_PT13 Position */ 374 #define MXC_F_PTG_SAFE_EN_PT13 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT13_POS)) /**< SAFE_EN_PT13 Mask */ 375 376 #define MXC_F_PTG_SAFE_EN_PT14_POS 14 /**< SAFE_EN_PT14 Position */ 377 #define MXC_F_PTG_SAFE_EN_PT14 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT14_POS)) /**< SAFE_EN_PT14 Mask */ 378 379 #define MXC_F_PTG_SAFE_EN_PT15_POS 15 /**< SAFE_EN_PT15 Position */ 380 #define MXC_F_PTG_SAFE_EN_PT15 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT15_POS)) /**< SAFE_EN_PT15 Mask */ 381 382 /**@} end of group PTG_SAFE_EN_Register */ 383 384 /** 385 * @ingroup ptg_registers 386 * @defgroup PTG_SAFE_DIS PTG_SAFE_DIS 387 * @brief Pulse Train Global Safe Disable. 388 * @{ 389 */ 390 #define MXC_F_PTG_SAFE_DIS_PT0_POS 0 /**< SAFE_DIS_PT0 Position */ 391 #define MXC_F_PTG_SAFE_DIS_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT0_POS)) /**< SAFE_DIS_PT0 Mask */ 392 393 #define MXC_F_PTG_SAFE_DIS_PT1_POS 1 /**< SAFE_DIS_PT1 Position */ 394 #define MXC_F_PTG_SAFE_DIS_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT1_POS)) /**< SAFE_DIS_PT1 Mask */ 395 396 #define MXC_F_PTG_SAFE_DIS_PT2_POS 2 /**< SAFE_DIS_PT2 Position */ 397 #define MXC_F_PTG_SAFE_DIS_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT2_POS)) /**< SAFE_DIS_PT2 Mask */ 398 399 #define MXC_F_PTG_SAFE_DIS_PT3_POS 3 /**< SAFE_DIS_PT3 Position */ 400 #define MXC_F_PTG_SAFE_DIS_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT3_POS)) /**< SAFE_DIS_PT3 Mask */ 401 402 #define MXC_F_PTG_SAFE_DIS_PT4_POS 4 /**< SAFE_DIS_PT4 Position */ 403 #define MXC_F_PTG_SAFE_DIS_PT4 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT4_POS)) /**< SAFE_DIS_PT4 Mask */ 404 405 #define MXC_F_PTG_SAFE_DIS_PT5_POS 5 /**< SAFE_DIS_PT5 Position */ 406 #define MXC_F_PTG_SAFE_DIS_PT5 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT5_POS)) /**< SAFE_DIS_PT5 Mask */ 407 408 #define MXC_F_PTG_SAFE_DIS_PT6_POS 6 /**< SAFE_DIS_PT6 Position */ 409 #define MXC_F_PTG_SAFE_DIS_PT6 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT6_POS)) /**< SAFE_DIS_PT6 Mask */ 410 411 #define MXC_F_PTG_SAFE_DIS_PT7_POS 7 /**< SAFE_DIS_PT7 Position */ 412 #define MXC_F_PTG_SAFE_DIS_PT7 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT7_POS)) /**< SAFE_DIS_PT7 Mask */ 413 414 #define MXC_F_PTG_SAFE_DIS_PT8_POS 8 /**< SAFE_DIS_PT8 Position */ 415 #define MXC_F_PTG_SAFE_DIS_PT8 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT8_POS)) /**< SAFE_DIS_PT8 Mask */ 416 417 #define MXC_F_PTG_SAFE_DIS_PT9_POS 9 /**< SAFE_DIS_PT9 Position */ 418 #define MXC_F_PTG_SAFE_DIS_PT9 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT9_POS)) /**< SAFE_DIS_PT9 Mask */ 419 420 #define MXC_F_PTG_SAFE_DIS_PT10_POS 10 /**< SAFE_DIS_PT10 Position */ 421 #define MXC_F_PTG_SAFE_DIS_PT10 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT10_POS)) /**< SAFE_DIS_PT10 Mask */ 422 423 #define MXC_F_PTG_SAFE_DIS_PT11_POS 11 /**< SAFE_DIS_PT11 Position */ 424 #define MXC_F_PTG_SAFE_DIS_PT11 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT11_POS)) /**< SAFE_DIS_PT11 Mask */ 425 426 #define MXC_F_PTG_SAFE_DIS_PT12_POS 12 /**< SAFE_DIS_PT12 Position */ 427 #define MXC_F_PTG_SAFE_DIS_PT12 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT12_POS)) /**< SAFE_DIS_PT12 Mask */ 428 429 #define MXC_F_PTG_SAFE_DIS_PT13_POS 13 /**< SAFE_DIS_PT13 Position */ 430 #define MXC_F_PTG_SAFE_DIS_PT13 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT13_POS)) /**< SAFE_DIS_PT13 Mask */ 431 432 #define MXC_F_PTG_SAFE_DIS_PT14_POS 14 /**< SAFE_DIS_PT14 Position */ 433 #define MXC_F_PTG_SAFE_DIS_PT14 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT14_POS)) /**< SAFE_DIS_PT14 Mask */ 434 435 #define MXC_F_PTG_SAFE_DIS_PT15_POS 15 /**< SAFE_DIS_PT15 Position */ 436 #define MXC_F_PTG_SAFE_DIS_PT15 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT15_POS)) /**< SAFE_DIS_PT15 Mask */ 437 438 /**@} end of group PTG_SAFE_DIS_Register */ 439 440 /** 441 * @ingroup ptg_registers 442 * @defgroup PTG_READY_INTFL PTG_READY_INTFL 443 * @brief Pulse Train Ready Interrupt Flags 444 * @{ 445 */ 446 #define MXC_F_PTG_READY_INTFL_PT0_POS 0 /**< READY_INTFL_PT0 Position */ 447 #define MXC_F_PTG_READY_INTFL_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT0_POS)) /**< READY_INTFL_PT0 Mask */ 448 449 #define MXC_F_PTG_READY_INTFL_PT1_POS 1 /**< READY_INTFL_PT1 Position */ 450 #define MXC_F_PTG_READY_INTFL_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT1_POS)) /**< READY_INTFL_PT1 Mask */ 451 452 #define MXC_F_PTG_READY_INTFL_PT2_POS 2 /**< READY_INTFL_PT2 Position */ 453 #define MXC_F_PTG_READY_INTFL_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT2_POS)) /**< READY_INTFL_PT2 Mask */ 454 455 #define MXC_F_PTG_READY_INTFL_PT3_POS 3 /**< READY_INTFL_PT3 Position */ 456 #define MXC_F_PTG_READY_INTFL_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT3_POS)) /**< READY_INTFL_PT3 Mask */ 457 458 #define MXC_F_PTG_READY_INTFL_PT4_POS 4 /**< READY_INTFL_PT4 Position */ 459 #define MXC_F_PTG_READY_INTFL_PT4 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT4_POS)) /**< READY_INTFL_PT4 Mask */ 460 461 #define MXC_F_PTG_READY_INTFL_PT5_POS 5 /**< READY_INTFL_PT5 Position */ 462 #define MXC_F_PTG_READY_INTFL_PT5 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT5_POS)) /**< READY_INTFL_PT5 Mask */ 463 464 #define MXC_F_PTG_READY_INTFL_PT6_POS 6 /**< READY_INTFL_PT6 Position */ 465 #define MXC_F_PTG_READY_INTFL_PT6 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT6_POS)) /**< READY_INTFL_PT6 Mask */ 466 467 #define MXC_F_PTG_READY_INTFL_PT7_POS 7 /**< READY_INTFL_PT7 Position */ 468 #define MXC_F_PTG_READY_INTFL_PT7 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT7_POS)) /**< READY_INTFL_PT7 Mask */ 469 470 #define MXC_F_PTG_READY_INTFL_PT8_POS 8 /**< READY_INTFL_PT8 Position */ 471 #define MXC_F_PTG_READY_INTFL_PT8 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT8_POS)) /**< READY_INTFL_PT8 Mask */ 472 473 #define MXC_F_PTG_READY_INTFL_PT9_POS 9 /**< READY_INTFL_PT9 Position */ 474 #define MXC_F_PTG_READY_INTFL_PT9 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT9_POS)) /**< READY_INTFL_PT9 Mask */ 475 476 #define MXC_F_PTG_READY_INTFL_PT10_POS 10 /**< READY_INTFL_PT10 Position */ 477 #define MXC_F_PTG_READY_INTFL_PT10 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT10_POS)) /**< READY_INTFL_PT10 Mask */ 478 479 #define MXC_F_PTG_READY_INTFL_PT11_POS 11 /**< READY_INTFL_PT11 Position */ 480 #define MXC_F_PTG_READY_INTFL_PT11 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT11_POS)) /**< READY_INTFL_PT11 Mask */ 481 482 #define MXC_F_PTG_READY_INTFL_PT12_POS 12 /**< READY_INTFL_PT12 Position */ 483 #define MXC_F_PTG_READY_INTFL_PT12 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT12_POS)) /**< READY_INTFL_PT12 Mask */ 484 485 #define MXC_F_PTG_READY_INTFL_PT13_POS 13 /**< READY_INTFL_PT13 Position */ 486 #define MXC_F_PTG_READY_INTFL_PT13 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT13_POS)) /**< READY_INTFL_PT13 Mask */ 487 488 #define MXC_F_PTG_READY_INTFL_PT14_POS 14 /**< READY_INTFL_PT14 Position */ 489 #define MXC_F_PTG_READY_INTFL_PT14 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT14_POS)) /**< READY_INTFL_PT14 Mask */ 490 491 #define MXC_F_PTG_READY_INTFL_PT15_POS 15 /**< READY_INTFL_PT15 Position */ 492 #define MXC_F_PTG_READY_INTFL_PT15 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT15_POS)) /**< READY_INTFL_PT15 Mask */ 493 494 /**@} end of group PTG_READY_INTFL_Register */ 495 496 /** 497 * @ingroup ptg_registers 498 * @defgroup PTG_READY_INTEN PTG_READY_INTEN 499 * @brief Pulse Train Ready Interrupt Enable/Disable 500 * @{ 501 */ 502 #define MXC_F_PTG_READY_INTEN_PT0_POS 0 /**< READY_INTEN_PT0 Position */ 503 #define MXC_F_PTG_READY_INTEN_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT0_POS)) /**< READY_INTEN_PT0 Mask */ 504 505 #define MXC_F_PTG_READY_INTEN_PT1_POS 1 /**< READY_INTEN_PT1 Position */ 506 #define MXC_F_PTG_READY_INTEN_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT1_POS)) /**< READY_INTEN_PT1 Mask */ 507 508 #define MXC_F_PTG_READY_INTEN_PT2_POS 2 /**< READY_INTEN_PT2 Position */ 509 #define MXC_F_PTG_READY_INTEN_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT2_POS)) /**< READY_INTEN_PT2 Mask */ 510 511 #define MXC_F_PTG_READY_INTEN_PT3_POS 3 /**< READY_INTEN_PT3 Position */ 512 #define MXC_F_PTG_READY_INTEN_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT3_POS)) /**< READY_INTEN_PT3 Mask */ 513 514 #define MXC_F_PTG_READY_INTEN_PT4_POS 4 /**< READY_INTEN_PT4 Position */ 515 #define MXC_F_PTG_READY_INTEN_PT4 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT4_POS)) /**< READY_INTEN_PT4 Mask */ 516 517 #define MXC_F_PTG_READY_INTEN_PT5_POS 5 /**< READY_INTEN_PT5 Position */ 518 #define MXC_F_PTG_READY_INTEN_PT5 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT5_POS)) /**< READY_INTEN_PT5 Mask */ 519 520 #define MXC_F_PTG_READY_INTEN_PT6_POS 6 /**< READY_INTEN_PT6 Position */ 521 #define MXC_F_PTG_READY_INTEN_PT6 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT6_POS)) /**< READY_INTEN_PT6 Mask */ 522 523 #define MXC_F_PTG_READY_INTEN_PT7_POS 7 /**< READY_INTEN_PT7 Position */ 524 #define MXC_F_PTG_READY_INTEN_PT7 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT7_POS)) /**< READY_INTEN_PT7 Mask */ 525 526 #define MXC_F_PTG_READY_INTEN_PT8_POS 8 /**< READY_INTEN_PT8 Position */ 527 #define MXC_F_PTG_READY_INTEN_PT8 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT8_POS)) /**< READY_INTEN_PT8 Mask */ 528 529 #define MXC_F_PTG_READY_INTEN_PT9_POS 9 /**< READY_INTEN_PT9 Position */ 530 #define MXC_F_PTG_READY_INTEN_PT9 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT9_POS)) /**< READY_INTEN_PT9 Mask */ 531 532 #define MXC_F_PTG_READY_INTEN_PT10_POS 10 /**< READY_INTEN_PT10 Position */ 533 #define MXC_F_PTG_READY_INTEN_PT10 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT10_POS)) /**< READY_INTEN_PT10 Mask */ 534 535 #define MXC_F_PTG_READY_INTEN_PT11_POS 11 /**< READY_INTEN_PT11 Position */ 536 #define MXC_F_PTG_READY_INTEN_PT11 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT11_POS)) /**< READY_INTEN_PT11 Mask */ 537 538 #define MXC_F_PTG_READY_INTEN_PT12_POS 12 /**< READY_INTEN_PT12 Position */ 539 #define MXC_F_PTG_READY_INTEN_PT12 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT12_POS)) /**< READY_INTEN_PT12 Mask */ 540 541 #define MXC_F_PTG_READY_INTEN_PT13_POS 13 /**< READY_INTEN_PT13 Position */ 542 #define MXC_F_PTG_READY_INTEN_PT13 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT13_POS)) /**< READY_INTEN_PT13 Mask */ 543 544 #define MXC_F_PTG_READY_INTEN_PT14_POS 14 /**< READY_INTEN_PT14 Position */ 545 #define MXC_F_PTG_READY_INTEN_PT14 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT14_POS)) /**< READY_INTEN_PT14 Mask */ 546 547 #define MXC_F_PTG_READY_INTEN_PT15_POS 15 /**< READY_INTEN_PT15 Position */ 548 #define MXC_F_PTG_READY_INTEN_PT15 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT15_POS)) /**< READY_INTEN_PT15 Mask */ 549 550 /**@} end of group PTG_READY_INTEN_Register */ 551 552 #ifdef __cplusplus 553 } 554 #endif 555 556 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_PTG_REGS_H_ 557
