1<?xml version='1.0' encoding='utf-8'?> 2<device xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xsi:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <vendor>Maxim-Integrated</vendor> 4 <vendorID>Maxim</vendorID> 5 <name>max32690</name> 6 <series>ARMCM4</series> 7 <version>1.0</version> 8 <description>MAX32655 32-bit ARM Cortex-M4 microcontroller, 1024KB of flash, 760KB of system RAM, 128KB of Boot ROM.</description> 9 <cpu> 10 <name>CM4</name> 11 <revision>r2p1</revision> 12 <endian>little</endian> 13 <mpuPresent>true</mpuPresent> 14 <fpuPresent>true</fpuPresent> 15 <nvicPrioBits>3</nvicPrioBits> 16 <vendorSystickConfig>false</vendorSystickConfig> 17 </cpu> 18 <addressUnitBits>8</addressUnitBits> 19 <width>32</width> 20 <size>0x20</size> 21 <access>read-write</access> 22 <resetValue>0x00000000</resetValue> 23 <resetMask>0xFFFFFFFF</resetMask> 24 <peripherals> 25 <peripheral> 26 <name>ADC</name> 27 <description>Inter-Integrated Circuit.</description> 28 <groupName>ADC</groupName> 29 <baseAddress>0x40034000</baseAddress> 30 <size>32</size> 31 <addressBlock> 32 <offset>0x00</offset> 33 <size>0x1000</size> 34 <usage>registers</usage> 35 </addressBlock> 36 <interrupt> 37 <name>ADC</name> 38 <description>ADC IRQ</description> 39 <value>20</value> 40 </interrupt> 41 <registers> 42 <register> 43 <name>CTRL0</name> 44 <description>Control Register 0.</description> 45 <addressOffset>0x00</addressOffset> 46 <fields> 47 <field> 48 <name>ADC_EN</name> 49 <description>ADC Enable.</description> 50 <bitRange>[0:0]</bitRange> 51 <access>read-write</access> 52 <enumeratedValues> 53 <enumeratedValue> 54 <name>dis</name> 55 <description>Disable ADC.</description> 56 <value>0</value> 57 </enumeratedValue> 58 <enumeratedValue> 59 <name>en</name> 60 <description>enable ADC.</description> 61 <value>1</value> 62 </enumeratedValue> 63 </enumeratedValues> 64 </field> 65 <field> 66 <name>BIAS_EN</name> 67 <description>Bias Enable.</description> 68 <bitRange>[1:1]</bitRange> 69 <access>read-write</access> 70 <enumeratedValues> 71 <enumeratedValue> 72 <name>dis</name> 73 <description>Disable Bias.</description> 74 <value>0</value> 75 </enumeratedValue> 76 <enumeratedValue> 77 <name>en</name> 78 <description>Enable Bias.</description> 79 <value>1</value> 80 </enumeratedValue> 81 </enumeratedValues> 82 </field> 83 <field> 84 <name>SKIP_CAL</name> 85 <description>Skip Calibration Enable.</description> 86 <bitRange>[2:2]</bitRange> 87 <access>read-write</access> 88 <enumeratedValues> 89 <enumeratedValue> 90 <name>no_skip</name> 91 <description>Do not skip calibration.</description> 92 <value>0</value> 93 </enumeratedValue> 94 <enumeratedValue> 95 <name>skip</name> 96 <description>Skip calibration.</description> 97 <value>1</value> 98 </enumeratedValue> 99 </enumeratedValues> 100 </field> 101 <field> 102 <name>CHOP_FORCE</name> 103 <description>Chop Force Control.</description> 104 <bitRange>[3:3]</bitRange> 105 <access>read-write</access> 106 <enumeratedValues> 107 <enumeratedValue> 108 <name>dis</name> 109 <description>Do not force chop mode.</description> 110 <value>0</value> 111 </enumeratedValue> 112 <enumeratedValue> 113 <name>en</name> 114 <description>Force chop Mode.</description> 115 <value>1</value> 116 </enumeratedValue> 117 </enumeratedValues> 118 </field> 119 <field> 120 <name>RESETB</name> 121 <description>Reset ADC.</description> 122 <bitRange>[4:4]</bitRange> 123 <access>read-write</access> 124 <enumeratedValues> 125 <enumeratedValue> 126 <name>reset</name> 127 <description>reset ADC.</description> 128 <value>0</value> 129 </enumeratedValue> 130 <enumeratedValue> 131 <name>activate</name> 132 <description>activate ADC.</description> 133 <value>1</value> 134 </enumeratedValue> 135 </enumeratedValues> 136 </field> 137 </fields> 138 </register> 139 <register> 140 <name>CTRL1</name> 141 <description>Control Register 1.</description> 142 <addressOffset>0x04</addressOffset> 143 <fields> 144 <field> 145 <name>START</name> 146 <description>Start conversion control.</description> 147 <bitRange>[0:0]</bitRange> 148 <access>read-write</access> 149 <enumeratedValues> 150 <enumeratedValue> 151 <name>stop</name> 152 <description>Stop conversions.</description> 153 <value>0</value> 154 </enumeratedValue> 155 <enumeratedValue> 156 <name>start</name> 157 <description>Start conversions.</description> 158 <value>1</value> 159 </enumeratedValue> 160 </enumeratedValues> 161 </field> 162 <field> 163 <name>TRIG_MODE</name> 164 <description>Trigger mode control.</description> 165 <bitRange>[1:1]</bitRange> 166 <access>read-write</access> 167 <enumeratedValues> 168 <enumeratedValue> 169 <name>software</name> 170 <description>software trigger mode.</description> 171 <value>0</value> 172 </enumeratedValue> 173 <enumeratedValue> 174 <name>hardware</name> 175 <description>hardware trigger mode.</description> 176 <value>1</value> 177 </enumeratedValue> 178 </enumeratedValues> 179 </field> 180 <field> 181 <name>CNV_MODE</name> 182 <description>Conversion mode control.</description> 183 <bitRange>[2:2]</bitRange> 184 <access>read-write</access> 185 <enumeratedValues> 186 <enumeratedValue> 187 <name>atomic</name> 188 <description>Do one conversion sequence.</description> 189 <value>0</value> 190 </enumeratedValue> 191 <enumeratedValue> 192 <name>continuous</name> 193 <description>Do continuous conversion sequences.</description> 194 <value>1</value> 195 </enumeratedValue> 196 </enumeratedValues> 197 </field> 198 <field> 199 <name>SAMP_CK_OFF</name> 200 <description>Sample clock off control.</description> 201 <bitRange>[3:3]</bitRange> 202 <access>read-write</access> 203 <enumeratedValues> 204 <enumeratedValue> 205 <name>always</name> 206 <description>Sample clock always generated.</description> 207 <value>0</value> 208 </enumeratedValue> 209 <enumeratedValue> 210 <name>cnv_only</name> 211 <description>Sample clock generated only when converting.</description> 212 <value>1</value> 213 </enumeratedValue> 214 </enumeratedValues> 215 </field> 216 <field> 217 <name>TRIG_SEL</name> 218 <description>Hardware trigger source select.</description> 219 <bitRange>[6:4]</bitRange> 220 <access>read-write</access> 221 </field> 222 <field> 223 <name>TS_SEL</name> 224 <description>Temp sensor select.</description> 225 <bitRange>[7:7]</bitRange> 226 <access>read-write</access> 227 <enumeratedValues> 228 <enumeratedValue> 229 <name>dis</name> 230 <description>Temp sensor is not one of the slots in the sequence.</description> 231 <value>0</value> 232 </enumeratedValue> 233 <enumeratedValue> 234 <name>en</name> 235 <description>Temp sensor is one of the slots in the sequence.</description> 236 <value>1</value> 237 </enumeratedValue> 238 </enumeratedValues> 239 </field> 240 <field> 241 <name>AVG</name> 242 <description>Number of samples to average for each output data code.</description> 243 <bitRange>[10:8]</bitRange> 244 <access>read-write</access> 245 <enumeratedValues> 246 <enumeratedValue> 247 <name>avg1</name> 248 <description>1 Sample per output code.</description> 249 <value>0</value> 250 </enumeratedValue> 251 <enumeratedValue> 252 <name>avg2</name> 253 <description>2 Samples per output code.</description> 254 <value>1</value> 255 </enumeratedValue> 256 <enumeratedValue> 257 <name>avg4</name> 258 <description>4 Samples per output code.</description> 259 <value>2</value> 260 </enumeratedValue> 261 <enumeratedValue> 262 <name>avg8</name> 263 <description>8 Samples per output code.</description> 264 <value>3</value> 265 </enumeratedValue> 266 <enumeratedValue> 267 <name>avg16</name> 268 <description>16 Samples per output code.</description> 269 <value>4</value> 270 </enumeratedValue> 271 <enumeratedValue> 272 <name>avg32</name> 273 <description>32 Samples per output code.</description> 274 <value>5</value> 275 </enumeratedValue> 276 </enumeratedValues> 277 </field> 278 <field> 279 <name>NUM_SLOTS</name> 280 <description>Number of slots enabled for the conversion sequence</description> 281 <bitRange>[20:16]</bitRange> 282 <access>read-write</access> 283 </field> 284 </fields> 285 </register> 286 <register> 287 <name>CLKCTRL</name> 288 <description>Clock Control Register.</description> 289 <addressOffset>0x08</addressOffset> 290 <fields> 291 <field> 292 <name>CLKSEL</name> 293 <description>Clock source select.</description> 294 <bitRange>[1:0]</bitRange> 295 <access>read-write</access> 296 <enumeratedValues> 297 <enumeratedValue> 298 <name>HCLK</name> 299 <description>Select HCLK.</description> 300 <value>0</value> 301 </enumeratedValue> 302 <enumeratedValue> 303 <name>CLK_ADC0</name> 304 <description>Select CLK_ADC0.</description> 305 <value>1</value> 306 </enumeratedValue> 307 <enumeratedValue> 308 <name>CLK_ADC1</name> 309 <description>Select CLK_ADC1.</description> 310 <value>2</value> 311 </enumeratedValue> 312 <enumeratedValue> 313 <name>CLK_ADC2</name> 314 <description>Select CLK_ADC2.</description> 315 <value>3</value> 316 </enumeratedValue> 317 </enumeratedValues> 318 </field> 319 <field> 320 <name>CLKDIV</name> 321 <description>Clock divider control.</description> 322 <bitRange>[6:4]</bitRange> 323 <access>read-write</access> 324 <enumeratedValues> 325 <enumeratedValue> 326 <name>DIV2</name> 327 <description>Divide by 2.</description> 328 <value>0</value> 329 </enumeratedValue> 330 <enumeratedValue> 331 <name>DIV4</name> 332 <description>Divide by 4.</description> 333 <value>1</value> 334 </enumeratedValue> 335 <enumeratedValue> 336 <name>DIV8</name> 337 <description>Divide by 8.</description> 338 <value>2</value> 339 </enumeratedValue> 340 <enumeratedValue> 341 <name>DIV16</name> 342 <description>Divide by 16.</description> 343 <value>3</value> 344 </enumeratedValue> 345 <enumeratedValue> 346 <name>DIV1</name> 347 <description>Divide by 1.</description> 348 <value>4</value> 349 </enumeratedValue> 350 </enumeratedValues> 351 </field> 352 </fields> 353 </register> 354 <register> 355 <name>SAMPCLKCTRL</name> 356 <description>Sample Clock Control Register.</description> 357 <addressOffset>0x0C</addressOffset> 358 <access>read-write</access> 359 <fields> 360 <field> 361 <name>TRACK_CNT</name> 362 <description>Number of cycles for SAMPLE_CLK high time.</description> 363 <bitRange>[7:0]</bitRange> 364 <access>read-write</access> 365 </field> 366 <field> 367 <name>IDLE_CNT</name> 368 <description>Number of cycles for SAMPLE_CLK low time.</description> 369 <bitRange>[31:16]</bitRange> 370 <access>read-write</access> 371 </field> 372 </fields> 373 </register> 374 <register> 375 <name>CHSEL0</name> 376 <description>Channel Select Register 0.</description> 377 <addressOffset>0x10</addressOffset> 378 <fields> 379 <field> 380 <name>slot0_id</name> 381 <description>channel assignment for slot 0.</description> 382 <bitRange>[4:0]</bitRange> 383 <access>read-write</access> 384 </field> 385 <field> 386 <name>slot1_id</name> 387 <description>channel assignment for slot 1.</description> 388 <bitRange>[12:8]</bitRange> 389 <access>read-write</access> 390 </field> 391 <field> 392 <name>slot2_id</name> 393 <description>channel assignment for slot 2.</description> 394 <bitRange>[20:16]</bitRange> 395 <access>read-write</access> 396 </field> 397 <field> 398 <name>slot3_id</name> 399 <description>channel assignment for slot 3.</description> 400 <bitRange>[28:24]</bitRange> 401 <access>read-write</access> 402 </field> 403 </fields> 404 </register> 405 <register> 406 <name>CHSEL1</name> 407 <description>Channel Select Register 1.</description> 408 <addressOffset>0x14</addressOffset> 409 <fields> 410 <field> 411 <name>slot4_id</name> 412 <description>channel assignment for slot 4.</description> 413 <bitRange>[4:0]</bitRange> 414 <access>read-write</access> 415 </field> 416 <field> 417 <name>slot5_id</name> 418 <description>channel assignment for slot 5.</description> 419 <bitRange>[12:8]</bitRange> 420 <access>read-write</access> 421 </field> 422 <field> 423 <name>slot6_id</name> 424 <description>channel assignment for slot 6.</description> 425 <bitRange>[20:16]</bitRange> 426 <access>read-write</access> 427 </field> 428 <field> 429 <name>slot7_id</name> 430 <description>channel assignment for slot 7.</description> 431 <bitRange>[28:24]</bitRange> 432 <access>read-write</access> 433 </field> 434 </fields> 435 </register> 436 <register> 437 <name>CHSEL2</name> 438 <description>Channel Select Register 2.</description> 439 <addressOffset>0x18</addressOffset> 440 <fields> 441 <field> 442 <name>slot8_id</name> 443 <description>channel assignment for slot 8.</description> 444 <bitRange>[4:0]</bitRange> 445 <access>read-write</access> 446 </field> 447 <field> 448 <name>slot9_id</name> 449 <description>channel assignment for slot 9.</description> 450 <bitRange>[12:8]</bitRange> 451 <access>read-write</access> 452 </field> 453 <field> 454 <name>slot10_id</name> 455 <description>channel assignment for slot 10.</description> 456 <bitRange>[20:16]</bitRange> 457 <access>read-write</access> 458 </field> 459 <field> 460 <name>slot11_id</name> 461 <description>channel assignment for slot 11.</description> 462 <bitRange>[28:24]</bitRange> 463 <access>read-write</access> 464 </field> 465 </fields> 466 </register> 467 <register> 468 <name>CHSEL3</name> 469 <description>Channel Select Register 3.</description> 470 <addressOffset>0x1C</addressOffset> 471 <fields> 472 <field> 473 <name>slot12_id</name> 474 <description>channel assignment for slot 12.</description> 475 <bitRange>[4:0]</bitRange> 476 <access>read-write</access> 477 </field> 478 <field> 479 <name>slot13_id</name> 480 <description>channel assignment for slot 13.</description> 481 <bitRange>[12:8]</bitRange> 482 <access>read-write</access> 483 </field> 484 <field> 485 <name>slot14_id</name> 486 <description>channel assignment for slot 14.</description> 487 <bitRange>[20:16]</bitRange> 488 <access>read-write</access> 489 </field> 490 <field> 491 <name>slot15_id</name> 492 <description>channel assignment for slot 15.</description> 493 <bitRange>[28:24]</bitRange> 494 <access>read-write</access> 495 </field> 496 </fields> 497 </register> 498 <register> 499 <name>RESTART</name> 500 <description>Restart Count Control Register</description> 501 <addressOffset>0x30</addressOffset> 502 <fields> 503 <field> 504 <name>CNT</name> 505 <description>Number of sample periods to skip before restarting a continuous mode sequence</description> 506 <bitRange>[15:0]</bitRange> 507 <access>read-write</access> 508 </field> 509 </fields> 510 </register> 511 <register> 512 <name>DATAFMT</name> 513 <description>Channel Data Format Register</description> 514 <addressOffset>0x3C</addressOffset> 515 <fields> 516 <field> 517 <name>MODE</name> 518 <description>Data format control</description> 519 <bitRange>[31:0]</bitRange> 520 <access>read-write</access> 521 </field> 522 </fields> 523 </register> 524 <register> 525 <name>FIFODMACTRL</name> 526 <description>FIFO and DMA control</description> 527 <addressOffset>0x40</addressOffset> 528 <fields> 529 <field> 530 <name>DMA_EN</name> 531 <description>DMA Enable.</description> 532 <bitRange>[0:0]</bitRange> 533 <access>read-write</access> 534 <enumeratedValues> 535 <enumeratedValue> 536 <name>dis</name> 537 <description>Disable DMA.</description> 538 <value>0</value> 539 </enumeratedValue> 540 <enumeratedValue> 541 <name>en</name> 542 <description>Enable DMA.</description> 543 <value>1</value> 544 </enumeratedValue> 545 </enumeratedValues> 546 </field> 547 <field> 548 <name>FLUSH</name> 549 <description>FIFO Flush.</description> 550 <bitRange>[1:1]</bitRange> 551 <access>read-write</access> 552 <enumeratedValues> 553 <enumeratedValue> 554 <name>normal</name> 555 <description>Normal FIFO operation.</description> 556 <value>0</value> 557 </enumeratedValue> 558 <enumeratedValue> 559 <name>flush</name> 560 <description>Flush FIFO.</description> 561 <value>1</value> 562 </enumeratedValue> 563 </enumeratedValues> 564 </field> 565 <field> 566 <name>DATA_FORMAT</name> 567 <description>DATA format control.</description> 568 <bitRange>[3:2]</bitRange> 569 <access>read-write</access> 570 <enumeratedValues> 571 <enumeratedValue> 572 <name>data_status</name> 573 <description>Data and Status in FIFO.</description> 574 <value>0</value> 575 </enumeratedValue> 576 <enumeratedValue> 577 <name>data_only</name> 578 <description>Only Data in FIFO.</description> 579 <value>1</value> 580 </enumeratedValue> 581 <enumeratedValue> 582 <name>raw_data_only</name> 583 <description>Only Raw Data in FIFO.</description> 584 <value>2</value> 585 </enumeratedValue> 586 </enumeratedValues> 587 </field> 588 <field> 589 <name>THRESH</name> 590 <description>FIFO Threshold. These bits define the FIFO interrupt threshold.</description> 591 <bitRange>[15:8]</bitRange> 592 <access>read-write</access> 593 </field> 594 </fields> 595 </register> 596 <register> 597 <name>DATA</name> 598 <description>Data Register (FIFO).</description> 599 <addressOffset>0x44</addressOffset> 600 <fields> 601 <field> 602 <name>DATA</name> 603 <description>Conversion data.</description> 604 <bitRange>[15:0]</bitRange> 605 <access>read-only</access> 606 </field> 607 <field> 608 <name>CHAN</name> 609 <description>Channel for the data.</description> 610 <bitRange>[20:16]</bitRange> 611 <access>read-only</access> 612 </field> 613 <field> 614 <name>INVALID</name> 615 <description>Invalid status for the data.</description> 616 <bitRange>[24:24]</bitRange> 617 <access>read-only</access> 618 </field> 619 <field> 620 <name>CLIPPED</name> 621 <description>Clipped status for the data.</description> 622 <bitRange>[31:31]</bitRange> 623 <access>read-only</access> 624 </field> 625 </fields> 626 </register> 627 <register> 628 <name>STATUS</name> 629 <description>Status Register</description> 630 <addressOffset>0x48</addressOffset> 631 <fields> 632 <field> 633 <name>READY</name> 634 <description>Indication that the ADC is in ON power state</description> 635 <bitRange>[0:0]</bitRange> 636 <access>read-only</access> 637 </field> 638 <field> 639 <name>EMPTY</name> 640 <description>FIFO Empty</description> 641 <bitRange>[1:1]</bitRange> 642 <access>read-only</access> 643 </field> 644 <field> 645 <name>FULL</name> 646 <description>FIFO full</description> 647 <bitRange>[2:2]</bitRange> 648 <access>read-only</access> 649 </field> 650 <field> 651 <name>FIFO_LEVEL</name> 652 <description>Number of entries in FIFO available to read</description> 653 <bitRange>[15:8]</bitRange> 654 <access>read-only</access> 655 </field> 656 </fields> 657 </register> 658 <register> 659 <name>CHSTATUS</name> 660 <description>Channel Status</description> 661 <addressOffset>0x4C</addressOffset> 662 <fields> 663 <field> 664 <name>CLIPPED</name> 665 <description /> 666 <bitRange>[31:0]</bitRange> 667 <access>read-write</access> 668 </field> 669 </fields> 670 </register> 671 <register> 672 <name>INTEN</name> 673 <description>Interrupt Enable Register.</description> 674 <addressOffset>0x50</addressOffset> 675 <fields> 676 <field> 677 <name>READY</name> 678 <description>ADC is ready.</description> 679 <bitRange>[0:0]</bitRange> 680 <access>read-write</access> 681 </field> 682 <field> 683 <name>ABORT</name> 684 <description>Conversion start is aborted.</description> 685 <bitRange>[2:2]</bitRange> 686 <access>read-write</access> 687 </field> 688 <field> 689 <name>START_DET</name> 690 <description>Conversion start is detected.</description> 691 <bitRange>[3:3]</bitRange> 692 <access>read-write</access> 693 </field> 694 <field> 695 <name>SEQ_STARTED</name> 696 <bitRange>[4:4]</bitRange> 697 <access>read-write</access> 698 </field> 699 <field> 700 <name>SEQ_DONE</name> 701 <bitRange>[5:5]</bitRange> 702 <access>read-write</access> 703 </field> 704 <field> 705 <name>CONV_DONE</name> 706 <bitRange>[6:6]</bitRange> 707 <access>read-write</access> 708 </field> 709 <field> 710 <name>CLIPPED</name> 711 <bitRange>[7:7]</bitRange> 712 <access>read-write</access> 713 </field> 714 <field> 715 <name>FIFO_LVL</name> 716 <bitRange>[8:8]</bitRange> 717 <access>read-write</access> 718 </field> 719 <field> 720 <name>FIFO_UFL</name> 721 <bitRange>[9:9]</bitRange> 722 <access>read-write</access> 723 </field> 724 <field> 725 <name>FIFO_OFL</name> 726 <bitRange>[10:10]</bitRange> 727 <access>read-write</access> 728 </field> 729 </fields> 730 </register> 731 <register> 732 <name>INTFL</name> 733 <description>Interrupt Flags Register.</description> 734 <addressOffset>0x54</addressOffset> 735 <fields> 736 <field> 737 <name>READY</name> 738 <description>ADC is ready.</description> 739 <bitRange>[0:0]</bitRange> 740 <access>read-write</access> 741 <modifiedWriteValues>oneToClear</modifiedWriteValues> 742 </field> 743 <field> 744 <name>ABORT</name> 745 <description>Conversion start is aborted.</description> 746 <bitRange>[2:2]</bitRange> 747 <access>read-write</access> 748 <modifiedWriteValues>oneToClear</modifiedWriteValues> 749 </field> 750 <field> 751 <name>START_DET</name> 752 <description>Conversion start is detected.</description> 753 <bitRange>[3:3]</bitRange> 754 <access>read-write</access> 755 <modifiedWriteValues>oneToClear</modifiedWriteValues> 756 </field> 757 <field> 758 <name>SEQ_STARTED</name> 759 <bitRange>[4:4]</bitRange> 760 <access>read-write</access> 761 <modifiedWriteValues>oneToClear</modifiedWriteValues> 762 </field> 763 <field> 764 <name>SEQ_DONE</name> 765 <bitRange>[5:5]</bitRange> 766 <access>read-write</access> 767 <modifiedWriteValues>oneToClear</modifiedWriteValues> 768 </field> 769 <field> 770 <name>CONV_DONE</name> 771 <bitRange>[6:6]</bitRange> 772 <access>read-write</access> 773 <modifiedWriteValues>oneToClear</modifiedWriteValues> 774 </field> 775 <field> 776 <name>CLIPPED</name> 777 <bitRange>[7:7]</bitRange> 778 <access>read-write</access> 779 <modifiedWriteValues>oneToClear</modifiedWriteValues> 780 </field> 781 <field> 782 <name>FIFO_LVL</name> 783 <bitRange>[8:8]</bitRange> 784 <access>read-write</access> 785 <modifiedWriteValues>oneToClear</modifiedWriteValues> 786 </field> 787 <field> 788 <name>FIFO_UFL</name> 789 <bitRange>[9:9]</bitRange> 790 <access>read-write</access> 791 <modifiedWriteValues>oneToClear</modifiedWriteValues> 792 </field> 793 <field> 794 <name>FIFO_OFL</name> 795 <bitRange>[10:10]</bitRange> 796 <access>read-write</access> 797 <modifiedWriteValues>oneToClear</modifiedWriteValues> 798 </field> 799 </fields> 800 </register> 801 <register> 802 <name>SFRADDROFFSET</name> 803 <description>SFR Address Offset Register</description> 804 <addressOffset>0x60</addressOffset> 805 <fields> 806 <field> 807 <name>OFFSET</name> 808 <description>Address Offset for SAR Digital</description> 809 <bitRange>[7:0]</bitRange> 810 <access>read-write</access> 811 </field> 812 </fields> 813 </register> 814 <register> 815 <name>SFRADDR</name> 816 <description>SFR Address Register</description> 817 <addressOffset>0x64</addressOffset> 818 <fields> 819 <field> 820 <name>ADDR</name> 821 <description>Address to SAR Digital</description> 822 <bitRange>[7:0]</bitRange> 823 <access>read-write</access> 824 </field> 825 </fields> 826 </register> 827 <register> 828 <name>SFRWRDATA</name> 829 <description>SFR Write Data Register</description> 830 <addressOffset>0x68</addressOffset> 831 <fields> 832 <field> 833 <name>DATA</name> 834 <description>DATA to SAR Digital</description> 835 <bitRange>[7:0]</bitRange> 836 <access>read-write</access> 837 </field> 838 </fields> 839 </register> 840 <register> 841 <name>SFRRDDATA</name> 842 <description>SFR Read Data Register</description> 843 <addressOffset>0x6C</addressOffset> 844 <fields> 845 <field> 846 <name>DATA</name> 847 <description>DATA from SAR Digital</description> 848 <bitRange>[7:0]</bitRange> 849 <access>read-only</access> 850 </field> 851 </fields> 852 </register> 853 <register> 854 <name>SFRSTATUS</name> 855 <description>SFR Status Register</description> 856 <addressOffset>0x70</addressOffset> 857 <fields> 858 <field> 859 <name>NACK</name> 860 <description>NACK status for SAR Digital SFR communication</description> 861 <bitRange>[0:0]</bitRange> 862 <access>read-only</access> 863 </field> 864 </fields> 865 </register> 866 </registers> 867 </peripheral> 868<!--ADC Inter-Integrated Circuit.--> 869 <peripheral> 870 <name>AESKEYS</name> 871 <description>AES Key Registers.</description> 872 <baseAddress>0x40005000</baseAddress> 873 <addressBlock> 874 <offset>0x00</offset> 875 <size>0x400</size> 876 <usage>registers</usage> 877 </addressBlock> 878 <registers> 879 <register> 880 <name>KEY0</name> 881 <description>AES Key 0.</description> 882 <addressOffset>0x000</addressOffset> 883 <size>128</size> 884 </register> 885 <register> 886 <name>KEY1</name> 887 <description>AES Key 1.</description> 888 <addressOffset>0x010</addressOffset> 889 <size>128</size> 890 </register> 891 </registers> 892 </peripheral> 893<!--AESKEYS AES Key Registers.--> 894 <peripheral> 895 <name>CAN0</name> 896 <description>Controller Area Network Registers</description> 897 <baseAddress>0x40064000</baseAddress> 898 <addressBlock> 899 <offset>0x00</offset> 900 <size>0x1000</size> 901 <usage>registers</usage> 902 </addressBlock> 903 <registers> 904 <register> 905 <name>MODE</name> 906 <description>Mode Register.</description> 907 <addressOffset>0x0000</addressOffset> 908 <size>8</size> 909 <access>read-write</access> 910 <fields> 911 <field> 912 <name>AFM</name> 913 <description>Hardware acceptance filter scheme.</description> 914 <bitOffset>0</bitOffset> 915 <bitWidth>1</bitWidth> 916 </field> 917 <field> 918 <name>LOM</name> 919 <description>Listen Only Mode.</description> 920 <bitOffset>1</bitOffset> 921 <bitWidth>1</bitWidth> 922 </field> 923 <field> 924 <name>RST</name> 925 <description>Reset Mode.</description> 926 <bitOffset>2</bitOffset> 927 <bitWidth>1</bitWidth> 928 </field> 929 <field> 930 <name>RXTRIG</name> 931 <description>Receive FIFO trigger in 32bit word.</description> 932 <bitOffset>3</bitOffset> 933 <bitWidth>3</bitWidth> 934 <enumeratedValues> 935 <enumeratedValue> 936 <name>1W</name> 937 <description>1 word</description> 938 <value>0</value> 939 </enumeratedValue> 940 <enumeratedValue> 941 <name>4W</name> 942 <description>4 word</description> 943 <value>1</value> 944 </enumeratedValue> 945 <enumeratedValue> 946 <name>8W</name> 947 <description>8 word</description> 948 <value>2</value> 949 </enumeratedValue> 950 <enumeratedValue> 951 <name>16W</name> 952 <description>16 word</description> 953 <value>3</value> 954 </enumeratedValue> 955 <enumeratedValue> 956 <name>32W</name> 957 <description>32 word</description> 958 <value>4</value> 959 </enumeratedValue> 960 <enumeratedValue> 961 <name>64W</name> 962 <description>64 word</description> 963 <value>5</value> 964 </enumeratedValue> 965 </enumeratedValues> 966 </field> 967 <field> 968 <name>DMA</name> 969 <description>Enable DMA mode.</description> 970 <bitOffset>6</bitOffset> 971 <bitWidth>1</bitWidth> 972 </field> 973 <field> 974 <name>SLP</name> 975 <description>Sleep mode.</description> 976 <bitOffset>7</bitOffset> 977 <bitWidth>1</bitWidth> 978 <enumeratedValues> 979 <enumeratedValue> 980 <name>enter</name> 981 <description>Enter sleep mode.</description> 982 <value>1</value> 983 </enumeratedValue> 984 <enumeratedValue> 985 <name>leave</name> 986 <description>Leave sleep mode.</description> 987 <value>0</value> 988 </enumeratedValue> 989 </enumeratedValues> 990 </field> 991 </fields> 992 </register> 993 <register> 994 <name>CMD</name> 995 <description>Command Register.</description> 996 <addressOffset>0x0001</addressOffset> 997 <size>8</size> 998 <access>read-write</access> 999 <fields> 1000 <field> 1001 <name>ABORT</name> 1002 <description>Abort Transmission</description> 1003 <bitOffset>1</bitOffset> 1004 <bitWidth>1</bitWidth> 1005 </field> 1006 <field> 1007 <name>TXREQ</name> 1008 <description>Transmit Request.</description> 1009 <bitOffset>2</bitOffset> 1010 <bitWidth>1</bitWidth> 1011 </field> 1012 </fields> 1013 </register> 1014 <register> 1015 <name>STAT</name> 1016 <description>Status Register.</description> 1017 <addressOffset>0x0002</addressOffset> 1018 <size>8</size> 1019 <access>read-only</access> 1020 <fields> 1021 <field> 1022 <name>BUS_OFF</name> 1023 <description>Bus off Status.</description> 1024 <bitOffset>0</bitOffset> 1025 <bitWidth>1</bitWidth> 1026 </field> 1027 <field> 1028 <name>ERR</name> 1029 <description>Error Status.</description> 1030 <bitOffset>1</bitOffset> 1031 <bitWidth>1</bitWidth> 1032 </field> 1033 <field> 1034 <name>TX</name> 1035 <description>Transmit Status.</description> 1036 <bitOffset>2</bitOffset> 1037 <bitWidth>1</bitWidth> 1038 </field> 1039 <field> 1040 <name>RX</name> 1041 <description>Receive Status.</description> 1042 <bitOffset>3</bitOffset> 1043 <bitWidth>1</bitWidth> 1044 </field> 1045 <field> 1046 <name>TXBUF</name> 1047 <description>Transmit Buffer Status.</description> 1048 <bitOffset>5</bitOffset> 1049 <bitWidth>1</bitWidth> 1050 </field> 1051 <field> 1052 <name>DOR</name> 1053 <description>Data Overrun Status.</description> 1054 <bitOffset>6</bitOffset> 1055 <bitWidth>1</bitWidth> 1056 </field> 1057 <field> 1058 <name>RXBUF</name> 1059 <description>Receive Buffer Status.</description> 1060 <bitOffset>7</bitOffset> 1061 <bitWidth>1</bitWidth> 1062 </field> 1063 </fields> 1064 </register> 1065 <register> 1066 <name>INTFL</name> 1067 <description>Interrupt Status Register.</description> 1068 <addressOffset>0x0003</addressOffset> 1069 <size>8</size> 1070 <access>read-write</access> 1071 <fields> 1072 <field> 1073 <name>DOR</name> 1074 <description>Data Overrun Interrupt.</description> 1075 <bitOffset>0</bitOffset> 1076 <bitWidth>1</bitWidth> 1077 </field> 1078 <field> 1079 <name>BERR</name> 1080 <description>Bus Error Interrupt.</description> 1081 <bitOffset>1</bitOffset> 1082 <bitWidth>1</bitWidth> 1083 </field> 1084 <field> 1085 <name>TX</name> 1086 <description>Transmission Interrupt.</description> 1087 <bitOffset>2</bitOffset> 1088 <bitWidth>1</bitWidth> 1089 </field> 1090 <field> 1091 <name>RX</name> 1092 <description>Receive Interrupt.</description> 1093 <bitOffset>3</bitOffset> 1094 <bitWidth>1</bitWidth> 1095 </field> 1096 <field> 1097 <name>ERPSV</name> 1098 <description>Error Passive Interrupt.</description> 1099 <bitOffset>4</bitOffset> 1100 <bitWidth>1</bitWidth> 1101 </field> 1102 <field> 1103 <name>ERWARN</name> 1104 <description>Error Warning Interrupt.</description> 1105 <bitOffset>5</bitOffset> 1106 <bitWidth>1</bitWidth> 1107 </field> 1108 <field> 1109 <name>AL</name> 1110 <description>Arbitration Lost Interrupt.</description> 1111 <bitOffset>6</bitOffset> 1112 <bitWidth>1</bitWidth> 1113 </field> 1114 <field> 1115 <name>WU</name> 1116 <description>Wake-up Interrupt.</description> 1117 <bitOffset>7</bitOffset> 1118 <bitWidth>1</bitWidth> 1119 </field> 1120 </fields> 1121 </register> 1122 <register> 1123 <name>INTEN</name> 1124 <description>Interrupt Enable Register.</description> 1125 <addressOffset>0x0004</addressOffset> 1126 <size>8</size> 1127 <access>read-write</access> 1128 <fields> 1129 <field> 1130 <name>DOR</name> 1131 <description>Data Overrun Interrupt.</description> 1132 <bitOffset>0</bitOffset> 1133 <bitWidth>1</bitWidth> 1134 </field> 1135 <field> 1136 <name>BERR</name> 1137 <description>Bus Error Interrupt.</description> 1138 <bitOffset>1</bitOffset> 1139 <bitWidth>1</bitWidth> 1140 </field> 1141 <field> 1142 <name>TX</name> 1143 <description>Transmit Interrupt.</description> 1144 <bitOffset>2</bitOffset> 1145 <bitWidth>1</bitWidth> 1146 </field> 1147 <field> 1148 <name>RX</name> 1149 <description>Receive Interrupt.</description> 1150 <bitOffset>3</bitOffset> 1151 <bitWidth>1</bitWidth> 1152 </field> 1153 <field> 1154 <name>ERPSV</name> 1155 <description>Error Passive Interrupt.</description> 1156 <bitOffset>4</bitOffset> 1157 <bitWidth>1</bitWidth> 1158 </field> 1159 <field> 1160 <name>ERWARN</name> 1161 <description>Error Warning Interrupt.</description> 1162 <bitOffset>5</bitOffset> 1163 <bitWidth>1</bitWidth> 1164 </field> 1165 <field> 1166 <name>AL</name> 1167 <description>Arbitration Lost Interrupt.</description> 1168 <bitOffset>6</bitOffset> 1169 <bitWidth>1</bitWidth> 1170 </field> 1171 <field> 1172 <name>WU</name> 1173 <description>Wakeup interrupt.</description> 1174 <bitOffset>7</bitOffset> 1175 <bitWidth>1</bitWidth> 1176 </field> 1177 </fields> 1178 </register> 1179 <register> 1180 <name>RMC</name> 1181 <description>Receive Message Counter Register.</description> 1182 <addressOffset>0x0005</addressOffset> 1183 <size>8</size> 1184 <access>read-write</access> 1185 <fields> 1186 <field> 1187 <name>NUM_MSGS</name> 1188 <description>Number of stored message frames.</description> 1189 <bitOffset>0</bitOffset> 1190 <bitWidth>5</bitWidth> 1191 </field> 1192 </fields> 1193 </register> 1194 <register> 1195 <name>BUSTIM0</name> 1196 <description>Bus Timing Register 0.</description> 1197 <addressOffset>0x0006</addressOffset> 1198 <size>8</size> 1199 <access>read-write</access> 1200 <fields> 1201 <field> 1202 <name>BR_CLKDIV</name> 1203 <description>Baud Rate Prescaler.</description> 1204 <bitOffset>0</bitOffset> 1205 <bitWidth>6</bitWidth> 1206 </field> 1207 <field> 1208 <name>SJW</name> 1209 <description>Synchronization Jump Width.</description> 1210 <bitOffset>6</bitOffset> 1211 <bitWidth>2</bitWidth> 1212 </field> 1213 </fields> 1214 </register> 1215 <register> 1216 <name>BUSTIM1</name> 1217 <description>Bus Timing Register 1.</description> 1218 <addressOffset>0x0007</addressOffset> 1219 <size>8</size> 1220 <access>read-write</access> 1221 <fields> 1222 <field> 1223 <name>TSEG1</name> 1224 <description>Number of clock cycles per Time Segment 1</description> 1225 <bitOffset>0</bitOffset> 1226 <bitWidth>4</bitWidth> 1227 </field> 1228 <field> 1229 <name>TSEG2</name> 1230 <description>Number of clock cycles per Time Segment 2</description> 1231 <bitOffset>4</bitOffset> 1232 <bitWidth>3</bitWidth> 1233 </field> 1234 <field> 1235 <name>SAM</name> 1236 <description>Number of bus level samples.</description> 1237 <bitOffset>7</bitOffset> 1238 <bitWidth>1</bitWidth> 1239 </field> 1240 </fields> 1241 </register> 1242 <register> 1243 <name>TXFIFO32</name> 1244 <description>Transmit FIFO Register.</description> 1245 <addressOffset>0x0008</addressOffset> 1246 <size>32</size> 1247 <access>read-write</access> 1248 <fields> 1249 <field> 1250 <name>DATA</name> 1251 <description>Write to put into TX FIFO.</description> 1252 <bitOffset>0</bitOffset> 1253 <bitWidth>32</bitWidth> 1254 </field> 1255 </fields> 1256 </register> 1257 <register> 1258 <dim>2</dim> 1259 <dimIncrement>2</dimIncrement> 1260 <name>TXFIFO16[%s]</name> 1261 <description>Transmit FIFO Register.</description> 1262 <addressOffset>0x0008</addressOffset> 1263 <size>16</size> 1264 <access>read-write</access> 1265 <fields> 1266 <field> 1267 <name>DATA</name> 1268 <description>Write to put into TX FIFO.</description> 1269 <bitOffset>0</bitOffset> 1270 <bitWidth>16</bitWidth> 1271 </field> 1272 </fields> 1273 </register> 1274 <register> 1275 <dim>4</dim> 1276 <dimIncrement>1</dimIncrement> 1277 <name>TXFIFO8[%s]</name> 1278 <description>Transmit FIFO Register.</description> 1279 <addressOffset>0x0008</addressOffset> 1280 <size>8</size> 1281 <access>read-write</access> 1282 <fields> 1283 <field> 1284 <name>DATA</name> 1285 <description>Write to put into TX FIFO.</description> 1286 <bitOffset>0</bitOffset> 1287 <bitWidth>8</bitWidth> 1288 </field> 1289 </fields> 1290 </register> 1291 <register> 1292 <name>RXFIFO32</name> 1293 <description>Receive FIFO Register.</description> 1294 <addressOffset>0x000C</addressOffset> 1295 <access>read-only</access> 1296 <fields> 1297 <field> 1298 <name>DATA</name> 1299 <description>Read from RX FIFO.</description> 1300 <bitOffset>0</bitOffset> 1301 <bitWidth>32</bitWidth> 1302 </field> 1303 </fields> 1304 </register> 1305 <register> 1306 <dim>2</dim> 1307 <dimIncrement>2</dimIncrement> 1308 <name>RXFIFO16[%s]</name> 1309 <description>Receive FIFO Register.</description> 1310 <addressOffset>0x000C</addressOffset> 1311 <size>16</size> 1312 <access>read-only</access> 1313 <fields> 1314 <field> 1315 <name>DATA</name> 1316 <description>Read from RX FIFO.</description> 1317 <bitOffset>0</bitOffset> 1318 <bitWidth>16</bitWidth> 1319 </field> 1320 </fields> 1321 </register> 1322 <register> 1323 <dim>4</dim> 1324 <dimIncrement>1</dimIncrement> 1325 <name>RXFIFO8[%s]</name> 1326 <description>Receive FIFO Register.</description> 1327 <addressOffset>0x000C</addressOffset> 1328 <size>8</size> 1329 <access>read-only</access> 1330 <fields> 1331 <field> 1332 <name>DATA</name> 1333 <description>Read from RX FIFO.</description> 1334 <bitOffset>0</bitOffset> 1335 <bitWidth>8</bitWidth> 1336 </field> 1337 </fields> 1338 </register> 1339 <register> 1340 <name>ACR32</name> 1341 <description>Acceptance Code Register.</description> 1342 <addressOffset>0x0010</addressOffset> 1343 <access>read-write</access> 1344 <fields> 1345 <field> 1346 <name>ACR</name> 1347 <description>Acceptance Code.</description> 1348 <bitOffset>0</bitOffset> 1349 <bitWidth>32</bitWidth> 1350 </field> 1351 </fields> 1352 </register> 1353 <register> 1354 <dim>2</dim> 1355 <dimIncrement>2</dimIncrement> 1356 <name>ACR16[%s]</name> 1357 <description>Acceptance Code Register.</description> 1358 <addressOffset>0x0010</addressOffset> 1359 <size>16</size> 1360 <access>read-write</access> 1361 <fields> 1362 <field> 1363 <name>ACR</name> 1364 <description>Acceptance Code.</description> 1365 <bitOffset>0</bitOffset> 1366 <bitWidth>16</bitWidth> 1367 </field> 1368 </fields> 1369 </register> 1370 <register> 1371 <dim>4</dim> 1372 <dimIncrement>1</dimIncrement> 1373 <name>ACR8[%s]</name> 1374 <description>Acceptance Code Register.</description> 1375 <addressOffset>0x0010</addressOffset> 1376 <size>8</size> 1377 <access>read-write</access> 1378 <fields> 1379 <field> 1380 <name>ACR</name> 1381 <description>Acceptance Code.</description> 1382 <bitOffset>0</bitOffset> 1383 <bitWidth>8</bitWidth> 1384 </field> 1385 </fields> 1386 </register> 1387 <register> 1388 <name>AMR32</name> 1389 <description>Acceptance Mask Register.</description> 1390 <addressOffset>0x0014</addressOffset> 1391 <access>read-write</access> 1392 <fields> 1393 <field> 1394 <name>AMR</name> 1395 <description>Acceptance Mask.</description> 1396 <bitOffset>0</bitOffset> 1397 <bitWidth>32</bitWidth> 1398 </field> 1399 </fields> 1400 </register> 1401 <register> 1402 <dim>2</dim> 1403 <dimIncrement>2</dimIncrement> 1404 <name>AMR16[%s]</name> 1405 <description>Acceptance Mask Register.</description> 1406 <addressOffset>0x0014</addressOffset> 1407 <size>16</size> 1408 <access>read-write</access> 1409 <fields> 1410 <field> 1411 <name>AMR</name> 1412 <description>Acceptance Mask.</description> 1413 <bitOffset>0</bitOffset> 1414 <bitWidth>16</bitWidth> 1415 </field> 1416 </fields> 1417 </register> 1418 <register> 1419 <dim>4</dim> 1420 <dimIncrement>1</dimIncrement> 1421 <name>AMR8[%s]</name> 1422 <description>Acceptance Mask Register.</description> 1423 <addressOffset>0x0014</addressOffset> 1424 <size>8</size> 1425 <access>read-write</access> 1426 <fields> 1427 <field> 1428 <name>AMR</name> 1429 <description>Acceptance Mask.</description> 1430 <bitOffset>0</bitOffset> 1431 <bitWidth>8</bitWidth> 1432 </field> 1433 </fields> 1434 </register> 1435 <register> 1436 <name>ECC</name> 1437 <description>Error Code Capture Register.</description> 1438 <addressOffset>0x0018</addressOffset> 1439 <size>8</size> 1440 <access>read-only</access> 1441 <fields> 1442 <field> 1443 <name>BER</name> 1444 <description>Bit Error Occurred.</description> 1445 <bitOffset>0</bitOffset> 1446 <bitWidth>1</bitWidth> 1447 </field> 1448 <field> 1449 <name>STFER</name> 1450 <description>Stuff Error Occurred.</description> 1451 <bitOffset>1</bitOffset> 1452 <bitWidth>1</bitWidth> 1453 </field> 1454 <field> 1455 <name>CRCER</name> 1456 <description>CRC Error Occurred.</description> 1457 <bitOffset>2</bitOffset> 1458 <bitWidth>1</bitWidth> 1459 </field> 1460 <field> 1461 <name>FRMER</name> 1462 <description>Form Error Occurred.</description> 1463 <bitOffset>3</bitOffset> 1464 <bitWidth>1</bitWidth> 1465 </field> 1466 <field> 1467 <name>ACKER</name> 1468 <description>ACK Error Occurred.</description> 1469 <bitOffset>4</bitOffset> 1470 <bitWidth>1</bitWidth> 1471 </field> 1472 <field> 1473 <name>EDIR</name> 1474 <description>Direction of transfer while error occurred.</description> 1475 <bitOffset>5</bitOffset> 1476 <bitWidth>1</bitWidth> 1477 <enumeratedValues> 1478 <enumeratedValue> 1479 <name>TX</name> 1480 <description>Transmission</description> 1481 <value>0</value> 1482 </enumeratedValue> 1483 <enumeratedValue> 1484 <name>RX</name> 1485 <description>Reception</description> 1486 <value>1</value> 1487 </enumeratedValue> 1488 </enumeratedValues> 1489 </field> 1490 <field> 1491 <name>TXWRN</name> 1492 <description>Set when TXERR counter is greater than or equal to 96.</description> 1493 <bitOffset>6</bitOffset> 1494 <bitWidth>1</bitWidth> 1495 </field> 1496 <field> 1497 <name>RXWRN</name> 1498 <description>Set when RXERR counter is greater than or equal to 96.</description> 1499 <bitOffset>7</bitOffset> 1500 <bitWidth>1</bitWidth> 1501 </field> 1502 </fields> 1503 </register> 1504 <register> 1505 <name>RXERR</name> 1506 <description>Receive Error Counter.</description> 1507 <addressOffset>0x0019</addressOffset> 1508 <size>8</size> 1509 <access>read-write</access> 1510 <fields> 1511 <field> 1512 <name>RXERR</name> 1513 <description>Receive Error Counter.</description> 1514 <bitOffset>0</bitOffset> 1515 <bitWidth>8</bitWidth> 1516 </field> 1517 </fields> 1518 </register> 1519 <register> 1520 <name>TXERR</name> 1521 <description>Invalidate All Registers.</description> 1522 <addressOffset>0x001A</addressOffset> 1523 <size>8</size> 1524 <access>read-write</access> 1525 <fields> 1526 <field> 1527 <name>TXERR</name> 1528 <description>Transmit Error Counter.</description> 1529 <bitOffset>0</bitOffset> 1530 <bitWidth>8</bitWidth> 1531 </field> 1532 </fields> 1533 </register> 1534 <register> 1535 <name>ALC</name> 1536 <description>Arbitration Lost Code Capture Register.</description> 1537 <addressOffset>0x001B</addressOffset> 1538 <size>8</size> 1539 <access>read-only</access> 1540 <fields> 1541 <field> 1542 <name>ALC</name> 1543 <description>Arbitration Lost Capture.</description> 1544 <bitOffset>0</bitOffset> 1545 <bitWidth>5</bitWidth> 1546 </field> 1547 </fields> 1548 </register> 1549 <register> 1550 <name>NBT</name> 1551 <description>Nominal Bit Timing Register.</description> 1552 <addressOffset>0x001C</addressOffset> 1553 <access>read-write</access> 1554 <fields> 1555 <field> 1556 <name>NBRP</name> 1557 <description>Baudrate Prescaler Used in Arbitration Phase.</description> 1558 <bitOffset>0</bitOffset> 1559 <bitWidth>10</bitWidth> 1560 </field> 1561 <field> 1562 <name>NSEG1</name> 1563 <description>The time segment before the sample point in Abritration Phase.</description> 1564 <bitOffset>10</bitOffset> 1565 <bitWidth>8</bitWidth> 1566 </field> 1567 <field> 1568 <name>NSEG2</name> 1569 <description>The time segment after the sample point in Abritration Phase.</description> 1570 <bitOffset>18</bitOffset> 1571 <bitWidth>7</bitWidth> 1572 </field> 1573 <field> 1574 <name>NSJW</name> 1575 <description>Synchronization Jump Width in Arbitration Phase.</description> 1576 <bitOffset>25</bitOffset> 1577 <bitWidth>7</bitWidth> 1578 </field> 1579 </fields> 1580 </register> 1581 <register> 1582 <name>DBT_SSPP</name> 1583 <description>Data Bit Timing Register.</description> 1584 <addressOffset>0x0020</addressOffset> 1585 <access>read-write</access> 1586 <fields> 1587 <field> 1588 <name>DBRP</name> 1589 <description>Baudrate Prescaler in Data Phase.</description> 1590 <bitOffset>0</bitOffset> 1591 <bitWidth>10</bitWidth> 1592 </field> 1593 <field> 1594 <name>DSEG1</name> 1595 <description>The time segment before the sample point in Data Phase.</description> 1596 <bitOffset>10</bitOffset> 1597 <bitWidth>6</bitWidth> 1598 </field> 1599 <field> 1600 <name>DSEG2</name> 1601 <description>The time segment before the sample point in Data Phase.</description> 1602 <bitOffset>16</bitOffset> 1603 <bitWidth>4</bitWidth> 1604 </field> 1605 <field> 1606 <name>DSJW</name> 1607 <description>Synchronization Jump Width in Data Phase</description> 1608 <bitOffset>20</bitOffset> 1609 <bitWidth>4</bitWidth> 1610 </field> 1611 <field> 1612 <name>SSPP</name> 1613 <description>Position of the secondary sample point.</description> 1614 <bitOffset>24</bitOffset> 1615 <bitWidth>7</bitWidth> 1616 </field> 1617 </fields> 1618 </register> 1619 <register> 1620 <name>FDCTRL</name> 1621 <description>FD Control Register.</description> 1622 <addressOffset>0x0024</addressOffset> 1623 <size>8</size> 1624 <access>read-write</access> 1625 <fields> 1626 <field> 1627 <name>FDEN</name> 1628 <description>FD Frame format/ Extended data length. This bit indicates CAN FD frame format.</description> 1629 <bitOffset>0</bitOffset> 1630 <bitWidth>1</bitWidth> 1631 <enumeratedValues> 1632 <enumeratedValue> 1633 <name>fd</name> 1634 <description>CAN FD Frame Format</description> 1635 <value>1</value> 1636 </enumeratedValue> 1637 <enumeratedValue> 1638 <name>classic</name> 1639 <description>Classic CAN Frame Format.</description> 1640 <value>0</value> 1641 </enumeratedValue> 1642 </enumeratedValues> 1643 </field> 1644 <field> 1645 <name>BRSEN</name> 1646 <description>This bit indicates whether the bit rate is switched in Data phase.</description> 1647 <bitOffset>1</bitOffset> 1648 <bitWidth>1</bitWidth> 1649 <enumeratedValues> 1650 <enumeratedValue> 1651 <name>NOSW</name> 1652 <description>Bit rate is not switced inside of CAN FD frame.</description> 1653 <value>0</value> 1654 </enumeratedValue> 1655 <enumeratedValue> 1656 <name>SW</name> 1657 <description>Bit rate is switched from nominal bit rate of the arbitration phase to alternate bit rate of data phase.</description> 1658 <value>1</value> 1659 </enumeratedValue> 1660 </enumeratedValues> 1661 </field> 1662 <field> 1663 <name>EXTBT</name> 1664 <description>This bit configure the Bit Time prescaler in Arbitration phase.</description> 1665 <bitOffset>2</bitOffset> 1666 <bitWidth>1</bitWidth> 1667 <enumeratedValues> 1668 <enumeratedValue> 1669 <name>BT</name> 1670 <description>Use contents of BT register to configure bit time in arbitration phase.</description> 1671 <value>0</value> 1672 </enumeratedValue> 1673 <enumeratedValue> 1674 <name>NBT</name> 1675 <description>Use contents of NBT register to configure bit time in arbitration phase.</description> 1676 <value>1</value> 1677 </enumeratedValue> 1678 </enumeratedValues> 1679 </field> 1680 <field> 1681 <name>ISO</name> 1682 <description>ISO CAN FD Format Selection.</description> 1683 <bitOffset>3</bitOffset> 1684 <bitWidth>1</bitWidth> 1685 <enumeratedValues> 1686 <enumeratedValue> 1687 <name>BOSCH</name> 1688 <description>Frame format according to Bosch CAN FD specification.</description> 1689 <value>0</value> 1690 </enumeratedValue> 1691 <enumeratedValue> 1692 <name>ISO</name> 1693 <description>Frame format according to ISO 11898 1, 2015.</description> 1694 <value>1</value> 1695 </enumeratedValue> 1696 </enumeratedValues> 1697 </field> 1698 <field> 1699 <name>DAR</name> 1700 <description>Disable Auto Retransmission</description> 1701 <bitOffset>4</bitOffset> 1702 <bitWidth>1</bitWidth> 1703 <enumeratedValues> 1704 <enumeratedValue> 1705 <name>EN</name> 1706 <description>Automatic retransmission enabled.</description> 1707 <value>0</value> 1708 </enumeratedValue> 1709 <enumeratedValue> 1710 <name>DIS</name> 1711 <description>Automatic retransmission disabled.</description> 1712 <value>1</value> 1713 </enumeratedValue> 1714 </enumeratedValues> 1715 </field> 1716 <field> 1717 <name>REOM</name> 1718 <description>Restricted Operation Mode.</description> 1719 <bitOffset>5</bitOffset> 1720 <bitWidth>1</bitWidth> 1721 </field> 1722 <field> 1723 <name>PED</name> 1724 <description>Protocol Exception Disable.</description> 1725 <bitOffset>6</bitOffset> 1726 <bitWidth>1</bitWidth> 1727 </field> 1728 </fields> 1729 </register> 1730 <register> 1731 <name>FDSTAT</name> 1732 <description>Invalidate All Registers.</description> 1733 <addressOffset>0x0025</addressOffset> 1734 <size>8</size> 1735 <access>read-only</access> 1736 <fields> 1737 <field> 1738 <name>BITERR</name> 1739 <description>Bit Error Indicator. When this bit is set the inconsistency occurs between the transmitted and the received bit in CAN FD frame.</description> 1740 <bitOffset>0</bitOffset> 1741 <bitWidth>1</bitWidth> 1742 </field> 1743 <field> 1744 <name>CRCERR</name> 1745 <description>Cyclic Redundancy Check Error indicator. This indicates that calculated CRC is different from received in CAN FD frame</description> 1746 <bitOffset>1</bitOffset> 1747 <bitWidth>1</bitWidth> 1748 </field> 1749 <field> 1750 <name>FRMERR</name> 1751 <description>Form Error indicator. This bit indicates, that a fixed form bit field contains at least one illegal bit in Data phase of CAN FD frame with the BRS 1752bit set</description> 1753 <bitOffset>2</bitOffset> 1754 <bitWidth>1</bitWidth> 1755 </field> 1756 <field> 1757 <name>STFERR</name> 1758 <description>Stuff Error Indicator. This bit indicates stuff error occurred in Data phase in CAN FD frame with the BRS bit set 1759</description> 1760 <bitOffset>3</bitOffset> 1761 <bitWidth>1</bitWidth> 1762 </field> 1763 <field> 1764 <name>PEE</name> 1765 <description>Protocol Exception Event indicator. Indicates that core detects recessive state on res position and enter to Bus integration state.</description> 1766 <bitOffset>4</bitOffset> 1767 <bitWidth>1</bitWidth> 1768 </field> 1769 <field> 1770 <name>STATE</name> 1771 <description>Operation state.</description> 1772 <bitOffset>6</bitOffset> 1773 <bitWidth>2</bitWidth> 1774 <enumeratedValues> 1775 <enumeratedValue> 1776 <name>INT</name> 1777 <description>Waiting for 11 recessive bit after reset or bus off</description> 1778 <value>0</value> 1779 </enumeratedValue> 1780 <enumeratedValue> 1781 <name>IDLE</name> 1782 <description>Waiting for Start of Frame.</description> 1783 <value>1</value> 1784 </enumeratedValue> 1785 <enumeratedValue> 1786 <name>RX</name> 1787 <description>Node operating as Receiver.</description> 1788 <value>2</value> 1789 </enumeratedValue> 1790 <enumeratedValue> 1791 <name>TX</name> 1792 <description>Node operating as Transmitter.</description> 1793 <value>3</value> 1794 </enumeratedValue> 1795 </enumeratedValues> 1796 </field> 1797 </fields> 1798 </register> 1799 <register> 1800 <name>DPERR</name> 1801 <description>Data Phase Error Counter Register.</description> 1802 <addressOffset>0x0026</addressOffset> 1803 <size>8</size> 1804 <access>read-only</access> 1805 <fields> 1806 <field> 1807 <name>DPERR</name> 1808 <description>Data Phase Error Counter.</description> 1809 <bitOffset>0</bitOffset> 1810 <bitWidth>8</bitWidth> 1811 </field> 1812 </fields> 1813 </register> 1814 <register> 1815 <name>APERR</name> 1816 <description>Arbitration Phase Error Counter Register.</description> 1817 <addressOffset>0x0027</addressOffset> 1818 <size>8</size> 1819 <access>read-only</access> 1820 <fields> 1821 <field> 1822 <name>APERR</name> 1823 <description>Arbitration Error Counter.</description> 1824 <bitOffset>0</bitOffset> 1825 <bitWidth>8</bitWidth> 1826 </field> 1827 </fields> 1828 </register> 1829 <register> 1830 <name>TEST</name> 1831 <description>Invalidate All Registers.</description> 1832 <addressOffset>0x0028</addressOffset> 1833 <size>8</size> 1834 <access>read-write</access> 1835 <fields> 1836 <field> 1837 <name>LBEN</name> 1838 <description>Loopback mode.</description> 1839 <bitOffset>0</bitOffset> 1840 <bitWidth>1</bitWidth> 1841 </field> 1842 <field> 1843 <name>TXC</name> 1844 <description>Transmitted frame.</description> 1845 <bitOffset>1</bitOffset> 1846 <bitWidth>1</bitWidth> 1847 </field> 1848 </fields> 1849 </register> 1850 <register> 1851 <name>WUPCLKDIV</name> 1852 <description>Wake-up timer prescaler.</description> 1853 <addressOffset>0x0029</addressOffset> 1854 <size>8</size> 1855 <access>read-write</access> 1856 <fields> 1857 <field> 1858 <name>WUPDIV</name> 1859 <description>Wake-up timer prescaler.</description> 1860 <bitOffset>0</bitOffset> 1861 <bitWidth>8</bitWidth> 1862 </field> 1863 </fields> 1864 </register> 1865 <register> 1866 <name>WUPFT</name> 1867 <description>Wake up Filter Time Register.</description> 1868 <addressOffset>0x002A</addressOffset> 1869 <size>16</size> 1870 <access>read-write</access> 1871 <fields> 1872 <field> 1873 <name>WUPFT</name> 1874 <description>Wake-up pattern filter time.</description> 1875 <bitOffset>0</bitOffset> 1876 <bitWidth>16</bitWidth> 1877 </field> 1878 </fields> 1879 </register> 1880 <register> 1881 <name>WUPET</name> 1882 <description>Wake-up Expire Time Register.</description> 1883 <addressOffset>0x002C</addressOffset> 1884 <access>read-write</access> 1885 <fields> 1886 <field> 1887 <name>WUPET</name> 1888 <description>Wake up patter expire time.</description> 1889 <bitOffset>0</bitOffset> 1890 <bitWidth>20</bitWidth> 1891 </field> 1892 </fields> 1893 </register> 1894 <register> 1895 <name>RXDCNT</name> 1896 <description>RX FIFO Data Counter Register.</description> 1897 <addressOffset>0x0030</addressOffset> 1898 <size>16</size> 1899 <access>read-write</access> 1900 <fields> 1901 <field> 1902 <name>RXDCNT</name> 1903 <description>RX FIFO data counter.</description> 1904 <bitOffset>0</bitOffset> 1905 <bitWidth>16</bitWidth> 1906 </field> 1907 </fields> 1908 </register> 1909 <register> 1910 <name>TXSCNT</name> 1911 <description>TX FIFO Space Counter.</description> 1912 <addressOffset>0x0032</addressOffset> 1913 <size>8</size> 1914 <access>read-write</access> 1915 <fields> 1916 <field> 1917 <name>TXSCNT</name> 1918 <description>TX FIFO Space Counter.</description> 1919 <bitOffset>0</bitOffset> 1920 <bitWidth>8</bitWidth> 1921 </field> 1922 </fields> 1923 </register> 1924 <register> 1925 <name>TXDECMP</name> 1926 <description>Invalidate All Registers.</description> 1927 <addressOffset>0x0033</addressOffset> 1928 <size>8</size> 1929 <access>read-write</access> 1930 <fields> 1931 <field> 1932 <name>TDCO</name> 1933 <description>Transceiver Delay Compensation Offset. This bit field contains the offset value added to the measured transceiver loop delay</description> 1934 <bitOffset>0</bitOffset> 1935 <bitWidth>7</bitWidth> 1936 </field> 1937 <field> 1938 <name>TDCEN</name> 1939 <description>Transceiver Delay Compensation Enable.</description> 1940 <bitOffset>7</bitOffset> 1941 <bitWidth>1</bitWidth> 1942 </field> 1943 </fields> 1944 </register> 1945 <register> 1946 <name>EINTFL</name> 1947 <description>Extended Interrupt Flag Register.</description> 1948 <addressOffset>0x0034</addressOffset> 1949 <size>8</size> 1950 <access>read-write</access> 1951 <fields> 1952 <field> 1953 <name>RX_THD</name> 1954 <description>RX FIFO reach programmed trigger level, it is set when the RX FIFO reaches programmed trigger level (RT[2:0] in MR register). To clear the 1955RXFT interrupt, write this bit 1</description> 1956 <bitOffset>0</bitOffset> 1957 <bitWidth>1</bitWidth> 1958 </field> 1959 <field> 1960 <name>RX_TO</name> 1961 <description>RX FIFO Timeout Indicator. It is set when there is no write or read from/in to RX FIFO for the user defined time (RXFTO register) and there is at 1962least 1 entry in RX FIFO during this time, this bit is clear by write 1</description> 1963 <bitOffset>1</bitOffset> 1964 <bitWidth>1</bitWidth> 1965 </field> 1966 </fields> 1967 </register> 1968 <register> 1969 <name>EINTEN</name> 1970 <description>Extended Interrupt Enable Register.</description> 1971 <addressOffset>0x0035</addressOffset> 1972 <size>8</size> 1973 <access>read-write</access> 1974 <fields> 1975 <field> 1976 <name>RX_THD</name> 1977 <description>RX FIFO reach programmed trigger level, it is set when the RX FIFO reaches programmed trigger level (RT[2:0] in MR register). To clear the 1978RXFT interrupt, write this bit 1</description> 1979 <bitOffset>0</bitOffset> 1980 <bitWidth>1</bitWidth> 1981 </field> 1982 <field> 1983 <name>RX_TO</name> 1984 <description>RX FIFO Timeout Indicator. It is set when there is no write or read from/in to RX FIFO for the user defined time (RXFTO register) and there is at 1985least 1 entry in RX FIFO during this time, this bit is clear by write 1</description> 1986 <bitOffset>1</bitOffset> 1987 <bitWidth>1</bitWidth> 1988 </field> 1989 </fields> 1990 </register> 1991 <register> 1992 <name>RXTO</name> 1993 <description>RX FIFO Timeout Register.</description> 1994 <addressOffset>0x0036</addressOffset> 1995 <size>16</size> 1996 <access>read-write</access> 1997 <fields> 1998 <field> 1999 <name>RX_TO</name> 2000 <description>RX FIFO Timeout</description> 2001 <bitOffset>0</bitOffset> 2002 <bitWidth>16</bitWidth> 2003 </field> 2004 </fields> 2005 </register> 2006 </registers> 2007 </peripheral> 2008<!--CAN0 Controller Area Network Registers--> 2009 <peripheral derivedFrom="CAN0"> 2010 <name>CAN1</name> 2011 <description>Controller Area Network Registers 1</description> 2012 <baseAddress>0x40065000</baseAddress> 2013 </peripheral> 2014<!--CAN1 Controller Area Network Registers 1--> 2015 <peripheral derivedFrom="CAN0"> 2016 <name>CAN2</name> 2017 <description>Controller Area Network Registers 2</description> 2018 <baseAddress /> 2019 </peripheral> 2020<!--CAN2 Controller Area Network Registers 2--> 2021 <peripheral> 2022 <name>CTB</name> 2023 <description>The Cryptographic Toolbox is a combination of cryptographic engines and a secure cryptographic accelerator (SCA) used to provide advanced cryptographic security.</description> 2024 <baseAddress>0x40001000</baseAddress> 2025 <addressBlock> 2026 <offset>0x00</offset> 2027 <size>0x1000</size> 2028 <usage>registers</usage> 2029 </addressBlock> 2030 <interrupt> 2031 <name>Crypto_Engine</name> 2032 <description>Crypto Engine interrupt.</description> 2033 <value>27</value> 2034 </interrupt> 2035 <registers> 2036 <register> 2037 <name>CTRL</name> 2038 <description>Crypto Control Register.</description> 2039 <addressOffset>0x00</addressOffset> 2040 <resetValue>0xC0000000</resetValue> 2041 <fields> 2042 <field> 2043 <name>RST</name> 2044 <description>Reset. This bit is used to reset the crypto accelerator. All crypto internal states and related registers are reset to their default reset values. Control register such as CRYPTO_CTRL, CIPHER_CTRL, HASH_CTRL, CRC_CTRL, MAA_CTRL (with the exception of the STC bit), HASH_MSG_SZ_[3:0] and MAA_MAWS will retain their values. This bit will automatically clear itself after one cycle.</description> 2045 <bitOffset>0</bitOffset> 2046 <bitWidth>1</bitWidth> 2047 <enumeratedValues> 2048 <name>reset_write</name> 2049 <usage>write</usage> 2050 <enumeratedValue> 2051 <name>reset</name> 2052 <description>Starts reset operation.</description> 2053 <value>1</value> 2054 </enumeratedValue> 2055 </enumeratedValues> 2056 <enumeratedValues> 2057 <name>reset_read</name> 2058 <usage>read</usage> 2059 <enumeratedValue> 2060 <name>reset_done</name> 2061 <description>Reset complete.</description> 2062 <value>0</value> 2063 </enumeratedValue> 2064 <enumeratedValue> 2065 <name>busy</name> 2066 <description>Reset in progress.</description> 2067 <value>1</value> 2068 </enumeratedValue> 2069 </enumeratedValues> 2070 </field> 2071 <field> 2072 <name>INTR</name> 2073 <description>Interrupt Enable. Generates an interrupt when done or error set.</description> 2074 <bitOffset>1</bitOffset> 2075 <bitWidth>1</bitWidth> 2076 <enumeratedValues> 2077 <enumeratedValue> 2078 <name>dis</name> 2079 <description>Disable</description> 2080 <value>0</value> 2081 </enumeratedValue> 2082 <enumeratedValue> 2083 <name>en</name> 2084 <description>Enable</description> 2085 <value>1</value> 2086 </enumeratedValue> 2087 </enumeratedValues> 2088 </field> 2089 <field> 2090 <name>SRC</name> 2091 <description>Source Select. This bit selects the hash function and CRC generator input source.</description> 2092 <bitOffset>2</bitOffset> 2093 <bitWidth>1</bitWidth> 2094 <enumeratedValues> 2095 <enumeratedValue> 2096 <name>inputFIFO</name> 2097 <description>Input FIFO</description> 2098 <value>0</value> 2099 </enumeratedValue> 2100 <enumeratedValue> 2101 <name>outputFIFO</name> 2102 <description>Output FIFO</description> 2103 <value>1</value> 2104 </enumeratedValue> 2105 </enumeratedValues> 2106 </field> 2107 <field derivedFrom="INTR"> 2108 <name>BSO</name> 2109 <description>Byte Swap Output. Note. No byte swap will occur if there is not a full word.</description> 2110 <bitOffset>4</bitOffset> 2111 <bitWidth>1</bitWidth> 2112 </field> 2113 <field derivedFrom="INTR"> 2114 <name>BSI</name> 2115 <description>Byte Swap Input. Note. No byte swap will occur if there is not a full word.</description> 2116 <bitOffset>5</bitOffset> 2117 <bitWidth>1</bitWidth> 2118 </field> 2119 <field derivedFrom="INTR"> 2120 <name>WAIT_EN</name> 2121 <description>Wait Pin Enable. This can be used to hold off the crypto DMA until an external memory is ready. This is useful for transferring pages from NAND flash which may take several microseconds to become ready.</description> 2122 <bitOffset>6</bitOffset> 2123 <bitWidth>1</bitWidth> 2124 </field> 2125 <field> 2126 <name>WAIT_POL</name> 2127 <description>Wait Pin Polarity. When the wait pin is enabled, this bit selects its active state.</description> 2128 <bitOffset>7</bitOffset> 2129 <bitWidth>1</bitWidth> 2130 <enumeratedValues> 2131 <enumeratedValue> 2132 <name>activeLo</name> 2133 <description>Active Low.</description> 2134 <value>0</value> 2135 </enumeratedValue> 2136 <enumeratedValue> 2137 <name>activeHi</name> 2138 <description>Active High.</description> 2139 <value>1</value> 2140 </enumeratedValue> 2141 </enumeratedValues> 2142 </field> 2143 <field> 2144 <name>WRSRC</name> 2145 <description>Write FIFO Source Select. This field determines where data written to the write FIFO comes from. When data is written to the write FIFO, it is always written out the DMA. To decrypt or encrypt data, the write FIFO source should be set to the cipher output. To implement memcpy() or memset() functions, or to fill memory with random data, the write FIFO source should be set to the read FIFO. When calculating a HASH or CMAC, the write FIFO should be disabled.</description> 2146 <bitOffset>8</bitOffset> 2147 <bitWidth>2</bitWidth> 2148 <enumeratedValues> 2149 <enumeratedValue> 2150 <name>none</name> 2151 <description>None.</description> 2152 <value>0</value> 2153 </enumeratedValue> 2154 <enumeratedValue> 2155 <name>cipherOutput</name> 2156 <description>Cipher Output.</description> 2157 <value>1</value> 2158 </enumeratedValue> 2159 <enumeratedValue> 2160 <name>readFIFO</name> 2161 <description>Read FIFO.</description> 2162 <value>2</value> 2163 </enumeratedValue> 2164 </enumeratedValues> 2165 </field> 2166 <field> 2167 <name>RDSRC</name> 2168 <description>Read FIFO Source Select. This field selects the source of the read FIFO. Typically, it is set to use the DMA. To implement a memset() function, the read FIFO DMA should be disabled. To fill memory with random data or to hash random numbers, the read FIFO source should be set to the random number generator.</description> 2169 <bitOffset>10</bitOffset> 2170 <bitWidth>2</bitWidth> 2171 <enumeratedValues> 2172 <enumeratedValue> 2173 <name>dmaDisabled</name> 2174 <description>DMA Disable.</description> 2175 <value>0</value> 2176 </enumeratedValue> 2177 <enumeratedValue> 2178 <name>dmaOrApb</name> 2179 <description>DMA Or APB.</description> 2180 <value>1</value> 2181 </enumeratedValue> 2182 <enumeratedValue> 2183 <name>rng</name> 2184 <description>RNG.</description> 2185 <value>2</value> 2186 </enumeratedValue> 2187 </enumeratedValues> 2188 </field> 2189 <field> 2190 <name>FLAG_MODE</name> 2191 <description>Done Flag Mode. This bit configures the access behavior of the individual CRYPTO_CTRL Done flags (CRYPTO_CTRL[27:24]). This bit is cleared only on reset to limit upkeep, i.e. once set, it will remain set until a reset occurs.</description> 2192 <bitOffset>14</bitOffset> 2193 <bitWidth>1</bitWidth> 2194 <enumeratedValues> 2195 <enumeratedValue> 2196 <name>unres_wr</name> 2197 <description>Unrestricted write (0 or 1) of CRYPTO_CTRL[27:24] flags.</description> 2198 <value>0</value> 2199 </enumeratedValue> 2200 <enumeratedValue> 2201 <name>res_wr</name> 2202 <description>Access to CRYPTO_CTRL[27:24] are write 1 to clear/write 0 no effect.</description> 2203 <value>1</value> 2204 </enumeratedValue> 2205 </enumeratedValues> 2206 </field> 2207 <field> 2208 <name>DMADNEMSK</name> 2209 <description>DMA Done Flag Mask. This bit masks the DMA_DONE flag from being used to generate the CRYPTO_CTRL.DONE flag, and this disables a DMA_DONE condition from generating and interrupt. The DMA_DONE flag itself is unaffected and still may be monitored. This allows more optimal interrupt-driven crypto operations using DMA.</description> 2210 <bitOffset>15</bitOffset> 2211 <bitWidth>1</bitWidth> 2212 <enumeratedValues> 2213 <enumeratedValue> 2214 <name>not_used</name> 2215 <description>DMA_DONE not used in setting CRYPTO_CTRL.DONE bit.</description> 2216 <value>0</value> 2217 </enumeratedValue> 2218 <enumeratedValue> 2219 <name>used</name> 2220 <description>DMA_DONE used in setting CRYPTO_CTRL.DONE bit.</description> 2221 <value>1</value> 2222 </enumeratedValue> 2223 </enumeratedValues> 2224 </field> 2225 <field> 2226 <name>DMA_DONE</name> 2227 <description>DMA Done. DMA write/read operation is complete. This bit must be cleared before starting a DMA operation.</description> 2228 <bitOffset>24</bitOffset> 2229 <bitWidth>1</bitWidth> 2230 <enumeratedValues> 2231 <enumeratedValue> 2232 <name>notDone</name> 2233 <description>Not Done.</description> 2234 <value>0</value> 2235 </enumeratedValue> 2236 <enumeratedValue> 2237 <name>done</name> 2238 <description>Done.</description> 2239 <value>1</value> 2240 </enumeratedValue> 2241 </enumeratedValues> 2242 </field> 2243 <field derivedFrom="DMA_DONE"> 2244 <name>GLS_DONE</name> 2245 <description>Galois Done. FIFO is full and CRC or Hamming Code Generator is enabled. This bit must be cleared before starting a CRC operation Note that DMA_DONE must be polled instead of this bit to determine the end of DMA operation during the utilization of Hamming Code Generator.</description> 2246 <bitOffset>25</bitOffset> 2247 <bitWidth>1</bitWidth> 2248 </field> 2249 <field derivedFrom="DMA_DONE"> 2250 <name>HSH_DONE</name> 2251 <description>Hash Done. SHA operation is complete. This bit must be cleared before starting a HASH operation.</description> 2252 <bitOffset>26</bitOffset> 2253 <bitWidth>1</bitWidth> 2254 </field> 2255 <field derivedFrom="DMA_DONE"> 2256 <name>CPH_DONE</name> 2257 <description>Cipher Done. Either AES or DES encryption/decryption operation is complete. This bit must be cleared before starting a cipher operation.</description> 2258 <bitOffset>27</bitOffset> 2259 <bitWidth>1</bitWidth> 2260 </field> 2261 <field> 2262 <name>ERR</name> 2263 <description>AHB Bus Error. This bit is set when the DMA encounters a bus error during a read or write operation. Once this bit is set, the DMA will stop. This bit can only be cleared by resetting the crypto block.</description> 2264 <bitOffset>29</bitOffset> 2265 <bitWidth>1</bitWidth> 2266 <access>read-only</access> 2267 <enumeratedValues> 2268 <enumeratedValue> 2269 <name>noError</name> 2270 <description>No Error.</description> 2271 <value>0</value> 2272 </enumeratedValue> 2273 <enumeratedValue> 2274 <name>error</name> 2275 <description>Error.</description> 2276 <value>1</value> 2277 </enumeratedValue> 2278 </enumeratedValues> 2279 </field> 2280 <field> 2281 <name>RDY</name> 2282 <description>Ready. Crypto block ready for more data.</description> 2283 <bitOffset>30</bitOffset> 2284 <bitWidth>1</bitWidth> 2285 <access>read-only</access> 2286 <enumeratedValues> 2287 <enumeratedValue> 2288 <name>busy</name> 2289 <description>Busy.</description> 2290 <value>0</value> 2291 </enumeratedValue> 2292 <enumeratedValue> 2293 <name>ready</name> 2294 <description>Ready.</description> 2295 <value>1</value> 2296 </enumeratedValue> 2297 </enumeratedValues> 2298 </field> 2299 <field derivedFrom="DMA_DONE"> 2300 <name>DONE</name> 2301 <description>Done. One or more cryptographic calculations complete (logical OR of done flags).</description> 2302 <bitOffset>31</bitOffset> 2303 <bitWidth>1</bitWidth> 2304 <access>read-only</access> 2305 </field> 2306 </fields> 2307 </register> 2308 <register> 2309 <name>CIPHER_CTRL</name> 2310 <description>Cipher Control Register.</description> 2311 <addressOffset>0x04</addressOffset> 2312 <fields> 2313 <field> 2314 <name>ENC</name> 2315 <description>Encrypt. Select encryption or decryption of input data.</description> 2316 <bitOffset>0</bitOffset> 2317 <bitWidth>1</bitWidth> 2318 <enumeratedValues> 2319 <enumeratedValue> 2320 <name>ENCRYPT</name> 2321 <description>Encrypt.</description> 2322 <value>0</value> 2323 </enumeratedValue> 2324 <enumeratedValue> 2325 <name>DECRYPT</name> 2326 <description>Decrypt.</description> 2327 <value>1</value> 2328 </enumeratedValue> 2329 </enumeratedValues> 2330 </field> 2331 <field> 2332 <name>KEY</name> 2333 <description>Load Key from crypto DMA. This bit is automatically cleared by hardware after the DMA has completed loading the key. When the DMA operation is done, it sets the appropriate crypto DMA Done flag.</description> 2334 <bitOffset>1</bitOffset> 2335 <bitWidth>1</bitWidth> 2336 <enumeratedValues> 2337 <enumeratedValue> 2338 <name>complete</name> 2339 <description>No operation/complete.</description> 2340 <value>0</value> 2341 </enumeratedValue> 2342 <enumeratedValue> 2343 <name>start</name> 2344 <description>Start operation.</description> 2345 <value>1</value> 2346 </enumeratedValue> 2347 </enumeratedValues> 2348 </field> 2349 <field> 2350 <name>SRC</name> 2351 <description>Source of Random key.</description> 2352 <bitOffset>2</bitOffset> 2353 <bitWidth>2</bitWidth> 2354 <enumeratedValues> 2355 <enumeratedValue> 2356 <name>cipherKey</name> 2357 <description>User cipher key (0x4000_1060).</description> 2358 <value>0</value> 2359 </enumeratedValue> 2360 <enumeratedValue> 2361 <name>regFile</name> 2362 <description>Key from battery-backed register file (0x4000_5000 to 0x4000_501F).</description> 2363 <value>2</value> 2364 </enumeratedValue> 2365 <enumeratedValue> 2366 <name>qspiKey_regFile</name> 2367 <description>Key from battery-backed register file (0x4000_5020 to 0x4000_502F).</description> 2368 <value>3</value> 2369 </enumeratedValue> 2370 </enumeratedValues> 2371 </field> 2372 <field> 2373 <name>CIPHER</name> 2374 <description>Cipher Operation Select. Symmetric Block Cipher algorithm selection or memory operation.</description> 2375 <bitOffset>4</bitOffset> 2376 <bitWidth>3</bitWidth> 2377 <enumeratedValues> 2378 <enumeratedValue> 2379 <name>dis</name> 2380 <description>Disabled.</description> 2381 <value>0</value> 2382 </enumeratedValue> 2383 <enumeratedValue> 2384 <name>aes128</name> 2385 <description>AES 128.</description> 2386 <value>1</value> 2387 </enumeratedValue> 2388 <enumeratedValue> 2389 <name>aes192</name> 2390 <description>AES 192.</description> 2391 <value>2</value> 2392 </enumeratedValue> 2393 <enumeratedValue> 2394 <name>aes256</name> 2395 <description>AES 256.</description> 2396 <value>3</value> 2397 </enumeratedValue> 2398 <enumeratedValue> 2399 <name>des</name> 2400 <description>DES.</description> 2401 <value>4</value> 2402 </enumeratedValue> 2403 <enumeratedValue> 2404 <name>tdes</name> 2405 <description>Triple DES.</description> 2406 <value>5</value> 2407 </enumeratedValue> 2408 </enumeratedValues> 2409 </field> 2410 <field> 2411 <name>MODE</name> 2412 <description>Mode Select. Mode of operation for block cipher or memory operation. DES/TDES cannot be used in CFB, OFB or CTR modes.</description> 2413 <bitOffset>8</bitOffset> 2414 <bitWidth>3</bitWidth> 2415 <enumeratedValues> 2416 <enumeratedValue> 2417 <name>ECB</name> 2418 <description>ECB Mode.</description> 2419 <value>0</value> 2420 </enumeratedValue> 2421 <enumeratedValue> 2422 <name>CBC</name> 2423 <description>CBC Mode.</description> 2424 <value>1</value> 2425 </enumeratedValue> 2426 <enumeratedValue> 2427 <name>CFB</name> 2428 <description>CFB (AES only).</description> 2429 <value>2</value> 2430 </enumeratedValue> 2431 <enumeratedValue> 2432 <name>OFB</name> 2433 <description>OFB (AES only).</description> 2434 <value>3</value> 2435 </enumeratedValue> 2436 <enumeratedValue> 2437 <name>CTR</name> 2438 <description>CTR (AES only).</description> 2439 <value>4</value> 2440 </enumeratedValue> 2441 <enumeratedValue> 2442 <name>GCM</name> 2443 <description>GCM.</description> 2444 <value>5</value> 2445 </enumeratedValue> 2446 <enumeratedValue> 2447 <name>CCM</name> 2448 <description>CCM.</description> 2449 <value>6</value> 2450 </enumeratedValue> 2451 </enumeratedValues> 2452 </field> 2453 <field> 2454 <name>HVC</name> 2455 <description>H Vector Computation.</description> 2456 <bitOffset>11</bitOffset> 2457 <bitWidth>1</bitWidth> 2458 <access>read-only</access> 2459 </field> 2460 <field> 2461 <name>DTYPE</name> 2462 <description>GCM/CCM data type.</description> 2463 <bitOffset>12</bitOffset> 2464 <bitWidth>1</bitWidth> 2465 <access>read-only</access> 2466 <enumeratedValues> 2467 <enumeratedValue> 2468 <name>AAD</name> 2469 <description>AAD.</description> 2470 <value>0</value> 2471 </enumeratedValue> 2472 <enumeratedValue> 2473 <name>PLD</name> 2474 <description>PLD.</description> 2475 <value>1</value> 2476 </enumeratedValue> 2477 </enumeratedValues> 2478 </field> 2479 <field> 2480 <name>CCMM</name> 2481 <description>CCM M Parameter.</description> 2482 <bitOffset>13</bitOffset> 2483 <bitWidth>3</bitWidth> 2484 <access>read-only</access> 2485 <enumeratedValues> 2486 <enumeratedValue> 2487 <name>4</name> 2488 <description>4</description> 2489 <value>1</value> 2490 </enumeratedValue> 2491 <enumeratedValue> 2492 <name>6</name> 2493 <description>6</description> 2494 <value>2</value> 2495 </enumeratedValue> 2496 <enumeratedValue> 2497 <name>8</name> 2498 <description>8</description> 2499 <value>3</value> 2500 </enumeratedValue> 2501 <enumeratedValue> 2502 <name>10</name> 2503 <description>10</description> 2504 <value>4</value> 2505 </enumeratedValue> 2506 <enumeratedValue> 2507 <name>12</name> 2508 <description>12</description> 2509 <value>5</value> 2510 </enumeratedValue> 2511 <enumeratedValue> 2512 <name>14</name> 2513 <description>14</description> 2514 <value>6</value> 2515 </enumeratedValue> 2516 <enumeratedValue> 2517 <name>16</name> 2518 <description>16</description> 2519 <value>7</value> 2520 </enumeratedValue> 2521 </enumeratedValues> 2522 </field> 2523 <field> 2524 <name>CCML</name> 2525 <description>CCM L Parameter.</description> 2526 <bitOffset>16</bitOffset> 2527 <bitWidth>3</bitWidth> 2528 <access>read-only</access> 2529 <enumeratedValues> 2530 <enumeratedValue> 2531 <name>2</name> 2532 <description>2</description> 2533 <value>1</value> 2534 </enumeratedValue> 2535 <enumeratedValue> 2536 <name>3</name> 2537 <description>3</description> 2538 <value>2</value> 2539 </enumeratedValue> 2540 <enumeratedValue> 2541 <name>4</name> 2542 <description>4</description> 2543 <value>3</value> 2544 </enumeratedValue> 2545 <enumeratedValue> 2546 <name>5</name> 2547 <description>5</description> 2548 <value>4</value> 2549 </enumeratedValue> 2550 <enumeratedValue> 2551 <name>6</name> 2552 <description>6</description> 2553 <value>5</value> 2554 </enumeratedValue> 2555 <enumeratedValue> 2556 <name>7</name> 2557 <description>7</description> 2558 <value>6</value> 2559 </enumeratedValue> 2560 <enumeratedValue> 2561 <name>8</name> 2562 <description>8</description> 2563 <value>7</value> 2564 </enumeratedValue> 2565 </enumeratedValues> 2566 </field> 2567 </fields> 2568 </register> 2569 <register> 2570 <name>HASH_CTRL</name> 2571 <description>HASH Control Register.</description> 2572 <addressOffset>0x08</addressOffset> 2573 <fields> 2574 <field> 2575 <name>INIT</name> 2576 <description>Initialize. Initializes hash registers with standard constants.</description> 2577 <bitOffset>0</bitOffset> 2578 <bitWidth>1</bitWidth> 2579 <enumeratedValues> 2580 <enumeratedValue> 2581 <name>nop</name> 2582 <description>No operation/complete.</description> 2583 <value>0</value> 2584 </enumeratedValue> 2585 <enumeratedValue> 2586 <name>start</name> 2587 <description>Start operation.</description> 2588 <value>1</value> 2589 </enumeratedValue> 2590 </enumeratedValues> 2591 </field> 2592 <field> 2593 <name>XOR</name> 2594 <description>XOR data with IV from cipher block. Useful when calculating HMAC to XOR the input pad and output pad.</description> 2595 <bitOffset>1</bitOffset> 2596 <bitWidth>1</bitWidth> 2597 <enumeratedValues> 2598 <enumeratedValue> 2599 <name>dis</name> 2600 <description>Disable.</description> 2601 <value>0</value> 2602 </enumeratedValue> 2603 <enumeratedValue> 2604 <name>en</name> 2605 <description>Enable.</description> 2606 <value>1</value> 2607 </enumeratedValue> 2608 </enumeratedValues> 2609 </field> 2610 <field> 2611 <name>HASH</name> 2612 <description>Hash function selection.</description> 2613 <bitOffset>2</bitOffset> 2614 <bitWidth>3</bitWidth> 2615 <enumeratedValues> 2616 <enumeratedValue> 2617 <name>dis</name> 2618 <description>Disabled.</description> 2619 <value>0</value> 2620 </enumeratedValue> 2621 <enumeratedValue> 2622 <name>sha1</name> 2623 <description>SHA-1.</description> 2624 <value>1</value> 2625 </enumeratedValue> 2626 <enumeratedValue> 2627 <name>sha224</name> 2628 <description>SHA 224.</description> 2629 <value>2</value> 2630 </enumeratedValue> 2631 <enumeratedValue> 2632 <name>sha256</name> 2633 <description>SHA 256.</description> 2634 <value>3</value> 2635 </enumeratedValue> 2636 <enumeratedValue> 2637 <name>sha384</name> 2638 <description>SHA 384.</description> 2639 <value>4</value> 2640 </enumeratedValue> 2641 <enumeratedValue> 2642 <name>sha512</name> 2643 <description>SHA 512.</description> 2644 <value>5</value> 2645 </enumeratedValue> 2646 </enumeratedValues> 2647 </field> 2648 <field> 2649 <name>LAST</name> 2650 <description>Last Message Bit. This bit shall be set along with the HASH_MSG_SZ register prior to hashing the last 512 or 1024-bit block of the message data. It will allow automatic preprocessing of the last message padding, which includes the trailing bit 1, followed by the respective number of zero bits for the last block size and finally the message length represented in bytes. The bit will be automatically cleared at the same time the HASH DONE is set, designating the completion of the last message hash.</description> 2651 <bitOffset>5</bitOffset> 2652 <bitWidth>1</bitWidth> 2653 <enumeratedValues> 2654 <enumeratedValue> 2655 <name>noEffect</name> 2656 <description>No Effect.</description> 2657 <value>0</value> 2658 </enumeratedValue> 2659 <enumeratedValue> 2660 <name>lastMsgData</name> 2661 <description>Last Message Data.</description> 2662 <value>1</value> 2663 </enumeratedValue> 2664 </enumeratedValues> 2665 </field> 2666 </fields> 2667 </register> 2668 <register> 2669 <name>CRC_CTRL</name> 2670 <description>CRC Control Register.</description> 2671 <addressOffset>0x0C</addressOffset> 2672 <fields> 2673 <field> 2674 <name>CRC</name> 2675 <description>Cyclic Redundancy Check Enable. The CRC cannot be enabled if the PRNG is enabled.</description> 2676 <bitOffset>0</bitOffset> 2677 <bitWidth>1</bitWidth> 2678 <enumeratedValues> 2679 <enumeratedValue> 2680 <name>dis</name> 2681 <description>Disable.</description> 2682 <value>0</value> 2683 </enumeratedValue> 2684 <enumeratedValue> 2685 <name>en</name> 2686 <description>Enable.</description> 2687 <value>1</value> 2688 </enumeratedValue> 2689 </enumeratedValues> 2690 </field> 2691 <field> 2692 <name>MSB</name> 2693 <description>MSB select. This bit selects the order of calculating CRC on data.</description> 2694 <bitOffset>1</bitOffset> 2695 <bitWidth>1</bitWidth> 2696 <enumeratedValues> 2697 <enumeratedValue> 2698 <name>lsbFirst</name> 2699 <description>LSB First.</description> 2700 <value>0</value> 2701 </enumeratedValue> 2702 <enumeratedValue> 2703 <name>msbFirst</name> 2704 <description>MSB First.</description> 2705 <value>1</value> 2706 </enumeratedValue> 2707 </enumeratedValues> 2708 </field> 2709 <field derivedFrom="CRC"> 2710 <name>PRNG</name> 2711 <description>Pseudo Random Number Generator Enable. If entropy is disabled, this outputs one byte of pseudo random data per clock cycle. If entropy is enabled, data is output at a rate of one bit per clock cycle.</description> 2712 <bitOffset>2</bitOffset> 2713 <bitWidth>1</bitWidth> 2714 </field> 2715 <field derivedFrom="CRC"> 2716 <name>ENT</name> 2717 <description>Entropy Enable. If the PRNG is enabled, this mixes the high frequency ring oscillator with the LFSR. If the PRNG is disabled, the raw entropy data is output at a rate of 1 bit per clock. This makes it possible to characterize the quality of the entropy source.</description> 2718 <bitOffset>3</bitOffset> 2719 <bitWidth>1</bitWidth> 2720 </field> 2721 <field derivedFrom="CRC"> 2722 <name>HAM</name> 2723 <description>Hamming Code Enable. Enable hamming code calculation.</description> 2724 <bitOffset>4</bitOffset> 2725 <bitWidth>1</bitWidth> 2726 </field> 2727 <field> 2728 <name>HRST</name> 2729 <description>Hamming Reset. Reset Hamming code ECC generator for next block.</description> 2730 <bitOffset>5</bitOffset> 2731 <bitWidth>1</bitWidth> 2732 <access>write-only</access> 2733 <enumeratedValues> 2734 <usage>write</usage> 2735 <enumeratedValue> 2736 <name>reset</name> 2737 <description>Starts reset operation.</description> 2738 <value>1</value> 2739 </enumeratedValue> 2740 </enumeratedValues> 2741 </field> 2742 </fields> 2743 </register> 2744 <register> 2745 <name>DMA_SRC</name> 2746 <description>Crypto DMA Source Address.</description> 2747 <addressOffset>0x10</addressOffset> 2748 <fields> 2749 <field> 2750 <name>ADDR</name> 2751 <description>DMA Source Address.</description> 2752 <bitOffset>0</bitOffset> 2753 <bitWidth>32</bitWidth> 2754 </field> 2755 </fields> 2756 </register> 2757 <register> 2758 <name>DMA_DEST</name> 2759 <description>Crypto DMA Destination Address.</description> 2760 <addressOffset>0x14</addressOffset> 2761 <fields> 2762 <field> 2763 <name>ADDR</name> 2764 <description>DMA Destination Address.</description> 2765 <bitOffset>0</bitOffset> 2766 <bitWidth>32</bitWidth> 2767 </field> 2768 </fields> 2769 </register> 2770 <register> 2771 <name>DMA_CNT</name> 2772 <description>Crypto DMA Byte Count.</description> 2773 <addressOffset>0x18</addressOffset> 2774 <fields> 2775 <field> 2776 <name>ADDR</name> 2777 <description>DMA Byte Address.</description> 2778 <bitOffset>0</bitOffset> 2779 <bitWidth>32</bitWidth> 2780 </field> 2781 </fields> 2782 </register> 2783 <register> 2784 <name>MAA_CTRL</name> 2785 <description>MAA Control Register.</description> 2786 <addressOffset>0x1C</addressOffset> 2787 </register> 2788 <register> 2789 <dim>4</dim> 2790 <dimIncrement>4</dimIncrement> 2791 <name>DIN[%s]</name> 2792 <description>Crypto Data Input. Data input can be written to this register instead of using the DMA. This register writes to the FIFO. This register occupies four successive words to allow the use of multi-store instructions. Words can be written to any location, they will be placed in the FIFO in the order they are written. The endian swap input control bit affects this register.</description> 2793 <addressOffset>0x20</addressOffset> 2794 <access>write-only</access> 2795 <fields> 2796 <field> 2797 <name>DATA</name> 2798 <description>Crypto Data Input. Input can be written to this register instead of using DMA.</description> 2799 <bitOffset>0</bitOffset> 2800 <bitWidth>32</bitWidth> 2801 </field> 2802 </fields> 2803 </register> 2804 <register> 2805 <dim>4</dim> 2806 <dimIncrement>4</dimIncrement> 2807 <name>DOUT[%s]</name> 2808 <description>Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on the algorithm. For block cipher modes, this register holds the result of most recent encryption or decryption operation. These registers are affected by the endian swap bits.</description> 2809 <addressOffset>0x30</addressOffset> 2810 <access>read-only</access> 2811 <fields> 2812 <field> 2813 <name>DATA</name> 2814 <description>Crypto Data Output. Resulting data from cipher calculation. Data is placed in the lower words of these four registers depending on algorithm.</description> 2815 <bitOffset>0</bitOffset> 2816 <bitWidth>32</bitWidth> 2817 </field> 2818 </fields> 2819 </register> 2820 <register> 2821 <name>CRC_POLY</name> 2822 <description>CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or LFSR) should be written to this register. This register is affected by the MSB control bit.</description> 2823 <addressOffset>0x40</addressOffset> 2824 <resetValue>0xEDB88320</resetValue> 2825 <fields> 2826 <field> 2827 <name>POLY</name> 2828 <description>CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or LFSR) should be written to this register. This register is affected by the MSB control bit.</description> 2829 <bitOffset>0</bitOffset> 2830 <bitWidth>32</bitWidth> 2831 </field> 2832 </fields> 2833 </register> 2834 <register> 2835 <name>CRC_VAL</name> 2836 <description>CRC Value. This is the state for the Galois Field. This register holds the result of a CRC calculation or the current state of the LFSR. This register is affected by the MSB control bit.</description> 2837 <addressOffset>0x44</addressOffset> 2838 <resetValue>0xFFFFFFFF</resetValue> 2839 <fields> 2840 <field> 2841 <name>VAL</name> 2842 <description>CRC Value. This is the state for the Galois Field. This register holds the result of a CRC calculation or the current state of LFSR. This register is affected by the MSB control bit.</description> 2843 <bitOffset>0</bitOffset> 2844 <bitWidth>32</bitWidth> 2845 </field> 2846 </fields> 2847 </register> 2848 <register> 2849 <name>CRC_PRNG</name> 2850 <description>CRC PRNG Register.</description> 2851 <addressOffset>0x48</addressOffset> 2852 <fields> 2853 <field> 2854 <name>PRNG</name> 2855 <description>PRNG</description> 2856 <bitOffset>0</bitOffset> 2857 <bitWidth>32</bitWidth> 2858 </field> 2859 </fields> 2860 </register> 2861 <register> 2862 <name>HAM_ECC</name> 2863 <description>Hamming ECC Register.</description> 2864 <addressOffset>0x4C</addressOffset> 2865 <fields> 2866 <field> 2867 <name>ECC</name> 2868 <description>Hamming ECC Value. These bits are the even parity of their corresponding bit groups.</description> 2869 <bitOffset>0</bitOffset> 2870 <bitWidth>16</bitWidth> 2871 </field> 2872 <field> 2873 <name>PAR</name> 2874 <description>Parity. This is the parity of the entire array.</description> 2875 <bitOffset>16</bitOffset> 2876 <bitWidth>1</bitWidth> 2877 <enumeratedValues> 2878 <enumeratedValue> 2879 <name>even</name> 2880 <description>Even.</description> 2881 <value>0</value> 2882 </enumeratedValue> 2883 <enumeratedValue> 2884 <name>odd</name> 2885 <description>Odd.</description> 2886 <value>1</value> 2887 </enumeratedValue> 2888 </enumeratedValues> 2889 </field> 2890 </fields> 2891 </register> 2892 <register> 2893 <dim>4</dim> 2894 <dimIncrement>4</dimIncrement> 2895 <name>CIPHER_INIT[%s]</name> 2896 <description>Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.</description> 2897 <addressOffset>0x50</addressOffset> 2898 <fields> 2899 <field> 2900 <name>IVEC</name> 2901 <description>Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR modes, this register holds the initial value. This register is updated with each encryption or decryption operation. This register is affected by the endian swap bits.</description> 2902 <bitOffset>0</bitOffset> 2903 <bitWidth>32</bitWidth> 2904 </field> 2905 </fields> 2906 </register> 2907 <register> 2908 <dim>8</dim> 2909 <dimIncrement>4</dimIncrement> 2910 <name>CIPHER_KEY[%s]</name> 2911 <description>Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter key lengths. This register is affected by the endian swap input control bits.</description> 2912 <addressOffset>0x60</addressOffset> 2913 <access>write-only</access> 2914 <fields> 2915 <field> 2916 <name>KEY</name> 2917 <description>Cipher Key. This register holds the key used for block cipher operations. The lower words are used for block ciphers that use shorter kye lengths. This register is affected by the endian swap input control bits.</description> 2918 <bitOffset>0</bitOffset> 2919 <bitWidth>32</bitWidth> 2920 </field> 2921 </fields> 2922 </register> 2923 <register> 2924 <dim>16</dim> 2925 <dimIncrement>4</dimIncrement> 2926 <name>HASH_DIGEST[%s]</name> 2927 <description>This register holds the calculated hash value. This register is affected by the endian swap bits.</description> 2928 <addressOffset>0x80</addressOffset> 2929 <fields> 2930 <field> 2931 <name>HASH</name> 2932 <description>This register holds the calculated hash value. This register is affected by the endian swap bits.</description> 2933 <bitOffset>0</bitOffset> 2934 <bitWidth>32</bitWidth> 2935 </field> 2936 </fields> 2937 </register> 2938 <register> 2939 <dim>4</dim> 2940 <dimIncrement>4</dimIncrement> 2941 <name>HASH_MSG_SZ[%s]</name> 2942 <description>Message Size. This register holds the lowest 32-bit of message size in bytes.</description> 2943 <addressOffset>0xC0</addressOffset> 2944 <fields> 2945 <field> 2946 <name>MSGSZ</name> 2947 <description>Message Size. This register holds the lowest 32-bit of message size in bytes.</description> 2948 <bitOffset>0</bitOffset> 2949 <bitWidth>32</bitWidth> 2950 </field> 2951 </fields> 2952 </register> 2953 <register> 2954 <name>MAA_MAWS</name> 2955 <description>MAA Word Size Register.</description> 2956 <addressOffset>0xD0</addressOffset> 2957 <resetValue>0x0</resetValue> 2958 <fields> 2959 <field> 2960 <name>SIZE</name> 2961 <description>MAA Word Size.</description> 2962 <bitOffset>0</bitOffset> 2963 <bitWidth>32</bitWidth> 2964 </field> 2965 </fields> 2966 </register> 2967 <register> 2968 <dim>2</dim> 2969 <dimIncrement>4</dimIncrement> 2970 <name>AAD_LENGTH[%s]</name> 2971 <description>AAD Length Registers.</description> 2972 <addressOffset>0xD0</addressOffset> 2973 <resetValue>0x0</resetValue> 2974 <fields> 2975 <field> 2976 <name>LENGTH</name> 2977 <description>AAD length in bytes for AES GCM and CCM operations.</description> 2978 <bitOffset>0</bitOffset> 2979 <bitWidth>32</bitWidth> 2980 </field> 2981 </fields> 2982 </register> 2983 <register> 2984 <dim>2</dim> 2985 <dimIncrement>4</dimIncrement> 2986 <name>PLD_LENGTH[%s]</name> 2987 <description>PLD Length Registers.</description> 2988 <addressOffset>0xD8</addressOffset> 2989 <resetValue>0x0</resetValue> 2990 <fields> 2991 <field> 2992 <name>LENGTH</name> 2993 <description>PLD length in bytes for AES GCM and CCM operations.</description> 2994 <bitOffset>0</bitOffset> 2995 <bitWidth>32</bitWidth> 2996 </field> 2997 </fields> 2998 </register> 2999 <register> 3000 <dim>4</dim> 3001 <dimIncrement>4</dimIncrement> 3002 <name>TAGMIC[%s]</name> 3003 <description>TAG/MIC Registers.</description> 3004 <addressOffset>0xE0</addressOffset> 3005 <fields> 3006 <field> 3007 <name>LENGTH</name> 3008 <description>TAG/MIC output for AES GCM and CCM operations.</description> 3009 <bitOffset>0</bitOffset> 3010 <bitWidth>32</bitWidth> 3011 </field> 3012 </fields> 3013 </register> 3014 </registers> 3015 </peripheral> 3016<!--CTB The Cryptographic Toolbox is a combination of cryptographic engines and a secure cryptographic accelerator (SCA) used to provide advanced cryptographic security.--> 3017 <peripheral> 3018 <name>DMA</name> 3019 <description>DMA Controller Fully programmable, chaining capable DMA channels.</description> 3020 <baseAddress>0x40028000</baseAddress> 3021 <size>32</size> 3022 <addressBlock> 3023 <offset>0x00</offset> 3024 <size>0x1000</size> 3025 <usage>registers</usage> 3026 </addressBlock> 3027 <interrupt> 3028 <name>DMA0</name> 3029 <value>28</value> 3030 </interrupt> 3031 <interrupt> 3032 <name>DMA1</name> 3033 <value>29</value> 3034 </interrupt> 3035 <interrupt> 3036 <name>DMA2</name> 3037 <value>30</value> 3038 </interrupt> 3039 <interrupt> 3040 <name>DMA3</name> 3041 <value>31</value> 3042 </interrupt> 3043 <interrupt> 3044 <name>DMA4</name> 3045 <value>68</value> 3046 </interrupt> 3047 <interrupt> 3048 <name>DMA5</name> 3049 <value>69</value> 3050 </interrupt> 3051 <interrupt> 3052 <name>DMA6</name> 3053 <value>70</value> 3054 </interrupt> 3055 <interrupt> 3056 <name>DMA7</name> 3057 <value>71</value> 3058 </interrupt> 3059 <interrupt> 3060 <name>DMA8</name> 3061 <value>72</value> 3062 </interrupt> 3063 <interrupt> 3064 <name>DMA9</name> 3065 <value>73</value> 3066 </interrupt> 3067 <interrupt> 3068 <name>DMA10</name> 3069 <value>74</value> 3070 </interrupt> 3071 <interrupt> 3072 <name>DMA11</name> 3073 <value>75</value> 3074 </interrupt> 3075 <interrupt> 3076 <name>DMA12</name> 3077 <value>76</value> 3078 </interrupt> 3079 <interrupt> 3080 <name>DMA13</name> 3081 <value>77</value> 3082 </interrupt> 3083 <interrupt> 3084 <name>DMA14</name> 3085 <value>78</value> 3086 </interrupt> 3087 <interrupt> 3088 <name>DMA15</name> 3089 <value>79</value> 3090 </interrupt> 3091 <registers> 3092 <register> 3093 <name>INTEN</name> 3094 <description>DMA Control Register.</description> 3095 <addressOffset>0x000</addressOffset> 3096 <fields> 3097 <field> 3098 <name>CH0</name> 3099 <description>Channel 0 Interrupt Enable.</description> 3100 <bitOffset>0</bitOffset> 3101 <bitWidth>1</bitWidth> 3102 <enumeratedValues> 3103 <enumeratedValue> 3104 <name>dis</name> 3105 <description>Disable.</description> 3106 <value>0</value> 3107 </enumeratedValue> 3108 <enumeratedValue> 3109 <name>en</name> 3110 <description>Enable.</description> 3111 <value>1</value> 3112 </enumeratedValue> 3113 </enumeratedValues> 3114 </field> 3115 <field derivedFrom="CH0"> 3116 <name>CH1</name> 3117 <description>Channel 1 Interrupt Enable.</description> 3118 <bitOffset>1</bitOffset> 3119 <bitWidth>1</bitWidth> 3120 </field> 3121 <field derivedFrom="CH0"> 3122 <name>CH2</name> 3123 <description>Channel 2 Interrupt Enable.</description> 3124 <bitOffset>2</bitOffset> 3125 <bitWidth>1</bitWidth> 3126 </field> 3127 <field derivedFrom="CH0"> 3128 <name>CH3</name> 3129 <description>Channel 3 Interrupt Enable.</description> 3130 <bitOffset>3</bitOffset> 3131 <bitWidth>1</bitWidth> 3132 </field> 3133 <field derivedFrom="CH0"> 3134 <name>CH4</name> 3135 <description>Channel 4 Interrupt Enable.</description> 3136 <bitOffset>4</bitOffset> 3137 <bitWidth>1</bitWidth> 3138 </field> 3139 <field derivedFrom="CH0"> 3140 <name>CH5</name> 3141 <description>Channel 5 Interrupt Enable.</description> 3142 <bitOffset>5</bitOffset> 3143 <bitWidth>1</bitWidth> 3144 </field> 3145 <field derivedFrom="CH0"> 3146 <name>CH6</name> 3147 <description>Channel 6 Interrupt Enable.</description> 3148 <bitOffset>6</bitOffset> 3149 <bitWidth>1</bitWidth> 3150 </field> 3151 <field derivedFrom="CH0"> 3152 <name>CH7</name> 3153 <description>Channel 7 Interrupt Enable.</description> 3154 <bitOffset>7</bitOffset> 3155 <bitWidth>1</bitWidth> 3156 </field> 3157 <field derivedFrom="CH0"> 3158 <name>CH8</name> 3159 <description>Channel 8 Interrupt Enable.</description> 3160 <bitOffset>8</bitOffset> 3161 <bitWidth>1</bitWidth> 3162 </field> 3163 <field derivedFrom="CH0"> 3164 <name>CH9</name> 3165 <description>Channel 9 Interrupt Enable.</description> 3166 <bitOffset>9</bitOffset> 3167 <bitWidth>1</bitWidth> 3168 </field> 3169 <field derivedFrom="CH0"> 3170 <name>CH10</name> 3171 <description>Channel 10 Interrupt Enable.</description> 3172 <bitOffset>10</bitOffset> 3173 <bitWidth>1</bitWidth> 3174 </field> 3175 <field derivedFrom="CH0"> 3176 <name>CH11</name> 3177 <description>Channel 11 Interrupt Enable.</description> 3178 <bitOffset>11</bitOffset> 3179 <bitWidth>1</bitWidth> 3180 </field> 3181 <field derivedFrom="CH0"> 3182 <name>CH12</name> 3183 <description>Channel 12 Interrupt Enable.</description> 3184 <bitOffset>12</bitOffset> 3185 <bitWidth>1</bitWidth> 3186 </field> 3187 <field derivedFrom="CH0"> 3188 <name>CH13</name> 3189 <description>Channel 13 Interrupt Enable.</description> 3190 <bitOffset>13</bitOffset> 3191 <bitWidth>1</bitWidth> 3192 </field> 3193 <field derivedFrom="CH0"> 3194 <name>CH14</name> 3195 <description>Channel 14 Interrupt Enable.</description> 3196 <bitOffset>14</bitOffset> 3197 <bitWidth>1</bitWidth> 3198 </field> 3199 <field derivedFrom="CH0"> 3200 <name>CH15</name> 3201 <description>Channel 15 Interrupt Enable.</description> 3202 <bitOffset>15</bitOffset> 3203 <bitWidth>1</bitWidth> 3204 </field> 3205 </fields> 3206 </register> 3207 <register> 3208 <name>INTFL</name> 3209 <description>DMA Interrupt Register.</description> 3210 <addressOffset>0x004</addressOffset> 3211 <access>read-only</access> 3212 <fields> 3213 <field> 3214 <name>CH0</name> 3215 <description>Channel Interrupt. To clear an interrupt, all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN.</description> 3216 <bitOffset>0</bitOffset> 3217 <bitWidth>1</bitWidth> 3218 <enumeratedValues> 3219 <enumeratedValue> 3220 <name>inactive</name> 3221 <description>No interrupt is pending.</description> 3222 <value>0</value> 3223 </enumeratedValue> 3224 <enumeratedValue> 3225 <name>pending</name> 3226 <description>An interrupt is pending.</description> 3227 <value>1</value> 3228 </enumeratedValue> 3229 </enumeratedValues> 3230 </field> 3231 <field derivedFrom="CH0"> 3232 <name>CH1</name> 3233 <bitOffset>1</bitOffset> 3234 <bitWidth>1</bitWidth> 3235 </field> 3236 <field derivedFrom="CH0"> 3237 <name>CH2</name> 3238 <bitOffset>2</bitOffset> 3239 <bitWidth>1</bitWidth> 3240 </field> 3241 <field derivedFrom="CH0"> 3242 <name>CH3</name> 3243 <bitOffset>3</bitOffset> 3244 <bitWidth>1</bitWidth> 3245 </field> 3246 <field derivedFrom="CH0"> 3247 <name>CH4</name> 3248 <bitOffset>4</bitOffset> 3249 <bitWidth>1</bitWidth> 3250 </field> 3251 <field derivedFrom="CH0"> 3252 <name>CH5</name> 3253 <bitOffset>5</bitOffset> 3254 <bitWidth>1</bitWidth> 3255 </field> 3256 <field derivedFrom="CH0"> 3257 <name>CH6</name> 3258 <bitOffset>6</bitOffset> 3259 <bitWidth>1</bitWidth> 3260 </field> 3261 <field derivedFrom="CH0"> 3262 <name>CH7</name> 3263 <bitOffset>7</bitOffset> 3264 <bitWidth>1</bitWidth> 3265 </field> 3266 <field derivedFrom="CH0"> 3267 <name>CH8</name> 3268 <bitOffset>8</bitOffset> 3269 <bitWidth>1</bitWidth> 3270 </field> 3271 <field derivedFrom="CH0"> 3272 <name>CH9</name> 3273 <bitOffset>9</bitOffset> 3274 <bitWidth>1</bitWidth> 3275 </field> 3276 <field derivedFrom="CH0"> 3277 <name>CH10</name> 3278 <bitOffset>10</bitOffset> 3279 <bitWidth>1</bitWidth> 3280 </field> 3281 <field derivedFrom="CH0"> 3282 <name>CH11</name> 3283 <bitOffset>11</bitOffset> 3284 <bitWidth>1</bitWidth> 3285 </field> 3286 <field derivedFrom="CH0"> 3287 <name>CH12</name> 3288 <bitOffset>12</bitOffset> 3289 <bitWidth>1</bitWidth> 3290 </field> 3291 <field derivedFrom="CH0"> 3292 <name>CH13</name> 3293 <bitOffset>13</bitOffset> 3294 <bitWidth>1</bitWidth> 3295 </field> 3296 <field derivedFrom="CH0"> 3297 <name>CH14</name> 3298 <bitOffset>14</bitOffset> 3299 <bitWidth>1</bitWidth> 3300 </field> 3301 <field derivedFrom="CH0"> 3302 <name>CH15</name> 3303 <bitOffset>15</bitOffset> 3304 <bitWidth>1</bitWidth> 3305 </field> 3306 </fields> 3307 </register> 3308 <cluster> 3309 <dim>16</dim> 3310 <dimIncrement>0x20</dimIncrement> 3311 <name>CH[%s]</name> 3312 <description>DMA Channel registers.</description> 3313 <headerStructName>dma_ch</headerStructName> 3314 <addressOffset>0x100</addressOffset> 3315 <access>read-write</access> 3316 <register> 3317 <name>CTRL</name> 3318 <description>DMA Channel Control Register.</description> 3319 <addressOffset>0x000</addressOffset> 3320 <fields> 3321 <field> 3322 <name>EN</name> 3323 <description>Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.</description> 3324 <bitOffset>0</bitOffset> 3325 <bitWidth>1</bitWidth> 3326 <enumeratedValues> 3327 <enumeratedValue> 3328 <name>dis</name> 3329 <description>Disable.</description> 3330 <value>0</value> 3331 </enumeratedValue> 3332 <enumeratedValue> 3333 <name>en</name> 3334 <description>Enable.</description> 3335 <value>1</value> 3336 </enumeratedValue> 3337 </enumeratedValues> 3338 </field> 3339 <field> 3340 <name>RLDEN</name> 3341 <description>Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.</description> 3342 <bitOffset>1</bitOffset> 3343 <bitWidth>1</bitWidth> 3344 <enumeratedValues> 3345 <enumeratedValue> 3346 <name>dis</name> 3347 <description>Disable.</description> 3348 <value>0</value> 3349 </enumeratedValue> 3350 <enumeratedValue> 3351 <name>en</name> 3352 <description>Enable.</description> 3353 <value>1</value> 3354 </enumeratedValue> 3355 </enumeratedValues> 3356 </field> 3357 <field> 3358 <name>PRI</name> 3359 <description>DMA Priority.</description> 3360 <bitOffset>2</bitOffset> 3361 <bitWidth>2</bitWidth> 3362 <enumeratedValues> 3363 <enumeratedValue> 3364 <name>high</name> 3365 <description>Highest Priority.</description> 3366 <value>0</value> 3367 </enumeratedValue> 3368 <enumeratedValue> 3369 <name>medHigh</name> 3370 <description>Medium High Priority.</description> 3371 <value>1</value> 3372 </enumeratedValue> 3373 <enumeratedValue> 3374 <name>medLow</name> 3375 <description>Medium Low Priority.</description> 3376 <value>2</value> 3377 </enumeratedValue> 3378 <enumeratedValue> 3379 <name>low</name> 3380 <description>Lowest Priority.</description> 3381 <value>3</value> 3382 </enumeratedValue> 3383 </enumeratedValues> 3384 </field> 3385 <field> 3386 <name>REQUEST</name> 3387 <description>Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.</description> 3388 <bitOffset>4</bitOffset> 3389 <bitWidth>6</bitWidth> 3390 <enumeratedValues> 3391 <enumeratedValue> 3392 <name>MEMTOMEM</name> 3393 <description>Memory To Memory</description> 3394 <value>0x00</value> 3395 </enumeratedValue> 3396 <enumeratedValue> 3397 <name>SPI0RX</name> 3398 <description>SPI0 RX</description> 3399 <value>0x01</value> 3400 </enumeratedValue> 3401 <enumeratedValue> 3402 <name>SPI1RX</name> 3403 <description>SPI1 RX</description> 3404 <value>0x02</value> 3405 </enumeratedValue> 3406 <enumeratedValue> 3407 <name>SPI2RX</name> 3408 <description>SPI2 RX</description> 3409 <value>0x03</value> 3410 </enumeratedValue> 3411 <enumeratedValue> 3412 <name>UART0RX</name> 3413 <description>UART0 RX</description> 3414 <value>0x04</value> 3415 </enumeratedValue> 3416 <enumeratedValue> 3417 <name>UART1RX</name> 3418 <description>UART1 RX</description> 3419 <value>0x05</value> 3420 </enumeratedValue> 3421 <enumeratedValue> 3422 <name>CAN0RX</name> 3423 <description>CAN0 RX</description> 3424 <value>0x06</value> 3425 </enumeratedValue> 3426 <enumeratedValue> 3427 <name>I2C0RX</name> 3428 <description>I2C0 RX</description> 3429 <value>0x07</value> 3430 </enumeratedValue> 3431 <enumeratedValue> 3432 <name>I2C1RX</name> 3433 <description>I2C1 RX</description> 3434 <value>0x08</value> 3435 </enumeratedValue> 3436 <enumeratedValue> 3437 <name>ADC</name> 3438 <description>ADC</description> 3439 <value>0x09</value> 3440 </enumeratedValue> 3441 <enumeratedValue> 3442 <name>I2C2RX</name> 3443 <description>I2C2 RX</description> 3444 <value>0x0A</value> 3445 </enumeratedValue> 3446 <enumeratedValue> 3447 <name>UART2RX</name> 3448 <description>UART2 RX</description> 3449 <value>0x0E</value> 3450 </enumeratedValue> 3451 <enumeratedValue> 3452 <name>SPI3RX</name> 3453 <description>SPI3 RX</description> 3454 <value>0x0F</value> 3455 </enumeratedValue> 3456 <enumeratedValue> 3457 <name>SPI4RX</name> 3458 <description>SPI4 RX</description> 3459 <value>0x10</value> 3460 </enumeratedValue> 3461 <enumeratedValue> 3462 <name>USBRX1</name> 3463 <description>USB RX1</description> 3464 <value>0x11</value> 3465 </enumeratedValue> 3466 <enumeratedValue> 3467 <name>USBRX2</name> 3468 <description>USB RX2</description> 3469 <value>0x12</value> 3470 </enumeratedValue> 3471 <enumeratedValue> 3472 <name>USBRX3</name> 3473 <description>USB RX3</description> 3474 <value>0x13</value> 3475 </enumeratedValue> 3476 <enumeratedValue> 3477 <name>USBRX4</name> 3478 <description>USB RX4</description> 3479 <value>0x14</value> 3480 </enumeratedValue> 3481 <enumeratedValue> 3482 <name>USBRX5</name> 3483 <description>USB RX5</description> 3484 <value>0x15</value> 3485 </enumeratedValue> 3486 <enumeratedValue> 3487 <name>USBRX6</name> 3488 <description>USB RX6</description> 3489 <value>0x16</value> 3490 </enumeratedValue> 3491 <enumeratedValue> 3492 <name>USBRX7</name> 3493 <description>USB RX7</description> 3494 <value>0x17</value> 3495 </enumeratedValue> 3496 <enumeratedValue> 3497 <name>USBRX8</name> 3498 <description>USB RX8</description> 3499 <value>0x18</value> 3500 </enumeratedValue> 3501 <enumeratedValue> 3502 <name>USBRX9</name> 3503 <description>USB RX9</description> 3504 <value>0x19</value> 3505 </enumeratedValue> 3506 <enumeratedValue> 3507 <name>USBRX10</name> 3508 <description>USB RX10</description> 3509 <value>0x1A</value> 3510 </enumeratedValue> 3511 <enumeratedValue> 3512 <name>USBRX11</name> 3513 <description>USB RX11</description> 3514 <value>0x1B</value> 3515 </enumeratedValue> 3516 <enumeratedValue> 3517 <name>UART3RX</name> 3518 <description>UART3 RX</description> 3519 <value>0x1C</value> 3520 </enumeratedValue> 3521 <enumeratedValue> 3522 <name>I2SRX</name> 3523 <description>I2S RX</description> 3524 <value>0x1E</value> 3525 </enumeratedValue> 3526 <enumeratedValue> 3527 <name>CAN1RX</name> 3528 <description>CAN1 RX</description> 3529 <value>0x1F</value> 3530 </enumeratedValue> 3531 <enumeratedValue> 3532 <name>SPI0TX</name> 3533 <description>SPI0 TX</description> 3534 <value>0x21</value> 3535 </enumeratedValue> 3536 <enumeratedValue> 3537 <name>SPI1TX</name> 3538 <description>SPI1 TX</description> 3539 <value>0x22</value> 3540 </enumeratedValue> 3541 <enumeratedValue> 3542 <name>SPI2TX</name> 3543 <description>SPI2 TX</description> 3544 <value>0x23</value> 3545 </enumeratedValue> 3546 <enumeratedValue> 3547 <name>UART0TX</name> 3548 <description>UART0 TX</description> 3549 <value>0x24</value> 3550 </enumeratedValue> 3551 <enumeratedValue> 3552 <name>UART1TX</name> 3553 <description>UART1 TX</description> 3554 <value>0x25</value> 3555 </enumeratedValue> 3556 <enumeratedValue> 3557 <name>CAN0TX</name> 3558 <description>CAN0 TX</description> 3559 <value>0x26</value> 3560 </enumeratedValue> 3561 <enumeratedValue> 3562 <name>I2C0TX</name> 3563 <description>I2C0 TX</description> 3564 <value>0x27</value> 3565 </enumeratedValue> 3566 <enumeratedValue> 3567 <name>I2C1TX</name> 3568 <description>I2C1 TX</description> 3569 <value>0x28</value> 3570 </enumeratedValue> 3571 <enumeratedValue> 3572 <name>I2C2TX</name> 3573 <description>I2C2 TX</description> 3574 <value>0x2A</value> 3575 </enumeratedValue> 3576 <enumeratedValue> 3577 <name>UART2TX</name> 3578 <description>UART2 TX</description> 3579 <value>0x2E</value> 3580 </enumeratedValue> 3581 <enumeratedValue> 3582 <name>SPI3TX</name> 3583 <description>SPI3 TX</description> 3584 <value>0x2F</value> 3585 </enumeratedValue> 3586 <enumeratedValue> 3587 <name>SPI4TX</name> 3588 <description>SPI4 TX</description> 3589 <value>0x30</value> 3590 </enumeratedValue> 3591 <enumeratedValue> 3592 <name>USBTX1</name> 3593 <description>USB TX1</description> 3594 <value>0x31</value> 3595 </enumeratedValue> 3596 <enumeratedValue> 3597 <name>USBTX2</name> 3598 <description>USB TX2</description> 3599 <value>0x32</value> 3600 </enumeratedValue> 3601 <enumeratedValue> 3602 <name>USBTX3</name> 3603 <description>USB TX3</description> 3604 <value>0x33</value> 3605 </enumeratedValue> 3606 <enumeratedValue> 3607 <name>USBTX4</name> 3608 <description>USB TX4</description> 3609 <value>0x34</value> 3610 </enumeratedValue> 3611 <enumeratedValue> 3612 <name>USBTX5</name> 3613 <description>USB TX5</description> 3614 <value>0x35</value> 3615 </enumeratedValue> 3616 <enumeratedValue> 3617 <name>USBTX6</name> 3618 <description>USB TX6</description> 3619 <value>0x36</value> 3620 </enumeratedValue> 3621 <enumeratedValue> 3622 <name>USBTX7</name> 3623 <description>USB TX7</description> 3624 <value>0x37</value> 3625 </enumeratedValue> 3626 <enumeratedValue> 3627 <name>USBTX8</name> 3628 <description>USB TX8</description> 3629 <value>0x38</value> 3630 </enumeratedValue> 3631 <enumeratedValue> 3632 <name>USBTX9</name> 3633 <description>USB TX9</description> 3634 <value>0x39</value> 3635 </enumeratedValue> 3636 <enumeratedValue> 3637 <name>USBTX10</name> 3638 <description>USB TX10</description> 3639 <value>0x3A</value> 3640 </enumeratedValue> 3641 <enumeratedValue> 3642 <name>USBTX11</name> 3643 <description>USB TX11</description> 3644 <value>0x3B</value> 3645 </enumeratedValue> 3646 <enumeratedValue> 3647 <name>UART3TX</name> 3648 <description>UART3 TX</description> 3649 <value>0x3C</value> 3650 </enumeratedValue> 3651 <enumeratedValue> 3652 <name>I2STX</name> 3653 <description>I2S TX</description> 3654 <value>0x3E</value> 3655 </enumeratedValue> 3656 <enumeratedValue> 3657 <name>CAN1TX</name> 3658 <description>CAN1 TX</description> 3659 <value>0x3F</value> 3660 </enumeratedValue> 3661 </enumeratedValues> 3662 </field> 3663 <field> 3664 <name>TO_WAIT</name> 3665 <description>Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.</description> 3666 <bitOffset>10</bitOffset> 3667 <bitWidth>1</bitWidth> 3668 <enumeratedValues> 3669 <enumeratedValue> 3670 <name>dis</name> 3671 <description>Disable.</description> 3672 <value>0</value> 3673 </enumeratedValue> 3674 <enumeratedValue> 3675 <name>en</name> 3676 <description>Enable.</description> 3677 <value>1</value> 3678 </enumeratedValue> 3679 </enumeratedValues> 3680 </field> 3681 <field> 3682 <name>TO_PER</name> 3683 <description>Timeout Period Select.</description> 3684 <bitOffset>11</bitOffset> 3685 <bitWidth>3</bitWidth> 3686 <enumeratedValues> 3687 <enumeratedValue> 3688 <name>to4</name> 3689 <description>Timeout of 3 to 4 prescale clocks.</description> 3690 <value>0</value> 3691 </enumeratedValue> 3692 <enumeratedValue> 3693 <name>to8</name> 3694 <description>Timeout of 7 to 8 prescale clocks.</description> 3695 <value>1</value> 3696 </enumeratedValue> 3697 <enumeratedValue> 3698 <name>to16</name> 3699 <description>Timeout of 15 to 16 prescale clocks.</description> 3700 <value>2</value> 3701 </enumeratedValue> 3702 <enumeratedValue> 3703 <name>to32</name> 3704 <description>Timeout of 31 to 32 prescale clocks.</description> 3705 <value>3</value> 3706 </enumeratedValue> 3707 <enumeratedValue> 3708 <name>to64</name> 3709 <description>Timeout of 63 to 64 prescale clocks.</description> 3710 <value>4</value> 3711 </enumeratedValue> 3712 <enumeratedValue> 3713 <name>to128</name> 3714 <description>Timeout of 127 to 128 prescale clocks.</description> 3715 <value>5</value> 3716 </enumeratedValue> 3717 <enumeratedValue> 3718 <name>to256</name> 3719 <description>Timeout of 255 to 256 prescale clocks.</description> 3720 <value>6</value> 3721 </enumeratedValue> 3722 <enumeratedValue> 3723 <name>to512</name> 3724 <description>Timeout of 511 to 512 prescale clocks.</description> 3725 <value>7</value> 3726 </enumeratedValue> 3727 </enumeratedValues> 3728 </field> 3729 <field> 3730 <name>TO_CLKDIV</name> 3731 <description>Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.</description> 3732 <bitOffset>14</bitOffset> 3733 <bitWidth>2</bitWidth> 3734 <enumeratedValues> 3735 <enumeratedValue> 3736 <name>dis</name> 3737 <description>Disable timer.</description> 3738 <value>0</value> 3739 </enumeratedValue> 3740 <enumeratedValue> 3741 <name>div256</name> 3742 <description>hclk / 256.</description> 3743 <value>1</value> 3744 </enumeratedValue> 3745 <enumeratedValue> 3746 <name>div64k</name> 3747 <description>hclk / 64k.</description> 3748 <value>2</value> 3749 </enumeratedValue> 3750 <enumeratedValue> 3751 <name>div16M</name> 3752 <description>hclk / 16M.</description> 3753 <value>3</value> 3754 </enumeratedValue> 3755 </enumeratedValues> 3756 </field> 3757 <field> 3758 <name>SRCWD</name> 3759 <description>Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.</description> 3760 <bitOffset>16</bitOffset> 3761 <bitWidth>2</bitWidth> 3762 <enumeratedValues> 3763 <enumeratedValue> 3764 <name>byte</name> 3765 <description>Byte.</description> 3766 <value>0</value> 3767 </enumeratedValue> 3768 <enumeratedValue> 3769 <name>halfWord</name> 3770 <description>Halfword.</description> 3771 <value>1</value> 3772 </enumeratedValue> 3773 <enumeratedValue> 3774 <name>word</name> 3775 <description>Word.</description> 3776 <value>2</value> 3777 </enumeratedValue> 3778 </enumeratedValues> 3779 </field> 3780 <field> 3781 <name>SRCINC</name> 3782 <description>Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.</description> 3783 <bitOffset>18</bitOffset> 3784 <bitWidth>1</bitWidth> 3785 <enumeratedValues> 3786 <enumeratedValue> 3787 <name>dis</name> 3788 <description>Disable.</description> 3789 <value>0</value> 3790 </enumeratedValue> 3791 <enumeratedValue> 3792 <name>en</name> 3793 <description>Enable.</description> 3794 <value>1</value> 3795 </enumeratedValue> 3796 </enumeratedValues> 3797 </field> 3798 <field> 3799 <name>DSTWD</name> 3800 <description>Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).</description> 3801 <bitOffset>20</bitOffset> 3802 <bitWidth>2</bitWidth> 3803 <enumeratedValues> 3804 <enumeratedValue> 3805 <name>byte</name> 3806 <description>Byte.</description> 3807 <value>0</value> 3808 </enumeratedValue> 3809 <enumeratedValue> 3810 <name>halfWord</name> 3811 <description>Halfword.</description> 3812 <value>1</value> 3813 </enumeratedValue> 3814 <enumeratedValue> 3815 <name>word</name> 3816 <description>Word.</description> 3817 <value>2</value> 3818 </enumeratedValue> 3819 </enumeratedValues> 3820 </field> 3821 <field> 3822 <name>DSTINC</name> 3823 <description>Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.</description> 3824 <bitOffset>22</bitOffset> 3825 <bitWidth>1</bitWidth> 3826 <enumeratedValues> 3827 <enumeratedValue> 3828 <name>dis</name> 3829 <description>Disable.</description> 3830 <value>0</value> 3831 </enumeratedValue> 3832 <enumeratedValue> 3833 <name>en</name> 3834 <description>Enable.</description> 3835 <value>1</value> 3836 </enumeratedValue> 3837 </enumeratedValues> 3838 </field> 3839 <field> 3840 <name>BURST_SIZE</name> 3841 <description>Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field.</description> 3842 <bitOffset>24</bitOffset> 3843 <bitWidth>5</bitWidth> 3844 </field> 3845 <field> 3846 <name>DIS_IE</name> 3847 <description>Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.</description> 3848 <bitOffset>30</bitOffset> 3849 <bitWidth>1</bitWidth> 3850 <enumeratedValues> 3851 <enumeratedValue> 3852 <name>dis</name> 3853 <description>Disable.</description> 3854 <value>0</value> 3855 </enumeratedValue> 3856 <enumeratedValue> 3857 <name>en</name> 3858 <description>Enable.</description> 3859 <value>1</value> 3860 </enumeratedValue> 3861 </enumeratedValues> 3862 </field> 3863 <field> 3864 <name>CTZ_IE</name> 3865 <description>Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.</description> 3866 <bitOffset>31</bitOffset> 3867 <bitWidth>1</bitWidth> 3868 <enumeratedValues> 3869 <enumeratedValue> 3870 <name>dis</name> 3871 <description>Disable.</description> 3872 <value>0</value> 3873 </enumeratedValue> 3874 <enumeratedValue> 3875 <name>en</name> 3876 <description>Enable.</description> 3877 <value>1</value> 3878 </enumeratedValue> 3879 </enumeratedValues> 3880 </field> 3881 </fields> 3882 </register> 3883 <register> 3884 <name>STATUS</name> 3885 <description>DMA Channel Status Register.</description> 3886 <addressOffset>0x004</addressOffset> 3887 <fields> 3888 <field> 3889 <name>STATUS</name> 3890 <description>Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).</description> 3891 <bitOffset>0</bitOffset> 3892 <bitWidth>1</bitWidth> 3893 <access>read-only</access> 3894 <enumeratedValues> 3895 <enumeratedValue> 3896 <name>dis</name> 3897 <description>Disable.</description> 3898 <value>0</value> 3899 </enumeratedValue> 3900 <enumeratedValue> 3901 <name>en</name> 3902 <description>Enable.</description> 3903 <value>1</value> 3904 </enumeratedValue> 3905 </enumeratedValues> 3906 </field> 3907 <field> 3908 <name>IPEND</name> 3909 <description>Channel Interrupt.</description> 3910 <bitOffset>1</bitOffset> 3911 <bitWidth>1</bitWidth> 3912 <access>read-only</access> 3913 <enumeratedValues> 3914 <enumeratedValue> 3915 <name>inactive</name> 3916 <description>No interrupt is pending.</description> 3917 <value>0</value> 3918 </enumeratedValue> 3919 <enumeratedValue> 3920 <name>pending</name> 3921 <description>An interrupt is pending.</description> 3922 <value>1</value> 3923 </enumeratedValue> 3924 </enumeratedValues> 3925 </field> 3926 <field> 3927 <name>CTZ_IF</name> 3928 <description>Count-to-Zero (CTZ) Interrupt Flag</description> 3929 <bitOffset>2</bitOffset> 3930 <bitWidth>1</bitWidth> 3931 <modifiedWriteValues>oneToClear</modifiedWriteValues> 3932 </field> 3933 <field> 3934 <name>RLD_IF</name> 3935 <description>Reload Event Interrupt Flag.</description> 3936 <bitOffset>3</bitOffset> 3937 <bitWidth>1</bitWidth> 3938 <modifiedWriteValues>oneToClear</modifiedWriteValues> 3939 </field> 3940 <field> 3941 <name>BUS_ERR</name> 3942 <description>Bus Error. Indicates that an AHB abort was received and the channel has been disabled.</description> 3943 <bitOffset>4</bitOffset> 3944 <bitWidth>1</bitWidth> 3945 <modifiedWriteValues>oneToClear</modifiedWriteValues> 3946 </field> 3947 <field> 3948 <name>TO_IF</name> 3949 <description>Time-Out Event Interrupt Flag.</description> 3950 <bitOffset>6</bitOffset> 3951 <bitWidth>1</bitWidth> 3952 <modifiedWriteValues>oneToClear</modifiedWriteValues> 3953 </field> 3954 </fields> 3955 </register> 3956 <register> 3957 <name>SRC</name> 3958 <description>Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.</description> 3959 <addressOffset>0x008</addressOffset> 3960 <fields> 3961 <field> 3962 <name>ADDR</name> 3963 <bitOffset>0</bitOffset> 3964 <bitWidth>32</bitWidth> 3965 </field> 3966 </fields> 3967 </register> 3968 <register> 3969 <name>DST</name> 3970 <description>Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.</description> 3971 <addressOffset>0x00C</addressOffset> 3972 <fields> 3973 <field> 3974 <name>ADDR</name> 3975 <bitOffset>0</bitOffset> 3976 <bitWidth>32</bitWidth> 3977 </field> 3978 </fields> 3979 </register> 3980 <register> 3981 <name>CNT</name> 3982 <description>DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.</description> 3983 <addressOffset>0x010</addressOffset> 3984 <fields> 3985 <field> 3986 <name>CNT</name> 3987 <description>DMA Counter.</description> 3988 <bitOffset>0</bitOffset> 3989 <bitWidth>24</bitWidth> 3990 </field> 3991 </fields> 3992 </register> 3993 <register> 3994 <name>SRCRLD</name> 3995 <description>Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.</description> 3996 <addressOffset>0x014</addressOffset> 3997 <fields> 3998 <field> 3999 <name>ADDR</name> 4000 <description>Source Address Reload Value.</description> 4001 <bitOffset>0</bitOffset> 4002 <bitWidth>31</bitWidth> 4003 </field> 4004 </fields> 4005 </register> 4006 <register> 4007 <name>DSTRLD</name> 4008 <description>Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.</description> 4009 <addressOffset>0x018</addressOffset> 4010 <fields> 4011 <field> 4012 <name>ADDR</name> 4013 <description>Destination Address Reload Value.</description> 4014 <bitOffset>0</bitOffset> 4015 <bitWidth>31</bitWidth> 4016 </field> 4017 </fields> 4018 </register> 4019 <register> 4020 <name>CNTRLD</name> 4021 <description>DMA Channel Count Reload Register.</description> 4022 <addressOffset>0x01C</addressOffset> 4023 <fields> 4024 <field> 4025 <name>CNT</name> 4026 <description>Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.</description> 4027 <bitOffset>0</bitOffset> 4028 <bitWidth>24</bitWidth> 4029 </field> 4030 <field> 4031 <name>EN</name> 4032 <description>Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.</description> 4033 <bitOffset>31</bitOffset> 4034 <bitWidth>1</bitWidth> 4035 <enumeratedValues> 4036 <enumeratedValue> 4037 <name>dis</name> 4038 <description>Disable.</description> 4039 <value>0</value> 4040 </enumeratedValue> 4041 <enumeratedValue> 4042 <name>en</name> 4043 <description>Enable.</description> 4044 <value>1</value> 4045 </enumeratedValue> 4046 </enumeratedValues> 4047 </field> 4048 </fields> 4049 </register> 4050 </cluster> 4051 </registers> 4052 </peripheral> 4053<!--DMA DMA Controller Fully programmable, chaining capable DMA channels.--> 4054 <peripheral> 4055 <name>EMCC</name> 4056 <description>External Memory Cache Controller Registers.</description> 4057 <baseAddress>0x40033000</baseAddress> 4058 <addressBlock> 4059 <offset>0x00</offset> 4060 <size>0x1000</size> 4061 <usage>registers</usage> 4062 </addressBlock> 4063 <registers> 4064 <register> 4065 <name>INFO</name> 4066 <description>Cache ID Register.</description> 4067 <addressOffset>0x0000</addressOffset> 4068 <access>read-only</access> 4069 <fields> 4070 <field> 4071 <name>RELNUM</name> 4072 <description>Release Number. Identifies the RTL release version.</description> 4073 <bitOffset>0</bitOffset> 4074 <bitWidth>6</bitWidth> 4075 </field> 4076 <field> 4077 <name>PARTNUM</name> 4078 <description>Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter.</description> 4079 <bitOffset>6</bitOffset> 4080 <bitWidth>4</bitWidth> 4081 </field> 4082 <field> 4083 <name>ID</name> 4084 <description>Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter.</description> 4085 <bitOffset>10</bitOffset> 4086 <bitWidth>6</bitWidth> 4087 </field> 4088 </fields> 4089 </register> 4090 <register> 4091 <name>SZ</name> 4092 <description>Memory Configuration Register.</description> 4093 <addressOffset>0x0004</addressOffset> 4094 <access>read-only</access> 4095 <resetValue>0x00080008</resetValue> 4096 <fields> 4097 <field> 4098 <name>CCH</name> 4099 <description>Cache Size. Indicates total size in Kbytes of cache.</description> 4100 <bitOffset>0</bitOffset> 4101 <bitWidth>16</bitWidth> 4102 </field> 4103 <field> 4104 <name>MEM</name> 4105 <description>Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller.</description> 4106 <bitOffset>16</bitOffset> 4107 <bitWidth>16</bitWidth> 4108 </field> 4109 </fields> 4110 </register> 4111 <register> 4112 <name>CTRL</name> 4113 <description>Cache Control and Status Register.</description> 4114 <addressOffset>0x0100</addressOffset> 4115 <fields> 4116 <field> 4117 <name>EN</name> 4118 <description>Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated.</description> 4119 <bitOffset>0</bitOffset> 4120 <bitWidth>1</bitWidth> 4121 <enumeratedValues> 4122 <enumeratedValue> 4123 <name>dis</name> 4124 <description>Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array.</description> 4125 <value>0</value> 4126 </enumeratedValue> 4127 <enumeratedValue> 4128 <name>en</name> 4129 <description>Cache Enabled.</description> 4130 <value>1</value> 4131 </enumeratedValue> 4132 </enumeratedValues> 4133 </field> 4134 <field> 4135 <name>WRITE_ALLOC</name> 4136 <description>Write Allocate Enable. This bit only writable while the cache is disabled.</description> 4137 <bitOffset>1</bitOffset> 4138 <bitWidth>1</bitWidth> 4139 <enumeratedValues> 4140 <enumeratedValue> 4141 <name>dis</name> 4142 <description>Write-no-allocate.</description> 4143 <value>0</value> 4144 </enumeratedValue> 4145 <enumeratedValue> 4146 <name>en</name> 4147 <description>Write-allocate enabled.</description> 4148 <value>1</value> 4149 </enumeratedValue> 4150 </enumeratedValues> 4151 </field> 4152 <field> 4153 <name>CWFST_DIS</name> 4154 <description>Critical word first and streaming disable. This bit only writeable while the cache is disabled.</description> 4155 <bitOffset>2</bitOffset> 4156 <bitWidth>1</bitWidth> 4157 <enumeratedValues> 4158 <enumeratedValue> 4159 <name>dis</name> 4160 <description>Critical word first and streaming disabled.</description> 4161 <value>1</value> 4162 </enumeratedValue> 4163 <enumeratedValue> 4164 <name>en</name> 4165 <description>Critical word first and streaming enabled.</description> 4166 <value>0</value> 4167 </enumeratedValue> 4168 </enumeratedValues> 4169 </field> 4170 <field> 4171 <name>RDY</name> 4172 <description>Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready.</description> 4173 <bitOffset>16</bitOffset> 4174 <bitWidth>1</bitWidth> 4175 <enumeratedValues> 4176 <enumeratedValue> 4177 <name>notReady</name> 4178 <description>Not Ready.</description> 4179 <value>0</value> 4180 </enumeratedValue> 4181 <enumeratedValue> 4182 <name>ready</name> 4183 <description>Ready.</description> 4184 <value>1</value> 4185 </enumeratedValue> 4186 </enumeratedValues> 4187 </field> 4188 </fields> 4189 </register> 4190 <register> 4191 <name>INVALIDATE</name> 4192 <description>Invalidate All Cache Contents. Any time this register location is written (regardless of the data value), the cache controller immediately begins invalidating the entire contents of the cache memory. The cache will be in bypass mode until the invalidate operation is complete. System software can examine the Cache Ready bit (CACHE_CTRL.CACHE_RDY) to determine when the invalidate operation is complete. Note that it is not necessary to disable the cache controller prior to beginning this operation. Reads from this register always return 0.</description> 4193 <addressOffset>0x0700</addressOffset> 4194 <fields> 4195 <field> 4196 <name>IA</name> 4197 <description>Invalidate all cache contents.</description> 4198 <bitOffset>0</bitOffset> 4199 <bitWidth>32</bitWidth> 4200 </field> 4201 </fields> 4202 </register> 4203 </registers> 4204 </peripheral> 4205<!--EMCC External Memory Cache Controller Registers.--> 4206 <peripheral> 4207 <name>FCR</name> 4208 <description>Function Control Register.</description> 4209 <baseAddress>0x40000800</baseAddress> 4210 <addressBlock> 4211 <offset>0x00</offset> 4212 <size>0x400</size> 4213 <usage>registers</usage> 4214 </addressBlock> 4215 <registers> 4216 <register> 4217 <name>FCTRL0</name> 4218 <description>Function Control 0.</description> 4219 <addressOffset>0x00</addressOffset> 4220 <access>read-write</access> 4221 <fields> 4222 <field> 4223 <name>RDSGCSEL</name> 4224 <description>Hyperbys RDS Gray Code Select.</description> 4225 <bitOffset>0</bitOffset> 4226 <bitWidth>6</bitWidth> 4227 </field> 4228 <field> 4229 <name>RDSGCSET</name> 4230 <description>Hyperbus RDS Set.</description> 4231 <bitOffset>6</bitOffset> 4232 <bitWidth>1</bitWidth> 4233 </field> 4234 <field> 4235 <name>HYPERCGDLY</name> 4236 <description>Hyperbus Clock Generator Delay.</description> 4237 <bitOffset>8</bitOffset> 4238 <bitWidth>6</bitWidth> 4239 </field> 4240 <field> 4241 <name>USBCLKSEL</name> 4242 <description>USB Core Clock Select.</description> 4243 <bitOffset>16</bitOffset> 4244 <bitWidth>2</bitWidth> 4245 </field> 4246 <field> 4247 <name>I2C0DGEN0</name> 4248 <description>I2C0 SDA Pad Deglitcher enable.</description> 4249 <bitOffset>20</bitOffset> 4250 <bitWidth>1</bitWidth> 4251 <enumeratedValues> 4252 <enumeratedValue> 4253 <name>dis</name> 4254 <description>Deglitcher disabled.</description> 4255 <value>0</value> 4256 </enumeratedValue> 4257 <enumeratedValue> 4258 <name>en</name> 4259 <description>Deglitcher enabled.</description> 4260 <value>1</value> 4261 </enumeratedValue> 4262 </enumeratedValues> 4263 </field> 4264 <field> 4265 <name>I2C0DGEN1</name> 4266 <description>I2C0 SCL Pad Deglitcher enable.</description> 4267 <bitOffset>21</bitOffset> 4268 <bitWidth>1</bitWidth> 4269 <enumeratedValues> 4270 <enumeratedValue> 4271 <name>dis</name> 4272 <description>Deglitcher disabled.</description> 4273 <value>0</value> 4274 </enumeratedValue> 4275 <enumeratedValue> 4276 <name>en</name> 4277 <description>Deglitcher enabled.</description> 4278 <value>1</value> 4279 </enumeratedValue> 4280 </enumeratedValues> 4281 </field> 4282 <field> 4283 <name>I2C1DGEN0</name> 4284 <description>I2C1 SDA Pad Deglitcher enable.</description> 4285 <bitOffset>22</bitOffset> 4286 <bitWidth>1</bitWidth> 4287 <enumeratedValues> 4288 <enumeratedValue> 4289 <name>dis</name> 4290 <description>Deglitcher disabled.</description> 4291 <value>0</value> 4292 </enumeratedValue> 4293 <enumeratedValue> 4294 <name>en</name> 4295 <description>Deglitcher enabled.</description> 4296 <value>1</value> 4297 </enumeratedValue> 4298 </enumeratedValues> 4299 </field> 4300 <field> 4301 <name>I2C1DGEN1</name> 4302 <description>I2C1 SCL Pad Deglitcher enable.</description> 4303 <bitOffset>23</bitOffset> 4304 <bitWidth>1</bitWidth> 4305 <enumeratedValues> 4306 <enumeratedValue> 4307 <name>dis</name> 4308 <description>Deglitcher disabled.</description> 4309 <value>0</value> 4310 </enumeratedValue> 4311 <enumeratedValue> 4312 <name>en</name> 4313 <description>Deglitcher enabled.</description> 4314 <value>1</value> 4315 </enumeratedValue> 4316 </enumeratedValues> 4317 </field> 4318 <field> 4319 <name>I2C2DGEN0</name> 4320 <description>I2C2 SDA Pad Deglitcher enable.</description> 4321 <bitOffset>24</bitOffset> 4322 <bitWidth>1</bitWidth> 4323 <enumeratedValues> 4324 <enumeratedValue> 4325 <name>dis</name> 4326 <description>Deglitcher disabled.</description> 4327 <value>0</value> 4328 </enumeratedValue> 4329 <enumeratedValue> 4330 <name>en</name> 4331 <description>Deglitcher enabled.</description> 4332 <value>1</value> 4333 </enumeratedValue> 4334 </enumeratedValues> 4335 </field> 4336 <field> 4337 <name>I2C2DGEN1</name> 4338 <description>I2C2 SCL Pad Deglitcher enable.</description> 4339 <bitOffset>25</bitOffset> 4340 <bitWidth>1</bitWidth> 4341 <enumeratedValues> 4342 <enumeratedValue> 4343 <name>dis</name> 4344 <description>Deglitcher disabled.</description> 4345 <value>0</value> 4346 </enumeratedValue> 4347 <enumeratedValue> 4348 <name>en</name> 4349 <description>Deglitcher enabled.</description> 4350 <value>1</value> 4351 </enumeratedValue> 4352 </enumeratedValues> 4353 </field> 4354 </fields> 4355 </register> 4356 <register> 4357 <name>AUTOCAL0</name> 4358 <description>Automatic Calibration 0.</description> 4359 <addressOffset>0x04</addressOffset> 4360 <access>read-write</access> 4361 <fields> 4362 <field> 4363 <name>ACEN</name> 4364 <description>Auto-calibration Enable.</description> 4365 <bitOffset>0</bitOffset> 4366 <bitWidth>1</bitWidth> 4367 <enumeratedValues> 4368 <enumeratedValue> 4369 <name>dis</name> 4370 <description>Disabled.</description> 4371 <value>0</value> 4372 </enumeratedValue> 4373 <enumeratedValue> 4374 <name>en</name> 4375 <description>Enabled.</description> 4376 <value>1</value> 4377 </enumeratedValue> 4378 </enumeratedValues> 4379 </field> 4380 <field> 4381 <name>ACRUN</name> 4382 <description>Autocalibration Run.</description> 4383 <bitOffset>1</bitOffset> 4384 <bitWidth>1</bitWidth> 4385 <enumeratedValues> 4386 <enumeratedValue> 4387 <name>not</name> 4388 <description>Not Running.</description> 4389 <value>0</value> 4390 </enumeratedValue> 4391 <enumeratedValue> 4392 <name>run</name> 4393 <description>Running.</description> 4394 <value>1</value> 4395 </enumeratedValue> 4396 </enumeratedValues> 4397 </field> 4398 <field> 4399 <name>LDTRM</name> 4400 <description>Load Trim.</description> 4401 <bitOffset>2</bitOffset> 4402 <bitWidth>1</bitWidth> 4403 </field> 4404 <field> 4405 <name>GAININV</name> 4406 <description>Invert Gain.</description> 4407 <bitOffset>3</bitOffset> 4408 <bitWidth>1</bitWidth> 4409 <enumeratedValues> 4410 <enumeratedValue> 4411 <name>not</name> 4412 <description>Not Running.</description> 4413 <value>0</value> 4414 </enumeratedValue> 4415 <enumeratedValue> 4416 <name>run</name> 4417 <description>Running.</description> 4418 <value>1</value> 4419 </enumeratedValue> 4420 </enumeratedValues> 4421 </field> 4422 <field> 4423 <name>ATOMIC</name> 4424 <description>Atomic mode.</description> 4425 <bitOffset>4</bitOffset> 4426 <bitWidth>1</bitWidth> 4427 <enumeratedValues> 4428 <enumeratedValue> 4429 <name>not</name> 4430 <description>Not Running.</description> 4431 <value>0</value> 4432 </enumeratedValue> 4433 <enumeratedValue> 4434 <name>run</name> 4435 <description>Running.</description> 4436 <value>1</value> 4437 </enumeratedValue> 4438 </enumeratedValues> 4439 </field> 4440 <field> 4441 <name>MU</name> 4442 <description>MU value.</description> 4443 <bitOffset>8</bitOffset> 4444 <bitWidth>12</bitWidth> 4445 </field> 4446 <field> 4447 <name>HIRC96MACTMROUT</name> 4448 <description>HIRC96M Trim Value.</description> 4449 <bitOffset>23</bitOffset> 4450 <bitWidth>9</bitWidth> 4451 </field> 4452 </fields> 4453 </register> 4454 <register> 4455 <name>AUTOCAL1</name> 4456 <description>Automatic Calibration 1.</description> 4457 <addressOffset>0x08</addressOffset> 4458 <access>read-write</access> 4459 <fields> 4460 <field> 4461 <name>INITTRM</name> 4462 <description>Initial Trim Setting.</description> 4463 <bitOffset>0</bitOffset> 4464 <bitWidth>9</bitWidth> 4465 </field> 4466 </fields> 4467 </register> 4468 <register> 4469 <name>AUTOCAL2</name> 4470 <description>Automatic Calibration 2</description> 4471 <addressOffset>0x0C</addressOffset> 4472 <access>read-write</access> 4473 <fields> 4474 <field> 4475 <name>DONECNT</name> 4476 <description>Auto-callibration Done Counter Setting.</description> 4477 <bitOffset>0</bitOffset> 4478 <bitWidth>8</bitWidth> 4479 </field> 4480 <field> 4481 <name>ACDIV</name> 4482 <description>Auto-callibration Div Setting.</description> 4483 <bitOffset>8</bitOffset> 4484 <bitWidth>13</bitWidth> 4485 </field> 4486 </fields> 4487 </register> 4488 <register> 4489 <name>URVBOOTADDR</name> 4490 <description>RISC-V Boot Address.</description> 4491 <addressOffset>0x10</addressOffset> 4492 <access>read-write</access> 4493 </register> 4494 <register> 4495 <name>URVCTRL</name> 4496 <description>RISC-V Control Register.</description> 4497 <addressOffset>0x14</addressOffset> 4498 <access>read-write</access> 4499 <fields> 4500 <field> 4501 <name>MEMSEL</name> 4502 <description>RAM2, RAM3 exclusive ownership.</description> 4503 <bitOffset>0</bitOffset> 4504 <bitWidth>1</bitWidth> 4505 </field> 4506 <field> 4507 <name>IFLUSHEN</name> 4508 <description>URV instruction flush enable.</description> 4509 <bitOffset>1</bitOffset> 4510 <bitWidth>1</bitWidth> 4511 </field> 4512 </fields> 4513 </register> 4514 <register> 4515 <name>XO32MKS</name> 4516 <description>RISC-V Control Register.</description> 4517 <addressOffset>0x18</addressOffset> 4518 <access>read-write</access> 4519 <fields> 4520 <field> 4521 <name>CLK</name> 4522 <description>Kick Start XO Counter Setting</description> 4523 <bitOffset>0</bitOffset> 4524 <bitWidth>7</bitWidth> 4525 </field> 4526 <field> 4527 <name>EN</name> 4528 <description>Kick Start XO Enable</description> 4529 <bitOffset>7</bitOffset> 4530 <bitWidth>1</bitWidth> 4531 </field> 4532 <field> 4533 <name>DRIVER</name> 4534 <description>Kick Start XO Driver</description> 4535 <bitOffset>8</bitOffset> 4536 <bitWidth>3</bitWidth> 4537 </field> 4538 <field> 4539 <name>PULSE</name> 4540 <description>Kick Start XO 2X Pulse</description> 4541 <bitOffset>11</bitOffset> 4542 <bitWidth>1</bitWidth> 4543 </field> 4544 <field> 4545 <name>CLKSEL</name> 4546 <description>Kick Start XO Clock Select</description> 4547 <bitOffset>12</bitOffset> 4548 <bitWidth>2</bitWidth> 4549 <enumeratedValues> 4550 <enumeratedValue> 4551 <name>none</name> 4552 <description>No kick start clock.</description> 4553 <value>0</value> 4554 </enumeratedValue> 4555 <enumeratedValue> 4556 <name>test</name> 4557 <description>Test Clock in P1.2 (TMR3[22]=1).</description> 4558 <value>1</value> 4559 </enumeratedValue> 4560 <enumeratedValue> 4561 <name>ISO</name> 4562 <description>Internal secondary oscilator</description> 4563 <value>2</value> 4564 </enumeratedValue> 4565 <enumeratedValue> 4566 <name>IPO</name> 4567 <description>Internal Primary Oscilator</description> 4568 <value>3</value> 4569 </enumeratedValue> 4570 </enumeratedValues> 4571 </field> 4572 </fields> 4573 </register> 4574 <register> 4575 <name>SARBUFCN</name> 4576 <description>TBD</description> 4577 <addressOffset>0x1C</addressOffset> 4578 <access>read-write</access> 4579 <fields> 4580 <field> 4581 <name>THRU_PAD_SW_EN</name> 4582 <description>TBD</description> 4583 <bitOffset>0</bitOffset> 4584 <bitWidth>8</bitWidth> 4585 </field> 4586 <field> 4587 <name>THRU_EN</name> 4588 <description>TBD</description> 4589 <bitOffset>8</bitOffset> 4590 <bitWidth>1</bitWidth> 4591 </field> 4592 <field> 4593 <name>RAMP_EN</name> 4594 <description>TBD</description> 4595 <bitOffset>9</bitOffset> 4596 <bitWidth>1</bitWidth> 4597 </field> 4598 <field> 4599 <name>THRU_RRI_EN</name> 4600 <description>TBD</description> 4601 <bitOffset>10</bitOffset> 4602 <bitWidth>1</bitWidth> 4603 </field> 4604 <field> 4605 <name>DIVSEL</name> 4606 <description>TBD</description> 4607 <bitOffset>11</bitOffset> 4608 <bitWidth>1</bitWidth> 4609 </field> 4610 </fields> 4611 </register> 4612 <register> 4613 <name>TS0</name> 4614 <description>Temp Sensor trim0</description> 4615 <addressOffset>0x20</addressOffset> 4616 <access>read-write</access> 4617 <fields> 4618 <field> 4619 <name>GAIN</name> 4620 <description>Unsigned gain for temp sensor normalization Temp degrees C = (ADC result * TS_GAIN) + TS_OFFSET.</description> 4621 <bitOffset>0</bitOffset> 4622 <bitWidth>12</bitWidth> 4623 </field> 4624 </fields> 4625 </register> 4626 <register> 4627 <name>TS1</name> 4628 <description>Temp Sensor trim1</description> 4629 <addressOffset>0x24</addressOffset> 4630 <access>read-write</access> 4631 <fields> 4632 <field> 4633 <name>OFFSET</name> 4634 <description>Signed gain for temp sensor normalization Temp degrees C = (ADC result * TS_GAIN) + TS_OFFSET.</description> 4635 <bitOffset>0</bitOffset> 4636 <bitWidth>14</bitWidth> 4637 </field> 4638 <field> 4639 <name>TS_OFFSET_SIGN</name> 4640 <description>Sign extension of TS_OFFSET[13:0]</description> 4641 <bitOffset>14</bitOffset> 4642 <bitWidth>18</bitWidth> 4643 </field> 4644 </fields> 4645 </register> 4646 <register> 4647 <name>ADCREFTRIM0</name> 4648 <description>Temp Sensor trim1</description> 4649 <addressOffset>0x28</addressOffset> 4650 <access>read-write</access> 4651 <fields> 4652 <field> 4653 <name>VREFP</name> 4654 <description>Trimming code for VREFP output of reference buffer</description> 4655 <bitOffset>0</bitOffset> 4656 <bitWidth>7</bitWidth> 4657 </field> 4658 <field> 4659 <name>VREFM</name> 4660 <description>Trimming code for VREFM output of reference buffer</description> 4661 <bitOffset>8</bitOffset> 4662 <bitWidth>7</bitWidth> 4663 </field> 4664 <field> 4665 <name>VCM</name> 4666 <description>Trimming code for VCM output of reference buffer</description> 4667 <bitOffset>16</bitOffset> 4668 <bitWidth>2</bitWidth> 4669 </field> 4670 <field> 4671 <name>VX2_TUNE</name> 4672 <description>Controls tuning capacitor in fine DAC (offset binary)</description> 4673 <bitOffset>24</bitOffset> 4674 <bitWidth>6</bitWidth> 4675 </field> 4676 </fields> 4677 </register> 4678 <register> 4679 <name>ADCREFTRIM1</name> 4680 <description>Temp Sensor trim1</description> 4681 <addressOffset>0x2C</addressOffset> 4682 <access>read-write</access> 4683 <fields> 4684 <field> 4685 <name>VREFP</name> 4686 <description>Trimming code for VREFP output of reference buffer</description> 4687 <bitOffset>0</bitOffset> 4688 <bitWidth>7</bitWidth> 4689 </field> 4690 <field> 4691 <name>VREFM</name> 4692 <description>Trimming code for VREFM output of reference buffer</description> 4693 <bitOffset>8</bitOffset> 4694 <bitWidth>7</bitWidth> 4695 </field> 4696 <field> 4697 <name>VCM</name> 4698 <description>Trimming code for VCM output of reference buffer</description> 4699 <bitOffset>16</bitOffset> 4700 <bitWidth>2</bitWidth> 4701 </field> 4702 <field> 4703 <name>VX2_TUNE</name> 4704 <description>Controls tuning capacitor in fine DAC (offset binary)</description> 4705 <bitOffset>24</bitOffset> 4706 <bitWidth>6</bitWidth> 4707 </field> 4708 </fields> 4709 </register> 4710 <register> 4711 <name>ADCREFTRIM2</name> 4712 <description>Temp Sensor trim1</description> 4713 <addressOffset>0x30</addressOffset> 4714 <access>read-write</access> 4715 <fields> 4716 <field> 4717 <name>IDRV_1P25</name> 4718 <description>Trimming code for reference buffer drive strength. 1.25V</description> 4719 <bitOffset>0</bitOffset> 4720 <bitWidth>4</bitWidth> 4721 </field> 4722 <field> 4723 <name>IBOOST_1P25</name> 4724 <description>Trimming value for extra drive current in reference buffer outputs. 2.048V</description> 4725 <bitOffset>4</bitOffset> 4726 <bitWidth>1</bitWidth> 4727 </field> 4728 <field> 4729 <name>IDRV_2P048</name> 4730 <description>Trimming code for reference buffer drive strength. 2.048V</description> 4731 <bitOffset>8</bitOffset> 4732 <bitWidth>4</bitWidth> 4733 </field> 4734 <field> 4735 <name>IBOOST_2P048</name> 4736 <description>Trimming value for extra drive current in reference buffer outputs. 2.048V</description> 4737 <bitOffset>12</bitOffset> 4738 <bitWidth>1</bitWidth> 4739 </field> 4740 <field> 4741 <name>VCM</name> 4742 <description>Trimming code for VCM output of reference buffer</description> 4743 <bitOffset>16</bitOffset> 4744 <bitWidth>2</bitWidth> 4745 </field> 4746 <field> 4747 <name>VX2_TUNE</name> 4748 <description>Controls tuning capacitor in fine DAC (offset binary)</description> 4749 <bitOffset>24</bitOffset> 4750 <bitWidth>6</bitWidth> 4751 </field> 4752 </fields> 4753 </register> 4754 </registers> 4755 </peripheral> 4756<!--FCR Function Control Register.--> 4757 <peripheral> 4758 <name>FLC</name> 4759 <description>Flash Memory Control.</description> 4760 <prependToName>FLSH_</prependToName> 4761 <baseAddress>0x40029000</baseAddress> 4762 <addressBlock> 4763 <offset>0x00</offset> 4764 <size>0x1000</size> 4765 <usage>registers</usage> 4766 </addressBlock> 4767 <interrupt> 4768 <name>Flash_Controller</name> 4769 <description>Flash Controller interrupt.</description> 4770 <value>23</value> 4771 </interrupt> 4772 <registers> 4773 <register> 4774 <name>ADDR</name> 4775 <description>Flash Write Address.</description> 4776 <addressOffset>0x00</addressOffset> 4777 <fields> 4778 <field> 4779 <name>ADDR</name> 4780 <description>Address for next operation.</description> 4781 <bitOffset>0</bitOffset> 4782 <bitWidth>32</bitWidth> 4783 </field> 4784 </fields> 4785 </register> 4786 <register> 4787 <name>CLKDIV</name> 4788 <description>Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller.</description> 4789 <addressOffset>0x04</addressOffset> 4790 <resetValue>0x00000064</resetValue> 4791 <fields> 4792 <field> 4793 <name>CLKDIV</name> 4794 <description>Flash Clock Divide. The clock is divided by this value to generate a 1MHz clock for flash controller.</description> 4795 <bitOffset>0</bitOffset> 4796 <bitWidth>8</bitWidth> 4797 </field> 4798 </fields> 4799 </register> 4800 <register> 4801 <name>CTRL</name> 4802 <description>Flash Control Register.</description> 4803 <addressOffset>0x08</addressOffset> 4804 <fields> 4805 <field> 4806 <name>WR</name> 4807 <description>Write. This bit is automatically cleared after the operation.</description> 4808 <bitOffset>0</bitOffset> 4809 <bitWidth>1</bitWidth> 4810 <enumeratedValues> 4811 <enumeratedValue> 4812 <name>complete</name> 4813 <description>No operation/complete.</description> 4814 <value>0</value> 4815 </enumeratedValue> 4816 <enumeratedValue> 4817 <name>start</name> 4818 <description>Start operation.</description> 4819 <value>1</value> 4820 </enumeratedValue> 4821 </enumeratedValues> 4822 </field> 4823 <field derivedFrom="WR"> 4824 <name>ME</name> 4825 <description>Mass Erase. This bit is automatically cleared after the operation.</description> 4826 <bitOffset>1</bitOffset> 4827 <bitWidth>1</bitWidth> 4828 </field> 4829 <field derivedFrom="WR"> 4830 <name>PGE</name> 4831 <description>Page Erase. This bit is automatically cleared after the operation.</description> 4832 <bitOffset>2</bitOffset> 4833 <bitWidth>1</bitWidth> 4834 </field> 4835 <field> 4836 <name>WDTH</name> 4837 <description>TBD</description> 4838 <bitOffset>4</bitOffset> 4839 <bitWidth>1</bitWidth> 4840 </field> 4841 <field> 4842 <name>ERASE_CODE</name> 4843 <description>Erase Code. The ERASE_CODE must be set up property before erase operation can be initiated. These bits are automatically cleared after the operation is complete.</description> 4844 <bitOffset>8</bitOffset> 4845 <bitWidth>8</bitWidth> 4846 <enumeratedValues> 4847 <enumeratedValue> 4848 <name>nop</name> 4849 <description>No operation.</description> 4850 <value>0</value> 4851 </enumeratedValue> 4852 <enumeratedValue> 4853 <name>erasePage</name> 4854 <description>Enable Page Erase.</description> 4855 <value>0x55</value> 4856 </enumeratedValue> 4857 <enumeratedValue> 4858 <name>eraseAll</name> 4859 <description>Enable Mass Erase. The debug port must be enabled.</description> 4860 <value>0xAA</value> 4861 </enumeratedValue> 4862 </enumeratedValues> 4863 </field> 4864 <field> 4865 <name>PEND</name> 4866 <description>Flash Pending. When Flash operation is in progress (busy), Flash reads and writes will fail. When PEND is set, write to all Flash registers, with exception of the Flash interrupt register, are ignored.</description> 4867 <bitOffset>24</bitOffset> 4868 <bitWidth>1</bitWidth> 4869 <access>read-only</access> 4870 <enumeratedValues> 4871 <enumeratedValue> 4872 <name>idle</name> 4873 <description>Idle.</description> 4874 <value>0</value> 4875 </enumeratedValue> 4876 <enumeratedValue> 4877 <name>busy</name> 4878 <description>Busy.</description> 4879 <value>1</value> 4880 </enumeratedValue> 4881 </enumeratedValues> 4882 </field> 4883 <field> 4884 <name>LVE</name> 4885 <description>Low Voltage enable.</description> 4886 <bitOffset>25</bitOffset> 4887 <bitWidth>1</bitWidth> 4888 </field> 4889 <field> 4890 <name>UNLOCK</name> 4891 <description>Flash Unlock. The correct unlock code must be written to these four bits before any Flash write or erase operation is allowed.</description> 4892 <bitOffset>28</bitOffset> 4893 <bitWidth>4</bitWidth> 4894 <enumeratedValues> 4895 <enumeratedValue> 4896 <name>unlocked</name> 4897 <description>Flash Unlocked.</description> 4898 <value>2</value> 4899 </enumeratedValue> 4900 <enumeratedValue> 4901 <name>locked</name> 4902 <description>Flash Locked.</description> 4903 <value>3</value> 4904 </enumeratedValue> 4905 </enumeratedValues> 4906 </field> 4907 </fields> 4908 </register> 4909 <register> 4910 <name>INTR</name> 4911 <description>Flash Interrupt Register.</description> 4912 <addressOffset>0x024</addressOffset> 4913 <fields> 4914 <field> 4915 <name>DONE</name> 4916 <description>Flash Done Interrupt. This bit is set to 1 upon Flash write or erase completion.</description> 4917 <bitOffset>0</bitOffset> 4918 <bitWidth>1</bitWidth> 4919 <enumeratedValues> 4920 <enumeratedValue> 4921 <name>inactive</name> 4922 <description>No interrupt is pending.</description> 4923 <value>0</value> 4924 </enumeratedValue> 4925 <enumeratedValue> 4926 <name>pending</name> 4927 <description>An interrupt is pending.</description> 4928 <value>1</value> 4929 </enumeratedValue> 4930 </enumeratedValues> 4931 </field> 4932 <field> 4933 <name>AF</name> 4934 <description>Flash Access Fail. This bit is set when an attempt is made to write the flash while the flash is busy or the flash is locked. This bit can only be set to 1 by hardware.</description> 4935 <bitOffset>1</bitOffset> 4936 <bitWidth>1</bitWidth> 4937 <enumeratedValues> 4938 <enumeratedValue> 4939 <name>noerr</name> 4940 <description>No Failure.</description> 4941 <value>0</value> 4942 </enumeratedValue> 4943 <enumeratedValue> 4944 <name>error</name> 4945 <description>Failure occurs.</description> 4946 <value>1</value> 4947 </enumeratedValue> 4948 </enumeratedValues> 4949 </field> 4950 <field> 4951 <name>PROG_PROT_ERR</name> 4952 <description>Program Protection Error.</description> 4953 <bitOffset>2</bitOffset> 4954 <bitWidth>1</bitWidth> 4955 <enumeratedValues> 4956 <enumeratedValue> 4957 <name>noerr</name> 4958 <description>No Failure.</description> 4959 <value>0</value> 4960 </enumeratedValue> 4961 <enumeratedValue> 4962 <name>error</name> 4963 <description>Failure occurs.</description> 4964 <value>1</value> 4965 </enumeratedValue> 4966 </enumeratedValues> 4967 </field> 4968 <field> 4969 <name>MASS_ER_PROT_ERR</name> 4970 <description>TBD</description> 4971 <bitOffset>3</bitOffset> 4972 <bitWidth>1</bitWidth> 4973 <enumeratedValues> 4974 <enumeratedValue> 4975 <name>noerr</name> 4976 <description>No Failure.</description> 4977 <value>0</value> 4978 </enumeratedValue> 4979 <enumeratedValue> 4980 <name>error</name> 4981 <description>Failure occurs.</description> 4982 <value>1</value> 4983 </enumeratedValue> 4984 </enumeratedValues> 4985 </field> 4986 <field> 4987 <name>PAGE_ER_PROT_ERR</name> 4988 <description>TBD</description> 4989 <bitOffset>4</bitOffset> 4990 <bitWidth>1</bitWidth> 4991 <enumeratedValues> 4992 <enumeratedValue> 4993 <name>noerr</name> 4994 <description>No Failure.</description> 4995 <value>0</value> 4996 </enumeratedValue> 4997 <enumeratedValue> 4998 <name>error</name> 4999 <description>Failure occurs.</description> 5000 <value>1</value> 5001 </enumeratedValue> 5002 </enumeratedValues> 5003 </field> 5004 <field> 5005 <name>PROT_AREA_PROT_ERR</name> 5006 <description>TBD</description> 5007 <bitOffset>5</bitOffset> 5008 <bitWidth>1</bitWidth> 5009 <enumeratedValues> 5010 <enumeratedValue> 5011 <name>noerr</name> 5012 <description>No Failure.</description> 5013 <value>0</value> 5014 </enumeratedValue> 5015 <enumeratedValue> 5016 <name>error</name> 5017 <description>Failure occurs.</description> 5018 <value>1</value> 5019 </enumeratedValue> 5020 </enumeratedValues> 5021 </field> 5022 <field> 5023 <name>DONEIE</name> 5024 <description>Flash Done Interrupt Enable.</description> 5025 <bitOffset>8</bitOffset> 5026 <bitWidth>1</bitWidth> 5027 <enumeratedValues> 5028 <enumeratedValue> 5029 <name>dis</name> 5030 <description>Disable.</description> 5031 <value>0</value> 5032 </enumeratedValue> 5033 <enumeratedValue> 5034 <name>en</name> 5035 <description>Enable.</description> 5036 <value>1</value> 5037 </enumeratedValue> 5038 </enumeratedValues> 5039 </field> 5040 <field> 5041 <name>AFIE</name> 5042 <bitOffset>9</bitOffset> 5043 <bitWidth>1</bitWidth> 5044 <enumeratedValues> 5045 <enumeratedValue> 5046 <name>dis</name> 5047 <description>Disable.</description> 5048 <value>0</value> 5049 </enumeratedValue> 5050 <enumeratedValue> 5051 <name>en</name> 5052 <description>Enable.</description> 5053 <value>1</value> 5054 </enumeratedValue> 5055 </enumeratedValues> 5056 </field> 5057 <field> 5058 <name>PROTIE</name> 5059 <bitOffset>10</bitOffset> 5060 <bitWidth>1</bitWidth> 5061 <enumeratedValues> 5062 <enumeratedValue> 5063 <name>dis</name> 5064 <description>Disable.</description> 5065 <value>0</value> 5066 </enumeratedValue> 5067 <enumeratedValue> 5068 <name>en</name> 5069 <description>Enable.</description> 5070 <value>1</value> 5071 </enumeratedValue> 5072 </enumeratedValues> 5073 </field> 5074 </fields> 5075 </register> 5076 <register> 5077 <dim>4</dim> 5078 <dimIncrement>4</dimIncrement> 5079 <name>DATA[%s]</name> 5080 <description>Flash Write Data.</description> 5081 <addressOffset>0x30</addressOffset> 5082 <fields> 5083 <field> 5084 <name>DATA</name> 5085 <description>Data next operation.</description> 5086 <bitOffset>0</bitOffset> 5087 <bitWidth>32</bitWidth> 5088 </field> 5089 </fields> 5090 </register> 5091 <register> 5092 <name>ACTRL</name> 5093 <description>Access Control Register. Writing the ACNTL register with the following values in the order shown, allows read and write access to the system and user Information block: pflc-acntl = 0x3a7f5ca3; pflc-acntl = 0xa1e34f20; pflc-acntl = 0x9608b2c1. When unlocked, a write of any word will disable access to system and user information block. Readback of this register is always zero.</description> 5094 <addressOffset>0x40</addressOffset> 5095 <access>write-only</access> 5096 <fields> 5097 <field> 5098 <name>ACTRL</name> 5099 <description>Access control.</description> 5100 <bitOffset>0</bitOffset> 5101 <bitWidth>32</bitWidth> 5102 </field> 5103 </fields> 5104 </register> 5105 <register> 5106 <name>WELR0</name> 5107 <description>Access control.</description> 5108 <addressOffset>0x80</addressOffset> 5109 <access>read-write</access> 5110 <fields> 5111 <field> 5112 <name>WELR0</name> 5113 <description>TBD</description> 5114 <bitOffset>0</bitOffset> 5115 <bitWidth>32</bitWidth> 5116 </field> 5117 </fields> 5118 </register> 5119 <register> 5120 <name>RLR0</name> 5121 <description>Access control.</description> 5122 <addressOffset>0x84</addressOffset> 5123 <access>read-write</access> 5124 <fields> 5125 <field> 5126 <name>RLR0</name> 5127 <description>TBD</description> 5128 <bitOffset>0</bitOffset> 5129 <bitWidth>32</bitWidth> 5130 </field> 5131 </fields> 5132 </register> 5133 <register> 5134 <name>WELR1</name> 5135 <description>Access control.</description> 5136 <addressOffset>0x88</addressOffset> 5137 <access>read-write</access> 5138 <fields> 5139 <field> 5140 <name>WELR1</name> 5141 <description>TBD</description> 5142 <bitOffset>0</bitOffset> 5143 <bitWidth>32</bitWidth> 5144 </field> 5145 </fields> 5146 </register> 5147 <register> 5148 <name>RLR1</name> 5149 <description>Access control.</description> 5150 <addressOffset>0x8C</addressOffset> 5151 <access>read-write</access> 5152 <fields> 5153 <field> 5154 <name>RLR1</name> 5155 <description>TBD</description> 5156 <bitOffset>0</bitOffset> 5157 <bitWidth>32</bitWidth> 5158 </field> 5159 </fields> 5160 </register> 5161 <register> 5162 <name>WELR2</name> 5163 <description>Access control.</description> 5164 <addressOffset>0x90</addressOffset> 5165 <access>read-write</access> 5166 <fields> 5167 <field> 5168 <name>WELR2</name> 5169 <description>TBD</description> 5170 <bitOffset>0</bitOffset> 5171 <bitWidth>32</bitWidth> 5172 </field> 5173 </fields> 5174 </register> 5175 <register> 5176 <name>RLR2</name> 5177 <description>Access control.</description> 5178 <addressOffset>0x94</addressOffset> 5179 <access>read-write</access> 5180 <fields> 5181 <field> 5182 <name>RLR2</name> 5183 <description>TBD</description> 5184 <bitOffset>0</bitOffset> 5185 <bitWidth>32</bitWidth> 5186 </field> 5187 </fields> 5188 </register> 5189 <register> 5190 <name>WELR3</name> 5191 <description>Access control.</description> 5192 <addressOffset>0x98</addressOffset> 5193 <access>read-write</access> 5194 <fields> 5195 <field> 5196 <name>WELR3</name> 5197 <description>TBD</description> 5198 <bitOffset>0</bitOffset> 5199 <bitWidth>32</bitWidth> 5200 </field> 5201 </fields> 5202 </register> 5203 <register> 5204 <name>RLR3</name> 5205 <description>Access control.</description> 5206 <addressOffset>0x9C</addressOffset> 5207 <access>read-write</access> 5208 <fields> 5209 <field> 5210 <name>RLR3</name> 5211 <description>TBD</description> 5212 <bitOffset>0</bitOffset> 5213 <bitWidth>32</bitWidth> 5214 </field> 5215 </fields> 5216 </register> 5217 <register> 5218 <name>WELR4</name> 5219 <description>Access control.</description> 5220 <addressOffset>0xA0</addressOffset> 5221 <access>read-write</access> 5222 <fields> 5223 <field> 5224 <name>WELR4</name> 5225 <description>TBD</description> 5226 <bitOffset>0</bitOffset> 5227 <bitWidth>32</bitWidth> 5228 </field> 5229 </fields> 5230 </register> 5231 <register> 5232 <name>RLR4</name> 5233 <description>Access control.</description> 5234 <addressOffset>0xA4</addressOffset> 5235 <access>read-write</access> 5236 <fields> 5237 <field> 5238 <name>RLR4</name> 5239 <description>TBD</description> 5240 <bitOffset>0</bitOffset> 5241 <bitWidth>32</bitWidth> 5242 </field> 5243 </fields> 5244 </register> 5245 <register> 5246 <name>WELR5</name> 5247 <description>Access control.</description> 5248 <addressOffset>0xA8</addressOffset> 5249 <access>read-write</access> 5250 <fields> 5251 <field> 5252 <name>WELR5</name> 5253 <description>TBD</description> 5254 <bitOffset>0</bitOffset> 5255 <bitWidth>32</bitWidth> 5256 </field> 5257 </fields> 5258 </register> 5259 <register> 5260 <name>RLR5</name> 5261 <description>Access control.</description> 5262 <addressOffset>0xAC</addressOffset> 5263 <access>read-write</access> 5264 <fields> 5265 <field> 5266 <name>RLR5</name> 5267 <description>TBD</description> 5268 <bitOffset>0</bitOffset> 5269 <bitWidth>32</bitWidth> 5270 </field> 5271 </fields> 5272 </register> 5273 </registers> 5274 </peripheral> 5275<!--FLC Flash Memory Control.--> 5276 <peripheral> 5277 <name>HPB</name> 5278 <description>HyperBus Memory Controller Registers</description> 5279 <baseAddress>0x40039000</baseAddress> 5280 <addressBlock> 5281 <offset>0x00</offset> 5282 <size>0x1000</size> 5283 <usage>registers</usage> 5284 </addressBlock> 5285 <registers> 5286 <register> 5287 <name>STAT</name> 5288 <description>Hyperbus Status Register.</description> 5289 <addressOffset>0x0000</addressOffset> 5290 <fields> 5291 <field> 5292 <name>RDTXN</name> 5293 <description>Read Transaction in Progress</description> 5294 <bitOffset>0</bitOffset> 5295 <bitWidth>1</bitWidth> 5296 <enumeratedValues> 5297 <enumeratedValue> 5298 <name>noread</name> 5299 <description>No read transaction currently in progress.</description> 5300 <value>0</value> 5301 </enumeratedValue> 5302 <enumeratedValue> 5303 <name>read</name> 5304 <description>Read transaction currently in progress.</description> 5305 <value>1</value> 5306 </enumeratedValue> 5307 </enumeratedValues> 5308 </field> 5309 <field> 5310 <name>RDADDRERR</name> 5311 <description>Read Address Error</description> 5312 <bitOffset>8</bitOffset> 5313 <bitWidth>1</bitWidth> 5314 <enumeratedValues> 5315 <enumeratedValue> 5316 <name>normal_op</name> 5317 <description>No error.</description> 5318 <value>0</value> 5319 </enumeratedValue> 5320 <enumeratedValue> 5321 <name>err</name> 5322 <description>External read address not responding.</description> 5323 <value>1</value> 5324 </enumeratedValue> 5325 </enumeratedValues> 5326 </field> 5327 <field> 5328 <name>RDSLVST</name> 5329 <description>Read Slave Status.</description> 5330 <bitOffset>9</bitOffset> 5331 <bitWidth>1</bitWidth> 5332 </field> 5333 <field> 5334 <name>RDRSTERR</name> 5335 <description>Reset During Read Error. If this field is set a reset orrcured during a read.</description> 5336 <bitOffset>10</bitOffset> 5337 <bitWidth>1</bitWidth> 5338 <enumeratedValues> 5339 <enumeratedValue> 5340 <name>normal_op</name> 5341 <description>No error.</description> 5342 <value>0</value> 5343 </enumeratedValue> 5344 <enumeratedValue> 5345 <name>err</name> 5346 <description>Memory controller was reset during read operation.</description> 5347 <value>1</value> 5348 </enumeratedValue> 5349 </enumeratedValues> 5350 </field> 5351 <field> 5352 <name>RDSTALL</name> 5353 <description>Read Data Stall.</description> 5354 <bitOffset>11</bitOffset> 5355 <bitWidth>1</bitWidth> 5356 <enumeratedValues> 5357 <enumeratedValue> 5358 <name>normal_op</name> 5359 <description>Memory Controller operating normally.</description> 5360 <value>0</value> 5361 </enumeratedValue> 5362 <enumeratedValue> 5363 <name>stalled</name> 5364 <description>Read transaction is stalled because RDS is low (stalled).</description> 5365 <value>1</value> 5366 </enumeratedValue> 5367 </enumeratedValues> 5368 </field> 5369 <field> 5370 <name>WRTXN</name> 5371 <description>Write Transaction in Progress</description> 5372 <bitOffset>16</bitOffset> 5373 <bitWidth>1</bitWidth> 5374 <enumeratedValues> 5375 <enumeratedValue> 5376 <name>nowrite</name> 5377 <description>No write transaction currently in progress.</description> 5378 <value>0</value> 5379 </enumeratedValue> 5380 <enumeratedValue> 5381 <name>write</name> 5382 <description>Write transaction currently in progress.</description> 5383 <value>1</value> 5384 </enumeratedValue> 5385 </enumeratedValues> 5386 </field> 5387 <field> 5388 <name>WRADDRERR</name> 5389 <description>Write Address Error. If this field is set a write address error orrcured.</description> 5390 <bitOffset>24</bitOffset> 5391 <bitWidth>1</bitWidth> 5392 <enumeratedValues> 5393 <enumeratedValue> 5394 <name>normal_op</name> 5395 <description>No error.</description> 5396 <value>0</value> 5397 </enumeratedValue> 5398 <enumeratedValue> 5399 <name>err</name> 5400 <description>The write address to external memory is invalid.</description> 5401 <value>1</value> 5402 </enumeratedValue> 5403 </enumeratedValues> 5404 </field> 5405 <field> 5406 <name>WRRSTERR</name> 5407 <description>Reset During Write Error. If this field is set a reset orrcured during a write.</description> 5408 <bitOffset>26</bitOffset> 5409 <bitWidth>1</bitWidth> 5410 <enumeratedValues> 5411 <enumeratedValue> 5412 <name>normal_op</name> 5413 <description>No error.</description> 5414 <value>0</value> 5415 </enumeratedValue> 5416 <enumeratedValue> 5417 <name>err</name> 5418 <description>Memory controller was reset during write operation.</description> 5419 <value>1</value> 5420 </enumeratedValue> 5421 </enumeratedValues> 5422 </field> 5423 </fields> 5424 </register> 5425 <register> 5426 <name>INTEN</name> 5427 <description>Hyperbus Interrupt Enable Register.</description> 5428 <addressOffset>0x0004</addressOffset> 5429 <fields> 5430 <field> 5431 <name>MEM</name> 5432 <description>Hyperbus Memory Interrupt Enable.</description> 5433 <bitOffset>0</bitOffset> 5434 <bitWidth>1</bitWidth> 5435 <enumeratedValues> 5436 <enumeratedValue> 5437 <name>dis</name> 5438 <description>Disable interrupt.</description> 5439 <value>0</value> 5440 </enumeratedValue> 5441 <enumeratedValue> 5442 <name>en</name> 5443 <description>Enable interrupt.</description> 5444 <value>1</value> 5445 </enumeratedValue> 5446 </enumeratedValues> 5447 </field> 5448 <field> 5449 <name>ERR</name> 5450 <description>Enables/disables the HPB error interrupt.</description> 5451 <bitOffset>1</bitOffset> 5452 <bitWidth>1</bitWidth> 5453 <enumeratedValues> 5454 <enumeratedValue> 5455 <name>dis</name> 5456 <description>Disable error interrupt.</description> 5457 <value>0</value> 5458 </enumeratedValue> 5459 <enumeratedValue> 5460 <name>en</name> 5461 <description>Enable error interrupt.</description> 5462 <value>1</value> 5463 </enumeratedValue> 5464 </enumeratedValues> 5465 </field> 5466 </fields> 5467 </register> 5468 <register> 5469 <name>INTFL</name> 5470 <description>Hyperbus Interrupt Flag Register.</description> 5471 <addressOffset>0x0008</addressOffset> 5472 <fields> 5473 <field> 5474 <name>MEM</name> 5475 <description>Hyperbus Memory Status Flag.</description> 5476 <bitOffset>0</bitOffset> 5477 <bitWidth>1</bitWidth> 5478 <enumeratedValues> 5479 <enumeratedValue> 5480 <name>noint</name> 5481 <description>Memory interrupt not active.</description> 5482 <value>0</value> 5483 </enumeratedValue> 5484 <enumeratedValue> 5485 <name>pending</name> 5486 <description>Memory interrupt currently pending.</description> 5487 <value>1</value> 5488 </enumeratedValue> 5489 </enumeratedValues> 5490 </field> 5491 <field> 5492 <name>ERR</name> 5493 <description>Error interrupt status flag.</description> 5494 <bitOffset>1</bitOffset> 5495 <bitWidth>1</bitWidth> 5496 <enumeratedValues> 5497 <enumeratedValue> 5498 <name>noint</name> 5499 <description>Error interrupt not active.</description> 5500 <value>0</value> 5501 </enumeratedValue> 5502 <enumeratedValue> 5503 <name>pending</name> 5504 <description>Error interrupt currently pending.</description> 5505 <value>1</value> 5506 </enumeratedValue> 5507 </enumeratedValues> 5508 </field> 5509 </fields> 5510 </register> 5511 <register> 5512 <dim>2</dim> 5513 <dimIncrement>4</dimIncrement> 5514 <name>MEMBADDR[%s]</name> 5515 <description>Hyperbus Memory Base Address Register.</description> 5516 <addressOffset>0x0010</addressOffset> 5517 <fields> 5518 <field> 5519 <name>ADDR</name> 5520 <description>Memory base address. This sets the base address of the addressable memory region where the port is mapped. Each address space is 512Mbytes. The lower 24 bits are read only and will always read 0.</description> 5521 <bitOffset>0</bitOffset> 5522 <bitWidth>32</bitWidth> 5523 </field> 5524 </fields> 5525 </register> 5526 <register> 5527 <dim>2</dim> 5528 <dimIncrement>4</dimIncrement> 5529 <name>MEMCTRL[%s]</name> 5530 <description>Hyperbus Memory Control Register.</description> 5531 <addressOffset>0x0020</addressOffset> 5532 <fields> 5533 <field> 5534 <name>WRAPSIZE</name> 5535 <description>The wrap burst length of HyperBus memory. This bit is 5536ignored when the asymmetry cache support bit is 0. When 5537the asymmetry cache support is 1, this bit should be set the 5538same as wrap size of configuration register in HyperBus 5539memory. 5540</description> 5541 <bitOffset>0</bitOffset> 5542 <bitWidth>2</bitWidth> 5543 <enumeratedValues> 5544 <enumeratedValue> 5545 <name>64B</name> 5546 <description>64 bytes</description> 5547 <value>1</value> 5548 </enumeratedValue> 5549 <enumeratedValue> 5550 <name>16B</name> 5551 <description>16 bytes</description> 5552 <value>2</value> 5553 </enumeratedValue> 5554 <enumeratedValue> 5555 <name>32B</name> 5556 <description>32 bytes</description> 5557 <value>3</value> 5558 </enumeratedValue> 5559 </enumeratedValues> 5560 </field> 5561 <field> 5562 <name>DEVTYPE</name> 5563 <description>Select the memory device type.</description> 5564 <bitOffset>3</bitOffset> 5565 <bitWidth>2</bitWidth> 5566 <enumeratedValues> 5567 <enumeratedValue> 5568 <name>hyperFlash</name> 5569 <description>HyperFlash</description> 5570 <value>0</value> 5571 </enumeratedValue> 5572 <enumeratedValue> 5573 <name>xccela_psram</name> 5574 <description>Xccela PSRAM</description> 5575 <value>1</value> 5576 </enumeratedValue> 5577 <enumeratedValue> 5578 <name>hyperRAM</name> 5579 <description>HyperRAM</description> 5580 <value>2</value> 5581 </enumeratedValue> 5582 </enumeratedValues> 5583 </field> 5584 <field> 5585 <name>CRT</name> 5586 <description>Configuration Register Target Select. For HyperRAM and Xccela Bus devices, this field selects between read/write target being the devices memory map or configuration register space. For HyperFlash set this field to 0.</description> 5587 <bitOffset>5</bitOffset> 5588 <bitWidth>1</bitWidth> 5589 <enumeratedValues> 5590 <enumeratedValue> 5591 <name>mem_space</name> 5592 <description>Access Memory space.</description> 5593 <value>0</value> 5594 </enumeratedValue> 5595 <enumeratedValue> 5596 <name>config_reg</name> 5597 <description>Access Configuration Register space.</description> 5598 <value>1</value> 5599 </enumeratedValue> 5600 </enumeratedValues> 5601 </field> 5602 <field> 5603 <name>RDLAT_EN</name> 5604 <description>Xccela Fixed Read Latency Enable. Set this bit to enable Xccela bus Fixed Read Latency. Set this field to match the latency Type configuration in the target PSRAM.</description> 5605 <bitOffset>6</bitOffset> 5606 <bitWidth>1</bitWidth> 5607 <enumeratedValues> 5608 <enumeratedValue> 5609 <name>variable</name> 5610 <description>Variable read latency.</description> 5611 <value>0</value> 5612 </enumeratedValue> 5613 <enumeratedValue> 5614 <name>fixed</name> 5615 <description>Fixed read latency.</description> 5616 <value>1</value> 5617 </enumeratedValue> 5618 </enumeratedValues> 5619 </field> 5620 <field> 5621 <name>HSE</name> 5622 <description>Xccela Half Sleep Exit. When half sleep exit is enabled, the CS# line is held low for ten clock cycles. This bit is automatically cleared by hardware when a Half Sleep Exit completes.</description> 5623 <bitOffset>7</bitOffset> 5624 <bitWidth>1</bitWidth> 5625 <enumeratedValues> 5626 <enumeratedValue> 5627 <name>dis</name> 5628 <description>Half Sleep Exit disabled.</description> 5629 <value>0</value> 5630 </enumeratedValue> 5631 <enumeratedValue> 5632 <name>en</name> 5633 <description>Half Sleep Exit enabled.</description> 5634 <value>1</value> 5635 </enumeratedValue> 5636 </enumeratedValues> 5637 </field> 5638 <field> 5639 <name>MAXLEN</name> 5640 <description>Maximum Read/Write. Set this field to the CS# low time in terms of clock cycles.</description> 5641 <bitOffset>18</bitOffset> 5642 <bitWidth>9</bitWidth> 5643 </field> 5644 <field> 5645 <name>MAX_EN</name> 5646 <description>Maximum CS# Length Enable.</description> 5647 <bitOffset>31</bitOffset> 5648 <bitWidth>1</bitWidth> 5649 <enumeratedValues> 5650 <enumeratedValue> 5651 <name>dis</name> 5652 <description>No configured CS# low time.</description> 5653 <value>0</value> 5654 </enumeratedValue> 5655 <enumeratedValue> 5656 <name>en</name> 5657 <description>CS# low time is configured.</description> 5658 <value>1</value> 5659 </enumeratedValue> 5660 </enumeratedValues> 5661 </field> 5662 </fields> 5663 </register> 5664 <register> 5665 <dim>2</dim> 5666 <dimIncrement>4</dimIncrement> 5667 <name>MEMTIM[%s]</name> 5668 <description>Hyperbus Memory Timing Register.</description> 5669 <addressOffset>0x0030</addressOffset> 5670 <fields> 5671 <field> 5672 <name>LAT</name> 5673 <description>RAM Latency.</description> 5674 <bitOffset>0</bitOffset> 5675 <bitWidth>4</bitWidth> 5676 <enumeratedValues> 5677 <enumeratedValue> 5678 <name>5clk</name> 5679 <description>5 Clock cycles.</description> 5680 <value>0</value> 5681 </enumeratedValue> 5682 <enumeratedValue> 5683 <name>6clk</name> 5684 <description>6 Clock cycles.</description> 5685 <value>1</value> 5686 </enumeratedValue> 5687 <enumeratedValue> 5688 <name>3clk</name> 5689 <description>3 Clock cycles.</description> 5690 <value>14</value> 5691 </enumeratedValue> 5692 <enumeratedValue> 5693 <name>4clk</name> 5694 <description>4 Clock cycles.</description> 5695 <value>15</value> 5696 </enumeratedValue> 5697 </enumeratedValues> 5698 </field> 5699 <field> 5700 <name>WRCSHD</name> 5701 <description>Write Chip Select Hold after CK falling edge.</description> 5702 <bitOffset>8</bitOffset> 5703 <bitWidth>4</bitWidth> 5704 </field> 5705 <field> 5706 <name>RDCSHD</name> 5707 <description>Read Chip Select Hold after CK falling edge.</description> 5708 <bitOffset>12</bitOffset> 5709 <bitWidth>4</bitWidth> 5710 </field> 5711 <field> 5712 <name>WRCSST</name> 5713 <description>Write Chip Select Setup Time to Next CK Rising Edge.</description> 5714 <bitOffset>16</bitOffset> 5715 <bitWidth>4</bitWidth> 5716 </field> 5717 <field> 5718 <name>RDCSST</name> 5719 <description>Read Chip Select Setup Time to Next CK Rising Edge.</description> 5720 <bitOffset>20</bitOffset> 5721 <bitWidth>4</bitWidth> 5722 </field> 5723 <field> 5724 <name>WRCSHI</name> 5725 <description>Write Chip Select High Between Operations.</description> 5726 <bitOffset>24</bitOffset> 5727 <bitWidth>4</bitWidth> 5728 </field> 5729 <field> 5730 <name>RDCSHI</name> 5731 <description>Read Chip Select High Between Operations.</description> 5732 <bitOffset>28</bitOffset> 5733 <bitWidth>4</bitWidth> 5734 </field> 5735 </fields> 5736 </register> 5737 </registers> 5738 </peripheral> 5739<!--HPB HyperBus Memory Controller Registers--> 5740 <peripheral> 5741 <name>GCR</name> 5742 <description>Global Control Registers.</description> 5743 <baseAddress>0x40000000</baseAddress> 5744 <addressBlock> 5745 <offset>0</offset> 5746 <size>0x400</size> 5747 <usage>registers</usage> 5748 </addressBlock> 5749 <registers> 5750 <register> 5751 <name>SYSCTRL</name> 5752 <description>System Control.</description> 5753 <addressOffset>0x00</addressOffset> 5754 <resetMask>0xFFFFFFFE</resetMask> 5755 <fields> 5756 <field> 5757 <name>BSTAPEN</name> 5758 <description>Boundary Scan TAP enable. When enabled, the JTAG port is conneted to the Boundary Scan TAP instead of the ARM ICE.</description> 5759 <bitOffset>0</bitOffset> 5760 <bitWidth>1</bitWidth> 5761 </field> 5762 <field> 5763 <name>FLASH_PAGE_FLIP</name> 5764 <description>Flips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer.</description> 5765 <bitOffset>4</bitOffset> 5766 <bitWidth>1</bitWidth> 5767 <enumeratedValues> 5768 <enumeratedValue> 5769 <name>normal</name> 5770 <description>Physical layout matches logical layout.</description> 5771 <value>0</value> 5772 </enumeratedValue> 5773 <enumeratedValue> 5774 <name>swapped</name> 5775 <description>Bottom half mapped to logical top half and vice versa.</description> 5776 <value>1</value> 5777 </enumeratedValue> 5778 </enumeratedValues> 5779 </field> 5780 <field> 5781 <name>ICC0_FLUSH</name> 5782 <description>Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. </description> 5783 <bitOffset>6</bitOffset> 5784 <bitWidth>1</bitWidth> 5785 <enumeratedValues> 5786 <enumeratedValue> 5787 <name>normal</name> 5788 <description>Normal Code Cache Operation</description> 5789 <value>0</value> 5790 </enumeratedValue> 5791 <enumeratedValue> 5792 <name>flush</name> 5793 <description>Code Caches and CPU instruction buffer are flushed </description> 5794 <value>1</value> 5795 </enumeratedValue> 5796 </enumeratedValues> 5797 </field> 5798 <field> 5799 <name>SYSCACHE_DIS</name> 5800 <description>System Cache Disable.</description> 5801 <bitOffset>9</bitOffset> 5802 <bitWidth>1</bitWidth> 5803 </field> 5804 <field> 5805 <name>ROMDONE</name> 5806 <description>ROM_DONE status. Used to disable SWD interface during system initialization procedure</description> 5807 <bitOffset>12</bitOffset> 5808 <bitWidth>1</bitWidth> 5809 </field> 5810 <field> 5811 <name>CCHK</name> 5812 <description>Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed.</description> 5813 <bitOffset>13</bitOffset> 5814 <bitWidth>1</bitWidth> 5815 <enumeratedValues> 5816 <enumeratedValue> 5817 <name>complete</name> 5818 <description>No operation/complete.</description> 5819 <value>0</value> 5820 </enumeratedValue> 5821 <enumeratedValue> 5822 <name>start</name> 5823 <description>Start operation.</description> 5824 <value>1</value> 5825 </enumeratedValue> 5826 </enumeratedValues> 5827 </field> 5828 <field> 5829 <name>SWD_DIS</name> 5830 <description> Serial Wire Debug Disable. This bit is used to disable the serial wire debug interface This bit is only writeable if (FMV lock word is not programmed) or if (ICE lock word is not programmed and the ROM_DONE bit is not set).</description> 5831 <bitOffset>14</bitOffset> 5832 <bitWidth>1</bitWidth> 5833 </field> 5834 <field> 5835 <name>CHKRES</name> 5836 <description>ROM Checksum Result. This bit is only valid when CHKRD=1.</description> 5837 <bitOffset>15</bitOffset> 5838 <bitWidth>1</bitWidth> 5839 <enumeratedValues> 5840 <enumeratedValue> 5841 <name>pass</name> 5842 <description>ROM Checksum Correct.</description> 5843 <value>0</value> 5844 </enumeratedValue> 5845 <enumeratedValue> 5846 <name>fail</name> 5847 <description>ROM Checksum Fail.</description> 5848 <value>1</value> 5849 </enumeratedValue> 5850 </enumeratedValues> 5851 </field> 5852 <field> 5853 <name>OVR</name> 5854 <description>Operating Voltage Range.</description> 5855 <bitOffset>16</bitOffset> 5856 <bitWidth>2</bitWidth> 5857 <enumeratedValues> 5858 <enumeratedValue> 5859 <name>V0_9</name> 5860 <description>0.9V</description> 5861 <value>0</value> 5862 </enumeratedValue> 5863 <enumeratedValue> 5864 <name>V1_0</name> 5865 <description>1.0V</description> 5866 <value>1</value> 5867 </enumeratedValue> 5868 <enumeratedValue> 5869 <name>V1_1</name> 5870 <description>1.1V</description> 5871 <value>2</value> 5872 </enumeratedValue> 5873 </enumeratedValues> 5874 </field> 5875 </fields> 5876 </register> 5877 <register> 5878 <name>RST0</name> 5879 <description>Reset.</description> 5880 <addressOffset>0x04</addressOffset> 5881 <fields> 5882 <field> 5883 <name>DMA</name> 5884 <description>DMA Reset.</description> 5885 <bitOffset>0</bitOffset> 5886 <bitWidth>1</bitWidth> 5887 <enumeratedValues> 5888 <name>reset</name> 5889 <usage>read-write</usage> 5890 <enumeratedValue> 5891 <name>reset_done</name> 5892 <description>Reset complete.</description> 5893 <value>0</value> 5894 </enumeratedValue> 5895 <enumeratedValue> 5896 <name>busy</name> 5897 <description>Starts Reset or indicates reset in progress.</description> 5898 <value>1</value> 5899 </enumeratedValue> 5900 </enumeratedValues> 5901 </field> 5902 <field derivedFrom="DMA"> 5903 <name>WDT0</name> 5904 <description>Watchdog Timer 0 Reset.</description> 5905 <bitOffset>1</bitOffset> 5906 <bitWidth>1</bitWidth> 5907 </field> 5908 <field derivedFrom="DMA"> 5909 <name>GPIO0</name> 5910 <description>GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states.</description> 5911 <bitOffset>2</bitOffset> 5912 <bitWidth>1</bitWidth> 5913 </field> 5914 <field derivedFrom="DMA"> 5915 <name>GPIO1</name> 5916 <description>GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states.</description> 5917 <bitOffset>3</bitOffset> 5918 <bitWidth>1</bitWidth> 5919 </field> 5920 <field derivedFrom="DMA"> 5921 <name>GPIO2</name> 5922 <description>GPIO2 Reset. Setting this bit to 1 resets GPIO2 pins to their default states.</description> 5923 <bitOffset>4</bitOffset> 5924 <bitWidth>1</bitWidth> 5925 </field> 5926 <field derivedFrom="DMA"> 5927 <name>TMR0</name> 5928 <description>Timer 0 Reset. Setting this bit to 1 resets Timer 0 blocks.</description> 5929 <bitOffset>5</bitOffset> 5930 <bitWidth>1</bitWidth> 5931 </field> 5932 <field derivedFrom="DMA"> 5933 <name>TMR1</name> 5934 <description>Timer 1 Reset. Setting this bit to 1 resets Timer 1 blocks.</description> 5935 <bitOffset>6</bitOffset> 5936 <bitWidth>1</bitWidth> 5937 </field> 5938 <field derivedFrom="DMA"> 5939 <name>TMR2</name> 5940 <description>Timer 2 Reset. Setting this bit to 1 resets Timer 2 blocks.</description> 5941 <bitOffset>7</bitOffset> 5942 <bitWidth>1</bitWidth> 5943 </field> 5944 <field derivedFrom="DMA"> 5945 <name>TMR3</name> 5946 <description>Timer 3 Reset. Setting this bit to 1 resets Timer 3 blocks.</description> 5947 <bitOffset>8</bitOffset> 5948 <bitWidth>1</bitWidth> 5949 </field> 5950 <field derivedFrom="DMA"> 5951 <name>UART0</name> 5952 <description>UART 0 Reset. Setting this bit to 1 resets all UART 0 blocks.</description> 5953 <bitOffset>11</bitOffset> 5954 <bitWidth>1</bitWidth> 5955 </field> 5956 <field derivedFrom="DMA"> 5957 <name>UART1</name> 5958 <description>UART 1 Reset. Setting this bit to 1 resets all UART 1 blocks.</description> 5959 <bitOffset>12</bitOffset> 5960 <bitWidth>1</bitWidth> 5961 </field> 5962 <field derivedFrom="DMA"> 5963 <name>SPI0</name> 5964 <description>SPI 0 Reset. Setting this bit to 1 resets all SPI 0 blocks.</description> 5965 <bitOffset>13</bitOffset> 5966 <bitWidth>1</bitWidth> 5967 </field> 5968 <field derivedFrom="DMA"> 5969 <name>SPI1</name> 5970 <description>SPI 1 Reset. Setting this bit to 1 resets all SPI 1 blocks.</description> 5971 <bitOffset>14</bitOffset> 5972 <bitWidth>1</bitWidth> 5973 </field> 5974 <field derivedFrom="DMA"> 5975 <name>SPI2</name> 5976 <description>SPI 2 Reset. Setting this bit to 1 resets all SPI 2 blocks.</description> 5977 <bitOffset>15</bitOffset> 5978 <bitWidth>1</bitWidth> 5979 </field> 5980 <field derivedFrom="DMA"> 5981 <name>I2C0</name> 5982 <description>I2C 0 Reset.</description> 5983 <bitOffset>16</bitOffset> 5984 <bitWidth>1</bitWidth> 5985 </field> 5986 <field derivedFrom="DMA"> 5987 <name>RTC</name> 5988 <description>Real Time Clock Reset.</description> 5989 <bitOffset>17</bitOffset> 5990 <bitWidth>1</bitWidth> 5991 </field> 5992 <field derivedFrom="DMA"> 5993 <name>CRYPTO</name> 5994 <description>Crypto Reset.</description> 5995 <bitOffset>18</bitOffset> 5996 <bitWidth>1</bitWidth> 5997 </field> 5998 <field derivedFrom="DMA"> 5999 <name>CAN0</name> 6000 <description>CAN0 Reset.</description> 6001 <bitOffset>19</bitOffset> 6002 <bitWidth>1</bitWidth> 6003 </field> 6004 <field derivedFrom="DMA"> 6005 <name>CAN1</name> 6006 <description>CAN1 Reset.</description> 6007 <bitOffset>20</bitOffset> 6008 <bitWidth>1</bitWidth> 6009 </field> 6010 <field derivedFrom="DMA"> 6011 <name>HPB</name> 6012 <description>Hyperbus Reset.</description> 6013 <bitOffset>21</bitOffset> 6014 <bitWidth>1</bitWidth> 6015 </field> 6016 <field derivedFrom="DMA"> 6017 <name>SMPHR</name> 6018 <description>Semaphore Reset.</description> 6019 <bitOffset>22</bitOffset> 6020 <bitWidth>1</bitWidth> 6021 </field> 6022 <field derivedFrom="DMA"> 6023 <name>USB</name> 6024 <description>USB Reset.</description> 6025 <bitOffset>23</bitOffset> 6026 <bitWidth>1</bitWidth> 6027 </field> 6028 <field derivedFrom="DMA"> 6029 <name>TRNG</name> 6030 <description>TRNG Reset. This reset is only available during the manufacture testing phase.</description> 6031 <bitOffset>24</bitOffset> 6032 <bitWidth>1</bitWidth> 6033 </field> 6034 <field derivedFrom="DMA"> 6035 <name>ADC</name> 6036 <description>ADC Reset.</description> 6037 <bitOffset>26</bitOffset> 6038 <bitWidth>1</bitWidth> 6039 </field> 6040 <field derivedFrom="DMA"> 6041 <name>UART2</name> 6042 <description>UART2 Reset. Setting this bit to 1 resets all UART 2 blocks.</description> 6043 <bitOffset>28</bitOffset> 6044 <bitWidth>1</bitWidth> 6045 </field> 6046 <field derivedFrom="DMA"> 6047 <name>SOFT</name> 6048 <description>Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer.</description> 6049 <bitOffset>29</bitOffset> 6050 <bitWidth>1</bitWidth> 6051 </field> 6052 <field derivedFrom="DMA"> 6053 <name>PERIPH</name> 6054 <description>Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset.</description> 6055 <bitOffset>30</bitOffset> 6056 <bitWidth>1</bitWidth> 6057 </field> 6058 <field derivedFrom="DMA"> 6059 <name>SYS</name> 6060 <description>System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer.</description> 6061 <bitOffset>31</bitOffset> 6062 <bitWidth>1</bitWidth> 6063 </field> 6064 </fields> 6065 </register> 6066 <register> 6067 <name>CLKCTRL</name> 6068 <description>Clock Control.</description> 6069 <addressOffset>0x08</addressOffset> 6070 <resetValue>0x00000008</resetValue> 6071 <fields> 6072 <field> 6073 <name>SYSCLK_DIV</name> 6074 <description>Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0.</description> 6075 <bitOffset>6</bitOffset> 6076 <bitWidth>3</bitWidth> 6077 <enumeratedValues> 6078 <enumeratedValue> 6079 <name>div1</name> 6080 <description>Divide by 1.</description> 6081 <value>0</value> 6082 </enumeratedValue> 6083 <enumeratedValue> 6084 <name>div2</name> 6085 <description>Divide by 2.</description> 6086 <value>1</value> 6087 </enumeratedValue> 6088 <enumeratedValue> 6089 <name>div4</name> 6090 <description>Divide by 4.</description> 6091 <value>2</value> 6092 </enumeratedValue> 6093 <enumeratedValue> 6094 <name>div8</name> 6095 <description>Divide by 8.</description> 6096 <value>3</value> 6097 </enumeratedValue> 6098 <enumeratedValue> 6099 <name>div16</name> 6100 <description>Divide by 16.</description> 6101 <value>4</value> 6102 </enumeratedValue> 6103 <enumeratedValue> 6104 <name>div32</name> 6105 <description>Divide by 32.</description> 6106 <value>5</value> 6107 </enumeratedValue> 6108 <enumeratedValue> 6109 <name>div64</name> 6110 <description>Divide by 64.</description> 6111 <value>6</value> 6112 </enumeratedValue> 6113 <enumeratedValue> 6114 <name>div128</name> 6115 <description>Divide by 128.</description> 6116 <value>7</value> 6117 </enumeratedValue> 6118 </enumeratedValues> 6119 </field> 6120 <field> 6121 <name>SYSCLK_SEL</name> 6122 <description>Clock Source Select. This 3 bit field selects the source for the system clock.</description> 6123 <bitOffset>9</bitOffset> 6124 <bitWidth>3</bitWidth> 6125 <enumeratedValues> 6126 <enumeratedValue> 6127 <name>ISO</name> 6128 <description>The internal 60 MHz oscillator is used for the system clock.</description> 6129 <value>0</value> 6130 </enumeratedValue> 6131 <enumeratedValue> 6132 <name>ITO</name> 6133 <description>The internal 120 MHz PLL is used for the system clock.</description> 6134 <value>1</value> 6135 </enumeratedValue> 6136 <enumeratedValue> 6137 <name>ERFO</name> 6138 <description>The external 32 MHz input is used for the system clock.</description> 6139 <value>2</value> 6140 </enumeratedValue> 6141 <enumeratedValue> 6142 <name>INRO</name> 6143 <description>8 kHz LIRC is used for the system clock.</description> 6144 <value>3</value> 6145 </enumeratedValue> 6146 <enumeratedValue> 6147 <name>IPO</name> 6148 <description>The internal 100 MHz oscillator is used for the system clock.</description> 6149 <value>4</value> 6150 </enumeratedValue> 6151 <enumeratedValue> 6152 <name>IBRO</name> 6153 <description>The internal 7.3725 MHz oscillator is used for the system clock.</description> 6154 <value>5</value> 6155 </enumeratedValue> 6156 <enumeratedValue> 6157 <name>ERTCO</name> 6158 <description>External 32 kHz input is used for the system clock.</description> 6159 <value>6</value> 6160 </enumeratedValue> 6161 <enumeratedValue> 6162 <name>EXTCLK</name> 6163 <description>External clock input is used for the system clock.</description> 6164 <value>7</value> 6165 </enumeratedValue> 6166 </enumeratedValues> 6167 </field> 6168 <field> 6169 <name>SYSCLK_RDY</name> 6170 <description>Clock Ready. This read only bit reflects whether the currently selected system clock source is running.</description> 6171 <bitOffset>13</bitOffset> 6172 <bitWidth>1</bitWidth> 6173 <access>read-only</access> 6174 <enumeratedValues> 6175 <enumeratedValue> 6176 <name>busy</name> 6177 <description>Switchover to the new clock source (as selected by CLKSEL) has not yet occurred.</description> 6178 <value>0</value> 6179 </enumeratedValue> 6180 <enumeratedValue> 6181 <name>ready</name> 6182 <description>System clock running from CLKSEL clock source.</description> 6183 <value>1</value> 6184 </enumeratedValue> 6185 </enumeratedValues> 6186 </field> 6187 <field> 6188 <name>ERFO_EN</name> 6189 <description>32 MHz Crystal Oscillator Enable.</description> 6190 <bitOffset>16</bitOffset> 6191 <bitWidth>1</bitWidth> 6192 <enumeratedValues> 6193 <enumeratedValue> 6194 <name>dis</name> 6195 <description>Is Disabled.</description> 6196 <value>0</value> 6197 </enumeratedValue> 6198 <enumeratedValue> 6199 <name>en</name> 6200 <description>Is Enabled.</description> 6201 <value>1</value> 6202 </enumeratedValue> 6203 </enumeratedValues> 6204 </field> 6205 <field derivedFrom="ERFO_EN"> 6206 <name>ERTCO_EN</name> 6207 <description>32 kHz Oscillator Enable.</description> 6208 <bitOffset>17</bitOffset> 6209 <bitWidth>1</bitWidth> 6210 </field> 6211 <field derivedFrom="ERFO_EN"> 6212 <name>ISO_EN</name> 6213 <description>60 MHz Internal Oscillator Enable.</description> 6214 <bitOffset>18</bitOffset> 6215 <bitWidth>1</bitWidth> 6216 </field> 6217 <field derivedFrom="ERFO_EN"> 6218 <name>IPO_EN</name> 6219 <description>100 MHz Clock Enable.</description> 6220 <bitOffset>19</bitOffset> 6221 <bitWidth>1</bitWidth> 6222 </field> 6223 <field derivedFrom="ERFO_EN"> 6224 <name>IBRO_EN</name> 6225 <description>7.3725 MHz Clock Enable.</description> 6226 <bitOffset>20</bitOffset> 6227 <bitWidth>1</bitWidth> 6228 </field> 6229 <field> 6230 <name>IBRO_VS</name> 6231 <description>7.3725 MHz High Frequency Internal Reference Clock Voltage Select. This register bit is used to select the power supply to the IBRO.</description> 6232 <bitOffset>21</bitOffset> 6233 <bitWidth>1</bitWidth> 6234 <enumeratedValues> 6235 <enumeratedValue> 6236 <name>Vcor</name> 6237 <description>VCore Supply</description> 6238 <value>0</value> 6239 </enumeratedValue> 6240 <enumeratedValue> 6241 <name>1V</name> 6242 <description>Dedicated 1V regulated supply.</description> 6243 <value>1</value> 6244 </enumeratedValue> 6245 </enumeratedValues> 6246 </field> 6247 <field> 6248 <name>ERFO_RDY</name> 6249 <description>32 MHz Oscillator Ready</description> 6250 <bitOffset>24</bitOffset> 6251 <bitWidth>1</bitWidth> 6252 <access>read-only</access> 6253 <enumeratedValues> 6254 <enumeratedValue> 6255 <name>not</name> 6256 <description>Is not Ready.</description> 6257 <value>0</value> 6258 </enumeratedValue> 6259 <enumeratedValue> 6260 <name>ready</name> 6261 <description>Is Ready.</description> 6262 <value>1</value> 6263 </enumeratedValue> 6264 </enumeratedValues> 6265 </field> 6266 <field derivedFrom="ERFO_RDY"> 6267 <name>ERTCO_RDY</name> 6268 <description>32 kHz Crystal Oscillator Ready</description> 6269 <bitOffset>25</bitOffset> 6270 <bitWidth>1</bitWidth> 6271 </field> 6272 <field derivedFrom="ERFO_RDY"> 6273 <name>ISO_RDY</name> 6274 <description>60 MHz Oscillator Ready.</description> 6275 <bitOffset>26</bitOffset> 6276 <bitWidth>1</bitWidth> 6277 </field> 6278 <field derivedFrom="ERFO_RDY"> 6279 <name>IPO_RDY</name> 6280 <description>100 MHz Clock Ready.</description> 6281 <bitOffset>27</bitOffset> 6282 <bitWidth>1</bitWidth> 6283 </field> 6284 <field derivedFrom="ERFO_RDY"> 6285 <name>IBRO_RDY</name> 6286 <description>7.3725 MHz HIRC Ready.</description> 6287 <bitOffset>28</bitOffset> 6288 <bitWidth>1</bitWidth> 6289 </field> 6290 <field derivedFrom="ERFO_RDY"> 6291 <name>INRO_RDY</name> 6292 <description>8 kHz Low Frequency Reference Clock Ready.</description> 6293 <bitOffset>29</bitOffset> 6294 <bitWidth>1</bitWidth> 6295 </field> 6296 </fields> 6297 </register> 6298 <register> 6299 <name>PM</name> 6300 <description>Power Management.</description> 6301 <addressOffset>0x0C</addressOffset> 6302 <fields> 6303 <field> 6304 <name>MODE</name> 6305 <description>Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode.</description> 6306 <bitOffset>0</bitOffset> 6307 <bitWidth>4</bitWidth> 6308 <enumeratedValues> 6309 <enumeratedValue> 6310 <name>active</name> 6311 <description>Active Mode.</description> 6312 <value>0</value> 6313 </enumeratedValue> 6314 <enumeratedValue> 6315 <name>sleep</name> 6316 <description>Cortex-M4 Active, RISC-V Sleep Mode.</description> 6317 <value>1</value> 6318 </enumeratedValue> 6319 <enumeratedValue> 6320 <name>standby</name> 6321 <description>Standby Mode.</description> 6322 <value>2</value> 6323 </enumeratedValue> 6324 <enumeratedValue> 6325 <name>backup</name> 6326 <description>Backup Mode.</description> 6327 <value>4</value> 6328 </enumeratedValue> 6329 <enumeratedValue> 6330 <name>lpm</name> 6331 <description>LPM or CM4 Deep Sleep Mode.</description> 6332 <value>8</value> 6333 </enumeratedValue> 6334 <enumeratedValue> 6335 <name>upm</name> 6336 <description>UPM.</description> 6337 <value>9</value> 6338 </enumeratedValue> 6339 <enumeratedValue> 6340 <name>powerdown</name> 6341 <description>Power Down Mode.</description> 6342 <value>10</value> 6343 </enumeratedValue> 6344 </enumeratedValues> 6345 </field> 6346 <field> 6347 <name>GPIO_WE</name> 6348 <description>GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set.</description> 6349 <bitOffset>4</bitOffset> 6350 <bitWidth>1</bitWidth> 6351 <enumeratedValues> 6352 <enumeratedValue> 6353 <name>dis</name> 6354 <description>Wake Up Disable.</description> 6355 <value>0</value> 6356 </enumeratedValue> 6357 <enumeratedValue> 6358 <name>en</name> 6359 <description>Wake Up Enable.</description> 6360 <value>1</value> 6361 </enumeratedValue> 6362 </enumeratedValues> 6363 </field> 6364 <field derivedFrom="GPIO_WE"> 6365 <name>RTC_WE</name> 6366 <description>RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers.</description> 6367 <bitOffset>5</bitOffset> 6368 <bitWidth>1</bitWidth> 6369 </field> 6370 <field derivedFrom="GPIO_WE"> 6371 <name>USB_WE</name> 6372 <description>USB Wake Up Enable. This bit enables USB IRQ as wakeup source</description> 6373 <bitOffset>6</bitOffset> 6374 <bitWidth>1</bitWidth> 6375 </field> 6376 <field derivedFrom="GPIO_WE"> 6377 <name>WUT_WE</name> 6378 <description>WUT Wake Up Enable. This bit enables the Wake-Up Timer as wakeup source. </description> 6379 <bitOffset>7</bitOffset> 6380 <bitWidth>1</bitWidth> 6381 </field> 6382 <field derivedFrom="GPIO_WE"> 6383 <name>AINCOMP_WE</name> 6384 <description>AIN COMP Wake Up Enable. This bit enables AIN COMP as wakeup source. </description> 6385 <bitOffset>9</bitOffset> 6386 <bitWidth>1</bitWidth> 6387 </field> 6388 <field> 6389 <name>ISO_PD</name> 6390 <description>60 MHz power down. This bit selects the 60 MHz clock power state in DEEPSLEEP mode.</description> 6391 <bitOffset>15</bitOffset> 6392 <bitWidth>1</bitWidth> 6393 <enumeratedValues> 6394 <enumeratedValue> 6395 <name>active</name> 6396 <description>Mode is Active.</description> 6397 <value>0</value> 6398 </enumeratedValue> 6399 <enumeratedValue> 6400 <name>deepsleep</name> 6401 <description>Powered down in DEEPSLEEP.</description> 6402 <value>1</value> 6403 </enumeratedValue> 6404 </enumeratedValues> 6405 </field> 6406 <field derivedFrom="ISO_PD"> 6407 <name>IPO_PD</name> 6408 <description>100 MHz power down. This bit selects 100 MHz clock power state in DEEPSLEEP mode. </description> 6409 <bitOffset>16</bitOffset> 6410 <bitWidth>1</bitWidth> 6411 </field> 6412 <field derivedFrom="ISO_PD"> 6413 <name>IBRO_PD</name> 6414 <description>7.3725 MHz power down. This bit selects 7.3725 MHz clock power state in DEEPSLEEP mode. </description> 6415 <bitOffset>17</bitOffset> 6416 <bitWidth>1</bitWidth> 6417 </field> 6418 <field> 6419 <name>ERFO_BP</name> 6420 <description>ERFO Bypass.</description> 6421 <bitOffset>20</bitOffset> 6422 <bitWidth>1</bitWidth> 6423 </field> 6424 </fields> 6425 </register> 6426 <register> 6427 <name>PCLKDIV</name> 6428 <description>Peripheral Clock Divider.</description> 6429 <addressOffset>0x18</addressOffset> 6430 <resetValue>0x00000001</resetValue> 6431 <fields> 6432 <field> 6433 <name>SDIOCLKDIV</name> 6434 <bitOffset>7</bitOffset> 6435 <bitWidth>1</bitWidth> 6436 <enumeratedValues> 6437 <enumeratedValue> 6438 <name>IPO_DIV2</name> 6439 <description>48 MHz</description> 6440 <value>0</value> 6441 </enumeratedValue> 6442 <enumeratedValue> 6443 <name>IPO_DIV4</name> 6444 <description>24 MHz</description> 6445 <value>1</value> 6446 </enumeratedValue> 6447 </enumeratedValues> 6448 </field> 6449 <field> 6450 <name>ADCFRQ</name> 6451 <description>ADC clock Frequency. These bits define the ADC clock frequency. fADC = fPCLK / (ADCFRQ)</description> 6452 <bitOffset>10</bitOffset> 6453 <bitWidth>4</bitWidth> 6454 </field> 6455 <field> 6456 <name>CNNCLKDIV</name> 6457 <description>CNN Clock Divider.</description> 6458 <bitOffset>14</bitOffset> 6459 <bitWidth>3</bitWidth> 6460 <enumeratedValues> 6461 <enumeratedValue> 6462 <name>div2</name> 6463 <value>0</value> 6464 </enumeratedValue> 6465 <enumeratedValue> 6466 <name>div4</name> 6467 <value>1</value> 6468 </enumeratedValue> 6469 <enumeratedValue> 6470 <name>div8</name> 6471 <value>2</value> 6472 </enumeratedValue> 6473 <enumeratedValue> 6474 <name>div16</name> 6475 <value>3</value> 6476 </enumeratedValue> 6477 <enumeratedValue> 6478 <name>div1</name> 6479 <value>4</value> 6480 </enumeratedValue> 6481 </enumeratedValues> 6482 </field> 6483 <field> 6484 <name>CNNCLKSEL</name> 6485 <description>CNN Clock Select.</description> 6486 <bitOffset>17</bitOffset> 6487 <bitWidth>2</bitWidth> 6488 <enumeratedValues> 6489 <enumeratedValue> 6490 <name>PCLK</name> 6491 <value>0</value> 6492 </enumeratedValue> 6493 <enumeratedValue> 6494 <name>ISO</name> 6495 <value>1</value> 6496 </enumeratedValue> 6497 <enumeratedValue> 6498 <name>ITO</name> 6499 <value>3</value> 6500 </enumeratedValue> 6501 </enumeratedValues> 6502 </field> 6503 </fields> 6504 </register> 6505 <register> 6506 <name>PCLKDIS0</name> 6507 <description>Peripheral Clock Disable.</description> 6508 <addressOffset>0x24</addressOffset> 6509 <fields> 6510 <field> 6511 <name>GPIO0</name> 6512 <description>GPIO0 Clock Disable.</description> 6513 <bitOffset>0</bitOffset> 6514 <bitWidth>1</bitWidth> 6515 <enumeratedValues> 6516 <enumeratedValue> 6517 <name>en</name> 6518 <description>enable it.</description> 6519 <value>0</value> 6520 </enumeratedValue> 6521 <enumeratedValue> 6522 <name>dis</name> 6523 <description>disable it.</description> 6524 <value>1</value> 6525 </enumeratedValue> 6526 </enumeratedValues> 6527 </field> 6528 <field derivedFrom="GPIO0"> 6529 <name>GPIO1</name> 6530 <description>GPIO1 Clock Disable.</description> 6531 <bitOffset>1</bitOffset> 6532 <bitWidth>1</bitWidth> 6533 </field> 6534 <field derivedFrom="GPIO0"> 6535 <name>GPIO2</name> 6536 <description>GPIO2 Clock Disable.</description> 6537 <bitOffset>2</bitOffset> 6538 <bitWidth>1</bitWidth> 6539 </field> 6540 <field derivedFrom="GPIO0"> 6541 <name>USB</name> 6542 <description>USB Clock Disable.</description> 6543 <bitOffset>3</bitOffset> 6544 <bitWidth>1</bitWidth> 6545 </field> 6546 <field derivedFrom="GPIO0"> 6547 <name>DMA</name> 6548 <description>DMA Clock Disable.</description> 6549 <bitOffset>5</bitOffset> 6550 <bitWidth>1</bitWidth> 6551 </field> 6552 <field derivedFrom="GPIO0"> 6553 <name>SPI0</name> 6554 <description>SPI 0 Clock Disable.</description> 6555 <bitOffset>6</bitOffset> 6556 <bitWidth>1</bitWidth> 6557 </field> 6558 <field derivedFrom="GPIO0"> 6559 <name>SPI1</name> 6560 <description>SPI 1 Clock Disable.</description> 6561 <bitOffset>7</bitOffset> 6562 <bitWidth>1</bitWidth> 6563 </field> 6564 <field derivedFrom="GPIO0"> 6565 <name>SPI2</name> 6566 <description>SPI 2 Clock Disable.</description> 6567 <bitOffset>8</bitOffset> 6568 <bitWidth>1</bitWidth> 6569 </field> 6570 <field derivedFrom="GPIO0"> 6571 <name>UART0</name> 6572 <description>UART 0 Clock Disable.</description> 6573 <bitOffset>9</bitOffset> 6574 <bitWidth>1</bitWidth> 6575 </field> 6576 <field derivedFrom="GPIO0"> 6577 <name>UART1</name> 6578 <description>UART 1 Clock Disable.</description> 6579 <bitOffset>10</bitOffset> 6580 <bitWidth>1</bitWidth> 6581 </field> 6582 <field derivedFrom="GPIO0"> 6583 <name>I2C0</name> 6584 <description>I2C 0 Clock Disable.</description> 6585 <bitOffset>13</bitOffset> 6586 <bitWidth>1</bitWidth> 6587 </field> 6588 <field derivedFrom="GPIO0"> 6589 <name>CRYPTO</name> 6590 <description>Crypto Clock Disable.</description> 6591 <bitOffset>14</bitOffset> 6592 <bitWidth>1</bitWidth> 6593 </field> 6594 <field derivedFrom="GPIO0"> 6595 <name>TMR0</name> 6596 <description>Timer 0 Clock Disable.</description> 6597 <bitOffset>15</bitOffset> 6598 <bitWidth>1</bitWidth> 6599 </field> 6600 <field derivedFrom="GPIO0"> 6601 <name>TMR1</name> 6602 <description>Timer 1 Clock Disable.</description> 6603 <bitOffset>16</bitOffset> 6604 <bitWidth>1</bitWidth> 6605 </field> 6606 <field derivedFrom="GPIO0"> 6607 <name>TMR2</name> 6608 <description>Timer 2 Clock Disable.</description> 6609 <bitOffset>17</bitOffset> 6610 <bitWidth>1</bitWidth> 6611 </field> 6612 <field derivedFrom="GPIO0"> 6613 <name>TMR3</name> 6614 <description>Timer 3 Clock Disable.</description> 6615 <bitOffset>18</bitOffset> 6616 <bitWidth>1</bitWidth> 6617 </field> 6618 <field derivedFrom="GPIO0"> 6619 <name>ADC</name> 6620 <description>ADC Clock Disable.</description> 6621 <bitOffset>23</bitOffset> 6622 <bitWidth>1</bitWidth> 6623 </field> 6624 <field derivedFrom="GPIO0"> 6625 <name>I2C1</name> 6626 <description>I2C 1 Clock Disable.</description> 6627 <bitOffset>28</bitOffset> 6628 <bitWidth>1</bitWidth> 6629 </field> 6630 <field derivedFrom="GPIO0"> 6631 <name>PT</name> 6632 <description>Pluse Train Clock Disable.</description> 6633 <bitOffset>29</bitOffset> 6634 <bitWidth>1</bitWidth> 6635 </field> 6636 <field derivedFrom="GPIO0"> 6637 <name>SPIXIP</name> 6638 <description>SPI XIP Clock Disable.</description> 6639 <bitOffset>30</bitOffset> 6640 <bitWidth>1</bitWidth> 6641 </field> 6642 <field derivedFrom="GPIO0"> 6643 <name>SPIXIPC</name> 6644 <description>SPI XIPC Clock Disable.</description> 6645 <bitOffset>31</bitOffset> 6646 <bitWidth>1</bitWidth> 6647 </field> 6648 </fields> 6649 </register> 6650 <register> 6651 <name>MEMCTRL</name> 6652 <description>Memory Clock Control Register.</description> 6653 <addressOffset>0x28</addressOffset> 6654 <fields> 6655 <field> 6656 <name>FWS</name> 6657 <description>Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2.</description> 6658 <bitOffset>0</bitOffset> 6659 <bitWidth>3</bitWidth> 6660 </field> 6661 <field> 6662 <name>HYPCLKDS</name> 6663 <description>HYP Clock Drive Strength Control.</description> 6664 <bitOffset>8</bitOffset> 6665 <bitWidth>2</bitWidth> 6666 </field> 6667 </fields> 6668 </register> 6669 <register> 6670 <name>MEMZ</name> 6671 <description>Memory Zeroize Control.</description> 6672 <addressOffset>0x2C</addressOffset> 6673 <fields> 6674 <field> 6675 <name>RAM0</name> 6676 <description>System RAM Block 0 Zeroization.</description> 6677 <bitOffset>0</bitOffset> 6678 <bitWidth>1</bitWidth> 6679 <enumeratedValues> 6680 <enumeratedValue> 6681 <name>nop</name> 6682 <description>No operation/complete.</description> 6683 <value>0</value> 6684 </enumeratedValue> 6685 <enumeratedValue> 6686 <name>start</name> 6687 <description>Start operation.</description> 6688 <value>1</value> 6689 </enumeratedValue> 6690 </enumeratedValues> 6691 </field> 6692 <field derivedFrom="RAM0"> 6693 <name>RAM1</name> 6694 <description>System RAM Block 1 Zeroization.</description> 6695 <bitOffset>1</bitOffset> 6696 <bitWidth>1</bitWidth> 6697 </field> 6698 <field derivedFrom="RAM0"> 6699 <name>RAM2</name> 6700 <description>System RAM Block 2 Zeroization.</description> 6701 <bitOffset>2</bitOffset> 6702 <bitWidth>1</bitWidth> 6703 </field> 6704 <field derivedFrom="RAM0"> 6705 <name>RAM3</name> 6706 <description>System RAM Block 3 Zeroization.</description> 6707 <bitOffset>3</bitOffset> 6708 <bitWidth>1</bitWidth> 6709 </field> 6710 <field derivedFrom="RAM0"> 6711 <name>RAM4</name> 6712 <description>System RAM Block 4 Zeroization.</description> 6713 <bitOffset>4</bitOffset> 6714 <bitWidth>1</bitWidth> 6715 </field> 6716 <field derivedFrom="RAM0"> 6717 <name>RAM5</name> 6718 <description>System RAM Block 5 Zeroization.</description> 6719 <bitOffset>5</bitOffset> 6720 <bitWidth>1</bitWidth> 6721 </field> 6722 <field derivedFrom="RAM0"> 6723 <name>RAM6</name> 6724 <description>System RAM Block 6 Zeroization.</description> 6725 <bitOffset>6</bitOffset> 6726 <bitWidth>1</bitWidth> 6727 </field> 6728 <field derivedFrom="RAM0"> 6729 <name>RAM7</name> 6730 <description>System RAM Block 7 Zeroization.</description> 6731 <bitOffset>7</bitOffset> 6732 <bitWidth>1</bitWidth> 6733 </field> 6734 <field derivedFrom="RAM0"> 6735 <name>RAM8</name> 6736 <description>System RAM Block 8 Zeroization.</description> 6737 <bitOffset>8</bitOffset> 6738 <bitWidth>1</bitWidth> 6739 </field> 6740 <field derivedFrom="RAM0"> 6741 <name>ICC0</name> 6742 <description>Instruction Cache 0 Zeroization.</description> 6743 <bitOffset>9</bitOffset> 6744 <bitWidth>1</bitWidth> 6745 </field> 6746 <field derivedFrom="RAM0"> 6747 <name>ICC1</name> 6748 <description>Instruction Cache 1 Zeroization.</description> 6749 <bitOffset>10</bitOffset> 6750 <bitWidth>1</bitWidth> 6751 </field> 6752 <field derivedFrom="RAM0"> 6753 <name>ICCXIP</name> 6754 <description>ICC-XIP Zeroization.</description> 6755 <bitOffset>11</bitOffset> 6756 <bitWidth>1</bitWidth> 6757 </field> 6758 <field derivedFrom="RAM0"> 6759 <name>USBFIFO</name> 6760 <description>USB FIFO Zeroization.</description> 6761 <bitOffset>12</bitOffset> 6762 <bitWidth>1</bitWidth> 6763 </field> 6764 <field derivedFrom="RAM0"> 6765 <name>MAARAM</name> 6766 <description>MAA RAM Zeroization.</description> 6767 <bitOffset>13</bitOffset> 6768 <bitWidth>1</bitWidth> 6769 </field> 6770 <field derivedFrom="RAM0"> 6771 <name>DCACHE_DATA</name> 6772 <description>Data-Cache Controller Data Zeroization.</description> 6773 <bitOffset>14</bitOffset> 6774 <bitWidth>1</bitWidth> 6775 </field> 6776 <field derivedFrom="RAM0"> 6777 <name>DCACHE_TAG</name> 6778 <description>Data-Cache Controller Tag Zeroization.</description> 6779 <bitOffset>15</bitOffset> 6780 <bitWidth>1</bitWidth> 6781 </field> 6782 </fields> 6783 </register> 6784 <register> 6785 <name>SYSST</name> 6786 <description>System Status Register.</description> 6787 <addressOffset>0x40</addressOffset> 6788 <fields> 6789 <field> 6790 <name>ICELOCK</name> 6791 <description>ARM ICE Lock Status.</description> 6792 <bitOffset>0</bitOffset> 6793 <bitWidth>1</bitWidth> 6794 <enumeratedValues> 6795 <enumeratedValue> 6796 <name>unlocked</name> 6797 <description>ICE is unlocked.</description> 6798 <value>0</value> 6799 </enumeratedValue> 6800 <enumeratedValue> 6801 <name>locked</name> 6802 <description>ICE is locked.</description> 6803 <value>1</value> 6804 </enumeratedValue> 6805 </enumeratedValues> 6806 </field> 6807 <field> 6808 <name>CODEINTERR</name> 6809 <description>Code Interrupt Error Status.</description> 6810 <bitOffset>1</bitOffset> 6811 <bitWidth>1</bitWidth> 6812 </field> 6813 <field> 6814 <name>DATAINTERR</name> 6815 <description>Data Interrupt Error Lock Status.</description> 6816 <bitOffset>2</bitOffset> 6817 <bitWidth>1</bitWidth> 6818 </field> 6819 </fields> 6820 </register> 6821 <register> 6822 <name>RST1</name> 6823 <description>Reset 1.</description> 6824 <addressOffset>0x44</addressOffset> 6825 <fields> 6826 <field> 6827 <name>I2C1</name> 6828 <description>I2C1 Reset.</description> 6829 <bitOffset>0</bitOffset> 6830 <bitWidth>1</bitWidth> 6831 <enumeratedValues> 6832 <name>reset_read</name> 6833 <usage>read</usage> 6834 <enumeratedValue> 6835 <name>reset_done</name> 6836 <description>Reset complete.</description> 6837 <value>0</value> 6838 </enumeratedValue> 6839 <enumeratedValue> 6840 <name>busy</name> 6841 <description>Starts reset or indicates reset in progress.</description> 6842 <value>1</value> 6843 </enumeratedValue> 6844 </enumeratedValues> 6845 </field> 6846 <field derivedFrom="I2C1"> 6847 <name>PT</name> 6848 <description>PT Reset.</description> 6849 <bitOffset>1</bitOffset> 6850 <bitWidth>1</bitWidth> 6851 </field> 6852 <field derivedFrom="I2C1"> 6853 <name>SPIXIP</name> 6854 <description>SPI XIPF Reset.</description> 6855 <bitOffset>3</bitOffset> 6856 <bitWidth>1</bitWidth> 6857 </field> 6858 <field derivedFrom="I2C1"> 6859 <name>SPIXIPM</name> 6860 <description>SPI XIP Master Reset.</description> 6861 <bitOffset>4</bitOffset> 6862 <bitWidth>1</bitWidth> 6863 </field> 6864 <field derivedFrom="I2C1"> 6865 <name>OWM</name> 6866 <description>OWM Reset.</description> 6867 <bitOffset>7</bitOffset> 6868 <bitWidth>1</bitWidth> 6869 </field> 6870 <field derivedFrom="I2C1"> 6871 <name>SPI3</name> 6872 <description>SPI3 Reset.</description> 6873 <bitOffset>11</bitOffset> 6874 <bitWidth>1</bitWidth> 6875 </field> 6876 <field derivedFrom="I2C1"> 6877 <name>SPI4</name> 6878 <description>SPI4 Reset.</description> 6879 <bitOffset>13</bitOffset> 6880 <bitWidth>1</bitWidth> 6881 </field> 6882 <field derivedFrom="I2C1"> 6883 <name>SMPHR</name> 6884 <description>SMPHR Reset.</description> 6885 <bitOffset>16</bitOffset> 6886 <bitWidth>1</bitWidth> 6887 </field> 6888 <field derivedFrom="I2C1"> 6889 <name>BTLE</name> 6890 <description>BTLE Reset.</description> 6891 <bitOffset>18</bitOffset> 6892 <bitWidth>1</bitWidth> 6893 </field> 6894 <field derivedFrom="I2C1"> 6895 <name>I2S</name> 6896 <description>I2S Reset.</description> 6897 <bitOffset>19</bitOffset> 6898 <bitWidth>1</bitWidth> 6899 </field> 6900 <field derivedFrom="I2C1"> 6901 <name>I2C2</name> 6902 <description>I2C2 Reset.</description> 6903 <bitOffset>20</bitOffset> 6904 <bitWidth>1</bitWidth> 6905 </field> 6906 <field derivedFrom="I2C1"> 6907 <name>PUF</name> 6908 <description>PUF Reset.</description> 6909 <bitOffset>28</bitOffset> 6910 <bitWidth>1</bitWidth> 6911 </field> 6912 <field derivedFrom="I2C1"> 6913 <name>CPU1</name> 6914 <description>CPU1 Reset.</description> 6915 <bitOffset>31</bitOffset> 6916 <bitWidth>1</bitWidth> 6917 </field> 6918 </fields> 6919 </register> 6920 <register> 6921 <name>PCLKDIS1</name> 6922 <description>Peripheral Clock Disable.</description> 6923 <addressOffset>0x48</addressOffset> 6924 <fields> 6925 <field> 6926 <name>BTLE</name> 6927 <description>BTLE Clock Disable.</description> 6928 <bitOffset>0</bitOffset> 6929 <bitWidth>1</bitWidth> 6930 <enumeratedValues> 6931 <enumeratedValue> 6932 <name>en</name> 6933 <description>Clock enabled to the peripheral.</description> 6934 <value>0</value> 6935 </enumeratedValue> 6936 <enumeratedValue> 6937 <name>dis</name> 6938 <description>Clock disabled to the peripheral.</description> 6939 <value>1</value> 6940 </enumeratedValue> 6941 </enumeratedValues> 6942 </field> 6943 <field derivedFrom="BTLE"> 6944 <name>UART2</name> 6945 <description>UART2 Clock Disable.</description> 6946 <bitOffset>1</bitOffset> 6947 <bitWidth>1</bitWidth> 6948 </field> 6949 <field derivedFrom="BTLE"> 6950 <name>TRNG</name> 6951 <description>TRNG Clock Disable.</description> 6952 <bitOffset>2</bitOffset> 6953 <bitWidth>1</bitWidth> 6954 </field> 6955 <field derivedFrom="BTLE"> 6956 <name>PUF</name> 6957 <description>PUF Clock Disable.</description> 6958 <bitOffset>3</bitOffset> 6959 <bitWidth>1</bitWidth> 6960 </field> 6961 <field derivedFrom="BTLE"> 6962 <name>HPB</name> 6963 <description>HyperBus/Xccela Clock Disable.</description> 6964 <bitOffset>4</bitOffset> 6965 <bitWidth>1</bitWidth> 6966 </field> 6967 <field derivedFrom="BTLE"> 6968 <name>SYSCACHE</name> 6969 <description>System Cache Clock Disable.</description> 6970 <bitOffset>7</bitOffset> 6971 <bitWidth>1</bitWidth> 6972 </field> 6973 <field derivedFrom="BTLE"> 6974 <name>SMPHR</name> 6975 <description>SMPHR Clock Disable.</description> 6976 <bitOffset>9</bitOffset> 6977 <bitWidth>1</bitWidth> 6978 </field> 6979 <field derivedFrom="BTLE"> 6980 <name>CAN0</name> 6981 <description>CAN0 Clock Disable.</description> 6982 <bitOffset>11</bitOffset> 6983 <bitWidth>1</bitWidth> 6984 </field> 6985 <field derivedFrom="BTLE"> 6986 <name>OWM</name> 6987 <description>One-Wire Clock Disable.</description> 6988 <bitOffset>13</bitOffset> 6989 <bitWidth>1</bitWidth> 6990 </field> 6991 <field derivedFrom="BTLE"> 6992 <name>SPI3</name> 6993 <description>SPI3 Clock Disable.</description> 6994 <bitOffset>16</bitOffset> 6995 <bitWidth>1</bitWidth> 6996 </field> 6997 <field derivedFrom="BTLE"> 6998 <name>SPI4</name> 6999 <description>SPI4 Clock Disable.</description> 7000 <bitOffset>17</bitOffset> 7001 <bitWidth>1</bitWidth> 7002 </field> 7003 <field derivedFrom="BTLE"> 7004 <name>CAN1</name> 7005 <description>CAN1 Clock Disable.</description> 7006 <bitOffset>19</bitOffset> 7007 <bitWidth>1</bitWidth> 7008 </field> 7009 <field derivedFrom="BTLE"> 7010 <name>SPIXR</name> 7011 <description>SPIXR Clock Disable.</description> 7012 <bitOffset>20</bitOffset> 7013 <bitWidth>1</bitWidth> 7014 </field> 7015 <field derivedFrom="BTLE"> 7016 <name>I2S</name> 7017 <description>I2S Clock Disable.</description> 7018 <bitOffset>23</bitOffset> 7019 <bitWidth>1</bitWidth> 7020 </field> 7021 <field derivedFrom="BTLE"> 7022 <name>I2C2</name> 7023 <description>I2C2 Clock Disable.</description> 7024 <bitOffset>24</bitOffset> 7025 <bitWidth>1</bitWidth> 7026 </field> 7027 <field derivedFrom="BTLE"> 7028 <name>WDT0</name> 7029 <description>Watch Dog Timer 0 Clock Disable.</description> 7030 <bitOffset>27</bitOffset> 7031 <bitWidth>1</bitWidth> 7032 </field> 7033 <field derivedFrom="BTLE"> 7034 <name>CPU1</name> 7035 <description>CPU1 Clock Disable.</description> 7036 <bitOffset>31</bitOffset> 7037 <bitWidth>1</bitWidth> 7038 </field> 7039 </fields> 7040 </register> 7041 <register> 7042 <name>EVENTEN</name> 7043 <description>Event Enable Register.</description> 7044 <addressOffset>0x4C</addressOffset> 7045 <fields> 7046 <field> 7047 <name>DMA</name> 7048 <description>Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode.</description> 7049 <bitOffset>0</bitOffset> 7050 <bitWidth>1</bitWidth> 7051 </field> 7052 <field> 7053 <name>RX</name> 7054 <description>Enable RXEV pin event. When this bit is set, RXEV event from the CPU is output to GPIO1.9.</description> 7055 <bitOffset>1</bitOffset> 7056 <bitWidth>1</bitWidth> 7057 </field> 7058 <field> 7059 <name>TX</name> 7060 <description>Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO1.9.</description> 7061 <bitOffset>2</bitOffset> 7062 <bitWidth>1</bitWidth> 7063 </field> 7064 </fields> 7065 </register> 7066 <register> 7067 <name>REVISION</name> 7068 <description>Revision Register.</description> 7069 <addressOffset>0x50</addressOffset> 7070 <access>read-only</access> 7071 <fields> 7072 <field> 7073 <name>REVISION</name> 7074 <description>Manufacturer Chip Revision.</description> 7075 <bitOffset>0</bitOffset> 7076 <bitWidth>16</bitWidth> 7077 </field> 7078 </fields> 7079 </register> 7080 <register> 7081 <name>SYSIE</name> 7082 <description>System Status Interrupt Enable Register.</description> 7083 <addressOffset>0x54</addressOffset> 7084 <fields> 7085 <field> 7086 <name>ICEUNLOCK</name> 7087 <description>ARM ICE Unlock Interrupt Enable.</description> 7088 <bitOffset>0</bitOffset> 7089 <bitWidth>1</bitWidth> 7090 <enumeratedValues> 7091 <enumeratedValue> 7092 <name>dis</name> 7093 <description>disabled.</description> 7094 <value>0</value> 7095 </enumeratedValue> 7096 <enumeratedValue> 7097 <name>en</name> 7098 <description>enabled.</description> 7099 <value>1</value> 7100 </enumeratedValue> 7101 </enumeratedValues> 7102 </field> 7103 </fields> 7104 </register> 7105 <register> 7106 <name>ECCERR</name> 7107 <description>ECC Error Register</description> 7108 <addressOffset>0x64</addressOffset> 7109 <fields> 7110 <field> 7111 <name>RAM0</name> 7112 <description>ECC System RAM0 Error Flag. Write 1 to clear.</description> 7113 <bitOffset>0</bitOffset> 7114 <bitWidth>1</bitWidth> 7115 </field> 7116 <field> 7117 <name>RAM1</name> 7118 <description>ECC System RAM1 Error Flag. Write 1 to clear.</description> 7119 <bitOffset>1</bitOffset> 7120 <bitWidth>1</bitWidth> 7121 </field> 7122 <field> 7123 <name>RAM2</name> 7124 <description>ECC System RAM2 Error Flag. Write 1 to clear.</description> 7125 <bitOffset>2</bitOffset> 7126 <bitWidth>1</bitWidth> 7127 </field> 7128 <field> 7129 <name>RAM3</name> 7130 <description>ECC System RAM3 Error Flag. Write 1 to clear.</description> 7131 <bitOffset>3</bitOffset> 7132 <bitWidth>1</bitWidth> 7133 </field> 7134 <field> 7135 <name>RAM4</name> 7136 <description>ECC System RAM4 Error Flag. Write 1 to clear.</description> 7137 <bitOffset>4</bitOffset> 7138 <bitWidth>1</bitWidth> 7139 </field> 7140 <field> 7141 <name>RAM5</name> 7142 <description>ECC System RAM5 Error Flag. Write 1 to clear.</description> 7143 <bitOffset>5</bitOffset> 7144 <bitWidth>1</bitWidth> 7145 </field> 7146 <field> 7147 <name>RAM6</name> 7148 <description>ECC System RAM6 Error Flag. Write 1 to clear.</description> 7149 <bitOffset>6</bitOffset> 7150 <bitWidth>1</bitWidth> 7151 </field> 7152 <field> 7153 <name>ICACHE0</name> 7154 <description>ECC System ICACHE0 Error Flag. Write 1 to clear.</description> 7155 <bitOffset>8</bitOffset> 7156 <bitWidth>1</bitWidth> 7157 </field> 7158 <field> 7159 <name>ICACHEXIP</name> 7160 <description>ECC System ICACHEXIP Error Flag. Write 1 to clear.</description> 7161 <bitOffset>10</bitOffset> 7162 <bitWidth>1</bitWidth> 7163 </field> 7164 </fields> 7165 </register> 7166 <register> 7167 <name>ECCCED</name> 7168 <description>ECC Not Double Error Detect Register</description> 7169 <addressOffset>0x68</addressOffset> 7170 <fields> 7171 <field> 7172 <name>RAM0</name> 7173 <description>ECC System RAM0 Error Flag. Write 1 to clear.</description> 7174 <bitOffset>0</bitOffset> 7175 <bitWidth>1</bitWidth> 7176 </field> 7177 <field> 7178 <name>RAM1</name> 7179 <description>ECC System RAM1 Error Flag. Write 1 to clear.</description> 7180 <bitOffset>1</bitOffset> 7181 <bitWidth>1</bitWidth> 7182 </field> 7183 <field> 7184 <name>RAM2</name> 7185 <description>ECC System RAM2 Error Flag. Write 1 to clear.</description> 7186 <bitOffset>2</bitOffset> 7187 <bitWidth>1</bitWidth> 7188 </field> 7189 <field> 7190 <name>RAM3</name> 7191 <description>ECC System RAM3 Error Flag. Write 1 to clear.</description> 7192 <bitOffset>3</bitOffset> 7193 <bitWidth>1</bitWidth> 7194 </field> 7195 <field> 7196 <name>RAM4</name> 7197 <description>ECC System RAM4 Error Flag. Write 1 to clear.</description> 7198 <bitOffset>4</bitOffset> 7199 <bitWidth>1</bitWidth> 7200 </field> 7201 <field> 7202 <name>RAM5</name> 7203 <description>ECC System RAM5 Error Flag. Write 1 to clear.</description> 7204 <bitOffset>5</bitOffset> 7205 <bitWidth>1</bitWidth> 7206 </field> 7207 <field> 7208 <name>RAM6</name> 7209 <description>ECC System RAM6 Error Flag. Write 1 to clear.</description> 7210 <bitOffset>6</bitOffset> 7211 <bitWidth>1</bitWidth> 7212 </field> 7213 <field> 7214 <name>ICACHE0</name> 7215 <description>ECC System ICACHE0 Error Flag. Write 1 to clear.</description> 7216 <bitOffset>8</bitOffset> 7217 <bitWidth>1</bitWidth> 7218 </field> 7219 <field> 7220 <name>ICACHEXIP</name> 7221 <description>ECC System ICACHEXIP Error Flag. Write 1 to clear.</description> 7222 <bitOffset>10</bitOffset> 7223 <bitWidth>1</bitWidth> 7224 </field> 7225 </fields> 7226 </register> 7227 <register> 7228 <name>ECCIE</name> 7229 <description>ECC IRQ Enable Register</description> 7230 <addressOffset>0x6C</addressOffset> 7231 <fields> 7232 <field> 7233 <name>RAM0</name> 7234 <description>ECC System RAM0 Error Flag. Write 1 to clear.</description> 7235 <bitOffset>0</bitOffset> 7236 <bitWidth>1</bitWidth> 7237 </field> 7238 <field> 7239 <name>RAM1</name> 7240 <description>ECC System RAM1 Error Flag. Write 1 to clear.</description> 7241 <bitOffset>1</bitOffset> 7242 <bitWidth>1</bitWidth> 7243 </field> 7244 <field> 7245 <name>RAM2</name> 7246 <description>ECC System RAM2 Error Flag. Write 1 to clear.</description> 7247 <bitOffset>2</bitOffset> 7248 <bitWidth>1</bitWidth> 7249 </field> 7250 <field> 7251 <name>RAM3</name> 7252 <description>ECC System RAM3 Error Flag. Write 1 to clear.</description> 7253 <bitOffset>3</bitOffset> 7254 <bitWidth>1</bitWidth> 7255 </field> 7256 <field> 7257 <name>RAM4</name> 7258 <description>ECC System RAM4 Error Flag. Write 1 to clear.</description> 7259 <bitOffset>4</bitOffset> 7260 <bitWidth>1</bitWidth> 7261 </field> 7262 <field> 7263 <name>RAM5</name> 7264 <description>ECC System RAM5 Error Flag. Write 1 to clear.</description> 7265 <bitOffset>5</bitOffset> 7266 <bitWidth>1</bitWidth> 7267 </field> 7268 <field> 7269 <name>RAM6</name> 7270 <description>ECC System RAM6 Error Flag. Write 1 to clear.</description> 7271 <bitOffset>6</bitOffset> 7272 <bitWidth>1</bitWidth> 7273 </field> 7274 <field> 7275 <name>ICACHE0</name> 7276 <description>ECC System ICACHE0 Error Flag. Write 1 to clear.</description> 7277 <bitOffset>8</bitOffset> 7278 <bitWidth>1</bitWidth> 7279 </field> 7280 <field> 7281 <name>ICACHEXIP</name> 7282 <description>ECC System ICACHEXIP Error Flag. Write 1 to clear.</description> 7283 <bitOffset>10</bitOffset> 7284 <bitWidth>1</bitWidth> 7285 </field> 7286 </fields> 7287 </register> 7288 <register> 7289 <name>ECCADDR</name> 7290 <description>ECC Error Address Register</description> 7291 <addressOffset>0x70</addressOffset> 7292 <fields> 7293 <field> 7294 <name>DADDR</name> 7295 <description>Data Address.</description> 7296 <bitOffset>0</bitOffset> 7297 <bitWidth>14</bitWidth> 7298 </field> 7299 <field> 7300 <name>DB</name> 7301 <description>Data Error Bank.</description> 7302 <bitOffset>14</bitOffset> 7303 <bitWidth>1</bitWidth> 7304 </field> 7305 <field> 7306 <name>DE</name> 7307 <description>DE Error.</description> 7308 <bitOffset>15</bitOffset> 7309 <bitWidth>1</bitWidth> 7310 </field> 7311 <field> 7312 <name>TADDR</name> 7313 <description>Tag Address.</description> 7314 <bitOffset>16</bitOffset> 7315 <bitWidth>14</bitWidth> 7316 </field> 7317 <field> 7318 <name>TB</name> 7319 <description>Tag Error Bank.</description> 7320 <bitOffset>30</bitOffset> 7321 <bitWidth>1</bitWidth> 7322 </field> 7323 <field> 7324 <name>TE</name> 7325 <description>Tag Error.</description> 7326 <bitOffset>31</bitOffset> 7327 <bitWidth>1</bitWidth> 7328 </field> 7329 </fields> 7330 </register> 7331 <register> 7332 <name>BTLELDOCTRL</name> 7333 <description>BTLE LDO Control Register</description> 7334 <addressOffset>0x74</addressOffset> 7335 <fields> 7336 <field> 7337 <name>LDOTXEN</name> 7338 <description>LDOTX Enable.</description> 7339 <bitOffset>0</bitOffset> 7340 <bitWidth>1</bitWidth> 7341 </field> 7342 <field> 7343 <name>LDOTXPULLD</name> 7344 <description>LDOTX Pull Down.</description> 7345 <bitOffset>1</bitOffset> 7346 <bitWidth>1</bitWidth> 7347 </field> 7348 <field> 7349 <name>LDOTXVSEL</name> 7350 <description>LDOTX Voltage Setting.</description> 7351 <bitOffset>2</bitOffset> 7352 <bitWidth>2</bitWidth> 7353 </field> 7354 <field> 7355 <name>LDORXEN</name> 7356 <description>LDORX Enable.</description> 7357 <bitOffset>4</bitOffset> 7358 <bitWidth>1</bitWidth> 7359 </field> 7360 <field> 7361 <name>LDORXPULLD</name> 7362 <description>LDOrX Pull Down.</description> 7363 <bitOffset>5</bitOffset> 7364 <bitWidth>1</bitWidth> 7365 </field> 7366 <field> 7367 <name>LDORXVSEL</name> 7368 <description>LDORX Voltage Setting.</description> 7369 <bitOffset>6</bitOffset> 7370 <bitWidth>2</bitWidth> 7371 </field> 7372 <field> 7373 <name>LDORXBYP</name> 7374 <description>LDORX Bypass Enable.</description> 7375 <bitOffset>8</bitOffset> 7376 <bitWidth>1</bitWidth> 7377 </field> 7378 <field> 7379 <name>LDORXDISCH</name> 7380 <description>LDORX Discharge.</description> 7381 <bitOffset>9</bitOffset> 7382 <bitWidth>1</bitWidth> 7383 </field> 7384 <field> 7385 <name>LDOTXBYP</name> 7386 <description>LDOTX Bypass Enable.</description> 7387 <bitOffset>10</bitOffset> 7388 <bitWidth>1</bitWidth> 7389 </field> 7390 <field> 7391 <name>LDOTXDISCH</name> 7392 <description>LDOTX Discharge.</description> 7393 <bitOffset>11</bitOffset> 7394 <bitWidth>1</bitWidth> 7395 </field> 7396 <field> 7397 <name>LDOTXENDLY</name> 7398 <description>LDOTX Enable Delay.</description> 7399 <bitOffset>12</bitOffset> 7400 <bitWidth>1</bitWidth> 7401 </field> 7402 <field> 7403 <name>LDORXENDLY</name> 7404 <description>LDORX Enable Delay.</description> 7405 <bitOffset>13</bitOffset> 7406 <bitWidth>1</bitWidth> 7407 </field> 7408 <field> 7409 <name>LDORXBYPENENDLY</name> 7410 <description>LDORX Bypass Enable Delay.</description> 7411 <bitOffset>14</bitOffset> 7412 <bitWidth>1</bitWidth> 7413 </field> 7414 <field> 7415 <name>LDOTXBYPENENDLY</name> 7416 <description>LDOTX Bypass Enable Delay.</description> 7417 <bitOffset>15</bitOffset> 7418 <bitWidth>1</bitWidth> 7419 </field> 7420 </fields> 7421 </register> 7422 <register> 7423 <name>BTLELDODLY</name> 7424 <description>BTLE LDO Delay Register</description> 7425 <addressOffset>0x78</addressOffset> 7426 <fields> 7427 <field> 7428 <name>BYPDLYCNT</name> 7429 <description>Bypass Delay Count.</description> 7430 <bitOffset>0</bitOffset> 7431 <bitWidth>8</bitWidth> 7432 </field> 7433 <field> 7434 <name>LDOTXDLYCNT</name> 7435 <description>LDOTX Delay Count.</description> 7436 <bitOffset>8</bitOffset> 7437 <bitWidth>9</bitWidth> 7438 </field> 7439 <field> 7440 <name>LDORXDLYCNT</name> 7441 <description>LDORX Delay Count.</description> 7442 <bitOffset>20</bitOffset> 7443 <bitWidth>9</bitWidth> 7444 </field> 7445 </fields> 7446 </register> 7447 <register> 7448 <name>GPR0</name> 7449 <description>General Purpose Register 0</description> 7450 <addressOffset>0x80</addressOffset> 7451 </register> 7452 </registers> 7453 </peripheral> 7454<!--GCR Global Control Registers.--> 7455 <peripheral> 7456 <name>GCFR</name> 7457 <description>Global Control Function Register.</description> 7458 <baseAddress>0x40005800</baseAddress> 7459 <addressBlock> 7460 <offset>0x00</offset> 7461 <size>0x400</size> 7462 <usage>registers</usage> 7463 </addressBlock> 7464 <registers> 7465 <register> 7466 <name>REG0</name> 7467 <description>Register 0.</description> 7468 <addressOffset>0x00</addressOffset> 7469 <access>read-write</access> 7470 <fields> 7471 <field> 7472 <name>CKPDRV</name> 7473 <description>Hyperbus CKP Drive Setting.</description> 7474 <bitOffset>0</bitOffset> 7475 <bitWidth>4</bitWidth> 7476 </field> 7477 <field> 7478 <name>CKNDRV</name> 7479 <description>Hyperbus CKN Drive Setting.</description> 7480 <bitOffset>4</bitOffset> 7481 <bitWidth>4</bitWidth> 7482 </field> 7483 <field> 7484 <name>RDSDLL_EN</name> 7485 <description>Hyperbus RDS DLL Enable.</description> 7486 <bitOffset>8</bitOffset> 7487 <bitWidth>1</bitWidth> 7488 </field> 7489 </fields> 7490 </register> 7491 </registers> 7492 </peripheral> 7493<!--GCFR Global Control Function Register.--> 7494 <peripheral> 7495 <name>GPIO0</name> 7496 <description>Individual I/O for each GPIO</description> 7497 <groupName>GPIO</groupName> 7498 <baseAddress>0x40008000</baseAddress> 7499 <addressBlock> 7500 <offset>0x00</offset> 7501 <size>0x1000</size> 7502 <usage>registers</usage> 7503 </addressBlock> 7504 <interrupt> 7505 <name>GPIO0</name> 7506 <description>GPIO0 interrupt.</description> 7507 <value>24</value> 7508 </interrupt> 7509 <registers> 7510 <register> 7511 <name>EN0</name> 7512 <description>GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port.</description> 7513 <addressOffset>0x00</addressOffset> 7514 <fields> 7515 <field> 7516 <name>GPIO_EN</name> 7517 <description>Mask of all of the pins on the port.</description> 7518 <bitOffset>0</bitOffset> 7519 <bitWidth>32</bitWidth> 7520 <enumeratedValues> 7521 <enumeratedValue> 7522 <name>ALTERNATE</name> 7523 <description>Alternate function enabled.</description> 7524 <value>0</value> 7525 </enumeratedValue> 7526 <enumeratedValue> 7527 <name>GPIO</name> 7528 <description>GPIO function is enabled.</description> 7529 <value>1</value> 7530 </enumeratedValue> 7531 </enumeratedValues> 7532 </field> 7533 </fields> 7534 </register> 7535 <register> 7536 <name>EN0_SET</name> 7537 <description>GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1, without affecting other bits in that register.</description> 7538 <addressOffset>0x04</addressOffset> 7539 <fields> 7540 <field> 7541 <name>ALL</name> 7542 <description>Mask of all of the pins on the port.</description> 7543 <bitOffset>0</bitOffset> 7544 <bitWidth>32</bitWidth> 7545 </field> 7546 </fields> 7547 </register> 7548 <register> 7549 <name>EN0_CLR</name> 7550 <description>GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register.</description> 7551 <addressOffset>0x08</addressOffset> 7552 <fields> 7553 <field> 7554 <name>ALL</name> 7555 <description>Mask of all of the pins on the port.</description> 7556 <bitOffset>0</bitOffset> 7557 <bitWidth>32</bitWidth> 7558 </field> 7559 </fields> 7560 </register> 7561 <register> 7562 <name>OUTEN</name> 7563 <description>GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port.</description> 7564 <addressOffset>0x0C</addressOffset> 7565 <fields> 7566 <field> 7567 <name>EN</name> 7568 <description>Mask of all of the pins on the port.</description> 7569 <bitOffset>0</bitOffset> 7570 <bitWidth>32</bitWidth> 7571 <enumeratedValues> 7572 <enumeratedValue> 7573 <name>dis</name> 7574 <description>GPIO Output Disable</description> 7575 <value>0</value> 7576 </enumeratedValue> 7577 <enumeratedValue> 7578 <name>en</name> 7579 <description>GPIO Output Enable</description> 7580 <value>1</value> 7581 </enumeratedValue> 7582 </enumeratedValues> 7583 </field> 7584 </fields> 7585 </register> 7586 <register> 7587 <name>OUTEN_SET</name> 7588 <description>GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1, without affecting other bits in that register.</description> 7589 <addressOffset>0x10</addressOffset> 7590 <fields> 7591 <field> 7592 <name>ALL</name> 7593 <description>Mask of all of the pins on the port.</description> 7594 <bitOffset>0</bitOffset> 7595 <bitWidth>32</bitWidth> 7596 </field> 7597 </fields> 7598 </register> 7599 <register> 7600 <name>OUTEN_CLR</name> 7601 <description>GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, without affecting other bits in that register.</description> 7602 <addressOffset>0x14</addressOffset> 7603 <fields> 7604 <field> 7605 <name>ALL</name> 7606 <description>Mask of all of the pins on the port.</description> 7607 <bitOffset>0</bitOffset> 7608 <bitWidth>32</bitWidth> 7609 </field> 7610 </fields> 7611 </register> 7612 <register> 7613 <name>OUT</name> 7614 <description>GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers.</description> 7615 <addressOffset>0x18</addressOffset> 7616 <fields> 7617 <field> 7618 <name>GPIO_OUT</name> 7619 <description>Mask of all of the pins on the port.</description> 7620 <bitOffset>0</bitOffset> 7621 <bitWidth>32</bitWidth> 7622 <enumeratedValues> 7623 <enumeratedValue> 7624 <name>low</name> 7625 <description>Drive Logic 0 (low) on GPIO output.</description> 7626 <value>0</value> 7627 </enumeratedValue> 7628 <enumeratedValue> 7629 <name>high</name> 7630 <description>Drive logic 1 (high) on GPIO output.</description> 7631 <value>1</value> 7632 </enumeratedValue> 7633 </enumeratedValues> 7634 </field> 7635 </fields> 7636 </register> 7637 <register> 7638 <name>OUT_SET</name> 7639 <description>GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1, without affecting other bits in that register.</description> 7640 <addressOffset>0x1C</addressOffset> 7641 <access>write-only</access> 7642 <fields> 7643 <field> 7644 <name>GPIO_OUT_SET</name> 7645 <description>Mask of all of the pins on the port.</description> 7646 <bitOffset>0</bitOffset> 7647 <bitWidth>32</bitWidth> 7648 <enumeratedValues> 7649 <enumeratedValue> 7650 <name>no</name> 7651 <description>No Effect.</description> 7652 <value>0</value> 7653 </enumeratedValue> 7654 <enumeratedValue> 7655 <name>set</name> 7656 <description>Set GPIO_OUT bit in this position to '1'</description> 7657 <value>1</value> 7658 </enumeratedValue> 7659 </enumeratedValues> 7660 </field> 7661 </fields> 7662 </register> 7663 <register> 7664 <name>OUT_CLR</name> 7665 <description>GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0, without affecting other bits in that register.</description> 7666 <addressOffset>0x20</addressOffset> 7667 <access>write-only</access> 7668 <fields> 7669 <field> 7670 <name>GPIO_OUT_CLR</name> 7671 <description>Mask of all of the pins on the port.</description> 7672 <bitOffset>0</bitOffset> 7673 <bitWidth>32</bitWidth> 7674 </field> 7675 </fields> 7676 </register> 7677 <register> 7678 <name>IN</name> 7679 <description>GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port.</description> 7680 <addressOffset>0x24</addressOffset> 7681 <access>read-only</access> 7682 <fields> 7683 <field> 7684 <name>GPIO_IN</name> 7685 <description>Mask of all of the pins on the port.</description> 7686 <bitOffset>0</bitOffset> 7687 <bitWidth>32</bitWidth> 7688 </field> 7689 </fields> 7690 </register> 7691 <register> 7692 <name>INTMODE</name> 7693 <description>GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port.</description> 7694 <addressOffset>0x28</addressOffset> 7695 <fields> 7696 <field> 7697 <name>GPIO_INTMODE</name> 7698 <description>Mask of all of the pins on the port.</description> 7699 <bitOffset>0</bitOffset> 7700 <bitWidth>32</bitWidth> 7701 <enumeratedValues> 7702 <enumeratedValue> 7703 <name>level</name> 7704 <description>Interrupts for this pin are level triggered.</description> 7705 <value>0</value> 7706 </enumeratedValue> 7707 <enumeratedValue> 7708 <name>edge</name> 7709 <description>Interrupts for this pin are edge triggered.</description> 7710 <value>1</value> 7711 </enumeratedValue> 7712 </enumeratedValues> 7713 </field> 7714 </fields> 7715 </register> 7716 <register> 7717 <name>INTPOL</name> 7718 <description>GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port.</description> 7719 <addressOffset>0x2C</addressOffset> 7720 <fields> 7721 <field> 7722 <name>GPIO_INTPOL</name> 7723 <description>Mask of all of the pins on the port.</description> 7724 <bitOffset>0</bitOffset> 7725 <bitWidth>32</bitWidth> 7726 <enumeratedValues> 7727 <enumeratedValue> 7728 <name>falling</name> 7729 <description>Interrupts are latched on a falling edge or low level condition for this pin.</description> 7730 <value>0</value> 7731 </enumeratedValue> 7732 <enumeratedValue> 7733 <name>rising</name> 7734 <description>Interrupts are latched on a rising edge or high condition for this pin.</description> 7735 <value>1</value> 7736 </enumeratedValue> 7737 </enumeratedValues> 7738 </field> 7739 </fields> 7740 </register> 7741 <register> 7742 <name>INEN</name> 7743 <description>GPIO Input Enable</description> 7744 <addressOffset>0x30</addressOffset> 7745 </register> 7746 <register> 7747 <name>INTEN</name> 7748 <description>GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port.</description> 7749 <addressOffset>0x34</addressOffset> 7750 <fields> 7751 <field> 7752 <name>GPIO_INTEN</name> 7753 <description>Mask of all of the pins on the port.</description> 7754 <bitOffset>0</bitOffset> 7755 <bitWidth>32</bitWidth> 7756 <enumeratedValues> 7757 <enumeratedValue> 7758 <name>dis</name> 7759 <description>Interrupts are disabled for this GPIO pin.</description> 7760 <value>0</value> 7761 </enumeratedValue> 7762 <enumeratedValue> 7763 <name>en</name> 7764 <description>Interrupts are enabled for this GPIO pin.</description> 7765 <value>1</value> 7766 </enumeratedValue> 7767 </enumeratedValues> 7768 </field> 7769 </fields> 7770 </register> 7771 <register> 7772 <name>INTEN_SET</name> 7773 <description>GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits in that register.</description> 7774 <addressOffset>0x38</addressOffset> 7775 <fields> 7776 <field> 7777 <name>GPIO_INTEN_SET</name> 7778 <description>Mask of all of the pins on the port.</description> 7779 <bitOffset>0</bitOffset> 7780 <bitWidth>32</bitWidth> 7781 <enumeratedValues> 7782 <enumeratedValue> 7783 <name>no</name> 7784 <description>No effect.</description> 7785 <value>0</value> 7786 </enumeratedValue> 7787 <enumeratedValue> 7788 <name>set</name> 7789 <description>Set GPIO_INT_EN bit in this position to '1'</description> 7790 <value>1</value> 7791 </enumeratedValue> 7792 </enumeratedValues> 7793 </field> 7794 </fields> 7795 </register> 7796 <register> 7797 <name>INTEN_CLR</name> 7798 <description>GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0, without affecting other bits in that register.</description> 7799 <addressOffset>0x3C</addressOffset> 7800 <fields> 7801 <field> 7802 <name>GPIO_INTEN_CLR</name> 7803 <description>Mask of all of the pins on the port.</description> 7804 <bitOffset>0</bitOffset> 7805 <bitWidth>32</bitWidth> 7806 <enumeratedValues> 7807 <enumeratedValue> 7808 <name>no</name> 7809 <description>No Effect.</description> 7810 <value>0</value> 7811 </enumeratedValue> 7812 <enumeratedValue> 7813 <name>clear</name> 7814 <description>Clear GPIO_INT_EN bit in this position to '0'</description> 7815 <value>1</value> 7816 </enumeratedValue> 7817 </enumeratedValues> 7818 </field> 7819 </fields> 7820 </register> 7821 <register> 7822 <name>INTFL</name> 7823 <description>GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port.</description> 7824 <addressOffset>0x40</addressOffset> 7825 <access>read-only</access> 7826 <fields> 7827 <field> 7828 <name>GPIO_INTFL</name> 7829 <description>Mask of all of the pins on the port.</description> 7830 <bitOffset>0</bitOffset> 7831 <bitWidth>32</bitWidth> 7832 <enumeratedValues> 7833 <enumeratedValue> 7834 <name>no</name> 7835 <description>No Interrupt is pending on this GPIO pin.</description> 7836 <value>0</value> 7837 </enumeratedValue> 7838 <enumeratedValue> 7839 <name>pending</name> 7840 <description>An Interrupt is pending on this GPIO pin.</description> 7841 <value>1</value> 7842 </enumeratedValue> 7843 </enumeratedValues> 7844 </field> 7845 </fields> 7846 </register> 7847 <register> 7848 <name>INTFL_CLR</name> 7849 <description>GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits in that register.</description> 7850 <addressOffset>0x48</addressOffset> 7851 <fields> 7852 <field> 7853 <name>ALL</name> 7854 <description>Mask of all of the pins on the port.</description> 7855 <bitOffset>0</bitOffset> 7856 <bitWidth>32</bitWidth> 7857 </field> 7858 </fields> 7859 </register> 7860 <register> 7861 <name>WKEN</name> 7862 <description>GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port.</description> 7863 <addressOffset>0x4C</addressOffset> 7864 <fields> 7865 <field> 7866 <name>GPIO_WKEN</name> 7867 <description>Mask of all of the pins on the port.</description> 7868 <bitOffset>0</bitOffset> 7869 <bitWidth>32</bitWidth> 7870 <enumeratedValues> 7871 <enumeratedValue> 7872 <name>dis</name> 7873 <description>PMU wakeup for this GPIO is disabled.</description> 7874 <value>0</value> 7875 </enumeratedValue> 7876 <enumeratedValue> 7877 <name>en</name> 7878 <description>PMU wakeup for this GPIO is enabled.</description> 7879 <value>1</value> 7880 </enumeratedValue> 7881 </enumeratedValues> 7882 </field> 7883 </fields> 7884 </register> 7885 <register> 7886 <name>WKEN_SET</name> 7887 <description>GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in that register.</description> 7888 <addressOffset>0x50</addressOffset> 7889 <fields> 7890 <field> 7891 <name>ALL</name> 7892 <description>Mask of all of the pins on the port.</description> 7893 <bitOffset>0</bitOffset> 7894 <bitWidth>32</bitWidth> 7895 </field> 7896 </fields> 7897 </register> 7898 <register> 7899 <name>WKEN_CLR</name> 7900 <description>GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other bits in that register.</description> 7901 <addressOffset>0x54</addressOffset> 7902 <fields> 7903 <field> 7904 <name>ALL</name> 7905 <description>Mask of all of the pins on the port.</description> 7906 <bitOffset>0</bitOffset> 7907 <bitWidth>32</bitWidth> 7908 </field> 7909 </fields> 7910 </register> 7911 <register> 7912 <name>DUALEDGE</name> 7913 <description>GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port.</description> 7914 <addressOffset>0x5C</addressOffset> 7915 <fields> 7916 <field> 7917 <name>GPIO_DUALEDGE</name> 7918 <description>Mask of all of the pins on the port.</description> 7919 <bitOffset>0</bitOffset> 7920 <bitWidth>32</bitWidth> 7921 <enumeratedValues> 7922 <enumeratedValue> 7923 <name>no</name> 7924 <description>No Effect.</description> 7925 <value>0</value> 7926 </enumeratedValue> 7927 <enumeratedValue> 7928 <name>en</name> 7929 <description>Dual Edge mode is enabled. If edge-triggered interrupts are enabled on this GPIO pin, then both rising and falling edges will trigger interrupts regardless of the GPIO_INT_POL setting.</description> 7930 <value>1</value> 7931 </enumeratedValue> 7932 </enumeratedValues> 7933 </field> 7934 </fields> 7935 </register> 7936 <register> 7937 <name>PADCTRL0</name> 7938 <description>GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port.</description> 7939 <addressOffset>0x60</addressOffset> 7940 <fields> 7941 <field> 7942 <name>GPIO_PADCTRL0</name> 7943 <description>The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode.</description> 7944 <bitOffset>0</bitOffset> 7945 <bitWidth>32</bitWidth> 7946 <enumeratedValues> 7947 <enumeratedValue> 7948 <name>impedance</name> 7949 <description>High Impedance.</description> 7950 <value>0</value> 7951 </enumeratedValue> 7952 <enumeratedValue> 7953 <name>pu</name> 7954 <description>Weak pull-up mode.</description> 7955 <value>1</value> 7956 </enumeratedValue> 7957 <enumeratedValue> 7958 <name>pd</name> 7959 <description>weak pull-down mode.</description> 7960 <value>2</value> 7961 </enumeratedValue> 7962 </enumeratedValues> 7963 </field> 7964 </fields> 7965 </register> 7966 <register> 7967 <name>PADCTRL1</name> 7968 <description>GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port.</description> 7969 <addressOffset>0x64</addressOffset> 7970 <fields> 7971 <field> 7972 <name>GPIO_PADCTRL1</name> 7973 <description>The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode.</description> 7974 <bitOffset>0</bitOffset> 7975 <bitWidth>32</bitWidth> 7976 <enumeratedValues> 7977 <enumeratedValue> 7978 <name>impedance</name> 7979 <description>High Impedance.</description> 7980 <value>0</value> 7981 </enumeratedValue> 7982 <enumeratedValue> 7983 <name>pu</name> 7984 <description>Weak pull-up mode.</description> 7985 <value>1</value> 7986 </enumeratedValue> 7987 <enumeratedValue> 7988 <name>pd</name> 7989 <description>weak pull-down mode.</description> 7990 <value>2</value> 7991 </enumeratedValue> 7992 </enumeratedValues> 7993 </field> 7994 </fields> 7995 </register> 7996 <register> 7997 <name>EN1</name> 7998 <description>GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port.</description> 7999 <addressOffset>0x68</addressOffset> 8000 <fields> 8001 <field> 8002 <name>GPIO_EN1</name> 8003 <description>Mask of all of the pins on the port.</description> 8004 <bitOffset>0</bitOffset> 8005 <bitWidth>32</bitWidth> 8006 <enumeratedValues> 8007 <enumeratedValue> 8008 <name>primary</name> 8009 <description>Primary function selected.</description> 8010 <value>0</value> 8011 </enumeratedValue> 8012 <enumeratedValue> 8013 <name>secondary</name> 8014 <description>Secondary function selected.</description> 8015 <value>1</value> 8016 </enumeratedValue> 8017 </enumeratedValues> 8018 </field> 8019 </fields> 8020 </register> 8021 <register> 8022 <name>EN1_SET</name> 8023 <description>GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1, without affecting other bits in that register.</description> 8024 <addressOffset>0x6C</addressOffset> 8025 <fields> 8026 <field> 8027 <name>ALL</name> 8028 <description>Mask of all of the pins on the port.</description> 8029 <bitOffset>0</bitOffset> 8030 <bitWidth>32</bitWidth> 8031 </field> 8032 </fields> 8033 </register> 8034 <register> 8035 <name>EN1_CLR</name> 8036 <description>GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0, without affecting other bits in that register.</description> 8037 <addressOffset>0x70</addressOffset> 8038 <fields> 8039 <field> 8040 <name>ALL</name> 8041 <description>Mask of all of the pins on the port.</description> 8042 <bitOffset>0</bitOffset> 8043 <bitWidth>32</bitWidth> 8044 </field> 8045 </fields> 8046 </register> 8047 <register> 8048 <name>EN2</name> 8049 <description>GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port.</description> 8050 <addressOffset>0x74</addressOffset> 8051 <fields> 8052 <field> 8053 <name>GPIO_EN2</name> 8054 <description>Mask of all of the pins on the port.</description> 8055 <bitOffset>0</bitOffset> 8056 <bitWidth>32</bitWidth> 8057 <enumeratedValues> 8058 <enumeratedValue> 8059 <name>primary</name> 8060 <description>Primary function selected.</description> 8061 <value>0</value> 8062 </enumeratedValue> 8063 <enumeratedValue> 8064 <name>secondary</name> 8065 <description>Secondary function selected.</description> 8066 <value>1</value> 8067 </enumeratedValue> 8068 </enumeratedValues> 8069 </field> 8070 </fields> 8071 </register> 8072 <register> 8073 <name>EN2_SET</name> 8074 <description>GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1, without affecting other bits in that register.</description> 8075 <addressOffset>0x78</addressOffset> 8076 <fields> 8077 <field> 8078 <name>ALL</name> 8079 <description>Mask of all of the pins on the port.</description> 8080 <bitOffset>0</bitOffset> 8081 <bitWidth>32</bitWidth> 8082 </field> 8083 </fields> 8084 </register> 8085 <register> 8086 <name>EN2_CLR</name> 8087 <description>GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0, without affecting other bits in that register.</description> 8088 <addressOffset>0x7C</addressOffset> 8089 <fields> 8090 <field> 8091 <name>ALL</name> 8092 <description>Mask of all of the pins on the port.</description> 8093 <bitOffset>0</bitOffset> 8094 <bitWidth>32</bitWidth> 8095 </field> 8096 </fields> 8097 </register> 8098 <register> 8099 <name>HYSEN</name> 8100 <description>GPIO Input Hysteresis Enable.</description> 8101 <addressOffset>0xA8</addressOffset> 8102 <fields> 8103 <field> 8104 <name>GPIO_HYSEN</name> 8105 <description>Mask of all of the pins on the port.</description> 8106 <bitOffset>0</bitOffset> 8107 <bitWidth>32</bitWidth> 8108 </field> 8109 </fields> 8110 </register> 8111 <register> 8112 <name>SRSEL</name> 8113 <description>GPIO Slew Rate Enable Register.</description> 8114 <addressOffset>0xAC</addressOffset> 8115 <fields> 8116 <field> 8117 <name>GPIO_SRSEL</name> 8118 <description>Mask of all of the pins on the port.</description> 8119 <bitOffset>0</bitOffset> 8120 <bitWidth>32</bitWidth> 8121 <enumeratedValues> 8122 <enumeratedValue> 8123 <name>FAST</name> 8124 <description>Fast Slew Rate selected.</description> 8125 <value>0</value> 8126 </enumeratedValue> 8127 <enumeratedValue> 8128 <name>SLOW</name> 8129 <description>Slow Slew Rate selected.</description> 8130 <value>1</value> 8131 </enumeratedValue> 8132 </enumeratedValues> 8133 </field> 8134 </fields> 8135 </register> 8136 <register> 8137 <name>DS0</name> 8138 <description>GPIO Drive Strength Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode.</description> 8139 <addressOffset>0xB0</addressOffset> 8140 <fields> 8141 <field> 8142 <name>GPIO_DS0</name> 8143 <description>Mask of all of the pins on the port.</description> 8144 <bitOffset>0</bitOffset> 8145 <bitWidth>32</bitWidth> 8146 <enumeratedValues> 8147 <enumeratedValue> 8148 <name>ld</name> 8149 <description>GPIO port pin is in low-drive mode.</description> 8150 <value>0</value> 8151 </enumeratedValue> 8152 <enumeratedValue> 8153 <name>hd</name> 8154 <description>GPIO port pin is in high-drive mode.</description> 8155 <value>1</value> 8156 </enumeratedValue> 8157 </enumeratedValues> 8158 </field> 8159 </fields> 8160 </register> 8161 <register> 8162 <name>DS1</name> 8163 <description>GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode.</description> 8164 <addressOffset>0xB4</addressOffset> 8165 <fields> 8166 <field> 8167 <name>GPIO_DS1</name> 8168 <description>Mask of all of the pins on the port.</description> 8169 <bitOffset>0</bitOffset> 8170 <bitWidth>32</bitWidth> 8171 </field> 8172 </fields> 8173 </register> 8174 <register> 8175 <name>PS</name> 8176 <description>GPIO Pull Select Mode.</description> 8177 <addressOffset>0xB8</addressOffset> 8178 <fields> 8179 <field> 8180 <name>ALL</name> 8181 <description>Mask of all of the pins on the port.</description> 8182 <bitOffset>0</bitOffset> 8183 <bitWidth>32</bitWidth> 8184 </field> 8185 </fields> 8186 </register> 8187 <register> 8188 <name>VSSEL</name> 8189 <description>GPIO Voltage Select.</description> 8190 <addressOffset>0xC0</addressOffset> 8191 <fields> 8192 <field> 8193 <name>ALL</name> 8194 <description>Mask of all of the pins on the port.</description> 8195 <bitOffset>0</bitOffset> 8196 <bitWidth>32</bitWidth> 8197 </field> 8198 </fields> 8199 </register> 8200 </registers> 8201 </peripheral> 8202<!--GPIO0 Individual I/O for each GPIO--> 8203 <peripheral derivedFrom="GPIO0"> 8204 <name>GPIO1</name> 8205 <description>Individual I/O for each GPIO 1</description> 8206 <baseAddress>0x40009000</baseAddress> 8207 <interrupt> 8208 <name>GPIO1</name> 8209 <description>GPIO1 IRQ</description> 8210 <value>25</value> 8211 </interrupt> 8212 </peripheral> 8213<!--GPIO1 Individual I/O for each GPIO 1--> 8214 <peripheral derivedFrom="GPIO0"> 8215 <name>GPIO2</name> 8216 <description>Individual I/O for each GPIO 2</description> 8217 <baseAddress>0x4000A000</baseAddress> 8218 <interrupt> 8219 <name>GPIO2</name> 8220 <description>GPIO2 IRQ</description> 8221 <value>26</value> 8222 </interrupt> 8223 </peripheral> 8224<!--GPIO2 Individual I/O for each GPIO 2--> 8225 <peripheral derivedFrom="GPIO0"> 8226 <name>GPIO3</name> 8227 <description>Individual I/O for each GPIO 3</description> 8228 <baseAddress>0x40080400</baseAddress> 8229 <interrupt> 8230 <name>GPIO3</name> 8231 <description>GPIO3 IRQ</description> 8232 <value>58</value> 8233 </interrupt> 8234 </peripheral> 8235<!--GPIO3 Individual I/O for each GPIO 3--> 8236 <peripheral> 8237 <name>I2C0</name> 8238 <description>Inter-Integrated Circuit.</description> 8239 <groupName>I2C</groupName> 8240 <baseAddress>0x4001D000</baseAddress> 8241 <size>32</size> 8242 <addressBlock> 8243 <offset>0x00</offset> 8244 <size>0x1000</size> 8245 <usage>registers</usage> 8246 </addressBlock> 8247 <interrupt> 8248 <name>I2C0</name> 8249 <description>I2C0 IRQ</description> 8250 <value>13</value> 8251 </interrupt> 8252 <registers> 8253 <register> 8254 <name>CTRL</name> 8255 <description>Control Register0.</description> 8256 <addressOffset>0x00</addressOffset> 8257 <fields> 8258 <field> 8259 <name>EN</name> 8260 <description>I2C Enable.</description> 8261 <bitRange>[0:0]</bitRange> 8262 <access>read-write</access> 8263 <enumeratedValues> 8264 <enumeratedValue> 8265 <name>dis</name> 8266 <description>Disable I2C.</description> 8267 <value>0</value> 8268 </enumeratedValue> 8269 <enumeratedValue> 8270 <name>en</name> 8271 <description>enable I2C.</description> 8272 <value>1</value> 8273 </enumeratedValue> 8274 </enumeratedValues> 8275 </field> 8276 <field> 8277 <name>MST_MODE</name> 8278 <description>Master Mode Enable.</description> 8279 <bitRange>[1:1]</bitRange> 8280 <access>read-write</access> 8281 <enumeratedValues> 8282 <enumeratedValue> 8283 <name>slave_mode</name> 8284 <description>Slave Mode.</description> 8285 <value>0</value> 8286 </enumeratedValue> 8287 <enumeratedValue> 8288 <name>master_mode</name> 8289 <description>Master Mode.</description> 8290 <value>1</value> 8291 </enumeratedValue> 8292 </enumeratedValues> 8293 </field> 8294 <field> 8295 <name>GC_ADDR_EN</name> 8296 <description>General Call Address Enable.</description> 8297 <bitRange>[2:2]</bitRange> 8298 <access>read-write</access> 8299 <enumeratedValues> 8300 <enumeratedValue> 8301 <name>dis</name> 8302 <description>Ignore Gneral Call Address.</description> 8303 <value>0</value> 8304 </enumeratedValue> 8305 <enumeratedValue> 8306 <name>en</name> 8307 <description>Acknowledge general call address.</description> 8308 <value>1</value> 8309 </enumeratedValue> 8310 </enumeratedValues> 8311 </field> 8312 <field> 8313 <name>IRXM_EN</name> 8314 <description>Interactive Receive Mode.</description> 8315 <bitRange>[3:3]</bitRange> 8316 <access>read-write</access> 8317 <enumeratedValues> 8318 <enumeratedValue> 8319 <name>dis</name> 8320 <description>Disable Interactive Receive Mode.</description> 8321 <value>0</value> 8322 </enumeratedValue> 8323 <enumeratedValue> 8324 <name>en</name> 8325 <description>Enable Interactive Receive Mode.</description> 8326 <value>1</value> 8327 </enumeratedValue> 8328 </enumeratedValues> 8329 </field> 8330 <field> 8331 <name>IRXM_ACK</name> 8332 <description>Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0.</description> 8333 <bitRange>[4:4]</bitRange> 8334 <access>read-write</access> 8335 <enumeratedValues> 8336 <enumeratedValue> 8337 <name>ack</name> 8338 <description>return ACK (pulling SDA LOW).</description> 8339 <value>0</value> 8340 </enumeratedValue> 8341 <enumeratedValue> 8342 <name>nack</name> 8343 <description>return NACK (leaving SDA HIGH).</description> 8344 <value>1</value> 8345 </enumeratedValue> 8346 </enumeratedValues> 8347 </field> 8348 <field> 8349 <name>SCL_OUT</name> 8350 <description>SCL Output. This bits control SCL output when SWOE =1.</description> 8351 <bitRange>[6:6]</bitRange> 8352 <access>read-write</access> 8353 <enumeratedValues> 8354 <enumeratedValue> 8355 <name>drive_scl_low</name> 8356 <description>Drive SCL low. </description> 8357 <value>0</value> 8358 </enumeratedValue> 8359 <enumeratedValue> 8360 <name>release_scl</name> 8361 <description>Release SCL.</description> 8362 <value>1</value> 8363 </enumeratedValue> 8364 </enumeratedValues> 8365 </field> 8366 <field> 8367 <name>SDA_OUT</name> 8368 <description>SDA Output. This bits control SDA output when SWOE = 1. </description> 8369 <bitRange>[7:7]</bitRange> 8370 <access>read-write</access> 8371 <enumeratedValues> 8372 <enumeratedValue> 8373 <name>drive_sda_low</name> 8374 <description>Drive SDA low. </description> 8375 <value>0</value> 8376 </enumeratedValue> 8377 <enumeratedValue> 8378 <name>release_sda</name> 8379 <description>Release SDA.</description> 8380 <value>1</value> 8381 </enumeratedValue> 8382 </enumeratedValues> 8383 </field> 8384 <field> 8385 <name>SCL</name> 8386 <description>SCL status. This bit reflects the logic gate of SCL signal. </description> 8387 <bitRange>[8:8]</bitRange> 8388 <access>read-only</access> 8389 </field> 8390 <field> 8391 <name>SDA</name> 8392 <description>SDA status. THis bit reflects the logic gate of SDA signal.</description> 8393 <bitRange>[9:9]</bitRange> 8394 <access>read-only</access> 8395 </field> 8396 <field> 8397 <name>BB_MODE</name> 8398 <description>Software Output Enable.</description> 8399 <bitRange>[10:10]</bitRange> 8400 <access>read-write</access> 8401 <enumeratedValues> 8402 <enumeratedValue> 8403 <name>outputs_disable</name> 8404 <description>I2C Outputs SCLO and SDAO disabled. </description> 8405 <value>0</value> 8406 </enumeratedValue> 8407 <enumeratedValue> 8408 <name>outputs_enable</name> 8409 <description>I2C Outputs SCLO and SDAO enabled.</description> 8410 <value>1</value> 8411 </enumeratedValue> 8412 </enumeratedValues> 8413 </field> 8414 <field> 8415 <name>READ</name> 8416 <description>Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match (GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set.</description> 8417 <bitRange>[11:11]</bitRange> 8418 <access>read-only</access> 8419 <enumeratedValues> 8420 <enumeratedValue> 8421 <name>write</name> 8422 <description>Write.</description> 8423 <value>0</value> 8424 </enumeratedValue> 8425 <enumeratedValue> 8426 <name>read</name> 8427 <description>Read.</description> 8428 <value>1</value> 8429 </enumeratedValue> 8430 </enumeratedValues> 8431 </field> 8432 <field> 8433 <name>CLKSTR_DIS</name> 8434 <description>This bit will disable slave clock stretching when set.</description> 8435 <bitRange>[12:12]</bitRange> 8436 <access>read-write</access> 8437 <enumeratedValues> 8438 <enumeratedValue> 8439 <name>en</name> 8440 <description>Slave clock stretching enabled.</description> 8441 <value>0</value> 8442 </enumeratedValue> 8443 <enumeratedValue> 8444 <name>dis</name> 8445 <description>Slave clock stretching disabled.</description> 8446 <value>1</value> 8447 </enumeratedValue> 8448 </enumeratedValues> 8449 </field> 8450 <field> 8451 <name>ONE_MST_MODE</name> 8452 <description>SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode, or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating as a master and communicating with slaves that are guaranteed to never drive SCL low. </description> 8453 <bitRange>[13:13]</bitRange> 8454 <access>read-write</access> 8455 <enumeratedValues> 8456 <enumeratedValue> 8457 <name>dis</name> 8458 <description>Standard open-drain operation: 8459 drive low for 0, Hi-Z for 1</description> 8460 <value>0</value> 8461 </enumeratedValue> 8462 <enumeratedValue> 8463 <name>en</name> 8464 <description>Non-standard push-pull operation: 8465 drive low for 0, drive high for 1</description> 8466 <value>1</value> 8467 </enumeratedValue> 8468 </enumeratedValues> 8469 </field> 8470 <field> 8471 <name>HS_EN</name> 8472 <description>High speed mode enable</description> 8473 <bitRange>[15:15]</bitRange> 8474 <access>read-write</access> 8475 </field> 8476 </fields> 8477 </register> 8478 <register> 8479 <name>STATUS</name> 8480 <description>Status Register.</description> 8481 <addressOffset>0x04</addressOffset> 8482 <fields> 8483 <field> 8484 <name>BUSY</name> 8485 <description>Bus Status.</description> 8486 <bitRange>[0:0]</bitRange> 8487 <access>read-only</access> 8488 <enumeratedValues> 8489 <enumeratedValue> 8490 <name>idle</name> 8491 <description>I2C Bus Idle.</description> 8492 <value>0</value> 8493 </enumeratedValue> 8494 <enumeratedValue> 8495 <name>busy</name> 8496 <description>I2C Bus Busy.</description> 8497 <value>1</value> 8498 </enumeratedValue> 8499 </enumeratedValues> 8500 </field> 8501 <field> 8502 <name>RX_EM</name> 8503 <description>RX empty.</description> 8504 <bitRange>[1:1]</bitRange> 8505 <access>read-only</access> 8506 <enumeratedValues> 8507 <enumeratedValue> 8508 <name>not_empty</name> 8509 <description>Not Empty.</description> 8510 <value>0</value> 8511 </enumeratedValue> 8512 <enumeratedValue> 8513 <name>empty</name> 8514 <description>Empty.</description> 8515 <value>1</value> 8516 </enumeratedValue> 8517 </enumeratedValues> 8518 </field> 8519 <field> 8520 <name>RX_FULL</name> 8521 <description>RX Full.</description> 8522 <bitRange>[2:2]</bitRange> 8523 <access>read-only</access> 8524 <enumeratedValues> 8525 <enumeratedValue> 8526 <name>not_full</name> 8527 <description>Not Full.</description> 8528 <value>0</value> 8529 </enumeratedValue> 8530 <enumeratedValue> 8531 <name>full</name> 8532 <description>Full.</description> 8533 <value>1</value> 8534 </enumeratedValue> 8535 </enumeratedValues> 8536 </field> 8537 <field> 8538 <name>TX_EM</name> 8539 <description>TX Empty.</description> 8540 <bitRange>[3:3]</bitRange> 8541 <enumeratedValues> 8542 <enumeratedValue> 8543 <name>not_empty</name> 8544 <description>Not Empty.</description> 8545 <value>0</value> 8546 </enumeratedValue> 8547 <enumeratedValue> 8548 <name>empty</name> 8549 <description>Empty.</description> 8550 <value>1</value> 8551 </enumeratedValue> 8552 </enumeratedValues> 8553 </field> 8554 <field> 8555 <name>TX_FULL</name> 8556 <description>TX Full.</description> 8557 <bitRange>[4:4]</bitRange> 8558 <enumeratedValues> 8559 <enumeratedValue> 8560 <name>not_empty</name> 8561 <description>Not Empty.</description> 8562 <value>0</value> 8563 </enumeratedValue> 8564 <enumeratedValue> 8565 <name>empty</name> 8566 <description>Empty.</description> 8567 <value>1</value> 8568 </enumeratedValue> 8569 </enumeratedValues> 8570 </field> 8571 <field> 8572 <name>MST_BUSY</name> 8573 <description>Clock Mode.</description> 8574 <bitRange>[5:5]</bitRange> 8575 <access>read-only</access> 8576 <enumeratedValues> 8577 <enumeratedValue> 8578 <name>not_actively_driving_scl_clock</name> 8579 <description>Device not actively driving SCL clock cycles.</description> 8580 <value>0</value> 8581 </enumeratedValue> 8582 <enumeratedValue> 8583 <name>actively_driving_scl_clock</name> 8584 <description>Device operating as master and actively driving SCL clock cycles.</description> 8585 <value>1</value> 8586 </enumeratedValue> 8587 </enumeratedValues> 8588 </field> 8589 </fields> 8590 </register> 8591 <register> 8592 <name>INTFL0</name> 8593 <description>Interrupt Status Register.</description> 8594 <addressOffset>0x08</addressOffset> 8595 <fields> 8596 <field> 8597 <name>DONE</name> 8598 <description>Transfer Done Interrupt.</description> 8599 <bitRange>[0:0]</bitRange> 8600 <enumeratedValues> 8601 <name>INT_FL0_Done</name> 8602 <enumeratedValue> 8603 <name>inactive</name> 8604 <description>No Interrupt is Pending.</description> 8605 <value>0</value> 8606 </enumeratedValue> 8607 <enumeratedValue> 8608 <name>pending</name> 8609 <description>An interrupt is pending.</description> 8610 <value>1</value> 8611 </enumeratedValue> 8612 </enumeratedValues> 8613 </field> 8614 <field> 8615 <name>IRXM</name> 8616 <description>Interactive Receive Interrupt.</description> 8617 <bitRange>[1:1]</bitRange> 8618 <enumeratedValues> 8619 <enumeratedValue> 8620 <name>inactive</name> 8621 <description>No Interrupt is Pending.</description> 8622 <value>0</value> 8623 </enumeratedValue> 8624 <enumeratedValue> 8625 <name>pending</name> 8626 <description>An interrupt is pending.</description> 8627 <value>1</value> 8628 </enumeratedValue> 8629 </enumeratedValues> 8630 </field> 8631 <field> 8632 <name>GC_ADDR_MATCH</name> 8633 <description>Slave General Call Address Match Interrupt.</description> 8634 <bitRange>[2:2]</bitRange> 8635 <enumeratedValues> 8636 <enumeratedValue> 8637 <name>inactive</name> 8638 <description>No Interrupt is Pending.</description> 8639 <value>0</value> 8640 </enumeratedValue> 8641 <enumeratedValue> 8642 <name>pending</name> 8643 <description>An interrupt is pending.</description> 8644 <value>1</value> 8645 </enumeratedValue> 8646 </enumeratedValues> 8647 </field> 8648 <field> 8649 <name>ADDR_MATCH</name> 8650 <description>Slave Address Match Interrupt.</description> 8651 <bitRange>[3:3]</bitRange> 8652 <enumeratedValues> 8653 <enumeratedValue> 8654 <name>inactive</name> 8655 <description>No Interrupt is Pending.</description> 8656 <value>0</value> 8657 </enumeratedValue> 8658 <enumeratedValue> 8659 <name>pending</name> 8660 <description>An interrupt is pending.</description> 8661 <value>1</value> 8662 </enumeratedValue> 8663 </enumeratedValues> 8664 </field> 8665 <field> 8666 <name>RX_THD</name> 8667 <description>Receive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level.</description> 8668 <bitRange>[4:4]</bitRange> 8669 <enumeratedValues> 8670 <enumeratedValue> 8671 <name>inactive</name> 8672 <description>No interrupt is pending.</description> 8673 <value>0</value> 8674 </enumeratedValue> 8675 <enumeratedValue> 8676 <name>pending</name> 8677 <description>An interrupt is pending. RX_FIFO equal or more bytes than the threshold.</description> 8678 <value>1</value> 8679 </enumeratedValue> 8680 </enumeratedValues> 8681 </field> 8682 <field> 8683 <name>TX_THD</name> 8684 <description>Transmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level.</description> 8685 <bitRange>[5:5]</bitRange> 8686 <enumeratedValues> 8687 <enumeratedValue> 8688 <name>inactive</name> 8689 <description>No interrupt is pending.</description> 8690 <value>0</value> 8691 </enumeratedValue> 8692 <enumeratedValue> 8693 <name>pending</name> 8694 <description>An interrupt is pending. TX_FIFO has equal or less bytes than the threshold.</description> 8695 <value>1</value> 8696 </enumeratedValue> 8697 </enumeratedValues> 8698 </field> 8699 <field> 8700 <name>STOP</name> 8701 <description>STOP Interrupt.</description> 8702 <bitRange>[6:6]</bitRange> 8703 <enumeratedValues> 8704 <enumeratedValue> 8705 <name>inactive</name> 8706 <description>No interrupt is pending.</description> 8707 <value>0</value> 8708 </enumeratedValue> 8709 <enumeratedValue> 8710 <name>pending</name> 8711 <description>An interrupt is pending. TX_FIFO has equal or less bytes than the threshold.</description> 8712 <value>1</value> 8713 </enumeratedValue> 8714 </enumeratedValues> 8715 </field> 8716 <field> 8717 <name>ADDR_ACK</name> 8718 <description>Address Acknowledge Interrupt.</description> 8719 <bitRange>[7:7]</bitRange> 8720 <enumeratedValues> 8721 <enumeratedValue> 8722 <name>inactive</name> 8723 <description>No Interrupt is Pending.</description> 8724 <value>0</value> 8725 </enumeratedValue> 8726 <enumeratedValue> 8727 <name>pending</name> 8728 <description>An interrupt is pending.</description> 8729 <value>1</value> 8730 </enumeratedValue> 8731 </enumeratedValues> 8732 </field> 8733 <field> 8734 <name>ARB_ERR</name> 8735 <description>Arbritation error Interrupt.</description> 8736 <bitRange>[8:8]</bitRange> 8737 <enumeratedValues> 8738 <enumeratedValue> 8739 <name>inactive</name> 8740 <description>No Interrupt is Pending.</description> 8741 <value>0</value> 8742 </enumeratedValue> 8743 <enumeratedValue> 8744 <name>pending</name> 8745 <description>An interrupt is pending.</description> 8746 <value>1</value> 8747 </enumeratedValue> 8748 </enumeratedValues> 8749 </field> 8750 <field> 8751 <name>TO_ERR</name> 8752 <description>timeout Error Interrupt.</description> 8753 <bitRange>[9:9]</bitRange> 8754 <enumeratedValues> 8755 <enumeratedValue> 8756 <name>inactive</name> 8757 <description>No Interrupt is Pending.</description> 8758 <value>0</value> 8759 </enumeratedValue> 8760 <enumeratedValue> 8761 <name>pending</name> 8762 <description>An interrupt is pending.</description> 8763 <value>1</value> 8764 </enumeratedValue> 8765 </enumeratedValues> 8766 </field> 8767 <field> 8768 <name>ADDR_NACK_ERR</name> 8769 <description>Address NACK Error Interrupt.</description> 8770 <bitRange>[10:10]</bitRange> 8771 <enumeratedValues> 8772 <enumeratedValue> 8773 <name>inactive</name> 8774 <description>No Interrupt is Pending.</description> 8775 <value>0</value> 8776 </enumeratedValue> 8777 <enumeratedValue> 8778 <name>pending</name> 8779 <description>An interrupt is pending.</description> 8780 <value>1</value> 8781 </enumeratedValue> 8782 </enumeratedValues> 8783 </field> 8784 <field> 8785 <name>DATA_ERR</name> 8786 <description>Data NACK Error Interrupt.</description> 8787 <bitRange>[11:11]</bitRange> 8788 <enumeratedValues> 8789 <enumeratedValue> 8790 <name>inactive</name> 8791 <description>No Interrupt is Pending.</description> 8792 <value>0</value> 8793 </enumeratedValue> 8794 <enumeratedValue> 8795 <name>pending</name> 8796 <description>An interrupt is pending.</description> 8797 <value>1</value> 8798 </enumeratedValue> 8799 </enumeratedValues> 8800 </field> 8801 <field> 8802 <name>DNR_ERR</name> 8803 <description>Do Not Respond Error Interrupt.</description> 8804 <bitRange>[12:12]</bitRange> 8805 <enumeratedValues> 8806 <enumeratedValue> 8807 <name>inactive</name> 8808 <description>No Interrupt is Pending.</description> 8809 <value>0</value> 8810 </enumeratedValue> 8811 <enumeratedValue> 8812 <name>pending</name> 8813 <description>An interrupt is pending.</description> 8814 <value>1</value> 8815 </enumeratedValue> 8816 </enumeratedValues> 8817 </field> 8818 <field> 8819 <name>START_ERR</name> 8820 <description>Start Error Interrupt.</description> 8821 <bitRange>[13:13]</bitRange> 8822 <enumeratedValues> 8823 <enumeratedValue> 8824 <name>inactive</name> 8825 <description>No Interrupt is Pending.</description> 8826 <value>0</value> 8827 </enumeratedValue> 8828 <enumeratedValue> 8829 <name>pending</name> 8830 <description>An interrupt is pending.</description> 8831 <value>1</value> 8832 </enumeratedValue> 8833 </enumeratedValues> 8834 </field> 8835 <field> 8836 <name>STOP_ERR</name> 8837 <description>Stop Error Interrupt.</description> 8838 <bitRange>[14:14]</bitRange> 8839 <enumeratedValues> 8840 <enumeratedValue> 8841 <name>inactive</name> 8842 <description>No Interrupt is Pending.</description> 8843 <value>0</value> 8844 </enumeratedValue> 8845 <enumeratedValue> 8846 <name>pending</name> 8847 <description>An interrupt is pending.</description> 8848 <value>1</value> 8849 </enumeratedValue> 8850 </enumeratedValues> 8851 </field> 8852 <field> 8853 <name>TX_LOCKOUT</name> 8854 <description>Transmit Lock Out Interrupt.</description> 8855 <bitRange>[15:15]</bitRange> 8856 </field> 8857 <field> 8858 <name>MAMI</name> 8859 <description>Multiple Address Match Interrupt</description> 8860 <bitRange>[21:16]</bitRange> 8861 </field> 8862 <field> 8863 <name>RD_ADDR_MATCH</name> 8864 <description>Slave Read Address Match Interrupt</description> 8865 <bitRange>[22:22]</bitRange> 8866 </field> 8867 <field> 8868 <name>WR_ADDR_MATCH</name> 8869 <description>Slave Write Address Match Interrupt</description> 8870 <bitRange>[23:23]</bitRange> 8871 </field> 8872 </fields> 8873 </register> 8874 <register> 8875 <name>INTEN0</name> 8876 <description>Interrupt Enable Register.</description> 8877 <addressOffset>0x0C</addressOffset> 8878 <access>read-write</access> 8879 <fields> 8880 <field> 8881 <name>DONE</name> 8882 <description>Transfer Done Interrupt Enable.</description> 8883 <bitRange>[0:0]</bitRange> 8884 <access>read-write</access> 8885 <enumeratedValues> 8886 <enumeratedValue> 8887 <name>dis</name> 8888 <description>Interrupt disabled.</description> 8889 <value>0</value> 8890 </enumeratedValue> 8891 <enumeratedValue> 8892 <name>en</name> 8893 <description>Interrupt enabled when DONE = 1.</description> 8894 <value>1</value> 8895 </enumeratedValue> 8896 </enumeratedValues> 8897 </field> 8898 <field> 8899 <name>IRXM</name> 8900 <description>Description not available.</description> 8901 <bitRange>[1:1]</bitRange> 8902 <access>read-write</access> 8903 <enumeratedValues> 8904 <enumeratedValue> 8905 <name>dis</name> 8906 <description>Interrupt disabled.</description> 8907 <value>0</value> 8908 </enumeratedValue> 8909 <enumeratedValue> 8910 <name>en</name> 8911 <description>Interrupt enabled when RX_MODE = 1.</description> 8912 <value>1</value> 8913 </enumeratedValue> 8914 </enumeratedValues> 8915 </field> 8916 <field> 8917 <name>GC_ADDR_MATCH</name> 8918 <description>Slave mode general call address match received input enable.</description> 8919 <bitRange>[2:2]</bitRange> 8920 <access>read-write</access> 8921 <enumeratedValues> 8922 <enumeratedValue> 8923 <name>dis</name> 8924 <description>Interrupt disabled.</description> 8925 <value>0</value> 8926 </enumeratedValue> 8927 <enumeratedValue> 8928 <name>en</name> 8929 <description>Interrupt enabled when GEN_CTRL_ADDR = 1.</description> 8930 <value>1</value> 8931 </enumeratedValue> 8932 </enumeratedValues> 8933 </field> 8934 <field> 8935 <name>ADDR_MATCH</name> 8936 <description>Slave mode incoming address match interrupt.</description> 8937 <bitRange>[3:3]</bitRange> 8938 <access>read-write</access> 8939 <enumeratedValues> 8940 <enumeratedValue> 8941 <name>dis</name> 8942 <description>Interrupt disabled.</description> 8943 <value>0</value> 8944 </enumeratedValue> 8945 <enumeratedValue> 8946 <name>en</name> 8947 <description>Interrupt enabled when ADDR_MATCH = 1.</description> 8948 <value>1</value> 8949 </enumeratedValue> 8950 </enumeratedValues> 8951 </field> 8952 <field> 8953 <name>RX_THD</name> 8954 <description>RX FIFO Above Treshold Level Interrupt Enable.</description> 8955 <bitRange>[4:4]</bitRange> 8956 <access>read-write</access> 8957 <enumeratedValues> 8958 <enumeratedValue> 8959 <name>dis</name> 8960 <description>Interrupt disabled.</description> 8961 <value>0</value> 8962 </enumeratedValue> 8963 <enumeratedValue> 8964 <name>en</name> 8965 <description>Interrupt enabled.</description> 8966 <value>1</value> 8967 </enumeratedValue> 8968 </enumeratedValues> 8969 </field> 8970 <field> 8971 <name>TX_THD</name> 8972 <description>TX FIFO Below Treshold Level Interrupt Enable.</description> 8973 <bitRange>[5:5]</bitRange> 8974 <enumeratedValues> 8975 <enumeratedValue> 8976 <name>dis</name> 8977 <description>Interrupt disabled.</description> 8978 <value>0</value> 8979 </enumeratedValue> 8980 <enumeratedValue> 8981 <name>en</name> 8982 <description>Interrupt enabled.</description> 8983 <value>1</value> 8984 </enumeratedValue> 8985 </enumeratedValues> 8986 </field> 8987 <field> 8988 <name>STOP</name> 8989 <description>Stop Interrupt Enable</description> 8990 <bitRange>[6:6]</bitRange> 8991 <access>read-write</access> 8992 <enumeratedValues> 8993 <enumeratedValue> 8994 <name>dis</name> 8995 <description>Interrupt disabled.</description> 8996 <value>0</value> 8997 </enumeratedValue> 8998 <enumeratedValue> 8999 <name>en</name> 9000 <description>Interrupt enabled when STOP = 1.</description> 9001 <value>1</value> 9002 </enumeratedValue> 9003 </enumeratedValues> 9004 </field> 9005 <field> 9006 <name>ADDR_ACK</name> 9007 <description>Received Address ACK from Slave Interrupt.</description> 9008 <bitRange>[7:7]</bitRange> 9009 <enumeratedValues> 9010 <enumeratedValue> 9011 <name>dis</name> 9012 <description>Interrupt disabled.</description> 9013 <value>0</value> 9014 </enumeratedValue> 9015 <enumeratedValue> 9016 <name>en</name> 9017 <description>Interrupt enabled.</description> 9018 <value>1</value> 9019 </enumeratedValue> 9020 </enumeratedValues> 9021 </field> 9022 <field> 9023 <name>ARB_ERR</name> 9024 <description>Master Mode Arbitration Lost Interrupt.</description> 9025 <bitRange>[8:8]</bitRange> 9026 <enumeratedValues> 9027 <enumeratedValue> 9028 <name>dis</name> 9029 <description>Interrupt disabled.</description> 9030 <value>0</value> 9031 </enumeratedValue> 9032 <enumeratedValue> 9033 <name>en</name> 9034 <description>Interrupt enabled.</description> 9035 <value>1</value> 9036 </enumeratedValue> 9037 </enumeratedValues> 9038 </field> 9039 <field> 9040 <name>TO_ERR</name> 9041 <description>Timeout Error Interrupt Enable.</description> 9042 <bitRange>[9:9]</bitRange> 9043 <enumeratedValues> 9044 <enumeratedValue> 9045 <name>dis</name> 9046 <description>Interrupt disabled.</description> 9047 <value>0</value> 9048 </enumeratedValue> 9049 <enumeratedValue> 9050 <name>en</name> 9051 <description>Interrupt enabled.</description> 9052 <value>1</value> 9053 </enumeratedValue> 9054 </enumeratedValues> 9055 </field> 9056 <field> 9057 <name>ADDR_NACK_ERR</name> 9058 <description>Master Mode Address NACK Received Interrupt.</description> 9059 <bitRange>[10:10]</bitRange> 9060 <enumeratedValues> 9061 <enumeratedValue> 9062 <name>dis</name> 9063 <description>Interrupt disabled.</description> 9064 <value>0</value> 9065 </enumeratedValue> 9066 <enumeratedValue> 9067 <name>en</name> 9068 <description>Interrupt enabled.</description> 9069 <value>1</value> 9070 </enumeratedValue> 9071 </enumeratedValues> 9072 </field> 9073 <field> 9074 <name>DATA_ERR</name> 9075 <description>Master Mode Data NACK Received Interrupt.</description> 9076 <bitRange>[11:11]</bitRange> 9077 <enumeratedValues> 9078 <enumeratedValue> 9079 <name>dis</name> 9080 <description>Interrupt disabled.</description> 9081 <value>0</value> 9082 </enumeratedValue> 9083 <enumeratedValue> 9084 <name>en</name> 9085 <description>Interrupt enabled.</description> 9086 <value>1</value> 9087 </enumeratedValue> 9088 </enumeratedValues> 9089 </field> 9090 <field> 9091 <name>DNR_ERR</name> 9092 <description>Slave Mode Do Not Respond Interrupt.</description> 9093 <bitRange>[12:12]</bitRange> 9094 <enumeratedValues> 9095 <enumeratedValue> 9096 <name>dis</name> 9097 <description>Interrupt disabled.</description> 9098 <value>0</value> 9099 </enumeratedValue> 9100 <enumeratedValue> 9101 <name>en</name> 9102 <description>Interrupt enabled.</description> 9103 <value>1</value> 9104 </enumeratedValue> 9105 </enumeratedValues> 9106 </field> 9107 <field> 9108 <name>START_ERR</name> 9109 <description>Out of Sequence START condition detected interrupt.</description> 9110 <bitRange>[13:13]</bitRange> 9111 <enumeratedValues> 9112 <enumeratedValue> 9113 <name>dis</name> 9114 <description>Interrupt disabled.</description> 9115 <value>0</value> 9116 </enumeratedValue> 9117 <enumeratedValue> 9118 <name>en</name> 9119 <description>Interrupt enabled.</description> 9120 <value>1</value> 9121 </enumeratedValue> 9122 </enumeratedValues> 9123 </field> 9124 <field> 9125 <name>STOP_ERR</name> 9126 <description>Out of Sequence STOP condition detected interrupt.</description> 9127 <bitRange>[14:14]</bitRange> 9128 <enumeratedValues> 9129 <enumeratedValue> 9130 <name>dis</name> 9131 <description>Interrupt disabled.</description> 9132 <value>0</value> 9133 </enumeratedValue> 9134 <enumeratedValue> 9135 <name>en</name> 9136 <description>Interrupt enabled.</description> 9137 <value>1</value> 9138 </enumeratedValue> 9139 </enumeratedValues> 9140 </field> 9141 <field> 9142 <name>TX_LOCKOUT</name> 9143 <description>TX FIFO Locked Out Interrupt.</description> 9144 <bitRange>[15:15]</bitRange> 9145 </field> 9146 <field> 9147 <name>MAMI</name> 9148 <description>Multiple Address Match Interrupt</description> 9149 <bitRange>[21:16]</bitRange> 9150 </field> 9151 <field> 9152 <name>RD_ADDR_MATCH</name> 9153 <description>Slave Read Address Match Interrupt</description> 9154 <bitRange>[22:22]</bitRange> 9155 </field> 9156 <field> 9157 <name>WR_ADDR_MATCH</name> 9158 <description>Slave Write Address Match Interrupt</description> 9159 <bitRange>[23:23]</bitRange> 9160 </field> 9161 </fields> 9162 </register> 9163 <register> 9164 <name>INTFL1</name> 9165 <description>Interrupt Status Register 1.</description> 9166 <addressOffset>0x10</addressOffset> 9167 <fields> 9168 <field> 9169 <name>RX_OV</name> 9170 <description>Receiver Overflow Interrupt. When operating as a slave receiver, this bit is set when you reach the first data bit and the RX FIFO and shift register are both full.</description> 9171 <bitRange>[0:0]</bitRange> 9172 <enumeratedValues> 9173 <enumeratedValue> 9174 <name>inactive</name> 9175 <description>No Interrupt is Pending.</description> 9176 <value>0</value> 9177 </enumeratedValue> 9178 <enumeratedValue> 9179 <name>pending</name> 9180 <description>An interrupt is pending.</description> 9181 <value>1</value> 9182 </enumeratedValue> 9183 </enumeratedValues> 9184 </field> 9185 <field> 9186 <name>TX_UN</name> 9187 <description>Transmit Underflow Interrupt. When operating as a slave transmitter, this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet).</description> 9188 <bitRange>[1:1]</bitRange> 9189 <enumeratedValues> 9190 <enumeratedValue> 9191 <name>inactive</name> 9192 <description>No Interrupt is Pending.</description> 9193 <value>0</value> 9194 </enumeratedValue> 9195 <enumeratedValue> 9196 <name>pending</name> 9197 <description>An interrupt is pending.</description> 9198 <value>1</value> 9199 </enumeratedValue> 9200 </enumeratedValues> 9201 </field> 9202 <field> 9203 <name>START</name> 9204 <description>START Condition Status Flag.</description> 9205 <bitRange>[2:2]</bitRange> 9206 </field> 9207 </fields> 9208 </register> 9209 <register> 9210 <name>INTEN1</name> 9211 <description>Interrupt Staus Register 1.</description> 9212 <addressOffset>0x14</addressOffset> 9213 <access>read-write</access> 9214 <fields> 9215 <field> 9216 <name>RX_OV</name> 9217 <description>Receiver Overflow Interrupt Enable.</description> 9218 <bitRange>[0:0]</bitRange> 9219 <enumeratedValues> 9220 <enumeratedValue> 9221 <name>dis</name> 9222 <description>No Interrupt is Pending.</description> 9223 <value>0</value> 9224 </enumeratedValue> 9225 <enumeratedValue> 9226 <name>en</name> 9227 <description>An interrupt is pending.</description> 9228 <value>1</value> 9229 </enumeratedValue> 9230 </enumeratedValues> 9231 </field> 9232 <field> 9233 <name>TX_UN</name> 9234 <description>Transmit Underflow Interrupt Enable.</description> 9235 <bitRange>[1:1]</bitRange> 9236 <enumeratedValues> 9237 <enumeratedValue> 9238 <name>dis</name> 9239 <description>No Interrupt is Pending.</description> 9240 <value>0</value> 9241 </enumeratedValue> 9242 <enumeratedValue> 9243 <name>en</name> 9244 <description>An interrupt is pending.</description> 9245 <value>1</value> 9246 </enumeratedValue> 9247 </enumeratedValues> 9248 </field> 9249 <field> 9250 <name>START</name> 9251 <description>START Condition Interrupt Enable.</description> 9252 <bitRange>[2:2]</bitRange> 9253 </field> 9254 </fields> 9255 </register> 9256 <register> 9257 <name>FIFOLEN</name> 9258 <description>FIFO Configuration Register.</description> 9259 <addressOffset>0x18</addressOffset> 9260 <fields> 9261 <field> 9262 <name>RX_DEPTH</name> 9263 <description>Receive FIFO Length.</description> 9264 <bitRange>[7:0]</bitRange> 9265 <access>read-only</access> 9266 </field> 9267 <field> 9268 <name>TX_DEPTH</name> 9269 <description>Transmit FIFO Length.</description> 9270 <bitRange>[15:8]</bitRange> 9271 <access>read-only</access> 9272 </field> 9273 </fields> 9274 </register> 9275 <register> 9276 <name>RXCTRL0</name> 9277 <description>Receive Control Register 0.</description> 9278 <addressOffset>0x1C</addressOffset> 9279 <fields> 9280 <field> 9281 <name>DNR</name> 9282 <description>Do Not Respond.</description> 9283 <bitRange>[0:0]</bitRange> 9284 <enumeratedValues> 9285 <enumeratedValue> 9286 <name>respond</name> 9287 <description>Always respond to address match.</description> 9288 <value>0</value> 9289 </enumeratedValue> 9290 <enumeratedValue> 9291 <name>not_respond_rx_fifo_empty</name> 9292 <description>Do not respond to address match when RX_FIFO is not empty.</description> 9293 <value>1</value> 9294 </enumeratedValue> 9295 </enumeratedValues> 9296 </field> 9297 <field> 9298 <name>FLUSH</name> 9299 <description>Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status.</description> 9300 <bitRange>[7:7]</bitRange> 9301 <enumeratedValues> 9302 <enumeratedValue> 9303 <name>not_flushed</name> 9304 <description>FIFO not flushed.</description> 9305 <value>0</value> 9306 </enumeratedValue> 9307 <enumeratedValue> 9308 <name>flush</name> 9309 <description>Flush RX_FIFO.</description> 9310 <value>1</value> 9311 </enumeratedValue> 9312 </enumeratedValues> 9313 </field> 9314 <field> 9315 <name>THD_LVL</name> 9316 <description>Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold.</description> 9317 <bitRange>[11:8]</bitRange> 9318 </field> 9319 </fields> 9320 </register> 9321 <register> 9322 <name>RXCTRL1</name> 9323 <description>Receive Control Register 1.</description> 9324 <addressOffset>0x20</addressOffset> 9325 <fields> 9326 <field> 9327 <name>CNT</name> 9328 <description>Receive Count Bits. These bits define the number of bytes to be received in a transaction, except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction.</description> 9329 <bitRange>[7:0]</bitRange> 9330 </field> 9331 <field> 9332 <name>LVL</name> 9333 <description>Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0.</description> 9334 <bitRange>[11:8]</bitRange> 9335 <access>read-only</access> 9336 </field> 9337 </fields> 9338 </register> 9339 <register> 9340 <name>TXCTRL0</name> 9341 <description>Transmit Control Register 0.</description> 9342 <addressOffset>0x24</addressOffset> 9343 <fields> 9344 <field> 9345 <name>PRELOAD_MODE</name> 9346 <description>Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match.</description> 9347 <bitRange>[0:0]</bitRange> 9348 </field> 9349 <field> 9350 <name>TX_READY_MODE</name> 9351 <description>Transmit FIFO Ready Manual Mode.</description> 9352 <bitRange>[1:1]</bitRange> 9353 <enumeratedValues> 9354 <enumeratedValue> 9355 <name>en</name> 9356 <description>HW control of I2CTXRDY enabled.</description> 9357 <value>0</value> 9358 </enumeratedValue> 9359 <enumeratedValue> 9360 <name>dis</name> 9361 <description>HW control of I2CTXRDY disabled.</description> 9362 <value>1</value> 9363 </enumeratedValue> 9364 </enumeratedValues> 9365 </field> 9366 <field> 9367 <name>GC_ADDR_FLUSH_DIS</name> 9368 <description>TX FIFO General Call Address Match Auto Flush Disable.</description> 9369 <bitRange>[2:2]</bitRange> 9370 <enumeratedValues> 9371 <enumeratedValue> 9372 <name>en</name> 9373 <description>Enabled.</description> 9374 <value>0</value> 9375 </enumeratedValue> 9376 <enumeratedValue> 9377 <name>dis</name> 9378 <description>Disabled.</description> 9379 <value>1</value> 9380 </enumeratedValue> 9381 </enumeratedValues> 9382 </field> 9383 <field> 9384 <name>WR_ADDR_FLUSH_DIS</name> 9385 <description>TX FIFO Slave Address Match Write Auto Flush Disable.</description> 9386 <bitRange>[3:3]</bitRange> 9387 <enumeratedValues> 9388 <enumeratedValue> 9389 <name>en</name> 9390 <description>Enabled.</description> 9391 <value>0</value> 9392 </enumeratedValue> 9393 <enumeratedValue> 9394 <name>dis</name> 9395 <description>Disabled.</description> 9396 <value>1</value> 9397 </enumeratedValue> 9398 </enumeratedValues> 9399 </field> 9400 <field> 9401 <name>RD_ADDR_FLUSH_DIS</name> 9402 <description>TX FIFO Slave Address Match Read Auto Flush Disable.</description> 9403 <bitRange>[4:4]</bitRange> 9404 <enumeratedValues> 9405 <enumeratedValue> 9406 <name>en</name> 9407 <description>Enabled.</description> 9408 <value>0</value> 9409 </enumeratedValue> 9410 <enumeratedValue> 9411 <name>dis</name> 9412 <description>Disabled.</description> 9413 <value>1</value> 9414 </enumeratedValue> 9415 </enumeratedValues> 9416 </field> 9417 <field> 9418 <name>NACK_FLUSH_DIS</name> 9419 <description>TX FIFO received NACK Auto Flush Disable.</description> 9420 <bitRange>[5:5]</bitRange> 9421 <enumeratedValues> 9422 <enumeratedValue> 9423 <name>en</name> 9424 <description>Enabled.</description> 9425 <value>0</value> 9426 </enumeratedValue> 9427 <enumeratedValue> 9428 <name>dis</name> 9429 <description>Disabled.</description> 9430 <value>1</value> 9431 </enumeratedValue> 9432 </enumeratedValues> 9433 </field> 9434 <field> 9435 <name>FLUSH</name> 9436 <description>Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation.</description> 9437 <bitRange>[7:7]</bitRange> 9438 <enumeratedValues> 9439 <enumeratedValue> 9440 <name>not_flushed</name> 9441 <description>FIFO not flushed.</description> 9442 <value>0</value> 9443 </enumeratedValue> 9444 <enumeratedValue> 9445 <name>flush</name> 9446 <description>Flush TX_FIFO.</description> 9447 <value>1</value> 9448 </enumeratedValue> 9449 </enumeratedValues> 9450 </field> 9451 <field> 9452 <name>THD_VAL</name> 9453 <description>Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold.</description> 9454 <bitRange>[11:8]</bitRange> 9455 </field> 9456 </fields> 9457 </register> 9458 <register> 9459 <name>TXCTRL1</name> 9460 <description>Transmit Control Register 1.</description> 9461 <addressOffset>0x28</addressOffset> 9462 <fields> 9463 <field> 9464 <name>PRELOAD_RDY</name> 9465 <description>Transmit FIFO Preload Ready.</description> 9466 <bitRange>[0:0]</bitRange> 9467 </field> 9468 <field> 9469 <name>LVL</name> 9470 <description>Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO.</description> 9471 <bitRange>[11:8]</bitRange> 9472 <access>read-only</access> 9473 </field> 9474 </fields> 9475 </register> 9476 <register> 9477 <name>FIFO</name> 9478 <description>Data Register.</description> 9479 <addressOffset>0x2C</addressOffset> 9480 <fields> 9481 <field> 9482 <name>DATA</name> 9483 <description>Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location.</description> 9484 <bitOffset>0</bitOffset> 9485 <bitWidth>8</bitWidth> 9486 </field> 9487 </fields> 9488 </register> 9489 <register> 9490 <name>MSTCTRL</name> 9491 <description>Master Control Register.</description> 9492 <addressOffset>0x30</addressOffset> 9493 <fields> 9494 <field> 9495 <name>START</name> 9496 <description>Setting this bit to 1 will start a master transfer.</description> 9497 <bitRange>[0:0]</bitRange> 9498 </field> 9499 <field> 9500 <name>RESTART</name> 9501 <description>Setting this bit to 1 will generate a repeated START.</description> 9502 <bitRange>[1:1]</bitRange> 9503 </field> 9504 <field> 9505 <name>STOP</name> 9506 <description>Setting this bit to 1 will generate a STOP condition.</description> 9507 <bitRange>[2:2]</bitRange> 9508 </field> 9509 <field> 9510 <name>EX_ADDR_EN</name> 9511 <description>Slave Extend Address Select.</description> 9512 <bitRange>[7:7]</bitRange> 9513 <enumeratedValues> 9514 <enumeratedValue> 9515 <name>7_bits_address</name> 9516 <description>7-bit address.</description> 9517 <value>0</value> 9518 </enumeratedValue> 9519 <enumeratedValue> 9520 <name>10_bits_address</name> 9521 <description>10-bit address.</description> 9522 <value>1</value> 9523 </enumeratedValue> 9524 </enumeratedValues> 9525 </field> 9526 </fields> 9527 </register> 9528 <register> 9529 <name>CLKLO</name> 9530 <description>Clock Low Register.</description> 9531 <addressOffset>0x34</addressOffset> 9532 <fields> 9533 <field> 9534 <name>LO</name> 9535 <description>Clock low. In master mode, these bits define the SCL low period. In slave mode, these bits define the time SCL will be held low after data is outputted.</description> 9536 <bitRange>[8:0]</bitRange> 9537 </field> 9538 </fields> 9539 </register> 9540 <register> 9541 <name>CLKHI</name> 9542 <description>Clock high Register.</description> 9543 <addressOffset>0x38</addressOffset> 9544 <fields> 9545 <field> 9546 <name>HI</name> 9547 <description>Clock High. In master mode, these bits define the SCL high period.</description> 9548 <bitRange>[8:0]</bitRange> 9549 </field> 9550 </fields> 9551 </register> 9552 <register> 9553 <name>HSCLK</name> 9554 <description>Clock high Register.</description> 9555 <addressOffset>0x3C</addressOffset> 9556 <fields> 9557 <field> 9558 <name>LO</name> 9559 <description>Clock Low. This field sets the Hs-Mode clock low count. In Slave mode, this is the time SCL is held low after data is output on SDA.</description> 9560 <bitRange>[7:0]</bitRange> 9561 </field> 9562 <field> 9563 <name>HI</name> 9564 <description>Clock High. This field sets the Hs-Mode clock high count. In Slave mode, this is the time SCL is held high after data is output on SDA</description> 9565 <bitRange>[15:8]</bitRange> 9566 </field> 9567 </fields> 9568 </register> 9569 <register> 9570 <name>TIMEOUT</name> 9571 <description>Timeout Register</description> 9572 <addressOffset>0x40</addressOffset> 9573 <fields> 9574 <field> 9575 <name>SCL_TO_VAL</name> 9576 <description>Timeout</description> 9577 <bitRange>[15:0]</bitRange> 9578 </field> 9579 </fields> 9580 </register> 9581 <register> 9582 <name>DMA</name> 9583 <description>DMA Register.</description> 9584 <addressOffset>0x48</addressOffset> 9585 <fields> 9586 <field> 9587 <name>TX_EN</name> 9588 <description>TX channel enable.</description> 9589 <bitRange>[0:0]</bitRange> 9590 <enumeratedValues> 9591 <enumeratedValue> 9592 <name>dis</name> 9593 <description>Disable.</description> 9594 <value>0</value> 9595 </enumeratedValue> 9596 <enumeratedValue> 9597 <name>en</name> 9598 <description>Enable.</description> 9599 <value>1</value> 9600 </enumeratedValue> 9601 </enumeratedValues> 9602 </field> 9603 <field> 9604 <name>RX_EN</name> 9605 <description>RX channel enable.</description> 9606 <bitRange>[1:1]</bitRange> 9607 <enumeratedValues> 9608 <enumeratedValue> 9609 <name>dis</name> 9610 <description>Disable.</description> 9611 <value>0</value> 9612 </enumeratedValue> 9613 <enumeratedValue> 9614 <name>en</name> 9615 <description>Enable.</description> 9616 <value>1</value> 9617 </enumeratedValue> 9618 </enumeratedValues> 9619 </field> 9620 </fields> 9621 </register> 9622 <register> 9623 <dim>4</dim> 9624 <dimIncrement>4</dimIncrement> 9625 <name>SLAVE_MULTI[%s]</name> 9626 <description>Slave Address Register.</description> 9627 <alternateRegister>SLAVE0</alternateRegister> 9628 <addressOffset>0x4C</addressOffset> 9629 <size>32</size> 9630 <access>read-write</access> 9631 <fields> 9632 <field> 9633 <name>ADDR</name> 9634 <description>Slave Address.</description> 9635 <bitRange>[9:0]</bitRange> 9636 </field> 9637 <field> 9638 <name>DIS</name> 9639 <description>Slave Disable.</description> 9640 <bitRange>[10:10]</bitRange> 9641 </field> 9642 <field> 9643 <name>EXT_ADDR_EN</name> 9644 <description>Extended Address Select.</description> 9645 <bitRange>[15:15]</bitRange> 9646 <enumeratedValues> 9647 <enumeratedValue> 9648 <name>7_bits_address</name> 9649 <description>7-bit address.</description> 9650 <value>0</value> 9651 </enumeratedValue> 9652 <enumeratedValue> 9653 <name>10_bits_address</name> 9654 <description>10-bit address.</description> 9655 <value>1</value> 9656 </enumeratedValue> 9657 </enumeratedValues> 9658 </field> 9659 </fields> 9660 </register> 9661 <register> 9662 <name>SLAVE0</name> 9663 <description>Slave Address Register.</description> 9664 <addressOffset>0x4C</addressOffset> 9665 </register> 9666 <register> 9667 <name>SLAVE1</name> 9668 <description>Slave Address Register.</description> 9669 <addressOffset>0x50</addressOffset> 9670 </register> 9671 <register> 9672 <name>SLAVE2</name> 9673 <description>Slave Address Register.</description> 9674 <addressOffset>0x54</addressOffset> 9675 </register> 9676 <register> 9677 <name>SLAVE3</name> 9678 <description>Slave Address Register.</description> 9679 <addressOffset>0x58</addressOffset> 9680 </register> 9681 </registers> 9682 </peripheral> 9683<!--I2C0 Inter-Integrated Circuit.--> 9684 <peripheral derivedFrom="I2C0"> 9685 <name>I2C1</name> 9686 <description>Inter-Integrated Circuit. 1</description> 9687 <baseAddress>0x4001E000</baseAddress> 9688 <interrupt> 9689 <name>I2C1</name> 9690 <description>I2C1 IRQ</description> 9691 <value>36</value> 9692 </interrupt> 9693 </peripheral> 9694<!--I2C1 Inter-Integrated Circuit. 1--> 9695 <peripheral derivedFrom="I2C0"> 9696 <name>I2C2</name> 9697 <description>Inter-Integrated Circuit. 2</description> 9698 <baseAddress>0x4001F000</baseAddress> 9699 <interrupt> 9700 <name>I2C2</name> 9701 <description>I2C2 IRQ</description> 9702 <value>62</value> 9703 </interrupt> 9704 </peripheral> 9705<!--I2C2 Inter-Integrated Circuit. 2--> 9706 <peripheral> 9707 <name>I2S</name> 9708 <description>Inter-IC Sound Interface.</description> 9709 <groupName>I2S</groupName> 9710 <baseAddress>0x40060000</baseAddress> 9711 <size>32</size> 9712 <addressBlock> 9713 <offset>0x00</offset> 9714 <size>0x1000</size> 9715 <usage>registers</usage> 9716 </addressBlock> 9717 <interrupt> 9718 <name>I2S</name> 9719 <description>I2S IRQ</description> 9720 <value>99</value> 9721 </interrupt> 9722 <registers> 9723 <register> 9724 <name>CTRL0CH0</name> 9725 <description>Global mode channel.</description> 9726 <addressOffset>0x00</addressOffset> 9727 <fields> 9728 <field> 9729 <name>LSB_FIRST</name> 9730 <description>LSB Transmit Receive First.</description> 9731 <bitRange>[1:1]</bitRange> 9732 <access>read-write</access> 9733 </field> 9734 <field> 9735 <name>PDM_FILT</name> 9736 <description>PDM Filter.</description> 9737 <bitRange>[2:2]</bitRange> 9738 <access>read-write</access> 9739 </field> 9740 <field> 9741 <name>PDM_EN</name> 9742 <description>PDM Enable.</description> 9743 <bitRange>[3:3]</bitRange> 9744 <access>read-write</access> 9745 </field> 9746 <field> 9747 <name>USEDDR</name> 9748 <description>DDR.</description> 9749 <bitRange>[4:4]</bitRange> 9750 <access>read-write</access> 9751 </field> 9752 <field> 9753 <name>PDM_INV</name> 9754 <description>Invert PDM.</description> 9755 <bitRange>[5:5]</bitRange> 9756 <access>read-write</access> 9757 </field> 9758 <field> 9759 <name>CH_MODE</name> 9760 <description>SCK Select.</description> 9761 <bitRange>[7:6]</bitRange> 9762 <access>read-write</access> 9763 </field> 9764 <field> 9765 <name>WS_POL</name> 9766 <description>WS polarity select. </description> 9767 <bitRange>[8:8]</bitRange> 9768 <access>read-write</access> 9769 </field> 9770 <field> 9771 <name>MSB_LOC</name> 9772 <description>MSB location. </description> 9773 <bitRange>[9:9]</bitRange> 9774 <access>read-only</access> 9775 </field> 9776 <field> 9777 <name>ALIGN</name> 9778 <description>Align to MSB or LSB.</description> 9779 <bitRange>[10:10]</bitRange> 9780 <access>read-only</access> 9781 </field> 9782 <field> 9783 <name>EXT_SEL</name> 9784 <description>External SCK/WS selection.</description> 9785 <bitRange>[11:11]</bitRange> 9786 <access>read-write</access> 9787 </field> 9788 <field> 9789 <name>STEREO</name> 9790 <description>Stereo mode of I2S.</description> 9791 <bitRange>[13:12]</bitRange> 9792 <access>read-only</access> 9793 </field> 9794 <field> 9795 <name>WSIZE</name> 9796 <description>Data size when write to FIFO.</description> 9797 <bitRange>[15:14]</bitRange> 9798 <access>read-write</access> 9799 </field> 9800 <field> 9801 <name>TX_EN</name> 9802 <description>TX channel enable. </description> 9803 <bitRange>[16:16]</bitRange> 9804 <access>read-write</access> 9805 </field> 9806 <field> 9807 <name>RX_EN</name> 9808 <description>RX channel enable. </description> 9809 <bitRange>[17:17]</bitRange> 9810 <access>read-write</access> 9811 </field> 9812 <field> 9813 <name>FLUSH</name> 9814 <description>Flushes the TX/RX FIFO buffer. </description> 9815 <bitRange>[18:18]</bitRange> 9816 <access>read-write</access> 9817 </field> 9818 <field> 9819 <name>RST</name> 9820 <description>Write 1 to reset channel. </description> 9821 <bitRange>[19:19]</bitRange> 9822 <access>read-write</access> 9823 </field> 9824 <field> 9825 <name>FIFO_LSB</name> 9826 <description>Bit Field Control. </description> 9827 <bitRange>[20:20]</bitRange> 9828 <access>read-write</access> 9829 </field> 9830 <field> 9831 <name>RX_THD_VAL</name> 9832 <description>depth of receive FIFO for threshold interrupt generation. </description> 9833 <bitRange>[31:24]</bitRange> 9834 <access>read-write</access> 9835 </field> 9836 </fields> 9837 </register> 9838 <register> 9839 <name>CTRL1CH0</name> 9840 <description>Local channel Setup.</description> 9841 <addressOffset>0x10</addressOffset> 9842 <fields> 9843 <field> 9844 <name>BITS_WORD</name> 9845 <description>I2S word length.</description> 9846 <bitRange>[4:0]</bitRange> 9847 <access>read-write</access> 9848 </field> 9849 <field> 9850 <name>EN</name> 9851 <description>I2S clock enable.</description> 9852 <bitRange>[8:8]</bitRange> 9853 <access>read-write</access> 9854 </field> 9855 <field> 9856 <name>SMP_SIZE</name> 9857 <description>I2S sample size length.</description> 9858 <bitRange>[13:9]</bitRange> 9859 <access>read-write</access> 9860 </field> 9861 <field> 9862 <name>CLKSEL</name> 9863 <description>I2S Clock Select.</description> 9864 <bitRange>[14:14]</bitRange> 9865 <access>read-write</access> 9866 </field> 9867 <field> 9868 <name>ADJUST</name> 9869 <description>LSB/MSB Justify.</description> 9870 <bitRange>[15:15]</bitRange> 9871 <access>read-write</access> 9872 </field> 9873 <field> 9874 <name>CLKDIV</name> 9875 <description>I2S clock frequency divisor.</description> 9876 <bitRange>[31:16]</bitRange> 9877 <access>read-write</access> 9878 </field> 9879 </fields> 9880 </register> 9881 <register> 9882 <name>FILTCH0</name> 9883 <description>Filter.</description> 9884 <addressOffset>0x20</addressOffset> 9885 </register> 9886 <register> 9887 <name>DMACH0</name> 9888 <description>DMA Control.</description> 9889 <addressOffset>0x30</addressOffset> 9890 <fields> 9891 <field> 9892 <name>DMA_TX_THD_VAL</name> 9893 <description>TX FIFO Level DMA Trigger.</description> 9894 <bitRange>[6:0]</bitRange> 9895 <access>read-write</access> 9896 </field> 9897 <field> 9898 <name>DMA_TX_EN</name> 9899 <description>TX DMA channel enable.</description> 9900 <bitRange>[7:7]</bitRange> 9901 <access>read-write</access> 9902 </field> 9903 <field> 9904 <name>DMA_RX_THD_VAL</name> 9905 <description>RX FIFO Level DMA Trigger.</description> 9906 <bitRange>[14:8]</bitRange> 9907 <access>read-write</access> 9908 </field> 9909 <field> 9910 <name>DMA_RX_EN</name> 9911 <description>RX DMA channel enable.</description> 9912 <bitRange>[15:15]</bitRange> 9913 <access>read-write</access> 9914 </field> 9915 <field> 9916 <name>TX_LVL</name> 9917 <description>Number of data word in the TX FIFO.</description> 9918 <bitRange>[23:16]</bitRange> 9919 <access>read-write</access> 9920 </field> 9921 <field> 9922 <name>RX_LVL</name> 9923 <description>Number of data word in the RX FIFO.</description> 9924 <bitRange>[31:24]</bitRange> 9925 <access>read-write</access> 9926 </field> 9927 </fields> 9928 </register> 9929 <register> 9930 <name>FIFOCH0</name> 9931 <description>I2S Fifo.</description> 9932 <addressOffset>0x40</addressOffset> 9933 <fields> 9934 <field> 9935 <name>DATA</name> 9936 <description>Load/unload location for TX and RX FIFO buffers.</description> 9937 <bitRange>[31:0]</bitRange> 9938 <access>read-write</access> 9939 </field> 9940 </fields> 9941 </register> 9942 <register> 9943 <name>INTFL</name> 9944 <description>ISR Status.</description> 9945 <addressOffset>0x50</addressOffset> 9946 <fields> 9947 <field> 9948 <name>RX_OV_CH0</name> 9949 <description>Status for RX FIFO Overrun interrupt.</description> 9950 <bitRange>[0:0]</bitRange> 9951 <access>read-write</access> 9952 </field> 9953 <field> 9954 <name>RX_THD_CH0</name> 9955 <description>Status for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.</description> 9956 <bitRange>[1:1]</bitRange> 9957 <access>read-write</access> 9958 </field> 9959 <field> 9960 <name>TX_OB_CH0</name> 9961 <description>Status for interrupt when TX FIFO has only one byte remaining.</description> 9962 <bitRange>[2:2]</bitRange> 9963 <access>read-write</access> 9964 </field> 9965 <field> 9966 <name>TX_HE_CH0</name> 9967 <description>Status for interrupt when TX FIFO is half empty.</description> 9968 <bitRange>[3:3]</bitRange> 9969 <access>read-write</access> 9970 </field> 9971 </fields> 9972 </register> 9973 <register> 9974 <name>INTEN</name> 9975 <description>Interrupt Enable.</description> 9976 <addressOffset>0x54</addressOffset> 9977 <fields> 9978 <field> 9979 <name>RX_OV_CH0</name> 9980 <description>Enable for RX FIFO Overrun interrupt.</description> 9981 <bitRange>[0:0]</bitRange> 9982 <access>read-write</access> 9983 </field> 9984 <field> 9985 <name>RX_THD_CH0</name> 9986 <description>Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.</description> 9987 <bitRange>[1:1]</bitRange> 9988 <access>read-write</access> 9989 </field> 9990 <field> 9991 <name>TX_OB_CH0</name> 9992 <description>Enable for interrupt when TX FIFO has only one byte remaining.</description> 9993 <bitRange>[2:2]</bitRange> 9994 <access>read-write</access> 9995 </field> 9996 <field> 9997 <name>TX_HE_CH0</name> 9998 <description>Enable for interrupt when TX FIFO is half empty.</description> 9999 <bitRange>[3:3]</bitRange> 10000 <access>read-write</access> 10001 </field> 10002 </fields> 10003 </register> 10004 <register> 10005 <name>EXTSETUP</name> 10006 <description>Ext Control.</description> 10007 <addressOffset>0x58</addressOffset> 10008 <fields> 10009 <field> 10010 <name>EXT_BITS_WORD</name> 10011 <description>Word Length for ch_mode.</description> 10012 <bitRange>[4:0]</bitRange> 10013 <access>read-write</access> 10014 </field> 10015 </fields> 10016 </register> 10017 <register> 10018 <name>WKEN</name> 10019 <description>Wakeup Enable.</description> 10020 <addressOffset>0x5C</addressOffset> 10021 </register> 10022 <register> 10023 <name>WKFL</name> 10024 <description>Wakeup Flags.</description> 10025 <addressOffset>0x60</addressOffset> 10026 </register> 10027 </registers> 10028 </peripheral> 10029<!--I2S Inter-IC Sound Interface.--> 10030 <peripheral> 10031 <name>ICC0</name> 10032 <description>Instruction Cache Controller Registers</description> 10033 <baseAddress>0x4002A000</baseAddress> 10034 <addressBlock> 10035 <offset>0x00</offset> 10036 <size>0x800</size> 10037 <usage>registers</usage> 10038 </addressBlock> 10039 <registers> 10040 <register> 10041 <name>INFO</name> 10042 <description>Cache ID Register.</description> 10043 <addressOffset>0x0000</addressOffset> 10044 <access>read-only</access> 10045 <fields> 10046 <field> 10047 <name>RELNUM</name> 10048 <description>Release Number. Identifies the RTL release version.</description> 10049 <bitOffset>0</bitOffset> 10050 <bitWidth>6</bitWidth> 10051 </field> 10052 <field> 10053 <name>PARTNUM</name> 10054 <description>Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter.</description> 10055 <bitOffset>6</bitOffset> 10056 <bitWidth>4</bitWidth> 10057 </field> 10058 <field> 10059 <name>ID</name> 10060 <description>Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter.</description> 10061 <bitOffset>10</bitOffset> 10062 <bitWidth>6</bitWidth> 10063 </field> 10064 </fields> 10065 </register> 10066 <register> 10067 <name>SZ</name> 10068 <description>Memory Configuration Register.</description> 10069 <addressOffset>0x0004</addressOffset> 10070 <access>read-only</access> 10071 <resetValue>0x00080008</resetValue> 10072 <fields> 10073 <field> 10074 <name>CCH</name> 10075 <description>Cache Size. Indicates total size in Kbytes of cache.</description> 10076 <bitOffset>0</bitOffset> 10077 <bitWidth>16</bitWidth> 10078 </field> 10079 <field> 10080 <name>MEM</name> 10081 <description>Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller.</description> 10082 <bitOffset>16</bitOffset> 10083 <bitWidth>16</bitWidth> 10084 </field> 10085 </fields> 10086 </register> 10087 <register> 10088 <name>CTRL</name> 10089 <description>Cache Control and Status Register.</description> 10090 <addressOffset>0x0100</addressOffset> 10091 <fields> 10092 <field> 10093 <name>EN</name> 10094 <description>Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated.</description> 10095 <bitOffset>0</bitOffset> 10096 <bitWidth>1</bitWidth> 10097 <enumeratedValues> 10098 <enumeratedValue> 10099 <name>dis</name> 10100 <description>Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array.</description> 10101 <value>0</value> 10102 </enumeratedValue> 10103 <enumeratedValue> 10104 <name>en</name> 10105 <description>Cache Enabled.</description> 10106 <value>1</value> 10107 </enumeratedValue> 10108 </enumeratedValues> 10109 </field> 10110 <field> 10111 <name>RDY</name> 10112 <description>Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready.</description> 10113 <bitOffset>16</bitOffset> 10114 <bitWidth>1</bitWidth> 10115 <access>read-only</access> 10116 <enumeratedValues> 10117 <enumeratedValue> 10118 <name>notReady</name> 10119 <description>Not Ready.</description> 10120 <value>0</value> 10121 </enumeratedValue> 10122 <enumeratedValue> 10123 <name>ready</name> 10124 <description>Ready.</description> 10125 <value>1</value> 10126 </enumeratedValue> 10127 </enumeratedValues> 10128 </field> 10129 </fields> 10130 </register> 10131 <register> 10132 <name>INVALIDATE</name> 10133 <description>Invalidate All Registers.</description> 10134 <addressOffset>0x0700</addressOffset> 10135 <access>read-write</access> 10136 <fields> 10137 <field> 10138 <name>INVALID</name> 10139 <description>Invalidate.</description> 10140 <bitOffset>0</bitOffset> 10141 <bitWidth>32</bitWidth> 10142 </field> 10143 </fields> 10144 </register> 10145 </registers> 10146 </peripheral> 10147<!--ICC0 Instruction Cache Controller Registers--> 10148 <peripheral> 10149 <name>LPCMP</name> 10150 <description>Low Power Comparator</description> 10151 <baseAddress>0x40088000</baseAddress> 10152 <addressBlock> 10153 <offset>0x00</offset> 10154 <size>0x400</size> 10155 <usage>registers</usage> 10156 </addressBlock> 10157 <interrupt> 10158 <name>LPCMP</name> 10159 <description>Low Power Comparato</description> 10160 <value>103</value> 10161 </interrupt> 10162 <registers> 10163 <register> 10164 <dim>3</dim> 10165 <dimIncrement>4</dimIncrement> 10166 <name>CTRL[%s]</name> 10167 <description>Comparator Control Register.</description> 10168 <addressOffset>0x00</addressOffset> 10169 <fields> 10170 <field> 10171 <name>EN</name> 10172 <description>Comparator Enable.</description> 10173 <bitOffset>0</bitOffset> 10174 <bitWidth>1</bitWidth> 10175 </field> 10176 <field> 10177 <name>POL</name> 10178 <description>Polarity Select</description> 10179 <bitOffset>5</bitOffset> 10180 <bitWidth>1</bitWidth> 10181 </field> 10182 <field> 10183 <name>INT_EN</name> 10184 <description>IRQ Enable.</description> 10185 <bitOffset>6</bitOffset> 10186 <bitWidth>1</bitWidth> 10187 </field> 10188 <field> 10189 <name>OUT</name> 10190 <description>Raw Compartor Input.</description> 10191 <bitOffset>14</bitOffset> 10192 <bitWidth>1</bitWidth> 10193 </field> 10194 <field> 10195 <name>INT_FL</name> 10196 <description>IRQ Flag</description> 10197 <bitOffset>15</bitOffset> 10198 <bitWidth>1</bitWidth> 10199 </field> 10200 </fields> 10201 </register> 10202 </registers> 10203 </peripheral> 10204<!--LPCMP Low Power Comparator--> 10205 <peripheral> 10206 <name>LPGCR</name> 10207 <description>Low Power Global Control.</description> 10208 <baseAddress>0x40080000</baseAddress> 10209 <addressBlock> 10210 <offset>0x00</offset> 10211 <size>0x400</size> 10212 <usage>registers</usage> 10213 </addressBlock> 10214 <registers> 10215 <register> 10216 <name>RST</name> 10217 <description>Low Power Reset Register.</description> 10218 <addressOffset>0x08</addressOffset> 10219 <fields> 10220 <field> 10221 <name>GPIO3</name> 10222 <description>Low Power GPIO 3 Reset.</description> 10223 <bitOffset>0</bitOffset> 10224 <bitWidth>1</bitWidth> 10225 <enumeratedValues> 10226 <name>reset</name> 10227 <usage>read-write</usage> 10228 <enumeratedValue> 10229 <name>reset_done</name> 10230 <description>Reset complete.</description> 10231 <value>0</value> 10232 </enumeratedValue> 10233 <enumeratedValue> 10234 <name>busy</name> 10235 <description>Starts Reset or indicates reset in progress.</description> 10236 <value>1</value> 10237 </enumeratedValue> 10238 </enumeratedValues> 10239 </field> 10240 <field derivedFrom="GPIO3"> 10241 <name>WDT1</name> 10242 <description>Low Power Watchdog Timer 1 Reset.</description> 10243 <bitOffset>1</bitOffset> 10244 <bitWidth>1</bitWidth> 10245 </field> 10246 <field derivedFrom="GPIO3"> 10247 <name>TMR4</name> 10248 <description>Low Power Timer 4 Reset.</description> 10249 <bitOffset>2</bitOffset> 10250 <bitWidth>1</bitWidth> 10251 </field> 10252 <field derivedFrom="GPIO3"> 10253 <name>TMR5</name> 10254 <description>Low Power Timer 5 Reset.</description> 10255 <bitOffset>3</bitOffset> 10256 <bitWidth>1</bitWidth> 10257 </field> 10258 <field derivedFrom="GPIO3"> 10259 <name>UART3</name> 10260 <description>Low Power UART 3 Reset.</description> 10261 <bitOffset>4</bitOffset> 10262 <bitWidth>1</bitWidth> 10263 </field> 10264 <field derivedFrom="GPIO3"> 10265 <name>LPCOMP</name> 10266 <description>Low Power Comparator Reset.</description> 10267 <bitOffset>6</bitOffset> 10268 <bitWidth>1</bitWidth> 10269 </field> 10270 </fields> 10271 </register> 10272 <register> 10273 <name>PCLKDIS</name> 10274 <description>Low Power Peripheral Clock Disable Register.</description> 10275 <addressOffset>0x0C</addressOffset> 10276 <fields> 10277 <field> 10278 <name>GPIO3</name> 10279 <description>Low Power GPIO 3 Clock Disable.</description> 10280 <bitOffset>0</bitOffset> 10281 <bitWidth>1</bitWidth> 10282 <enumeratedValues> 10283 <enumeratedValue> 10284 <name>en</name> 10285 <description>enable it.</description> 10286 <value>0</value> 10287 </enumeratedValue> 10288 <enumeratedValue> 10289 <name>dis</name> 10290 <description>disable it.</description> 10291 <value>1</value> 10292 </enumeratedValue> 10293 </enumeratedValues> 10294 </field> 10295 <field derivedFrom="GPIO3"> 10296 <name>WDT1</name> 10297 <description>Low Power Watchdog 1 Clock Disable.</description> 10298 <bitOffset>1</bitOffset> 10299 <bitWidth>1</bitWidth> 10300 </field> 10301 <field derivedFrom="GPIO3"> 10302 <name>TMR4</name> 10303 <description>Low Power Timer 4 Clock Disable.</description> 10304 <bitOffset>2</bitOffset> 10305 <bitWidth>1</bitWidth> 10306 </field> 10307 <field derivedFrom="GPIO3"> 10308 <name>TMR5</name> 10309 <description>Low Power Timer 5 Clock Disable.</description> 10310 <bitOffset>3</bitOffset> 10311 <bitWidth>1</bitWidth> 10312 </field> 10313 <field derivedFrom="GPIO3"> 10314 <name>UART3</name> 10315 <description>Low Power UART 3 Clock Disable.</description> 10316 <bitOffset>4</bitOffset> 10317 <bitWidth>1</bitWidth> 10318 </field> 10319 <field derivedFrom="GPIO3"> 10320 <name>LPCOMP</name> 10321 <description>Low Power Comparator Clock Disable.</description> 10322 <bitOffset>6</bitOffset> 10323 <bitWidth>1</bitWidth> 10324 </field> 10325 </fields> 10326 </register> 10327 </registers> 10328 </peripheral> 10329<!--LPGCR Low Power Global Control.--> 10330 <peripheral> 10331 <name>MCR</name> 10332 <description>Misc Control.</description> 10333 <baseAddress>0x40006C00</baseAddress> 10334 <addressBlock> 10335 <offset>0x00</offset> 10336 <size>0x400</size> 10337 <usage>registers</usage> 10338 </addressBlock> 10339 <registers> 10340 <register> 10341 <name>ECCEN</name> 10342 <description>ECC Enable Register</description> 10343 <addressOffset>0x00</addressOffset> 10344 <fields> 10345 <field> 10346 <name>RAM0</name> 10347 <description>ECC System RAM0 Enable.</description> 10348 <bitOffset>0</bitOffset> 10349 <bitWidth>1</bitWidth> 10350 <enumeratedValues> 10351 <enumeratedValue> 10352 <name>dis</name> 10353 <description>disabled.</description> 10354 <value>0</value> 10355 </enumeratedValue> 10356 <enumeratedValue> 10357 <name>en</name> 10358 <description>enabled.</description> 10359 <value>1</value> 10360 </enumeratedValue> 10361 </enumeratedValues> 10362 </field> 10363 <field> 10364 <name>RAM1</name> 10365 <description>ECC System RAM1 Enable.</description> 10366 <bitOffset>1</bitOffset> 10367 <bitWidth>1</bitWidth> 10368 <enumeratedValues> 10369 <enumeratedValue> 10370 <name>dis</name> 10371 <description>disabled.</description> 10372 <value>0</value> 10373 </enumeratedValue> 10374 <enumeratedValue> 10375 <name>en</name> 10376 <description>enabled.</description> 10377 <value>1</value> 10378 </enumeratedValue> 10379 </enumeratedValues> 10380 </field> 10381 <field> 10382 <name>RAM2</name> 10383 <description>ECC System RAM2 Enable.</description> 10384 <bitOffset>2</bitOffset> 10385 <bitWidth>1</bitWidth> 10386 <enumeratedValues> 10387 <enumeratedValue> 10388 <name>dis</name> 10389 <description>disabled.</description> 10390 <value>0</value> 10391 </enumeratedValue> 10392 <enumeratedValue> 10393 <name>en</name> 10394 <description>enabled.</description> 10395 <value>1</value> 10396 </enumeratedValue> 10397 </enumeratedValues> 10398 </field> 10399 <field> 10400 <name>RAM3</name> 10401 <description>ECC System RAM3 Enable.</description> 10402 <bitOffset>3</bitOffset> 10403 <bitWidth>1</bitWidth> 10404 <enumeratedValues> 10405 <enumeratedValue> 10406 <name>dis</name> 10407 <description>disabled.</description> 10408 <value>0</value> 10409 </enumeratedValue> 10410 <enumeratedValue> 10411 <name>en</name> 10412 <description>enabled.</description> 10413 <value>1</value> 10414 </enumeratedValue> 10415 </enumeratedValues> 10416 </field> 10417 <field> 10418 <name>RAM4</name> 10419 <description>ECC System RAM4 Enable.</description> 10420 <bitOffset>4</bitOffset> 10421 <bitWidth>1</bitWidth> 10422 <enumeratedValues> 10423 <enumeratedValue> 10424 <name>dis</name> 10425 <description>disabled.</description> 10426 <value>0</value> 10427 </enumeratedValue> 10428 <enumeratedValue> 10429 <name>en</name> 10430 <description>enabled.</description> 10431 <value>1</value> 10432 </enumeratedValue> 10433 </enumeratedValues> 10434 </field> 10435 <field> 10436 <name>RAM5</name> 10437 <description>ECC System RAM5 Enable.</description> 10438 <bitOffset>5</bitOffset> 10439 <bitWidth>1</bitWidth> 10440 <enumeratedValues> 10441 <enumeratedValue> 10442 <name>dis</name> 10443 <description>disabled.</description> 10444 <value>0</value> 10445 </enumeratedValue> 10446 <enumeratedValue> 10447 <name>en</name> 10448 <description>enabled.</description> 10449 <value>1</value> 10450 </enumeratedValue> 10451 </enumeratedValues> 10452 </field> 10453 <field> 10454 <name>RAM6</name> 10455 <description>ECC System RAM6 Enable.</description> 10456 <bitOffset>6</bitOffset> 10457 <bitWidth>1</bitWidth> 10458 <enumeratedValues> 10459 <enumeratedValue> 10460 <name>dis</name> 10461 <description>disabled.</description> 10462 <value>0</value> 10463 </enumeratedValue> 10464 <enumeratedValue> 10465 <name>en</name> 10466 <description>enabled.</description> 10467 <value>1</value> 10468 </enumeratedValue> 10469 </enumeratedValues> 10470 </field> 10471 <field> 10472 <name>ICACHE0</name> 10473 <description>ECC ICACHE0 Enable.</description> 10474 <bitOffset>8</bitOffset> 10475 <bitWidth>1</bitWidth> 10476 <enumeratedValues> 10477 <enumeratedValue> 10478 <name>dis</name> 10479 <description>disabled.</description> 10480 <value>0</value> 10481 </enumeratedValue> 10482 <enumeratedValue> 10483 <name>en</name> 10484 <description>enabled.</description> 10485 <value>1</value> 10486 </enumeratedValue> 10487 </enumeratedValues> 10488 </field> 10489 <field> 10490 <name>ICACHEXIP</name> 10491 <description>ECC ICACHE XIP Enable.</description> 10492 <bitOffset>10</bitOffset> 10493 <bitWidth>1</bitWidth> 10494 <enumeratedValues> 10495 <enumeratedValue> 10496 <name>dis</name> 10497 <description>disabled.</description> 10498 <value>0</value> 10499 </enumeratedValue> 10500 <enumeratedValue> 10501 <name>en</name> 10502 <description>enabled.</description> 10503 <value>1</value> 10504 </enumeratedValue> 10505 </enumeratedValues> 10506 </field> 10507 </fields> 10508 </register> 10509 <register> 10510 <name>IPO_MTRIM</name> 10511 <description>IPO Manual Register</description> 10512 <addressOffset>0x04</addressOffset> 10513 <fields> 10514 <field> 10515 <name>MTRIM</name> 10516 <description>Manual Trim Value.</description> 10517 <bitOffset>0</bitOffset> 10518 <bitWidth>8</bitWidth> 10519 </field> 10520 <field> 10521 <name>TRIM_RANGE</name> 10522 <description>Trim Range Select.</description> 10523 <bitOffset>8</bitOffset> 10524 <bitWidth>1</bitWidth> 10525 </field> 10526 </fields> 10527 </register> 10528 <register> 10529 <name>OUTEN</name> 10530 <description>Output Enable Register</description> 10531 <addressOffset>0x08</addressOffset> 10532 <fields> 10533 <field> 10534 <name>SQWOUT_EN</name> 10535 <description>Square Wave Output Enable.</description> 10536 <bitOffset>0</bitOffset> 10537 <bitWidth>1</bitWidth> 10538 </field> 10539 <field> 10540 <name>PDOWN_OUT_EN</name> 10541 <description>Power Down Output Enable.</description> 10542 <bitOffset>1</bitOffset> 10543 <bitWidth>1</bitWidth> 10544 </field> 10545 </fields> 10546 </register> 10547 <register> 10548 <name>CMP_CTRL</name> 10549 <description>Comparator Control Register.</description> 10550 <addressOffset>0x0C</addressOffset> 10551 <fields> 10552 <field> 10553 <name>EN</name> 10554 <description>Comparator Enable.</description> 10555 <bitOffset>0</bitOffset> 10556 <bitWidth>1</bitWidth> 10557 </field> 10558 <field> 10559 <name>POL</name> 10560 <description>Polarity Select</description> 10561 <bitOffset>5</bitOffset> 10562 <bitWidth>1</bitWidth> 10563 </field> 10564 <field> 10565 <name>INT_EN</name> 10566 <description>IRQ Enable.</description> 10567 <bitOffset>6</bitOffset> 10568 <bitWidth>1</bitWidth> 10569 </field> 10570 <field> 10571 <name>OUT</name> 10572 <description>Comparator Output State.</description> 10573 <bitOffset>14</bitOffset> 10574 <bitWidth>1</bitWidth> 10575 </field> 10576 <field> 10577 <name>INT_FL</name> 10578 <description>IRQ Flag</description> 10579 <bitOffset>15</bitOffset> 10580 <bitWidth>1</bitWidth> 10581 </field> 10582 </fields> 10583 </register> 10584 <register> 10585 <name>CTRL</name> 10586 <description>Miscellaneous Control Register.</description> 10587 <addressOffset>0x10</addressOffset> 10588 <fields> 10589 <field> 10590 <name>CMPHYST</name> 10591 <description>Comparator HYST.</description> 10592 <bitOffset>0</bitOffset> 10593 <bitWidth>2</bitWidth> 10594 </field> 10595 <field> 10596 <name>INRO_EN</name> 10597 <description>INRO Enable.</description> 10598 <bitOffset>2</bitOffset> 10599 <bitWidth>1</bitWidth> 10600 </field> 10601 <field> 10602 <name>ERTCO_EN</name> 10603 <description>ERTCO Enable.</description> 10604 <bitOffset>3</bitOffset> 10605 <bitWidth>1</bitWidth> 10606 </field> 10607 <field> 10608 <name>IBRO_EN</name> 10609 <description>IBRO Enable.</description> 10610 <bitOffset>4</bitOffset> 10611 <bitWidth>1</bitWidth> 10612 </field> 10613 <field> 10614 <name>RSTNP1M</name> 10615 <description>RSTNP1M</description> 10616 <bitOffset>9</bitOffset> 10617 <bitWidth>1</bitWidth> 10618 </field> 10619 <field> 10620 <name>RSTNVDDIOHSEL</name> 10621 <description>RSTNVFFIOHSEL</description> 10622 <bitOffset>10</bitOffset> 10623 <bitWidth>1</bitWidth> 10624 </field> 10625 </fields> 10626 </register> 10627 <register> 10628 <name>GPIO4_CTRL</name> 10629 <description>GPIO4 Pin Control Register.</description> 10630 <addressOffset>0x20</addressOffset> 10631 <fields> 10632 <field> 10633 <name>P40_DO</name> 10634 <description>GPIO4 Pin 0 Data Output.</description> 10635 <bitOffset>0</bitOffset> 10636 <bitWidth>1</bitWidth> 10637 </field> 10638 <field> 10639 <name>P40_OE</name> 10640 <description>GPIO4 Pin 0 Output Enable.</description> 10641 <bitOffset>1</bitOffset> 10642 <bitWidth>1</bitWidth> 10643 </field> 10644 <field> 10645 <name>P40_PE</name> 10646 <description>GPIO4 Pin 0 Pull-up Enable.</description> 10647 <bitOffset>2</bitOffset> 10648 <bitWidth>1</bitWidth> 10649 </field> 10650 <field> 10651 <name>P40_IN</name> 10652 <description>GPIO4 Pin 0 Input Status.</description> 10653 <bitOffset>3</bitOffset> 10654 <bitWidth>1</bitWidth> 10655 </field> 10656 <field> 10657 <name>P41_DO</name> 10658 <description>GPIO4 Pin 1 Data Output.</description> 10659 <bitOffset>4</bitOffset> 10660 <bitWidth>1</bitWidth> 10661 </field> 10662 <field> 10663 <name>P41_OE</name> 10664 <description>GPIO4 Pin 1 Output Enable.</description> 10665 <bitOffset>5</bitOffset> 10666 <bitWidth>1</bitWidth> 10667 </field> 10668 <field> 10669 <name>P41_PE</name> 10670 <description>GPIO4 Pin 1 Pull-up Enable.</description> 10671 <bitOffset>6</bitOffset> 10672 <bitWidth>1</bitWidth> 10673 </field> 10674 <field> 10675 <name>P41_IN</name> 10676 <description>GPIO4 Pin 1 Input Status.</description> 10677 <bitOffset>7</bitOffset> 10678 <bitWidth>1</bitWidth> 10679 </field> 10680 </fields> 10681 </register> 10682 <register> 10683 <name>CWD0</name> 10684 <description>Code Word Data0</description> 10685 <addressOffset>0x40</addressOffset> 10686 <fields> 10687 <field> 10688 <name>data</name> 10689 <description>Code word Data0 the register retains its value while vregi supply present</description> 10690 <bitOffset>0</bitOffset> 10691 <bitWidth>32</bitWidth> 10692 </field> 10693 </fields> 10694 </register> 10695 <register> 10696 <name>CWD1</name> 10697 <description>Code Word Data1</description> 10698 <addressOffset>0x44</addressOffset> 10699 <fields> 10700 <field> 10701 <name>data</name> 10702 <description>Code word Data0 the register retains its value while vregi supply present</description> 10703 <bitOffset>0</bitOffset> 10704 <bitWidth>32</bitWidth> 10705 </field> 10706 </fields> 10707 </register> 10708 <register> 10709 <name>ADCCFG0</name> 10710 <description>ADC Config 0</description> 10711 <addressOffset>0x50</addressOffset> 10712 <fields> 10713 <field> 10714 <name>LP_5K_DIS</name> 10715 <description>Disable 5K divider optionin low power modes</description> 10716 <bitOffset>0</bitOffset> 10717 <bitWidth>1</bitWidth> 10718 </field> 10719 <field> 10720 <name>LP_50K_DIS</name> 10721 <description>Disable 50K divider optionin low power modes</description> 10722 <bitOffset>1</bitOffset> 10723 <bitWidth>1</bitWidth> 10724 </field> 10725 <field> 10726 <name>EXT_REF</name> 10727 <description>External Reference Select Option</description> 10728 <bitOffset>2</bitOffset> 10729 <bitWidth>1</bitWidth> 10730 </field> 10731 <field> 10732 <name>REF_SEL</name> 10733 <description>Internal Reference Select Option</description> 10734 <bitOffset>3</bitOffset> 10735 <bitWidth>1</bitWidth> 10736 </field> 10737 </fields> 10738 </register> 10739 <register> 10740 <name>ADCCFG1</name> 10741 <description>ADC Config 1</description> 10742 <addressOffset>0x54</addressOffset> 10743 <fields> 10744 <field> 10745 <name>CHX_PU_DYN</name> 10746 <description>ADC PU dynamic control</description> 10747 <bitOffset>0</bitOffset> 10748 <bitWidth>13</bitWidth> 10749 </field> 10750 </fields> 10751 </register> 10752 <register> 10753 <name>ADCCFG2</name> 10754 <description>ADC Config 2</description> 10755 <addressOffset>0x58</addressOffset> 10756 <fields> 10757 <field> 10758 <name>CH0</name> 10759 <description>Divider option for ADC input channel 0</description> 10760 <bitOffset>0</bitOffset> 10761 <bitWidth>2</bitWidth> 10762 <enumeratedValues> 10763 <enumeratedValue> 10764 <name>div1</name> 10765 <description>div1</description> 10766 <value>0</value> 10767 </enumeratedValue> 10768 <enumeratedValue> 10769 <name>div2_5k</name> 10770 <description>5k ohom</description> 10771 <value>1</value> 10772 </enumeratedValue> 10773 <enumeratedValue> 10774 <name>div2_50k</name> 10775 <description>50k ohom</description> 10776 <value>2</value> 10777 </enumeratedValue> 10778 </enumeratedValues> 10779 </field> 10780 <field derivedFrom="CH0"> 10781 <name>CH1</name> 10782 <description>Divider option for ADC input channel 1</description> 10783 <bitOffset>2</bitOffset> 10784 <bitWidth>2</bitWidth> 10785 </field> 10786 <field derivedFrom="CH0"> 10787 <name>CH2</name> 10788 <description>Divider option for ADC input channel 2</description> 10789 <bitOffset>4</bitOffset> 10790 <bitWidth>2</bitWidth> 10791 </field> 10792 <field derivedFrom="CH0"> 10793 <name>CH3</name> 10794 <description>Divider option for ADC input channel 3</description> 10795 <bitOffset>6</bitOffset> 10796 <bitWidth>2</bitWidth> 10797 </field> 10798 <field derivedFrom="CH0"> 10799 <name>CH4</name> 10800 <description>Divider option for ADC input channel 4</description> 10801 <bitOffset>8</bitOffset> 10802 <bitWidth>2</bitWidth> 10803 </field> 10804 <field derivedFrom="CH0"> 10805 <name>CH5</name> 10806 <description>Divider option for ADC input channel 5</description> 10807 <bitOffset>10</bitOffset> 10808 <bitWidth>2</bitWidth> 10809 </field> 10810 <field derivedFrom="CH0"> 10811 <name>CH6</name> 10812 <description>Divider option for ADC input channel 6</description> 10813 <bitOffset>12</bitOffset> 10814 <bitWidth>2</bitWidth> 10815 </field> 10816 <field derivedFrom="CH0"> 10817 <name>CH7</name> 10818 <description>Divider option for ADC input channel 7</description> 10819 <bitOffset>14</bitOffset> 10820 <bitWidth>2</bitWidth> 10821 </field> 10822 </fields> 10823 </register> 10824 <register> 10825 <name>LDOCTRL</name> 10826 <description>LDO Control</description> 10827 <addressOffset>0x60</addressOffset> 10828 <fields> 10829 <field> 10830 <name>0P9EN</name> 10831 <description>LDO 0.9V Enable</description> 10832 <bitOffset>0</bitOffset> 10833 <bitWidth>1</bitWidth> 10834 </field> 10835 <field> 10836 <name>2P5EN</name> 10837 <description>LDO 2.5V Enable</description> 10838 <bitOffset>1</bitOffset> 10839 <bitWidth>1</bitWidth> 10840 </field> 10841 </fields> 10842 </register> 10843 </registers> 10844 </peripheral> 10845<!--MCR Misc Control.--> 10846 <peripheral> 10847 <name>OWM</name> 10848 <description>1-Wire Master Interface.</description> 10849 <baseAddress>0x4003D000</baseAddress> 10850 <size>32</size> 10851 <access>read-write</access> 10852 <addressBlock> 10853 <offset>0</offset> 10854 <size>0x1000</size> 10855 <usage>registers</usage> 10856 </addressBlock> 10857 <interrupt> 10858 <name>OneWire</name> 10859 <value>67</value> 10860 </interrupt> 10861 <registers> 10862 <register> 10863 <name>CFG</name> 10864 <description>1-Wire Master Configuration.</description> 10865 <addressOffset>0x0000</addressOffset> 10866 <access>read-write</access> 10867 <fields> 10868 <field> 10869 <name>long_line_mode</name> 10870 <description>Long Line Mode.</description> 10871 <bitRange>[0:0]</bitRange> 10872 <access>read-write</access> 10873 </field> 10874 <field> 10875 <name>force_pres_det</name> 10876 <description>Force Line During Presence Detect.</description> 10877 <bitRange>[1:1]</bitRange> 10878 <access>read-write</access> 10879 </field> 10880 <field> 10881 <name>bit_bang_en</name> 10882 <description>Bit Bang Enable.</description> 10883 <bitRange>[2:2]</bitRange> 10884 <access>read-write</access> 10885 </field> 10886 <field> 10887 <name>ext_pullup_mode</name> 10888 <description>Provide an extra output control to control an external pullup.</description> 10889 <bitRange>[3:3]</bitRange> 10890 <access>read-write</access> 10891 </field> 10892 <field> 10893 <name>ext_pullup_enable</name> 10894 <description>Enable External Pullup.</description> 10895 <bitRange>[4:4]</bitRange> 10896 <access>read-write</access> 10897 </field> 10898 <field> 10899 <name>single_bit_mode</name> 10900 <description>Enable Single Bit TX/RX Mode.</description> 10901 <bitRange>[5:5]</bitRange> 10902 <access>read-write</access> 10903 </field> 10904 <field> 10905 <name>overdrive</name> 10906 <description>Enables overdrive speed for 1-Wire operations.</description> 10907 <bitRange>[6:6]</bitRange> 10908 <access>read-write</access> 10909 </field> 10910 <field> 10911 <name>int_pullup_enable</name> 10912 <description>Enable intenral pullup.</description> 10913 <bitRange>[7:7]</bitRange> 10914 <access>read-write</access> 10915 </field> 10916 </fields> 10917 </register> 10918 <register> 10919 <name>CLK_DIV_1US</name> 10920 <description>1-Wire Master Clock Divisor.</description> 10921 <addressOffset>0x0004</addressOffset> 10922 <access>read-write</access> 10923 <fields> 10924 <field> 10925 <name>divisor</name> 10926 <description>Clock Divisor for 1Mhz.</description> 10927 <bitRange>[7:0]</bitRange> 10928 <access>read-write</access> 10929 </field> 10930 </fields> 10931 </register> 10932 <register> 10933 <name>CTRL_STAT</name> 10934 <description>1-Wire Master Control/Status.</description> 10935 <addressOffset>0x0008</addressOffset> 10936 <access>read-write</access> 10937 <fields> 10938 <field> 10939 <name>start_ow_reset</name> 10940 <description>Start OW Reset.</description> 10941 <bitRange>[0:0]</bitRange> 10942 <access>read-write</access> 10943 </field> 10944 <field> 10945 <name>sra_mode</name> 10946 <description>SRA Mode.</description> 10947 <bitRange>[1:1]</bitRange> 10948 <access>read-write</access> 10949 </field> 10950 <field> 10951 <name>bit_bang_oe</name> 10952 <description>Bit Bang Output Enable.</description> 10953 <bitRange>[2:2]</bitRange> 10954 <access>read-write</access> 10955 </field> 10956 <field> 10957 <name>ow_input</name> 10958 <description>OW Input State.</description> 10959 <bitRange>[3:3]</bitRange> 10960 <access>read-only</access> 10961 </field> 10962 <field> 10963 <name>od_spec_mode</name> 10964 <description>Overdrive Spec Mode.</description> 10965 <bitRange>[4:4]</bitRange> 10966 <access>read-only</access> 10967 </field> 10968 <field> 10969 <name>presence_detect</name> 10970 <description>Presence Pulse Detected.</description> 10971 <bitRange>[7:7]</bitRange> 10972 <access>read-only</access> 10973 </field> 10974 </fields> 10975 </register> 10976 <register> 10977 <name>DATA</name> 10978 <description>1-Wire Master Data Buffer.</description> 10979 <addressOffset>0x000C</addressOffset> 10980 <access>read-write</access> 10981 <fields> 10982 <field> 10983 <name>tx_rx</name> 10984 <description>TX/RX Buffer.</description> 10985 <bitRange>[7:0]</bitRange> 10986 <access>read-write</access> 10987 </field> 10988 </fields> 10989 </register> 10990 <register> 10991 <name>INTFL</name> 10992 <description>1-Wire Master Interrupt Flags.</description> 10993 <addressOffset>0x0010</addressOffset> 10994 <access>read-write</access> 10995 <fields> 10996 <field> 10997 <name>ow_reset_done</name> 10998 <description>OW Reset Sequence Completed.</description> 10999 <bitRange>[0:0]</bitRange> 11000 <access>read-write</access> 11001 </field> 11002 <field> 11003 <name>tx_data_empty</name> 11004 <description>TX Data Empty Interrupt Flag.</description> 11005 <bitRange>[1:1]</bitRange> 11006 <access>read-write</access> 11007 </field> 11008 <field> 11009 <name>rx_data_ready</name> 11010 <description>RX Data Ready Interrupt Flag</description> 11011 <bitRange>[2:2]</bitRange> 11012 <access>read-write</access> 11013 </field> 11014 <field> 11015 <name>line_short</name> 11016 <description>OW Line Short Detected Interrupt Flag.</description> 11017 <bitRange>[3:3]</bitRange> 11018 <access>read-write</access> 11019 </field> 11020 <field> 11021 <name>line_low</name> 11022 <description>OW Line Low Detected Interrupt Flag.</description> 11023 <bitRange>[4:4]</bitRange> 11024 <access>read-write</access> 11025 </field> 11026 </fields> 11027 </register> 11028 <register> 11029 <name>INTEN</name> 11030 <description>1-Wire Master Interrupt Enables.</description> 11031 <addressOffset>0x0014</addressOffset> 11032 <access>read-write</access> 11033 <fields> 11034 <field> 11035 <name>ow_reset_done</name> 11036 <description>OW Reset Sequence Completed.</description> 11037 <bitRange>[0:0]</bitRange> 11038 <access>read-write</access> 11039 <modifiedWriteValues>oneToClear</modifiedWriteValues> 11040 </field> 11041 <field> 11042 <name>tx_data_empty</name> 11043 <description>Tx Data Empty Interrupt Enable.</description> 11044 <bitRange>[1:1]</bitRange> 11045 <access>read-write</access> 11046 <modifiedWriteValues>oneToClear</modifiedWriteValues> 11047 </field> 11048 <field> 11049 <name>rx_data_ready</name> 11050 <description>Rx Data Ready Interrupt Enable.</description> 11051 <bitRange>[2:2]</bitRange> 11052 <access>read-write</access> 11053 <modifiedWriteValues>oneToClear</modifiedWriteValues> 11054 </field> 11055 <field> 11056 <name>line_short</name> 11057 <description>OW Line Short Detected Interrupt Enable.</description> 11058 <bitRange>[3:3]</bitRange> 11059 <access>read-write</access> 11060 <modifiedWriteValues>oneToClear</modifiedWriteValues> 11061 </field> 11062 <field> 11063 <name>line_low</name> 11064 <description>OW Line Low Detected Interrupt Enable.</description> 11065 <bitRange>[4:4]</bitRange> 11066 <access>read-write</access> 11067 <modifiedWriteValues>oneToClear</modifiedWriteValues> 11068 </field> 11069 </fields> 11070 </register> 11071 </registers> 11072 </peripheral> 11073<!--OWM 1-Wire Master Interface.--> 11074 <peripheral> 11075 <name>PT</name> 11076 <description>Pulse Train</description> 11077 <groupName>Pulse_Train</groupName> 11078 <baseAddress>0x4003C020</baseAddress> 11079 <size>32</size> 11080 <access>read-write</access> 11081 <addressBlock> 11082 <offset>0</offset> 11083 <size>0x0010</size> 11084 <usage>registers</usage> 11085 </addressBlock> 11086 <registers> 11087 <register> 11088 <name>RATE_LENGTH</name> 11089 <description>Pulse Train Configuration</description> 11090 <addressOffset>0x0000</addressOffset> 11091 <access>read-write</access> 11092 <fields> 11093 <field> 11094 <name>rate_control</name> 11095 <description>Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train.</description> 11096 <bitOffset>0</bitOffset> 11097 <bitWidth>27</bitWidth> 11098 <access>read-write</access> 11099 </field> 11100 <field> 11101 <name>mode</name> 11102 <description>Pulse Train Output Mode/Train Length</description> 11103 <bitOffset>27</bitOffset> 11104 <bitWidth>5</bitWidth> 11105 <access>read-write</access> 11106 <enumeratedValues> 11107 <enumeratedValue> 11108 <name>32_BIT</name> 11109 <description>Pulse train, 32 bit pattern.</description> 11110 <value>0</value> 11111 </enumeratedValue> 11112 <enumeratedValue> 11113 <name>SQUARE_WAVE</name> 11114 <description>Square wave mode.</description> 11115 <value>1</value> 11116 </enumeratedValue> 11117 <enumeratedValue> 11118 <name>2_BIT</name> 11119 <description>Pulse train, 2 bit pattern.</description> 11120 <value>2</value> 11121 </enumeratedValue> 11122 <enumeratedValue> 11123 <name>3_BIT</name> 11124 <description>Pulse train, 3 bit pattern.</description> 11125 <value>3</value> 11126 </enumeratedValue> 11127 <enumeratedValue> 11128 <name>4_BIT</name> 11129 <description>Pulse train, 4 bit pattern.</description> 11130 <value>4</value> 11131 </enumeratedValue> 11132 <enumeratedValue> 11133 <name>5_BIT</name> 11134 <description>Pulse train, 5 bit pattern.</description> 11135 <value>5</value> 11136 </enumeratedValue> 11137 <enumeratedValue> 11138 <name>6_BIT</name> 11139 <description>Pulse train, 6 bit pattern.</description> 11140 <value>6</value> 11141 </enumeratedValue> 11142 <enumeratedValue> 11143 <name>7_BIT</name> 11144 <description>Pulse train, 7 bit pattern.</description> 11145 <value>7</value> 11146 </enumeratedValue> 11147 <enumeratedValue> 11148 <name>8_BIT</name> 11149 <description>Pulse train, 8 bit pattern.</description> 11150 <value>8</value> 11151 </enumeratedValue> 11152 <enumeratedValue> 11153 <name>9_BIT</name> 11154 <description>Pulse train, 9 bit pattern.</description> 11155 <value>9</value> 11156 </enumeratedValue> 11157 <enumeratedValue> 11158 <name>10_BIT</name> 11159 <description>Pulse train, 10 bit pattern.</description> 11160 <value>10</value> 11161 </enumeratedValue> 11162 <enumeratedValue> 11163 <name>11_BIT</name> 11164 <description>Pulse train, 11 bit pattern.</description> 11165 <value>11</value> 11166 </enumeratedValue> 11167 <enumeratedValue> 11168 <name>12_BIT</name> 11169 <description>Pulse train, 12 bit pattern.</description> 11170 <value>12</value> 11171 </enumeratedValue> 11172 <enumeratedValue> 11173 <name>13_BIT</name> 11174 <description>Pulse train, 13 bit pattern.</description> 11175 <value>13</value> 11176 </enumeratedValue> 11177 <enumeratedValue> 11178 <name>14_BIT</name> 11179 <description>Pulse train, 14 bit pattern.</description> 11180 <value>14</value> 11181 </enumeratedValue> 11182 <enumeratedValue> 11183 <name>15_BIT</name> 11184 <description>Pulse train, 15 bit pattern.</description> 11185 <value>15</value> 11186 </enumeratedValue> 11187 <enumeratedValue> 11188 <name>16_BIT</name> 11189 <description>Pulse train, 16 bit pattern.</description> 11190 <value>16</value> 11191 </enumeratedValue> 11192 <enumeratedValue> 11193 <name>17_BIT</name> 11194 <description>Pulse train, 17 bit pattern.</description> 11195 <value>17</value> 11196 </enumeratedValue> 11197 <enumeratedValue> 11198 <name>18_BIT</name> 11199 <description>Pulse train, 18 bit pattern.</description> 11200 <value>18</value> 11201 </enumeratedValue> 11202 <enumeratedValue> 11203 <name>19_BIT</name> 11204 <description>Pulse train, 19 bit pattern.</description> 11205 <value>19</value> 11206 </enumeratedValue> 11207 <enumeratedValue> 11208 <name>20_BIT</name> 11209 <description>Pulse train, 20 bit pattern.</description> 11210 <value>20</value> 11211 </enumeratedValue> 11212 <enumeratedValue> 11213 <name>21_BIT</name> 11214 <description>Pulse train, 21 bit pattern.</description> 11215 <value>21</value> 11216 </enumeratedValue> 11217 <enumeratedValue> 11218 <name>22_BIT</name> 11219 <description>Pulse train, 22 bit pattern.</description> 11220 <value>22</value> 11221 </enumeratedValue> 11222 <enumeratedValue> 11223 <name>23_BIT</name> 11224 <description>Pulse train, 23 bit pattern.</description> 11225 <value>23</value> 11226 </enumeratedValue> 11227 <enumeratedValue> 11228 <name>24_BIT</name> 11229 <description>Pulse train, 24 bit pattern.</description> 11230 <value>24</value> 11231 </enumeratedValue> 11232 <enumeratedValue> 11233 <name>25_BIT</name> 11234 <description>Pulse train, 25 bit pattern.</description> 11235 <value>25</value> 11236 </enumeratedValue> 11237 <enumeratedValue> 11238 <name>26_BIT</name> 11239 <description>Pulse train, 26 bit pattern.</description> 11240 <value>26</value> 11241 </enumeratedValue> 11242 <enumeratedValue> 11243 <name>27_BIT</name> 11244 <description>Pulse train, 27 bit pattern.</description> 11245 <value>27</value> 11246 </enumeratedValue> 11247 <enumeratedValue> 11248 <name>28_BIT</name> 11249 <description>Pulse train, 28 bit pattern.</description> 11250 <value>28</value> 11251 </enumeratedValue> 11252 <enumeratedValue> 11253 <name>29_BIT</name> 11254 <description>Pulse train, 29 bit pattern.</description> 11255 <value>29</value> 11256 </enumeratedValue> 11257 <enumeratedValue> 11258 <name>30_BIT</name> 11259 <description>Pulse train, 30 bit pattern.</description> 11260 <value>30</value> 11261 </enumeratedValue> 11262 <enumeratedValue> 11263 <name>31_BIT</name> 11264 <description>Pulse train, 31 bit pattern.</description> 11265 <value>31</value> 11266 </enumeratedValue> 11267 </enumeratedValues> 11268 </field> 11269 </fields> 11270 </register> 11271 <register> 11272 <name>TRAIN</name> 11273 <description>Write the repeating bit pattern that is shifted out, LSB first, when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length.</description> 11274 <addressOffset>0x0004</addressOffset> 11275 <access>read-write</access> 11276 </register> 11277 <register> 11278 <name>LOOP</name> 11279 <description>Pulse Train Loop Count</description> 11280 <addressOffset>0x0008</addressOffset> 11281 <access>read-write</access> 11282 <fields> 11283 <field> 11284 <name>count</name> 11285 <description>Number of loops for this pulse train to repeat.</description> 11286 <bitOffset>0</bitOffset> 11287 <bitWidth>16</bitWidth> 11288 <access>read-write</access> 11289 </field> 11290 <field> 11291 <name>delay</name> 11292 <description>Delay between loops of the Pulse Train in PT Peripheral Clock cycles</description> 11293 <bitOffset>16</bitOffset> 11294 <bitWidth>12</bitWidth> 11295 <access>read-write</access> 11296 </field> 11297 </fields> 11298 </register> 11299 <register> 11300 <name>RESTART</name> 11301 <description> Pulse Train Auto-Restart Configuration.</description> 11302 <addressOffset>0x000C</addressOffset> 11303 <access>read-write</access> 11304 <fields> 11305 <field> 11306 <name>pt_x_select</name> 11307 <description>Auto-Restart PT X Select</description> 11308 <bitOffset>0</bitOffset> 11309 <bitWidth>5</bitWidth> 11310 <access>read-write</access> 11311 </field> 11312 <field> 11313 <name>on_pt_x_loop_exit</name> 11314 <description>Enable Auto-Restart on PT X Loop Exit</description> 11315 <bitOffset>7</bitOffset> 11316 <bitWidth>1</bitWidth> 11317 <access>read-write</access> 11318 </field> 11319 <field> 11320 <name>pt_y_select</name> 11321 <description>Auto-Restart PT Y Select</description> 11322 <bitOffset>8</bitOffset> 11323 <bitWidth>5</bitWidth> 11324 <access>read-write</access> 11325 </field> 11326 <field> 11327 <name>on_pt_y_loop_exit</name> 11328 <description>Enable Auto-Restart on PT Y Loop Exit</description> 11329 <bitOffset>15</bitOffset> 11330 <bitWidth>1</bitWidth> 11331 <access>read-write</access> 11332 </field> 11333 </fields> 11334 </register> 11335 </registers> 11336 </peripheral> 11337<!--PT Pulse Train--> 11338 <peripheral derivedFrom="PT"> 11339 <name>PT1</name> 11340 <description>Pulse Train 1</description> 11341 <baseAddress>0x4003C030</baseAddress> 11342 </peripheral> 11343<!--PT1 Pulse Train 1--> 11344 <peripheral derivedFrom="PT"> 11345 <name>PT2</name> 11346 <description>Pulse Train 2</description> 11347 <baseAddress>0x4003C040</baseAddress> 11348 </peripheral> 11349<!--PT2 Pulse Train 2--> 11350 <peripheral derivedFrom="PT"> 11351 <name>PT3</name> 11352 <description>Pulse Train 3</description> 11353 <baseAddress>0x4003C050</baseAddress> 11354 </peripheral> 11355<!--PT3 Pulse Train 3--> 11356 <peripheral derivedFrom="PT"> 11357 <name>PT4</name> 11358 <description>Pulse Train 4</description> 11359 <baseAddress>0x4003C060</baseAddress> 11360 </peripheral> 11361<!--PT4 Pulse Train 4--> 11362 <peripheral derivedFrom="PT"> 11363 <name>PT5</name> 11364 <description>Pulse Train 5</description> 11365 <baseAddress>0x4003C070</baseAddress> 11366 </peripheral> 11367<!--PT5 Pulse Train 5--> 11368 <peripheral derivedFrom="PT"> 11369 <name>PT6</name> 11370 <description>Pulse Train 6</description> 11371 <baseAddress>0x4003C080</baseAddress> 11372 </peripheral> 11373<!--PT6 Pulse Train 6--> 11374 <peripheral derivedFrom="PT"> 11375 <name>PT7</name> 11376 <description>Pulse Train 7</description> 11377 <baseAddress>0x4003C090</baseAddress> 11378 </peripheral> 11379<!--PT7 Pulse Train 7--> 11380 <peripheral derivedFrom="PT"> 11381 <name>PT8</name> 11382 <description>Pulse Train 8</description> 11383 <baseAddress>0x4003C0A0</baseAddress> 11384 </peripheral> 11385<!--PT8 Pulse Train 8--> 11386 <peripheral derivedFrom="PT"> 11387 <name>PT9</name> 11388 <description>Pulse Train 9</description> 11389 <baseAddress>0x4003C0B0</baseAddress> 11390 </peripheral> 11391<!--PT9 Pulse Train 9--> 11392 <peripheral derivedFrom="PT"> 11393 <name>PT10</name> 11394 <description>Pulse Train 10</description> 11395 <baseAddress>0x4003C0C0</baseAddress> 11396 </peripheral> 11397<!--PT10 Pulse Train 10--> 11398 <peripheral derivedFrom="PT"> 11399 <name>PT11</name> 11400 <description>Pulse Train 11</description> 11401 <baseAddress>0x4003C0D0</baseAddress> 11402 </peripheral> 11403<!--PT11 Pulse Train 11--> 11404 <peripheral derivedFrom="PT"> 11405 <name>PT12</name> 11406 <description>Pulse Train 12</description> 11407 <baseAddress>0x4003C0E0</baseAddress> 11408 </peripheral> 11409<!--PT12 Pulse Train 12--> 11410 <peripheral derivedFrom="PT"> 11411 <name>PT13</name> 11412 <description>Pulse Train 13</description> 11413 <baseAddress>0x4003C0F0</baseAddress> 11414 </peripheral> 11415<!--PT13 Pulse Train 13--> 11416 <peripheral derivedFrom="PT"> 11417 <name>PT14</name> 11418 <description>Pulse Train 14</description> 11419 <baseAddress>0x4003C100</baseAddress> 11420 </peripheral> 11421<!--PT14 Pulse Train 14--> 11422 <peripheral derivedFrom="PT"> 11423 <name>PT15</name> 11424 <description>Pulse Train 15</description> 11425 <baseAddress>0x4003C110</baseAddress> 11426 </peripheral> 11427<!--PT15 Pulse Train 15--> 11428 <peripheral> 11429 <name>PTG</name> 11430 <description>Pulse Train Generation</description> 11431 <groupName>Pulse_Train</groupName> 11432 <baseAddress>0x4003C000</baseAddress> 11433 <size>32</size> 11434 <access>read-write</access> 11435 <addressBlock> 11436 <offset>0</offset> 11437 <size>0x0020</size> 11438 <usage>registers</usage> 11439 </addressBlock> 11440 <interrupt> 11441 <name>PT</name> 11442 <description>Pulse Train IRQ</description> 11443 <value>59</value> 11444 </interrupt> 11445 <registers> 11446 <register> 11447 <name>ENABLE</name> 11448 <description>Global Enable/Disable Controls for All Pulse Trains</description> 11449 <addressOffset>0x0000</addressOffset> 11450 <access>read-write</access> 11451 <fields> 11452 <field> 11453 <name>pt0</name> 11454 <description>Enable/Disable control for PT0</description> 11455 <bitOffset>0</bitOffset> 11456 <bitWidth>1</bitWidth> 11457 <access>read-write</access> 11458 </field> 11459 <field> 11460 <name>pt1</name> 11461 <description>Enable/Disable control for PT1</description> 11462 <bitOffset>1</bitOffset> 11463 <bitWidth>1</bitWidth> 11464 <access>read-write</access> 11465 </field> 11466 <field> 11467 <name>pt2</name> 11468 <description>Enable/Disable control for PT2</description> 11469 <bitOffset>2</bitOffset> 11470 <bitWidth>1</bitWidth> 11471 <access>read-write</access> 11472 </field> 11473 <field> 11474 <name>pt3</name> 11475 <description>Enable/Disable control for PT3</description> 11476 <bitOffset>3</bitOffset> 11477 <bitWidth>1</bitWidth> 11478 <access>read-write</access> 11479 </field> 11480 <field> 11481 <name>pt4</name> 11482 <description>Enable/Disable control for PT4</description> 11483 <bitOffset>4</bitOffset> 11484 <bitWidth>1</bitWidth> 11485 <access>read-write</access> 11486 </field> 11487 <field> 11488 <name>pt5</name> 11489 <description>Enable/Disable control for PT5</description> 11490 <bitOffset>5</bitOffset> 11491 <bitWidth>1</bitWidth> 11492 <access>read-write</access> 11493 </field> 11494 <field> 11495 <name>pt6</name> 11496 <description>Enable/Disable control for PT6</description> 11497 <bitOffset>6</bitOffset> 11498 <bitWidth>1</bitWidth> 11499 <access>read-write</access> 11500 </field> 11501 <field> 11502 <name>pt7</name> 11503 <description>Enable/Disable control for PT7</description> 11504 <bitOffset>7</bitOffset> 11505 <bitWidth>1</bitWidth> 11506 <access>read-write</access> 11507 </field> 11508 <field> 11509 <name>pt8</name> 11510 <description>Enable/Disable control for PT8</description> 11511 <bitOffset>8</bitOffset> 11512 <bitWidth>1</bitWidth> 11513 <access>read-write</access> 11514 </field> 11515 <field> 11516 <name>pt9</name> 11517 <description>Enable/Disable control for PT9</description> 11518 <bitOffset>9</bitOffset> 11519 <bitWidth>1</bitWidth> 11520 <access>read-write</access> 11521 </field> 11522 <field> 11523 <name>pt10</name> 11524 <description>Enable/Disable control for PT10</description> 11525 <bitOffset>10</bitOffset> 11526 <bitWidth>1</bitWidth> 11527 <access>read-write</access> 11528 </field> 11529 <field> 11530 <name>pt11</name> 11531 <description>Enable/Disable control for PT11</description> 11532 <bitOffset>11</bitOffset> 11533 <bitWidth>1</bitWidth> 11534 <access>read-write</access> 11535 </field> 11536 <field> 11537 <name>pt12</name> 11538 <description>Enable/Disable control for PT12</description> 11539 <bitOffset>12</bitOffset> 11540 <bitWidth>1</bitWidth> 11541 <access>read-write</access> 11542 </field> 11543 <field> 11544 <name>pt13</name> 11545 <description>Enable/Disable control for PT13</description> 11546 <bitOffset>13</bitOffset> 11547 <bitWidth>1</bitWidth> 11548 <access>read-write</access> 11549 </field> 11550 <field> 11551 <name>pt14</name> 11552 <description>Enable/Disable control for PT14</description> 11553 <bitOffset>14</bitOffset> 11554 <bitWidth>1</bitWidth> 11555 <access>read-write</access> 11556 </field> 11557 <field> 11558 <name>pt15</name> 11559 <description>Enable/Disable control for PT15</description> 11560 <bitOffset>15</bitOffset> 11561 <bitWidth>1</bitWidth> 11562 <access>read-write</access> 11563 </field> 11564 </fields> 11565 </register> 11566 <register> 11567 <name>RESYNC</name> 11568 <description>Global Resync (All Pulse Trains) Control</description> 11569 <addressOffset>0x0004</addressOffset> 11570 <access>read-write</access> 11571 <fields> 11572 <field> 11573 <name>pt0</name> 11574 <description>Resync control for PT0</description> 11575 <bitOffset>0</bitOffset> 11576 <bitWidth>1</bitWidth> 11577 <access>read-write</access> 11578 </field> 11579 <field> 11580 <name>pt1</name> 11581 <description>Resync control for PT1</description> 11582 <bitOffset>1</bitOffset> 11583 <bitWidth>1</bitWidth> 11584 <access>read-write</access> 11585 </field> 11586 <field> 11587 <name>pt2</name> 11588 <description>Resync control for PT2</description> 11589 <bitOffset>2</bitOffset> 11590 <bitWidth>1</bitWidth> 11591 <access>read-write</access> 11592 </field> 11593 <field> 11594 <name>pt3</name> 11595 <description>Resync control for PT3</description> 11596 <bitOffset>3</bitOffset> 11597 <bitWidth>1</bitWidth> 11598 <access>read-write</access> 11599 </field> 11600 <field> 11601 <name>pt4</name> 11602 <description>Resync control for PT4</description> 11603 <bitOffset>4</bitOffset> 11604 <bitWidth>1</bitWidth> 11605 <access>read-write</access> 11606 </field> 11607 <field> 11608 <name>pt5</name> 11609 <description>Resync control for PT5</description> 11610 <bitOffset>5</bitOffset> 11611 <bitWidth>1</bitWidth> 11612 <access>read-write</access> 11613 </field> 11614 <field> 11615 <name>pt6</name> 11616 <description>Resync control for PT6</description> 11617 <bitOffset>6</bitOffset> 11618 <bitWidth>1</bitWidth> 11619 <access>read-write</access> 11620 </field> 11621 <field> 11622 <name>pt7</name> 11623 <description>Resync control for PT7</description> 11624 <bitOffset>7</bitOffset> 11625 <bitWidth>1</bitWidth> 11626 <access>read-write</access> 11627 </field> 11628 <field> 11629 <name>pt8</name> 11630 <description>Resync control for PT8</description> 11631 <bitOffset>8</bitOffset> 11632 <bitWidth>1</bitWidth> 11633 <access>read-write</access> 11634 </field> 11635 <field> 11636 <name>pt9</name> 11637 <description>Resync control for PT9</description> 11638 <bitOffset>9</bitOffset> 11639 <bitWidth>1</bitWidth> 11640 <access>read-write</access> 11641 </field> 11642 <field> 11643 <name>pt10</name> 11644 <description>Resync control for PT10</description> 11645 <bitOffset>10</bitOffset> 11646 <bitWidth>1</bitWidth> 11647 <access>read-write</access> 11648 </field> 11649 <field> 11650 <name>pt11</name> 11651 <description>Resync control for PT11</description> 11652 <bitOffset>11</bitOffset> 11653 <bitWidth>1</bitWidth> 11654 <access>read-write</access> 11655 </field> 11656 <field> 11657 <name>pt12</name> 11658 <description>Resync control for PT12</description> 11659 <bitOffset>12</bitOffset> 11660 <bitWidth>1</bitWidth> 11661 <access>read-write</access> 11662 </field> 11663 <field> 11664 <name>pt13</name> 11665 <description>Resync control for PT13</description> 11666 <bitOffset>13</bitOffset> 11667 <bitWidth>1</bitWidth> 11668 <access>read-write</access> 11669 </field> 11670 <field> 11671 <name>pt14</name> 11672 <description>Resync control for PT14</description> 11673 <bitOffset>14</bitOffset> 11674 <bitWidth>1</bitWidth> 11675 <access>read-write</access> 11676 </field> 11677 <field> 11678 <name>pt15</name> 11679 <description>Resync control for PT15</description> 11680 <bitOffset>15</bitOffset> 11681 <bitWidth>1</bitWidth> 11682 <access>read-write</access> 11683 </field> 11684 </fields> 11685 </register> 11686 <register> 11687 <name>STOP_INTFL</name> 11688 <description>Pulse Train Interrupt Flags</description> 11689 <addressOffset>0x0008</addressOffset> 11690 <access>read-write</access> 11691 <fields> 11692 <field> 11693 <name>pt0</name> 11694 <description>Pulse Train 0 Stopped Interrupt Flag</description> 11695 <bitOffset>0</bitOffset> 11696 <bitWidth>1</bitWidth> 11697 <access>read-write</access> 11698 </field> 11699 <field> 11700 <name>pt1</name> 11701 <description>Pulse Train 1 Stopped Interrupt Flag</description> 11702 <bitOffset>1</bitOffset> 11703 <bitWidth>1</bitWidth> 11704 <access>read-write</access> 11705 </field> 11706 <field> 11707 <name>pt2</name> 11708 <description>Pulse Train 2 Stopped Interrupt Flag</description> 11709 <bitOffset>2</bitOffset> 11710 <bitWidth>1</bitWidth> 11711 <access>read-write</access> 11712 </field> 11713 <field> 11714 <name>pt3</name> 11715 <description>Pulse Train 3 Stopped Interrupt Flag</description> 11716 <bitOffset>3</bitOffset> 11717 <bitWidth>1</bitWidth> 11718 <access>read-write</access> 11719 </field> 11720 <field> 11721 <name>pt4</name> 11722 <description>Pulse Train 4 Stopped Interrupt Flag</description> 11723 <bitOffset>4</bitOffset> 11724 <bitWidth>1</bitWidth> 11725 <access>read-write</access> 11726 </field> 11727 <field> 11728 <name>pt5</name> 11729 <description>Pulse Train 5 Stopped Interrupt Flag</description> 11730 <bitOffset>5</bitOffset> 11731 <bitWidth>1</bitWidth> 11732 <access>read-write</access> 11733 </field> 11734 <field> 11735 <name>pt6</name> 11736 <description>Pulse Train 6 Stopped Interrupt Flag</description> 11737 <bitOffset>6</bitOffset> 11738 <bitWidth>1</bitWidth> 11739 <access>read-write</access> 11740 </field> 11741 <field> 11742 <name>pt7</name> 11743 <description>Pulse Train 7 Stopped Interrupt Flag</description> 11744 <bitOffset>7</bitOffset> 11745 <bitWidth>1</bitWidth> 11746 <access>read-write</access> 11747 </field> 11748 <field> 11749 <name>pt8</name> 11750 <description>Pulse Train 8 Stopped Interrupt Flag</description> 11751 <bitOffset>8</bitOffset> 11752 <bitWidth>1</bitWidth> 11753 <access>read-write</access> 11754 </field> 11755 <field> 11756 <name>pt9</name> 11757 <description>Pulse Train 9 Stopped Interrupt Flag</description> 11758 <bitOffset>9</bitOffset> 11759 <bitWidth>1</bitWidth> 11760 <access>read-write</access> 11761 </field> 11762 <field> 11763 <name>pt10</name> 11764 <description>Pulse Train 10 Stopped Interrupt Flag</description> 11765 <bitOffset>10</bitOffset> 11766 <bitWidth>1</bitWidth> 11767 <access>read-write</access> 11768 </field> 11769 <field> 11770 <name>pt11</name> 11771 <description>Pulse Train 11 Stopped Interrupt Flag</description> 11772 <bitOffset>11</bitOffset> 11773 <bitWidth>1</bitWidth> 11774 <access>read-write</access> 11775 </field> 11776 <field> 11777 <name>pt12</name> 11778 <description>Pulse Train 12 Stopped Interrupt Flag</description> 11779 <bitOffset>12</bitOffset> 11780 <bitWidth>1</bitWidth> 11781 <access>read-write</access> 11782 </field> 11783 <field> 11784 <name>pt13</name> 11785 <description>Pulse Train 13 Stopped Interrupt Flag</description> 11786 <bitOffset>13</bitOffset> 11787 <bitWidth>1</bitWidth> 11788 <access>read-write</access> 11789 </field> 11790 <field> 11791 <name>pt14</name> 11792 <description>Pulse Train 14 Stopped Interrupt Flag</description> 11793 <bitOffset>14</bitOffset> 11794 <bitWidth>1</bitWidth> 11795 <access>read-write</access> 11796 </field> 11797 <field> 11798 <name>pt15</name> 11799 <description>Pulse Train 15 Stopped Interrupt Flag</description> 11800 <bitOffset>15</bitOffset> 11801 <bitWidth>1</bitWidth> 11802 <access>read-write</access> 11803 </field> 11804 </fields> 11805 </register> 11806 <register> 11807 <name>STOP_INTEN</name> 11808 <description>Pulse Train Interrupt Enable/Disable</description> 11809 <addressOffset>0x000C</addressOffset> 11810 <access>read-write</access> 11811 <fields> 11812 <field> 11813 <name>pt0</name> 11814 <description>Pulse Train 0 Stopped Interrupt Enable/Disable</description> 11815 <bitOffset>0</bitOffset> 11816 <bitWidth>1</bitWidth> 11817 <access>read-write</access> 11818 </field> 11819 <field> 11820 <name>pt1</name> 11821 <description>Pulse Train 1 Stopped Interrupt Enable/Disable</description> 11822 <bitOffset>1</bitOffset> 11823 <bitWidth>1</bitWidth> 11824 <access>read-write</access> 11825 </field> 11826 <field> 11827 <name>pt2</name> 11828 <description>Pulse Train 2 Stopped Interrupt Enable/Disable</description> 11829 <bitOffset>2</bitOffset> 11830 <bitWidth>1</bitWidth> 11831 <access>read-write</access> 11832 </field> 11833 <field> 11834 <name>pt3</name> 11835 <description>Pulse Train 3 Stopped Interrupt Enable/Disable</description> 11836 <bitOffset>3</bitOffset> 11837 <bitWidth>1</bitWidth> 11838 <access>read-write</access> 11839 </field> 11840 <field> 11841 <name>pt4</name> 11842 <description>Pulse Train 4 Stopped Interrupt Enable/Disable</description> 11843 <bitOffset>4</bitOffset> 11844 <bitWidth>1</bitWidth> 11845 <access>read-write</access> 11846 </field> 11847 <field> 11848 <name>pt5</name> 11849 <description>Pulse Train 5 Stopped Interrupt Enable/Disable</description> 11850 <bitOffset>5</bitOffset> 11851 <bitWidth>1</bitWidth> 11852 <access>read-write</access> 11853 </field> 11854 <field> 11855 <name>pt6</name> 11856 <description>Pulse Train 6 Stopped Interrupt Enable/Disable</description> 11857 <bitOffset>6</bitOffset> 11858 <bitWidth>1</bitWidth> 11859 <access>read-write</access> 11860 </field> 11861 <field> 11862 <name>pt7</name> 11863 <description>Pulse Train 7 Stopped Interrupt Enable/Disable</description> 11864 <bitOffset>7</bitOffset> 11865 <bitWidth>1</bitWidth> 11866 <access>read-write</access> 11867 </field> 11868 <field> 11869 <name>pt8</name> 11870 <description>Pulse Train 8 Stopped Interrupt Enable/Disable</description> 11871 <bitOffset>8</bitOffset> 11872 <bitWidth>1</bitWidth> 11873 <access>read-write</access> 11874 </field> 11875 <field> 11876 <name>pt9</name> 11877 <description>Pulse Train 9 Stopped Interrupt Enable/Disable</description> 11878 <bitOffset>9</bitOffset> 11879 <bitWidth>1</bitWidth> 11880 <access>read-write</access> 11881 </field> 11882 <field> 11883 <name>pt10</name> 11884 <description>Pulse Train 10 Stopped Interrupt Enable/Disable</description> 11885 <bitOffset>10</bitOffset> 11886 <bitWidth>1</bitWidth> 11887 <access>read-write</access> 11888 </field> 11889 <field> 11890 <name>pt11</name> 11891 <description>Pulse Train 11 Stopped Interrupt Enable/Disable</description> 11892 <bitOffset>11</bitOffset> 11893 <bitWidth>1</bitWidth> 11894 <access>read-write</access> 11895 </field> 11896 <field> 11897 <name>pt12</name> 11898 <description>Pulse Train 12 Stopped Interrupt Enable/Disable</description> 11899 <bitOffset>12</bitOffset> 11900 <bitWidth>1</bitWidth> 11901 <access>read-write</access> 11902 </field> 11903 <field> 11904 <name>pt13</name> 11905 <description>Pulse Train 13 Stopped Interrupt Enable/Disable</description> 11906 <bitOffset>13</bitOffset> 11907 <bitWidth>1</bitWidth> 11908 <access>read-write</access> 11909 </field> 11910 <field> 11911 <name>pt14</name> 11912 <description>Pulse Train 14 Stopped Interrupt Enable/Disable</description> 11913 <bitOffset>14</bitOffset> 11914 <bitWidth>1</bitWidth> 11915 <access>read-write</access> 11916 </field> 11917 <field> 11918 <name>pt15</name> 11919 <description>Pulse Train 15 Stopped Interrupt Enable/Disable</description> 11920 <bitOffset>15</bitOffset> 11921 <bitWidth>1</bitWidth> 11922 <access>read-write</access> 11923 </field> 11924 </fields> 11925 </register> 11926 <register> 11927 <name>SAFE_EN</name> 11928 <description>Pulse Train Global Safe Enable.</description> 11929 <addressOffset>0x0010</addressOffset> 11930 <access>write-only</access> 11931 <fields> 11932 <field> 11933 <name>PT0</name> 11934 <bitOffset>0</bitOffset> 11935 <bitWidth>1</bitWidth> 11936 <access>write-only</access> 11937 </field> 11938 <field> 11939 <name>PT1</name> 11940 <bitOffset>1</bitOffset> 11941 <bitWidth>1</bitWidth> 11942 <access>write-only</access> 11943 </field> 11944 <field> 11945 <name>PT2</name> 11946 <bitOffset>2</bitOffset> 11947 <bitWidth>1</bitWidth> 11948 <access>write-only</access> 11949 </field> 11950 <field> 11951 <name>PT3</name> 11952 <bitOffset>3</bitOffset> 11953 <bitWidth>1</bitWidth> 11954 <access>write-only</access> 11955 </field> 11956 <field> 11957 <name>PT4</name> 11958 <bitOffset>4</bitOffset> 11959 <bitWidth>1</bitWidth> 11960 <access>write-only</access> 11961 </field> 11962 <field> 11963 <name>PT5</name> 11964 <bitOffset>5</bitOffset> 11965 <bitWidth>1</bitWidth> 11966 <access>write-only</access> 11967 </field> 11968 <field> 11969 <name>PT6</name> 11970 <bitOffset>6</bitOffset> 11971 <bitWidth>1</bitWidth> 11972 <access>write-only</access> 11973 </field> 11974 <field> 11975 <name>PT7</name> 11976 <bitOffset>7</bitOffset> 11977 <bitWidth>1</bitWidth> 11978 <access>write-only</access> 11979 </field> 11980 <field> 11981 <name>PT8</name> 11982 <bitOffset>8</bitOffset> 11983 <bitWidth>1</bitWidth> 11984 <access>write-only</access> 11985 </field> 11986 <field> 11987 <name>PT9</name> 11988 <bitOffset>9</bitOffset> 11989 <bitWidth>1</bitWidth> 11990 <access>write-only</access> 11991 </field> 11992 <field> 11993 <name>PT10</name> 11994 <bitOffset>10</bitOffset> 11995 <bitWidth>1</bitWidth> 11996 <access>write-only</access> 11997 </field> 11998 <field> 11999 <name>PT11</name> 12000 <bitOffset>11</bitOffset> 12001 <bitWidth>1</bitWidth> 12002 <access>write-only</access> 12003 </field> 12004 <field> 12005 <name>PT12</name> 12006 <bitOffset>12</bitOffset> 12007 <bitWidth>1</bitWidth> 12008 <access>write-only</access> 12009 </field> 12010 <field> 12011 <name>PT13</name> 12012 <bitOffset>13</bitOffset> 12013 <bitWidth>1</bitWidth> 12014 <access>write-only</access> 12015 </field> 12016 <field> 12017 <name>PT14</name> 12018 <bitOffset>14</bitOffset> 12019 <bitWidth>1</bitWidth> 12020 <access>write-only</access> 12021 </field> 12022 <field> 12023 <name>PT15</name> 12024 <bitOffset>15</bitOffset> 12025 <bitWidth>1</bitWidth> 12026 <access>write-only</access> 12027 </field> 12028 </fields> 12029 </register> 12030 <register> 12031 <name>SAFE_DIS</name> 12032 <description>Pulse Train Global Safe Disable.</description> 12033 <addressOffset>0x0014</addressOffset> 12034 <access>write-only</access> 12035 <fields> 12036 <field> 12037 <name>PT0</name> 12038 <bitOffset>0</bitOffset> 12039 <bitWidth>1</bitWidth> 12040 <access>write-only</access> 12041 </field> 12042 <field> 12043 <name>PT1</name> 12044 <bitOffset>1</bitOffset> 12045 <bitWidth>1</bitWidth> 12046 <access>write-only</access> 12047 </field> 12048 <field> 12049 <name>PT2</name> 12050 <bitOffset>2</bitOffset> 12051 <bitWidth>1</bitWidth> 12052 <access>write-only</access> 12053 </field> 12054 <field> 12055 <name>PT3</name> 12056 <bitOffset>3</bitOffset> 12057 <bitWidth>1</bitWidth> 12058 <access>write-only</access> 12059 </field> 12060 <field> 12061 <name>PT4</name> 12062 <bitOffset>4</bitOffset> 12063 <bitWidth>1</bitWidth> 12064 <access>write-only</access> 12065 </field> 12066 <field> 12067 <name>PT5</name> 12068 <bitOffset>5</bitOffset> 12069 <bitWidth>1</bitWidth> 12070 <access>write-only</access> 12071 </field> 12072 <field> 12073 <name>PT6</name> 12074 <bitOffset>6</bitOffset> 12075 <bitWidth>1</bitWidth> 12076 <access>write-only</access> 12077 </field> 12078 <field> 12079 <name>PT7</name> 12080 <bitOffset>7</bitOffset> 12081 <bitWidth>1</bitWidth> 12082 <access>write-only</access> 12083 </field> 12084 <field> 12085 <name>PT8</name> 12086 <bitOffset>8</bitOffset> 12087 <bitWidth>1</bitWidth> 12088 <access>write-only</access> 12089 </field> 12090 <field> 12091 <name>PT9</name> 12092 <bitOffset>9</bitOffset> 12093 <bitWidth>1</bitWidth> 12094 <access>write-only</access> 12095 </field> 12096 <field> 12097 <name>PT10</name> 12098 <bitOffset>10</bitOffset> 12099 <bitWidth>1</bitWidth> 12100 <access>write-only</access> 12101 </field> 12102 <field> 12103 <name>PT11</name> 12104 <bitOffset>11</bitOffset> 12105 <bitWidth>1</bitWidth> 12106 <access>write-only</access> 12107 </field> 12108 <field> 12109 <name>PT12</name> 12110 <bitOffset>12</bitOffset> 12111 <bitWidth>1</bitWidth> 12112 <access>write-only</access> 12113 </field> 12114 <field> 12115 <name>PT13</name> 12116 <bitOffset>13</bitOffset> 12117 <bitWidth>1</bitWidth> 12118 <access>write-only</access> 12119 </field> 12120 <field> 12121 <name>PT14</name> 12122 <bitOffset>14</bitOffset> 12123 <bitWidth>1</bitWidth> 12124 <access>write-only</access> 12125 </field> 12126 <field> 12127 <name>PT15</name> 12128 <bitOffset>15</bitOffset> 12129 <bitWidth>1</bitWidth> 12130 <access>write-only</access> 12131 </field> 12132 </fields> 12133 </register> 12134 <register> 12135 <name>READY_INTFL</name> 12136 <description>Pulse Train Ready Interrupt Flags</description> 12137 <addressOffset>0x0018</addressOffset> 12138 <access>read-write</access> 12139 <fields> 12140 <field> 12141 <name>pt0</name> 12142 <description>Pulse Train 0 Ready Interrupt Flag</description> 12143 <bitOffset>0</bitOffset> 12144 <bitWidth>1</bitWidth> 12145 <access>read-write</access> 12146 </field> 12147 <field> 12148 <name>pt1</name> 12149 <description>Pulse Train 1 Ready Interrupt Flag</description> 12150 <bitOffset>1</bitOffset> 12151 <bitWidth>1</bitWidth> 12152 <access>read-write</access> 12153 </field> 12154 <field> 12155 <name>pt2</name> 12156 <description>Pulse Train 2 Ready Interrupt Flag</description> 12157 <bitOffset>2</bitOffset> 12158 <bitWidth>1</bitWidth> 12159 <access>read-write</access> 12160 </field> 12161 <field> 12162 <name>pt3</name> 12163 <description>Pulse Train 3 Ready Interrupt Flag</description> 12164 <bitOffset>3</bitOffset> 12165 <bitWidth>1</bitWidth> 12166 <access>read-write</access> 12167 </field> 12168 <field> 12169 <name>pt4</name> 12170 <description>Pulse Train 4 Ready Interrupt Flag</description> 12171 <bitOffset>4</bitOffset> 12172 <bitWidth>1</bitWidth> 12173 <access>read-write</access> 12174 </field> 12175 <field> 12176 <name>pt5</name> 12177 <description>Pulse Train 5 Ready Interrupt Flag</description> 12178 <bitOffset>5</bitOffset> 12179 <bitWidth>1</bitWidth> 12180 <access>read-write</access> 12181 </field> 12182 <field> 12183 <name>pt6</name> 12184 <description>Pulse Train 6 Ready Interrupt Flag</description> 12185 <bitOffset>6</bitOffset> 12186 <bitWidth>1</bitWidth> 12187 <access>read-write</access> 12188 </field> 12189 <field> 12190 <name>pt7</name> 12191 <description>Pulse Train 7 Ready Interrupt Flag</description> 12192 <bitOffset>7</bitOffset> 12193 <bitWidth>1</bitWidth> 12194 <access>read-write</access> 12195 </field> 12196 <field> 12197 <name>pt8</name> 12198 <description>Pulse Train 8 Ready Interrupt Flag</description> 12199 <bitOffset>8</bitOffset> 12200 <bitWidth>1</bitWidth> 12201 <access>read-write</access> 12202 </field> 12203 <field> 12204 <name>pt9</name> 12205 <description>Pulse Train 9 Ready Interrupt Flag</description> 12206 <bitOffset>9</bitOffset> 12207 <bitWidth>1</bitWidth> 12208 <access>read-write</access> 12209 </field> 12210 <field> 12211 <name>pt10</name> 12212 <description>Pulse Train 10 Ready Interrupt Flag</description> 12213 <bitOffset>10</bitOffset> 12214 <bitWidth>1</bitWidth> 12215 <access>read-write</access> 12216 </field> 12217 <field> 12218 <name>pt11</name> 12219 <description>Pulse Train 11 Ready Interrupt Flag</description> 12220 <bitOffset>11</bitOffset> 12221 <bitWidth>1</bitWidth> 12222 <access>read-write</access> 12223 </field> 12224 <field> 12225 <name>pt12</name> 12226 <description>Pulse Train 12 Ready Interrupt Flag</description> 12227 <bitOffset>12</bitOffset> 12228 <bitWidth>1</bitWidth> 12229 <access>read-write</access> 12230 </field> 12231 <field> 12232 <name>pt13</name> 12233 <description>Pulse Train 13 Ready Interrupt Flag</description> 12234 <bitOffset>13</bitOffset> 12235 <bitWidth>1</bitWidth> 12236 <access>read-write</access> 12237 </field> 12238 <field> 12239 <name>pt14</name> 12240 <description>Pulse Train 14 Ready Interrupt Flag</description> 12241 <bitOffset>14</bitOffset> 12242 <bitWidth>1</bitWidth> 12243 <access>read-write</access> 12244 </field> 12245 <field> 12246 <name>pt15</name> 12247 <description>Pulse Train 15 Ready Interrupt Flag</description> 12248 <bitOffset>15</bitOffset> 12249 <bitWidth>1</bitWidth> 12250 <access>read-write</access> 12251 </field> 12252 </fields> 12253 </register> 12254 <register> 12255 <name>READY_INTEN</name> 12256 <description>Pulse Train Ready Interrupt Enable/Disable</description> 12257 <addressOffset>0x001C</addressOffset> 12258 <access>read-write</access> 12259 <fields> 12260 <field> 12261 <name>pt0</name> 12262 <description>Pulse Train 0 Ready Interrupt Enable/Disable</description> 12263 <bitOffset>0</bitOffset> 12264 <bitWidth>1</bitWidth> 12265 <access>read-write</access> 12266 </field> 12267 <field> 12268 <name>pt1</name> 12269 <description>Pulse Train 1 Ready Interrupt Enable/Disable</description> 12270 <bitOffset>1</bitOffset> 12271 <bitWidth>1</bitWidth> 12272 <access>read-write</access> 12273 </field> 12274 <field> 12275 <name>pt2</name> 12276 <description>Pulse Train 2 Ready Interrupt Enable/Disable</description> 12277 <bitOffset>2</bitOffset> 12278 <bitWidth>1</bitWidth> 12279 <access>read-write</access> 12280 </field> 12281 <field> 12282 <name>pt3</name> 12283 <description>Pulse Train 3 Ready Interrupt Enable/Disable</description> 12284 <bitOffset>3</bitOffset> 12285 <bitWidth>1</bitWidth> 12286 <access>read-write</access> 12287 </field> 12288 <field> 12289 <name>pt4</name> 12290 <description>Pulse Train 4 Ready Interrupt Enable/Disable</description> 12291 <bitOffset>4</bitOffset> 12292 <bitWidth>1</bitWidth> 12293 <access>read-write</access> 12294 </field> 12295 <field> 12296 <name>pt5</name> 12297 <description>Pulse Train 5 Ready Interrupt Enable/Disable</description> 12298 <bitOffset>5</bitOffset> 12299 <bitWidth>1</bitWidth> 12300 <access>read-write</access> 12301 </field> 12302 <field> 12303 <name>pt6</name> 12304 <description>Pulse Train 6 Ready Interrupt Enable/Disable</description> 12305 <bitOffset>6</bitOffset> 12306 <bitWidth>1</bitWidth> 12307 <access>read-write</access> 12308 </field> 12309 <field> 12310 <name>pt7</name> 12311 <description>Pulse Train 7 Ready Interrupt Enable/Disable</description> 12312 <bitOffset>7</bitOffset> 12313 <bitWidth>1</bitWidth> 12314 <access>read-write</access> 12315 </field> 12316 <field> 12317 <name>pt8</name> 12318 <description>Pulse Train 8 Ready Interrupt Enable/Disable</description> 12319 <bitOffset>8</bitOffset> 12320 <bitWidth>1</bitWidth> 12321 <access>read-write</access> 12322 </field> 12323 <field> 12324 <name>pt9</name> 12325 <description>Pulse Train 9 Ready Interrupt Enable/Disable</description> 12326 <bitOffset>9</bitOffset> 12327 <bitWidth>1</bitWidth> 12328 <access>read-write</access> 12329 </field> 12330 <field> 12331 <name>pt10</name> 12332 <description>Pulse Train 10 Ready Interrupt Enable/Disable</description> 12333 <bitOffset>10</bitOffset> 12334 <bitWidth>1</bitWidth> 12335 <access>read-write</access> 12336 </field> 12337 <field> 12338 <name>pt11</name> 12339 <description>Pulse Train 11 Ready Interrupt Enable/Disable</description> 12340 <bitOffset>11</bitOffset> 12341 <bitWidth>1</bitWidth> 12342 <access>read-write</access> 12343 </field> 12344 <field> 12345 <name>pt12</name> 12346 <description>Pulse Train 12 Ready Interrupt Enable/Disable</description> 12347 <bitOffset>12</bitOffset> 12348 <bitWidth>1</bitWidth> 12349 <access>read-write</access> 12350 </field> 12351 <field> 12352 <name>pt13</name> 12353 <description>Pulse Train 13 Ready Interrupt Enable/Disable</description> 12354 <bitOffset>13</bitOffset> 12355 <bitWidth>1</bitWidth> 12356 <access>read-write</access> 12357 </field> 12358 <field> 12359 <name>pt14</name> 12360 <description>Pulse Train 14 Ready Interrupt Enable/Disable</description> 12361 <bitOffset>14</bitOffset> 12362 <bitWidth>1</bitWidth> 12363 <access>read-write</access> 12364 </field> 12365 <field> 12366 <name>pt15</name> 12367 <description>Pulse Train 15 Ready Interrupt Enable/Disable</description> 12368 <bitOffset>15</bitOffset> 12369 <bitWidth>1</bitWidth> 12370 <access>read-write</access> 12371 </field> 12372 </fields> 12373 </register> 12374 </registers> 12375 </peripheral> 12376<!--PTG Pulse Train Generation--> 12377 <peripheral> 12378 <name>PWRSEQ</name> 12379 <description>Power Sequencer / Low Power Control Register.</description> 12380 <baseAddress>0x40006800</baseAddress> 12381 <addressBlock> 12382 <offset>0x00</offset> 12383 <size>0x400</size> 12384 <usage>registers</usage> 12385 </addressBlock> 12386 <registers> 12387 <register> 12388 <name>LPCN</name> 12389 <description>Low Power Control Register.</description> 12390 <addressOffset>0x00</addressOffset> 12391 <fields> 12392 <field> 12393 <name>RAMRET0</name> 12394 <description>System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description> 12395 <bitOffset>0</bitOffset> 12396 <bitWidth>1</bitWidth> 12397 <enumeratedValues> 12398 <enumeratedValue> 12399 <name>dis</name> 12400 <description>Disable Ram Retention.</description> 12401 <value>0</value> 12402 </enumeratedValue> 12403 <enumeratedValue> 12404 <name>en</name> 12405 <description>Enable System RAM 0 retention.</description> 12406 <value>1</value> 12407 </enumeratedValue> 12408 </enumeratedValues> 12409 </field> 12410 <field> 12411 <name>RAMRET1</name> 12412 <description>System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description> 12413 <bitOffset>1</bitOffset> 12414 <bitWidth>1</bitWidth> 12415 <enumeratedValues> 12416 <enumeratedValue> 12417 <name>dis</name> 12418 <description>Disable Ram Retention.</description> 12419 <value>0</value> 12420 </enumeratedValue> 12421 <enumeratedValue> 12422 <name>en</name> 12423 <description>Enable System RAM 1 retention.</description> 12424 <value>1</value> 12425 </enumeratedValue> 12426 </enumeratedValues> 12427 </field> 12428 <field> 12429 <name>RAMRET2</name> 12430 <description>System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description> 12431 <bitOffset>2</bitOffset> 12432 <bitWidth>1</bitWidth> 12433 <enumeratedValues> 12434 <enumeratedValue> 12435 <name>dis</name> 12436 <description>Disable Ram Retention.</description> 12437 <value>0</value> 12438 </enumeratedValue> 12439 <enumeratedValue> 12440 <name>en</name> 12441 <description>Enable System RAM 2 retention.</description> 12442 <value>1</value> 12443 </enumeratedValue> 12444 </enumeratedValues> 12445 </field> 12446 <field> 12447 <name>RAMRET3</name> 12448 <description>System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description> 12449 <bitOffset>3</bitOffset> 12450 <bitWidth>1</bitWidth> 12451 <enumeratedValues> 12452 <enumeratedValue> 12453 <name>dis</name> 12454 <description>Disable Ram Retention.</description> 12455 <value>0</value> 12456 </enumeratedValue> 12457 <enumeratedValue> 12458 <name>en</name> 12459 <description>Enable System RAM 3 retention.</description> 12460 <value>1</value> 12461 </enumeratedValue> 12462 </enumeratedValues> 12463 </field> 12464 <field> 12465 <name>RAMRET4</name> 12466 <description>System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description> 12467 <bitOffset>4</bitOffset> 12468 <bitWidth>1</bitWidth> 12469 <enumeratedValues> 12470 <enumeratedValue> 12471 <name>dis</name> 12472 <description>Disable Ram Retention.</description> 12473 <value>0</value> 12474 </enumeratedValue> 12475 <enumeratedValue> 12476 <name>en</name> 12477 <description>Enable System RAM 3 retention.</description> 12478 <value>1</value> 12479 </enumeratedValue> 12480 </enumeratedValues> 12481 </field> 12482 <field> 12483 <name>RAMRET5</name> 12484 <description>System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description> 12485 <bitOffset>5</bitOffset> 12486 <bitWidth>1</bitWidth> 12487 <enumeratedValues> 12488 <enumeratedValue> 12489 <name>dis</name> 12490 <description>Disable Ram Retention.</description> 12491 <value>0</value> 12492 </enumeratedValue> 12493 <enumeratedValue> 12494 <name>en</name> 12495 <description>Enable System RAM 3 retention.</description> 12496 <value>1</value> 12497 </enumeratedValue> 12498 </enumeratedValues> 12499 </field> 12500 <field> 12501 <name>RAMRET6</name> 12502 <description>System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description> 12503 <bitOffset>6</bitOffset> 12504 <bitWidth>1</bitWidth> 12505 <enumeratedValues> 12506 <enumeratedValue> 12507 <name>dis</name> 12508 <description>Disable Ram Retention.</description> 12509 <value>0</value> 12510 </enumeratedValue> 12511 <enumeratedValue> 12512 <name>en</name> 12513 <description>Enable System RAM 3 retention.</description> 12514 <value>1</value> 12515 </enumeratedValue> 12516 </enumeratedValues> 12517 </field> 12518 <field> 12519 <name>RAMRET8</name> 12520 <description>System RAM retention in BACKUP mode. RAM7 is retained if any of RAM0 to RAM6 is retained.</description> 12521 <bitOffset>7</bitOffset> 12522 <bitWidth>1</bitWidth> 12523 <enumeratedValues> 12524 <enumeratedValue> 12525 <name>dis</name> 12526 <description>Disable Ram Retention.</description> 12527 <value>0</value> 12528 </enumeratedValue> 12529 <enumeratedValue> 12530 <name>en</name> 12531 <description>Enable System RAM 3 retention.</description> 12532 <value>1</value> 12533 </enumeratedValue> 12534 </enumeratedValues> 12535 </field> 12536 <field> 12537 <name>ISOCLK_SELECT</name> 12538 <description>0 = PCLK 1= ISO CLK use for RISV in Low power mode </description> 12539 <bitOffset>8</bitOffset> 12540 <bitWidth>1</bitWidth> 12541 </field> 12542 <field> 12543 <name>FAST_ENTRY_DIS</name> 12544 <description>Fast Low Power mode entry disable</description> 12545 <bitOffset>9</bitOffset> 12546 <bitWidth>1</bitWidth> 12547 </field> 12548 <field> 12549 <name>BGOFF</name> 12550 <description>Bandgap OFF. This controls the System Bandgap in DeepSleep mode.</description> 12551 <bitOffset>11</bitOffset> 12552 <bitWidth>1</bitWidth> 12553 <enumeratedValues> 12554 <enumeratedValue> 12555 <name>on</name> 12556 <description>Bandgap is always ON.</description> 12557 <value>0</value> 12558 </enumeratedValue> 12559 <enumeratedValue> 12560 <name>off</name> 12561 <description>Bandgap is OFF in DeepSleep mode (default).</description> 12562 <value>1</value> 12563 </enumeratedValue> 12564 </enumeratedValues> 12565 </field> 12566 <field> 12567 <name>WKRST</name> 12568 <description>Reset wakeup status registers</description> 12569 <bitOffset>31</bitOffset> 12570 <bitWidth>1</bitWidth> 12571 </field> 12572 </fields> 12573 </register> 12574 <register> 12575 <name>LPWKST0</name> 12576 <description>Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO0.</description> 12577 <addressOffset>0x04</addressOffset> 12578 <fields> 12579 <field> 12580 <name>WAKEST</name> 12581 <description>Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode.</description> 12582 <bitOffset>0</bitOffset> 12583 <bitWidth>1</bitWidth> 12584 </field> 12585 </fields> 12586 </register> 12587 <register> 12588 <name>LPWKEN0</name> 12589 <description>Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0.</description> 12590 <addressOffset>0x08</addressOffset> 12591 <fields> 12592 <field> 12593 <name>WAKEEN</name> 12594 <description>Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register.</description> 12595 <bitOffset>0</bitOffset> 12596 <bitWidth>31</bitWidth> 12597 </field> 12598 </fields> 12599 </register> 12600 <register> 12601 <name>LPWKST1</name> 12602 <description>Low Power I/O Wakeup Status Register 1. This register indicates the low power wakeup status for GPIO1.</description> 12603 <addressOffset>0x0C</addressOffset> 12604 <fields> 12605 <field> 12606 <name>WAKEST</name> 12607 <description>Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode.</description> 12608 <bitOffset>0</bitOffset> 12609 <bitWidth>10</bitWidth> 12610 </field> 12611 </fields> 12612 </register> 12613 <register> 12614 <name>LPWKEN1</name> 12615 <description>Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup functionality for GPIO1.</description> 12616 <addressOffset>0x10</addressOffset> 12617 <fields> 12618 <field> 12619 <name>WAKEEN</name> 12620 <description>Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register.</description> 12621 <bitOffset>0</bitOffset> 12622 <bitWidth>10</bitWidth> 12623 </field> 12624 </fields> 12625 </register> 12626 <register> 12627 <name>LPWKST2</name> 12628 <description>Low Power I/O Wakeup Status Register 2. This register indicates the low power wakeup status for GPIO2.</description> 12629 <addressOffset>0x14</addressOffset> 12630 <fields> 12631 <field> 12632 <name>WAKEST</name> 12633 <description>Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode.</description> 12634 <bitOffset>0</bitOffset> 12635 <bitWidth>8</bitWidth> 12636 </field> 12637 </fields> 12638 </register> 12639 <register> 12640 <name>LPWKEN2</name> 12641 <description>Low Power I/O Wakeup Enable Register 2. This register enables low power wakeup functionality for GPIO2.</description> 12642 <addressOffset>0x18</addressOffset> 12643 <fields> 12644 <field> 12645 <name>WAKEEN</name> 12646 <description>Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register.</description> 12647 <bitOffset>0</bitOffset> 12648 <bitWidth>8</bitWidth> 12649 </field> 12650 </fields> 12651 </register> 12652 <register> 12653 <name>LPWKST3</name> 12654 <description>Low Power I/O Wakeup Status Register 3. This register indicates the low power wakeup status for GPIO3.</description> 12655 <addressOffset>0x1C</addressOffset> 12656 <fields> 12657 <field> 12658 <name>WAKEST</name> 12659 <description>Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode.</description> 12660 <bitOffset>0</bitOffset> 12661 <bitWidth>2</bitWidth> 12662 </field> 12663 </fields> 12664 </register> 12665 <register> 12666 <name>LPWKEN3</name> 12667 <description>Low Power I/O Wakeup Enable Register 3. This register enables low power wakeup functionality for GPIO3.</description> 12668 <addressOffset>0x20</addressOffset> 12669 <fields> 12670 <field> 12671 <name>WAKEEN</name> 12672 <description>Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register.</description> 12673 <bitOffset>0</bitOffset> 12674 <bitWidth>2</bitWidth> 12675 </field> 12676 </fields> 12677 </register> 12678 <register> 12679 <name>LPWKST4</name> 12680 <description>Low Power I/O Wakeup Status Register 4. This register indicates the low power wakeup status for GPIO4.</description> 12681 <addressOffset>0x24</addressOffset> 12682 <fields> 12683 <field> 12684 <name>WAKEST</name> 12685 <description>Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode.</description> 12686 <bitOffset>0</bitOffset> 12687 <bitWidth>2</bitWidth> 12688 </field> 12689 </fields> 12690 </register> 12691 <register> 12692 <name>LPWKEN4</name> 12693 <description>Low Power I/O Wakeup Enable Register 4. This register enables low power wakeup functionality for GPIO4.</description> 12694 <addressOffset>0x28</addressOffset> 12695 <fields> 12696 <field> 12697 <name>WAKEEN</name> 12698 <description>Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register.</description> 12699 <bitOffset>0</bitOffset> 12700 <bitWidth>2</bitWidth> 12701 </field> 12702 </fields> 12703 </register> 12704 <register> 12705 <name>LPPWST</name> 12706 <description>Low Power Peripheral Wakeup Status Register.</description> 12707 <addressOffset>0x30</addressOffset> 12708 <fields> 12709 <field> 12710 <name>AINCOMP0</name> 12711 <description>Analog Input Comparator Wakeup Flag.</description> 12712 <bitOffset>4</bitOffset> 12713 <bitWidth>1</bitWidth> 12714 </field> 12715 <field> 12716 <name>BACKUP</name> 12717 <description>Backup Mode Wakeup Flag.</description> 12718 <bitOffset>16</bitOffset> 12719 <bitWidth>1</bitWidth> 12720 </field> 12721 <field> 12722 <name>RESET</name> 12723 <description>Reset Detected Wakeup Flag.</description> 12724 <bitOffset>17</bitOffset> 12725 <bitWidth>1</bitWidth> 12726 </field> 12727 </fields> 12728 </register> 12729 <register> 12730 <name>LPPWEN</name> 12731 <description>Low Power Peripheral Wakeup Enable Register.</description> 12732 <addressOffset>0x34</addressOffset> 12733 <fields> 12734 <field> 12735 <name>USBLS</name> 12736 <description> USB UTMI Linestate Detect Wakeup Enable. These bits allow wakeup from the corresponding USB linestate 12737signal(s) on transition(s) from low to high or high to low when PM.USBWKEN is set.</description> 12738 <bitOffset>0</bitOffset> 12739 <bitWidth>2</bitWidth> 12740 </field> 12741 <field> 12742 <name>USBVBUS</name> 12743 <description> USB VBUS Detect Wakeup Enable. This bit allows wakeup from the USB power supply on or off status.</description> 12744 <bitOffset>2</bitOffset> 12745 <bitWidth>1</bitWidth> 12746 </field> 12747 <field> 12748 <name>AINCOMP0</name> 12749 <description> AINCOMP0 Wakeup Enable. This bit allows wakeup from the AINCOMP0.</description> 12750 <bitOffset>4</bitOffset> 12751 <bitWidth>1</bitWidth> 12752 </field> 12753 <field> 12754 <name>WDT0</name> 12755 <description> WDT0 Wakeup Enable. This bit allows wakeup from the WDT0.</description> 12756 <bitOffset>8</bitOffset> 12757 <bitWidth>1</bitWidth> 12758 </field> 12759 <field> 12760 <name>WDT1</name> 12761 <description> WDT1 Wakeup Enable. This bit allows wakeup from the WDT1.</description> 12762 <bitOffset>9</bitOffset> 12763 <bitWidth>1</bitWidth> 12764 </field> 12765 <field> 12766 <name>CPU1</name> 12767 <description> CPU1 Wakeup Enable. This bit allows wakeup from the CPU1.</description> 12768 <bitOffset>10</bitOffset> 12769 <bitWidth>1</bitWidth> 12770 </field> 12771 <field> 12772 <name>TMR0</name> 12773 <description> TMR0 Wakeup Enable. This bit allows wakeup from the TMR0.</description> 12774 <bitOffset>11</bitOffset> 12775 <bitWidth>1</bitWidth> 12776 </field> 12777 <field> 12778 <name>TMR1</name> 12779 <description> TMR1 Wakeup Enable. This bit allows wakeup from the TMR1.</description> 12780 <bitOffset>12</bitOffset> 12781 <bitWidth>1</bitWidth> 12782 </field> 12783 <field> 12784 <name>TMR2</name> 12785 <description> TMR2 Wakeup Enable. This bit allows wakeup from the TMR2.</description> 12786 <bitOffset>13</bitOffset> 12787 <bitWidth>1</bitWidth> 12788 </field> 12789 <field> 12790 <name>TMR3</name> 12791 <description> TMR3 Wakeup Enable. This bit allows wakeup from the TMR3.</description> 12792 <bitOffset>14</bitOffset> 12793 <bitWidth>1</bitWidth> 12794 </field> 12795 <field> 12796 <name>TMR4</name> 12797 <description> TMR4 Wakeup Enable. This bit allows wakeup from the TMR4.</description> 12798 <bitOffset>15</bitOffset> 12799 <bitWidth>1</bitWidth> 12800 </field> 12801 <field> 12802 <name>TMR5</name> 12803 <description> TMR5 Wakeup Enable. This bit allows wakeup from the TMR5.</description> 12804 <bitOffset>16</bitOffset> 12805 <bitWidth>1</bitWidth> 12806 </field> 12807 <field> 12808 <name>UART0</name> 12809 <description> UART0 Wakeup Enable. This bit allows wakeup from the UART0.</description> 12810 <bitOffset>17</bitOffset> 12811 <bitWidth>1</bitWidth> 12812 </field> 12813 <field> 12814 <name>UART1</name> 12815 <description> UART1 Wakeup Enable. This bit allows wakeup from the UART1.</description> 12816 <bitOffset>18</bitOffset> 12817 <bitWidth>1</bitWidth> 12818 </field> 12819 <field> 12820 <name>UART2</name> 12821 <description> UART2 Wakeup Enable. This bit allows wakeup from the UART2.</description> 12822 <bitOffset>19</bitOffset> 12823 <bitWidth>1</bitWidth> 12824 </field> 12825 <field> 12826 <name>UART3</name> 12827 <description> UART3 Wakeup Enable. This bit allows wakeup from the UART3.</description> 12828 <bitOffset>20</bitOffset> 12829 <bitWidth>1</bitWidth> 12830 </field> 12831 <field> 12832 <name>I2C0</name> 12833 <description> I2C0 Wakeup Enable. This bit allows wakeup from the I2C0.</description> 12834 <bitOffset>21</bitOffset> 12835 <bitWidth>1</bitWidth> 12836 </field> 12837 <field> 12838 <name>I2C1</name> 12839 <description> I2C1 Wakeup Enable. This bit allows wakeup from the I2C1.</description> 12840 <bitOffset>22</bitOffset> 12841 <bitWidth>1</bitWidth> 12842 </field> 12843 <field> 12844 <name>I2C2</name> 12845 <description> I2C2 Wakeup Enable. This bit allows wakeup from the I2C2.</description> 12846 <bitOffset>23</bitOffset> 12847 <bitWidth>1</bitWidth> 12848 </field> 12849 <field> 12850 <name>I2S</name> 12851 <description> I2S Wakeup Enable. This bit allows wakeup from the I2S.</description> 12852 <bitOffset>24</bitOffset> 12853 <bitWidth>1</bitWidth> 12854 </field> 12855 <field> 12856 <name>SPI0</name> 12857 <description> SPI0 Wakeup Enable. This bit allows wakeup from the SPI0.</description> 12858 <bitOffset>25</bitOffset> 12859 <bitWidth>1</bitWidth> 12860 </field> 12861 <field> 12862 <name>LPCMP</name> 12863 <description> LPCMP Wakeup Enable. This bit allows wakeup from the LPCMP.</description> 12864 <bitOffset>26</bitOffset> 12865 <bitWidth>1</bitWidth> 12866 </field> 12867 <field> 12868 <name>BTLE</name> 12869 <description>BTLE Wakeup Enable. This bit allows wakeup from the BTLE.</description> 12870 <bitOffset>27</bitOffset> 12871 <bitWidth>1</bitWidth> 12872 </field> 12873 <field> 12874 <name>SPI1</name> 12875 <description> SPI1 Wakeup Enable. This bit allows wakeup from the SPI1.</description> 12876 <bitOffset>28</bitOffset> 12877 <bitWidth>1</bitWidth> 12878 </field> 12879 <field> 12880 <name>SPI2</name> 12881 <description> SPI2 Wakeup Enable. This bit allows wakeup from the SPI2.</description> 12882 <bitOffset>29</bitOffset> 12883 <bitWidth>1</bitWidth> 12884 </field> 12885 <field> 12886 <name>CAN0</name> 12887 <description>CAN0 Wakeup Enable. This bit allows wakeup from the CAN0.</description> 12888 <bitOffset>30</bitOffset> 12889 <bitWidth>1</bitWidth> 12890 </field> 12891 <field> 12892 <name>CAN1</name> 12893 <description>CAN1 Wakeup Enable. This bit allows wakeup from the CAN1.</description> 12894 <bitOffset>31</bitOffset> 12895 <bitWidth>1</bitWidth> 12896 </field> 12897 </fields> 12898 </register> 12899 <register> 12900 <name>GP0</name> 12901 <description>General Purpose Register 0</description> 12902 <addressOffset>0x48</addressOffset> 12903 </register> 12904 <register> 12905 <name>GP1</name> 12906 <description>General Purpose Register 1</description> 12907 <addressOffset>0x4C</addressOffset> 12908 </register> 12909 </registers> 12910 </peripheral> 12911<!--PWRSEQ Power Sequencer / Low Power Control Register.--> 12912 <peripheral> 12913 <name>RTC</name> 12914 <description>Real Time Clock and Alarm.</description> 12915 <baseAddress>0x40006000</baseAddress> 12916 <addressBlock> 12917 <offset>0x00</offset> 12918 <size>0x400</size> 12919 <usage>registers</usage> 12920 </addressBlock> 12921 <interrupt> 12922 <name>RTC</name> 12923 <description>RTC interrupt.</description> 12924 <value>3</value> 12925 </interrupt> 12926 <registers> 12927 <register> 12928 <name>SEC</name> 12929 <description>RTC Second Counter. This register contains the 32-bit second counter.</description> 12930 <addressOffset>0x00</addressOffset> 12931 <resetMask>0x00000000</resetMask> 12932 <fields> 12933 <field> 12934 <name>SEC</name> 12935 <description>Seconds Counter.</description> 12936 <bitOffset>0</bitOffset> 12937 <bitWidth>32</bitWidth> 12938 </field> 12939 </fields> 12940 </register> 12941 <register> 12942 <name>SSEC</name> 12943 <description>RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented when this register rolls over from 0xFF to 0x00.</description> 12944 <addressOffset>0x04</addressOffset> 12945 <resetMask>0x00000000</resetMask> 12946 <fields> 12947 <field> 12948 <name>SSEC</name> 12949 <description>Sub-Seconds Counter (12-bit).</description> 12950 <bitOffset>0</bitOffset> 12951 <bitWidth>12</bitWidth> 12952 </field> 12953 </fields> 12954 </register> 12955 <register> 12956 <name>TODA</name> 12957 <description>Time-of-day Alarm.</description> 12958 <addressOffset>0x08</addressOffset> 12959 <resetMask>0x00000000</resetMask> 12960 <fields> 12961 <field> 12962 <name>TOD_ALARM</name> 12963 <description>Time-of-day Alarm.</description> 12964 <bitOffset>0</bitOffset> 12965 <bitWidth>20</bitWidth> 12966 </field> 12967 </fields> 12968 </register> 12969 <register> 12970 <name>SSECA</name> 12971 <description>RTC sub-second alarm. This register contains the reload value for the sub-second alarm.</description> 12972 <addressOffset>0x0C</addressOffset> 12973 <resetMask>0x00000000</resetMask> 12974 <fields> 12975 <field> 12976 <name>SSEC_ALARM</name> 12977 <description>This register contains the reload value for the sub-second alarm.</description> 12978 <bitOffset>0</bitOffset> 12979 <bitWidth>32</bitWidth> 12980 </field> 12981 </fields> 12982 </register> 12983 <register> 12984 <name>CTRL</name> 12985 <description>RTC Control Register.</description> 12986 <addressOffset>0x10</addressOffset> 12987 <resetValue>0x00000008</resetValue> 12988 <resetMask>0xFFFFFF38</resetMask> 12989 <fields> 12990 <field> 12991 <name>EN</name> 12992 <description>Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0.</description> 12993 <bitOffset>0</bitOffset> 12994 <bitWidth>1</bitWidth> 12995 <enumeratedValues> 12996 <enumeratedValue> 12997 <name>dis</name> 12998 <description>Disable.</description> 12999 <value>0</value> 13000 </enumeratedValue> 13001 <enumeratedValue> 13002 <name>en</name> 13003 <description>Enable.</description> 13004 <value>1</value> 13005 </enumeratedValue> 13006 </enumeratedValues> 13007 </field> 13008 <field> 13009 <name>TOD_ALARM_IE</name> 13010 <description>Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0.</description> 13011 <bitOffset>1</bitOffset> 13012 <bitWidth>1</bitWidth> 13013 <enumeratedValues> 13014 <enumeratedValue> 13015 <name>dis</name> 13016 <description>Disable.</description> 13017 <value>0</value> 13018 </enumeratedValue> 13019 <enumeratedValue> 13020 <name>en</name> 13021 <description>Enable.</description> 13022 <value>1</value> 13023 </enumeratedValue> 13024 </enumeratedValues> 13025 </field> 13026 <field> 13027 <name>SSEC_ALARM_IE</name> 13028 <description>Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0.</description> 13029 <bitOffset>2</bitOffset> 13030 <bitWidth>1</bitWidth> 13031 <enumeratedValues> 13032 <enumeratedValue> 13033 <name>dis</name> 13034 <description>Disable.</description> 13035 <value>0</value> 13036 </enumeratedValue> 13037 <enumeratedValue> 13038 <name>en</name> 13039 <description>Enable.</description> 13040 <value>1</value> 13041 </enumeratedValue> 13042 </enumeratedValues> 13043 </field> 13044 <field> 13045 <name>BUSY</name> 13046 <description>RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware.</description> 13047 <bitOffset>3</bitOffset> 13048 <bitWidth>1</bitWidth> 13049 <access>read-only</access> 13050 <enumeratedValues> 13051 <enumeratedValue> 13052 <name>idle</name> 13053 <description>Idle.</description> 13054 <value>0</value> 13055 </enumeratedValue> 13056 <enumeratedValue> 13057 <name>busy</name> 13058 <description>Busy.</description> 13059 <value>1</value> 13060 </enumeratedValue> 13061 </enumeratedValues> 13062 </field> 13063 <field> 13064 <name>RDY</name> 13065 <description>RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register.</description> 13066 <bitOffset>4</bitOffset> 13067 <bitWidth>1</bitWidth> 13068 <enumeratedValues> 13069 <enumeratedValue> 13070 <name>busy</name> 13071 <description>Register has not updated.</description> 13072 <value>0</value> 13073 </enumeratedValue> 13074 <enumeratedValue> 13075 <name>ready</name> 13076 <description>Ready.</description> 13077 <value>1</value> 13078 </enumeratedValue> 13079 </enumeratedValues> 13080 </field> 13081 <field> 13082 <name>RDY_IE</name> 13083 <description>RTC Ready Interrupt Enable.</description> 13084 <bitOffset>5</bitOffset> 13085 <bitWidth>1</bitWidth> 13086 <enumeratedValues> 13087 <enumeratedValue> 13088 <name>dis</name> 13089 <description>Disable.</description> 13090 <value>0</value> 13091 </enumeratedValue> 13092 <enumeratedValue> 13093 <name>en</name> 13094 <description>Enable.</description> 13095 <value>1</value> 13096 </enumeratedValue> 13097 </enumeratedValues> 13098 </field> 13099 <field> 13100 <name>TOD_ALARM</name> 13101 <description>Time-of-Day Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor.</description> 13102 <bitOffset>6</bitOffset> 13103 <bitWidth>1</bitWidth> 13104 <access>read-only</access> 13105 <enumeratedValues> 13106 <enumeratedValue> 13107 <name>inactive</name> 13108 <description>Not active</description> 13109 <value>0</value> 13110 </enumeratedValue> 13111 <enumeratedValue> 13112 <name>Pending</name> 13113 <description>Active</description> 13114 <value>1</value> 13115 </enumeratedValue> 13116 </enumeratedValues> 13117 </field> 13118 <field> 13119 <name>SSEC_ALARM</name> 13120 <description>Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor.</description> 13121 <bitOffset>7</bitOffset> 13122 <bitWidth>1</bitWidth> 13123 <access>read-only</access> 13124 <enumeratedValues> 13125 <enumeratedValue> 13126 <name>inactive</name> 13127 <description>Not active</description> 13128 <value>0</value> 13129 </enumeratedValue> 13130 <enumeratedValue> 13131 <name>Pending</name> 13132 <description>Active</description> 13133 <value>1</value> 13134 </enumeratedValue> 13135 </enumeratedValues> 13136 </field> 13137 <field> 13138 <name>SQW_EN</name> 13139 <description>Square Wave Output Enable.</description> 13140 <bitOffset>8</bitOffset> 13141 <bitWidth>1</bitWidth> 13142 <enumeratedValues> 13143 <enumeratedValue> 13144 <name>inactive</name> 13145 <description>Not active</description> 13146 <value>0</value> 13147 </enumeratedValue> 13148 <enumeratedValue> 13149 <name>Pending</name> 13150 <description>Active</description> 13151 <value>1</value> 13152 </enumeratedValue> 13153 </enumeratedValues> 13154 </field> 13155 <field> 13156 <name>SQW_SEL</name> 13157 <description>Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin.</description> 13158 <bitOffset>9</bitOffset> 13159 <bitWidth>2</bitWidth> 13160 <enumeratedValues> 13161 <enumeratedValue> 13162 <name>freq1Hz</name> 13163 <description>1 Hz (Compensated).</description> 13164 <value>0</value> 13165 </enumeratedValue> 13166 <enumeratedValue> 13167 <name>freq512Hz</name> 13168 <description>512 Hz (Compensated).</description> 13169 <value>1</value> 13170 </enumeratedValue> 13171 <enumeratedValue> 13172 <name>freq4KHz</name> 13173 <description>4 KHz.</description> 13174 <value>2</value> 13175 </enumeratedValue> 13176 <enumeratedValue> 13177 <name>clkDiv8</name> 13178 <description>RTC Input Clock / 8.</description> 13179 <value>3</value> 13180 </enumeratedValue> 13181 </enumeratedValues> 13182 </field> 13183 <field> 13184 <name>RD_EN</name> 13185 <description>Asynchronous Counter Read Enable.</description> 13186 <bitOffset>14</bitOffset> 13187 <bitWidth>1</bitWidth> 13188 </field> 13189 <field> 13190 <name>WR_EN</name> 13191 <description>Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits.</description> 13192 <bitOffset>15</bitOffset> 13193 <bitWidth>1</bitWidth> 13194 <enumeratedValues> 13195 <enumeratedValue> 13196 <name>inactive</name> 13197 <description>Not active</description> 13198 <value>0</value> 13199 </enumeratedValue> 13200 <enumeratedValue> 13201 <name>Pending</name> 13202 <description>Active</description> 13203 <value>1</value> 13204 </enumeratedValue> 13205 </enumeratedValues> 13206 </field> 13207 </fields> 13208 </register> 13209 <register> 13210 <name>TRIM</name> 13211 <description>RTC Trim Register.</description> 13212 <addressOffset>0x14</addressOffset> 13213 <resetMask>0x00000000</resetMask> 13214 <fields> 13215 <field> 13216 <name>TRIM</name> 13217 <description>RTC Trim. This register contains the 2's complement value that specifies the trim resolution. Each increment or decrement of the bit adds or subtracts 1ppm at each 4KHz clock value, with a maximum correction of +/- 127ppm.</description> 13218 <bitOffset>0</bitOffset> 13219 <bitWidth>8</bitWidth> 13220 </field> 13221 <field> 13222 <name>VRTC_TMR</name> 13223 <description>VBAT Timer Value. When RTC is running off of VBAT, this field is incremented every 32 seconds.</description> 13224 <bitOffset>8</bitOffset> 13225 <bitWidth>24</bitWidth> 13226 </field> 13227 </fields> 13228 </register> 13229 <register> 13230 <name>OSCCTRL</name> 13231 <description>RTC Oscillator Control Register.</description> 13232 <addressOffset>0x18</addressOffset> 13233 <resetMask>0x00000000</resetMask> 13234 <fields> 13235 <field> 13236 <name>FILTER_EN</name> 13237 <description>Enables analog deglitch filter.</description> 13238 <bitOffset>0</bitOffset> 13239 <bitWidth>1</bitWidth> 13240 </field> 13241 <field> 13242 <name>IBIAS_SEL</name> 13243 <description>If IBIAS_EN is 1, selects 4x,2x mode.</description> 13244 <bitOffset>1</bitOffset> 13245 <bitWidth>1</bitWidth> 13246 </field> 13247 <field> 13248 <name>HYST_EN</name> 13249 <description>Enables high current hysteresis buffer.</description> 13250 <bitOffset>2</bitOffset> 13251 <bitWidth>1</bitWidth> 13252 </field> 13253 <field> 13254 <name>IBIAS_EN</name> 13255 <description>Enables higher 4x,2x current modes.</description> 13256 <bitOffset>3</bitOffset> 13257 <bitWidth>1</bitWidth> 13258 </field> 13259 <field> 13260 <name>BYPASS</name> 13261 <description>RTC Crystal Bypass</description> 13262 <bitOffset>4</bitOffset> 13263 <bitWidth>1</bitWidth> 13264 </field> 13265 <field> 13266 <name>SQW_32K</name> 13267 <description>RTC 32kHz Square Wave Output</description> 13268 <bitOffset>5</bitOffset> 13269 <bitWidth>1</bitWidth> 13270 </field> 13271 </fields> 13272 </register> 13273 </registers> 13274 </peripheral> 13275<!--RTC Real Time Clock and Alarm.--> 13276 <peripheral> 13277 <name>SEMA</name> 13278 <description>The Semaphore peripheral allows multiple cores in a system to cooperate when accessing shred resources. 13279 The peripheral contains eight semaphores that can be atomically set and cleared. It is left to the discretion of the software 13280 architect to decide how and when the semaphores are used and how they are allocated. Existing hardware does not have to be 13281 13282 modified for this type of cooperative sharing, and the use of semaphores is exclusively within the software domain.</description> 13283 <baseAddress>0x4003E000</baseAddress> 13284 <addressBlock> 13285 <offset>0x00</offset> 13286 <size>0x1000</size> 13287 <usage>registers</usage> 13288 </addressBlock> 13289 <registers> 13290 <register> 13291 <dim>8</dim> 13292 <dimIncrement>4</dimIncrement> 13293 <name>SEMAPHORES[%s]</name> 13294 <description>Read to test and set, returns prior value. Write 0 to clear semaphore.</description> 13295 <addressOffset>0x00</addressOffset> 13296 <size>32</size> 13297 <fields> 13298 <field> 13299 <name>sema</name> 13300 <bitOffset>0</bitOffset> 13301 <bitWidth>1</bitWidth> 13302 </field> 13303 </fields> 13304 </register> 13305 <register> 13306 <name>irq0</name> 13307 <description>Semaphore IRQ0 register.</description> 13308 <addressOffset>0x40</addressOffset> 13309 <size>32</size> 13310 <fields> 13311 <field> 13312 <name>en</name> 13313 <bitOffset>0</bitOffset> 13314 <bitWidth>1</bitWidth> 13315 </field> 13316 <field> 13317 <name>cm4_irq</name> 13318 <bitOffset>16</bitOffset> 13319 <bitWidth>1</bitWidth> 13320 </field> 13321 </fields> 13322 </register> 13323 <register> 13324 <name>mail0</name> 13325 <description>Semaphore Mailbox 0 register.</description> 13326 <addressOffset>0x44</addressOffset> 13327 <size>32</size> 13328 <fields> 13329 <field> 13330 <name>data</name> 13331 <bitOffset>0</bitOffset> 13332 <bitWidth>32</bitWidth> 13333 </field> 13334 </fields> 13335 </register> 13336 <register> 13337 <name>irq1</name> 13338 <description>Semaphore IRQ1 register.</description> 13339 <addressOffset>0x48</addressOffset> 13340 <size>32</size> 13341 <fields> 13342 <field> 13343 <name>en</name> 13344 <bitOffset>0</bitOffset> 13345 <bitWidth>1</bitWidth> 13346 </field> 13347 <field> 13348 <name>rv32_irq</name> 13349 <bitOffset>16</bitOffset> 13350 <bitWidth>1</bitWidth> 13351 </field> 13352 </fields> 13353 </register> 13354 <register> 13355 <name>mail1</name> 13356 <description>Semaphore Mailbox 1 register.</description> 13357 <addressOffset>0x4C</addressOffset> 13358 <size>32</size> 13359 <fields> 13360 <field> 13361 <name>data</name> 13362 <bitOffset>0</bitOffset> 13363 <bitWidth>32</bitWidth> 13364 </field> 13365 </fields> 13366 </register> 13367 <register> 13368 <name>status</name> 13369 <description>Semaphore status bits. 0 indicates the semaphore is free, 1 indicates taken.</description> 13370 <addressOffset>0x100</addressOffset> 13371 <size>32</size> 13372 <fields> 13373 <field> 13374 <name>status0</name> 13375 <bitOffset>0</bitOffset> 13376 <bitWidth>1</bitWidth> 13377 </field> 13378 <field> 13379 <name>status1</name> 13380 <bitOffset>1</bitOffset> 13381 <bitWidth>1</bitWidth> 13382 </field> 13383 <field> 13384 <name>status2</name> 13385 <bitOffset>2</bitOffset> 13386 <bitWidth>1</bitWidth> 13387 </field> 13388 <field> 13389 <name>status3</name> 13390 <bitOffset>3</bitOffset> 13391 <bitWidth>1</bitWidth> 13392 </field> 13393 <field> 13394 <name>status4</name> 13395 <bitOffset>4</bitOffset> 13396 <bitWidth>1</bitWidth> 13397 </field> 13398 <field> 13399 <name>status5</name> 13400 <bitOffset>5</bitOffset> 13401 <bitWidth>1</bitWidth> 13402 </field> 13403 <field> 13404 <name>status6</name> 13405 <bitOffset>6</bitOffset> 13406 <bitWidth>1</bitWidth> 13407 </field> 13408 <field> 13409 <name>status7</name> 13410 <bitOffset>7</bitOffset> 13411 <bitWidth>1</bitWidth> 13412 </field> 13413 </fields> 13414 </register> 13415 </registers> 13416 </peripheral> 13417<!--SEMA The Semaphore peripheral allows multiple cores in a system to cooperate when accessing shred resources. 13418 The peripheral contains eight semaphores that can be atomically set and cleared. It is left to the discretion of the software 13419 architect to decide how and when the semaphores are used and how they are allocated. Existing hardware does not have to be 13420 13421 modified for this type of cooperative sharing, and the use of semaphores is exclusively within the software domain.--> 13422 <peripheral> 13423 <name>SIR</name> 13424 <description>System Initialization Registers.</description> 13425 <baseAddress>0x40000400</baseAddress> 13426 <access>read-only</access> 13427 <addressBlock> 13428 <offset>0x00</offset> 13429 <size>0x400</size> 13430 <usage>registers</usage> 13431 </addressBlock> 13432 <registers> 13433 <register> 13434 <name>SISTAT</name> 13435 <description>System Initialization Status Register.</description> 13436 <addressOffset>0x00</addressOffset> 13437 <access>read-only</access> 13438 <fields> 13439 <field> 13440 <name>MAGIC</name> 13441 <description>Magic Word Validation. This bit is set by the system initialization block following power-up.</description> 13442 <bitOffset>0</bitOffset> 13443 <bitWidth>1</bitWidth> 13444 <access>read-only</access> 13445 <enumeratedValues> 13446 <usage>read</usage> 13447 <enumeratedValue> 13448 <name>magicNotSet</name> 13449 <description>Magic word was not set (OTP has not been initialized properly).</description> 13450 <value>0</value> 13451 </enumeratedValue> 13452 <enumeratedValue> 13453 <name>magicSet</name> 13454 <description>Magic word was set (OTP contains valid settings).</description> 13455 <value>1</value> 13456 </enumeratedValue> 13457 </enumeratedValues> 13458 </field> 13459 <field> 13460 <name>CRCERR</name> 13461 <description>CRC Error Status. This bit is set by the system initialization block following power-up.</description> 13462 <bitOffset>1</bitOffset> 13463 <bitWidth>1</bitWidth> 13464 <access>read-only</access> 13465 <enumeratedValues> 13466 <usage>read</usage> 13467 <enumeratedValue> 13468 <name>noError</name> 13469 <description>No CRC errors occurred during the read of the OTP memory block.</description> 13470 <value>0</value> 13471 </enumeratedValue> 13472 <enumeratedValue> 13473 <name>error</name> 13474 <description>A CRC error occurred while reading the OTP. The address of the failure location in the OTP memory is stored in the ERRADDR register.</description> 13475 <value>1</value> 13476 </enumeratedValue> 13477 </enumeratedValues> 13478 </field> 13479 </fields> 13480 </register> 13481 <register> 13482 <name>SIADDR</name> 13483 <description>Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1).</description> 13484 <addressOffset>0x04</addressOffset> 13485 <access>read-only</access> 13486 <fields> 13487 <field> 13488 <name>ERRADDR</name> 13489 <bitOffset>0</bitOffset> 13490 <bitWidth>32</bitWidth> 13491 </field> 13492 </fields> 13493 </register> 13494 <register> 13495 <name>BTLE_LDO_TRIM</name> 13496 <description>BTLE LDO Trim register.</description> 13497 <addressOffset>0x28</addressOffset> 13498 <access>read-write</access> 13499 <fields> 13500 <field> 13501 <name>TX</name> 13502 <description>TX LDO trim value.</description> 13503 <bitOffset>0</bitOffset> 13504 <bitWidth>5</bitWidth> 13505 <access>read-write</access> 13506 </field> 13507 <field> 13508 <name>RX</name> 13509 <description>RX LDO trim value.</description> 13510 <bitOffset>5</bitOffset> 13511 <bitWidth>5</bitWidth> 13512 <access>read-write</access> 13513 </field> 13514 </fields> 13515 </register> 13516 <register> 13517 <name>FSTAT</name> 13518 <description>funcstat register.</description> 13519 <addressOffset>0x100</addressOffset> 13520 <access>read-only</access> 13521 <fields> 13522 <field> 13523 <name>FPU</name> 13524 <description>FPU Function.</description> 13525 <bitOffset>0</bitOffset> 13526 <bitWidth>1</bitWidth> 13527 <enumeratedValues> 13528 <enumeratedValue> 13529 <name>no</name> 13530 <value>0</value> 13531 </enumeratedValue> 13532 <enumeratedValue> 13533 <name>yes</name> 13534 <value>1</value> 13535 </enumeratedValue> 13536 </enumeratedValues> 13537 </field> 13538 <field> 13539 <name>USB</name> 13540 <description>USB Function.</description> 13541 <bitOffset>1</bitOffset> 13542 <bitWidth>1</bitWidth> 13543 <enumeratedValues> 13544 <enumeratedValue> 13545 <name>no</name> 13546 <value>0</value> 13547 </enumeratedValue> 13548 <enumeratedValue> 13549 <name>yes</name> 13550 <value>1</value> 13551 </enumeratedValue> 13552 </enumeratedValues> 13553 </field> 13554 <field> 13555 <name>ADC</name> 13556 <description>ADC Function.</description> 13557 <bitOffset>2</bitOffset> 13558 <bitWidth>1</bitWidth> 13559 <enumeratedValues> 13560 <enumeratedValue> 13561 <name>no</name> 13562 <value>0</value> 13563 </enumeratedValue> 13564 <enumeratedValue> 13565 <name>yes</name> 13566 <value>1</value> 13567 </enumeratedValue> 13568 </enumeratedValues> 13569 </field> 13570 <field> 13571 <name>SPIXIP</name> 13572 <description>SPIXIP Function.</description> 13573 <bitOffset>3</bitOffset> 13574 <bitWidth>1</bitWidth> 13575 <enumeratedValues> 13576 <enumeratedValue> 13577 <name>no</name> 13578 <value>0</value> 13579 </enumeratedValue> 13580 <enumeratedValue> 13581 <name>yes</name> 13582 <value>1</value> 13583 </enumeratedValue> 13584 </enumeratedValues> 13585 </field> 13586 <field> 13587 <name>HBC</name> 13588 <description>HBC Function.</description> 13589 <bitOffset>4</bitOffset> 13590 <bitWidth>1</bitWidth> 13591 <enumeratedValues> 13592 <enumeratedValue> 13593 <name>no</name> 13594 <value>0</value> 13595 </enumeratedValue> 13596 <enumeratedValue> 13597 <name>yes</name> 13598 <value>1</value> 13599 </enumeratedValue> 13600 </enumeratedValues> 13601 </field> 13602 <field> 13603 <name>SMPHR</name> 13604 <description>SMPHR function.</description> 13605 <bitOffset>7</bitOffset> 13606 <bitWidth>1</bitWidth> 13607 <enumeratedValues> 13608 <enumeratedValue> 13609 <name>no</name> 13610 <value>0</value> 13611 </enumeratedValue> 13612 <enumeratedValue> 13613 <name>yes</name> 13614 <value>1</value> 13615 </enumeratedValue> 13616 </enumeratedValues> 13617 </field> 13618 <field> 13619 <name>BTLE</name> 13620 <description>BTLE function.</description> 13621 <bitOffset>9</bitOffset> 13622 <bitWidth>1</bitWidth> 13623 <enumeratedValues> 13624 <enumeratedValue> 13625 <name>no</name> 13626 <value>0</value> 13627 </enumeratedValue> 13628 <enumeratedValue> 13629 <name>yes</name> 13630 <value>1</value> 13631 </enumeratedValue> 13632 </enumeratedValues> 13633 </field> 13634 </fields> 13635 </register> 13636 <register> 13637 <name>SFSTAT</name> 13638 <description>Security function status register.</description> 13639 <addressOffset>0x104</addressOffset> 13640 <access>read-only</access> 13641 <fields> 13642 <field> 13643 <name>TRNG</name> 13644 <description> TRNG Function.</description> 13645 <bitOffset>2</bitOffset> 13646 <bitWidth>1</bitWidth> 13647 <enumeratedValues> 13648 <enumeratedValue> 13649 <name>no</name> 13650 <value>0</value> 13651 </enumeratedValue> 13652 <enumeratedValue> 13653 <name>yes</name> 13654 <value>1</value> 13655 </enumeratedValue> 13656 </enumeratedValues> 13657 </field> 13658 <field> 13659 <name>AES</name> 13660 <description>AES Block.</description> 13661 <bitOffset>3</bitOffset> 13662 <bitWidth>1</bitWidth> 13663 <enumeratedValues> 13664 <enumeratedValue> 13665 <name>no</name> 13666 <value>0</value> 13667 </enumeratedValue> 13668 <enumeratedValue> 13669 <name>yes</name> 13670 <value>1</value> 13671 </enumeratedValue> 13672 </enumeratedValues> 13673 </field> 13674 <field> 13675 <name>SHA</name> 13676 <description>SHA Block.</description> 13677 <bitOffset>4</bitOffset> 13678 <bitWidth>1</bitWidth> 13679 <enumeratedValues> 13680 <enumeratedValue> 13681 <name>no</name> 13682 <value>0</value> 13683 </enumeratedValue> 13684 <enumeratedValue> 13685 <name>yes</name> 13686 <value>1</value> 13687 </enumeratedValue> 13688 </enumeratedValues> 13689 </field> 13690 <field> 13691 <name>MAA</name> 13692 <description>MAA Block.</description> 13693 <bitOffset>5</bitOffset> 13694 <bitWidth>1</bitWidth> 13695 <enumeratedValues> 13696 <enumeratedValue> 13697 <name>no</name> 13698 <value>0</value> 13699 </enumeratedValue> 13700 <enumeratedValue> 13701 <name>yes</name> 13702 <value>1</value> 13703 </enumeratedValue> 13704 </enumeratedValues> 13705 </field> 13706 </fields> 13707 </register> 13708 </registers> 13709 </peripheral> 13710<!--SIR System Initialization Registers.--> 13711 <peripheral> 13712 <name>SMON</name> 13713 <description>The Security Monitor block used to monitor system threat conditions.</description> 13714 <baseAddress>0x40004000</baseAddress> 13715 <addressBlock> 13716 <offset>0x00</offset> 13717 <size>0x400</size> 13718 <usage>registers</usage> 13719 </addressBlock> 13720 <registers> 13721 <register> 13722 <name>EXTSCN</name> 13723 <description>External Sensor Control Register.</description> 13724 <addressOffset>0x00</addressOffset> 13725 <resetMask>0x3800FFC0</resetMask> 13726 <fields> 13727 <field> 13728 <name>EXTS_EN0</name> 13729 <description>External Sensor Enable for input/output pair 0.</description> 13730 <bitOffset>0</bitOffset> 13731 <bitWidth>1</bitWidth> 13732 <enumeratedValues> 13733 <enumeratedValue> 13734 <name>dis</name> 13735 <description>Disable.</description> 13736 <value>0</value> 13737 </enumeratedValue> 13738 <enumeratedValue> 13739 <name>en</name> 13740 <description>Enable.</description> 13741 <value>1</value> 13742 </enumeratedValue> 13743 </enumeratedValues> 13744 </field> 13745 <field> 13746 <name>EXTS_EN1</name> 13747 <description>External Sensor Enable for input/output pair 1.</description> 13748 <bitOffset>1</bitOffset> 13749 <bitWidth>1</bitWidth> 13750 <enumeratedValues> 13751 <enumeratedValue> 13752 <name>dis</name> 13753 <description>Disable.</description> 13754 <value>0</value> 13755 </enumeratedValue> 13756 <enumeratedValue> 13757 <name>en</name> 13758 <description>Enable.</description> 13759 <value>1</value> 13760 </enumeratedValue> 13761 </enumeratedValues> 13762 </field> 13763 <field> 13764 <name>EXTS_EN2</name> 13765 <description>External Sensor Enable for input/output pair 2.</description> 13766 <bitOffset>2</bitOffset> 13767 <bitWidth>1</bitWidth> 13768 <enumeratedValues> 13769 <enumeratedValue> 13770 <name>dis</name> 13771 <description>Disable.</description> 13772 <value>0</value> 13773 </enumeratedValue> 13774 <enumeratedValue> 13775 <name>en</name> 13776 <description>Enable.</description> 13777 <value>1</value> 13778 </enumeratedValue> 13779 </enumeratedValues> 13780 </field> 13781 <field> 13782 <name>EXTS_EN3</name> 13783 <description>External Sensor Enable for input/output pair 3.</description> 13784 <bitOffset>3</bitOffset> 13785 <bitWidth>1</bitWidth> 13786 <enumeratedValues> 13787 <enumeratedValue> 13788 <name>dis</name> 13789 <description>Disable.</description> 13790 <value>0</value> 13791 </enumeratedValue> 13792 <enumeratedValue> 13793 <name>en</name> 13794 <description>Enable.</description> 13795 <value>1</value> 13796 </enumeratedValue> 13797 </enumeratedValues> 13798 </field> 13799 <field> 13800 <name>EXTS_EN4</name> 13801 <description>External Sensor Enable for input/output pair 4.</description> 13802 <bitOffset>4</bitOffset> 13803 <bitWidth>1</bitWidth> 13804 <enumeratedValues> 13805 <enumeratedValue> 13806 <name>dis</name> 13807 <description>Disable.</description> 13808 <value>0</value> 13809 </enumeratedValue> 13810 <enumeratedValue> 13811 <name>en</name> 13812 <description>Enable.</description> 13813 <value>1</value> 13814 </enumeratedValue> 13815 </enumeratedValues> 13816 </field> 13817 <field> 13818 <name>EXTS_EN5</name> 13819 <description>External Sensor Enable for input/output pair 5.</description> 13820 <bitOffset>5</bitOffset> 13821 <bitWidth>1</bitWidth> 13822 <enumeratedValues> 13823 <enumeratedValue> 13824 <name>dis</name> 13825 <description>Disable.</description> 13826 <value>0</value> 13827 </enumeratedValue> 13828 <enumeratedValue> 13829 <name>en</name> 13830 <description>Enable.</description> 13831 <value>1</value> 13832 </enumeratedValue> 13833 </enumeratedValues> 13834 </field> 13835 <field> 13836 <name>EXTCNT</name> 13837 <description>External Sensor Error Counter. These bits set the number of external sensor accepted mismatches that have to occur within a single bit period before an external sensor alarm is triggered.</description> 13838 <bitOffset>16</bitOffset> 13839 <bitWidth>5</bitWidth> 13840 </field> 13841 <field> 13842 <name>EXTFRQ</name> 13843 <description>External Sensor Frequency. These bits define the frequency at which the external sensors are clocked to/from the EXTS_IN and EXTS_OUT pair.</description> 13844 <bitOffset>21</bitOffset> 13845 <bitWidth>3</bitWidth> 13846 <enumeratedValues> 13847 <enumeratedValue> 13848 <name>freq2000Hz</name> 13849 <description>Div 4 (2000Hz).</description> 13850 <value>0</value> 13851 </enumeratedValue> 13852 <enumeratedValue> 13853 <name>freq1000Hz</name> 13854 <description>Div 8 (1000Hz).</description> 13855 <value>1</value> 13856 </enumeratedValue> 13857 <enumeratedValue> 13858 <name>freq500Hz</name> 13859 <description>Div 16 (500Hz).</description> 13860 <value>2</value> 13861 </enumeratedValue> 13862 <enumeratedValue> 13863 <name>freq250Hz</name> 13864 <description>Div 32 (250Hz).</description> 13865 <value>3</value> 13866 </enumeratedValue> 13867 <enumeratedValue> 13868 <name>freq125Hz</name> 13869 <description>Div 64 (125Hz).</description> 13870 <value>4</value> 13871 </enumeratedValue> 13872 <enumeratedValue> 13873 <name>freq63Hz</name> 13874 <description>Div 128 (63Hz).</description> 13875 <value>5</value> 13876 </enumeratedValue> 13877 <enumeratedValue> 13878 <name>freq31Hz</name> 13879 <description>Div 256 (31Hz).</description> 13880 <value>6</value> 13881 </enumeratedValue> 13882 <enumeratedValue> 13883 <name>RFU</name> 13884 <description>Reserved. Do not use.</description> 13885 <value>7</value> 13886 </enumeratedValue> 13887 </enumeratedValues> 13888 </field> 13889 <field> 13890 <name>DIVCLK</name> 13891 <description>Clock Divide. These bits are used to divide the 8KHz input clock. The resulting divided clock is used for all logic within the Security Monitor Block. Note: 13892 If the input clock is divided with these bits, the error count threshold table and output frequency will be affected accordingly with the same divide factor.</description> 13893 <bitOffset>24</bitOffset> 13894 <bitWidth>3</bitWidth> 13895 <enumeratedValues> 13896 <enumeratedValue> 13897 <name>div1</name> 13898 <description>Divide by 1 (8000 Hz).</description> 13899 <value>0</value> 13900 </enumeratedValue> 13901 <enumeratedValue> 13902 <name>div2</name> 13903 <description>Divide by 2 (4000 Hz).</description> 13904 <value>1</value> 13905 </enumeratedValue> 13906 <enumeratedValue> 13907 <name>div4</name> 13908 <description>Divide by 4 (2000 Hz).</description> 13909 <value>2</value> 13910 </enumeratedValue> 13911 <enumeratedValue> 13912 <name>div8</name> 13913 <description>Divide by 8 (1000 Hz).</description> 13914 <value>3</value> 13915 </enumeratedValue> 13916 <enumeratedValue> 13917 <name>div16</name> 13918 <description>Divide by 16 (500 Hz).</description> 13919 <value>4</value> 13920 </enumeratedValue> 13921 <enumeratedValue> 13922 <name>div32</name> 13923 <description>Divide by 32 (250 Hz).</description> 13924 <value>5</value> 13925 </enumeratedValue> 13926 <enumeratedValue> 13927 <name>div64</name> 13928 <description>Divide by 64 (125 Hz).</description> 13929 <value>6</value> 13930 </enumeratedValue> 13931 </enumeratedValues> 13932 </field> 13933 <field> 13934 <name>BUSY</name> 13935 <description>Busy. This bit is set to 1 by hardware after EXTSCN register is written to. This bit is automatically cleared to 0 after this register information has been transferred to the security monitor domain.</description> 13936 <bitOffset>30</bitOffset> 13937 <bitWidth>1</bitWidth> 13938 <access>read-only</access> 13939 <enumeratedValues> 13940 <enumeratedValue> 13941 <name>idle</name> 13942 <description>Idle.</description> 13943 <value>0</value> 13944 </enumeratedValue> 13945 <enumeratedValue> 13946 <name>busy</name> 13947 <description>Update in Progress.</description> 13948 <value>1</value> 13949 </enumeratedValue> 13950 </enumeratedValues> 13951 </field> 13952 <field> 13953 <name>LOCK</name> 13954 <description>Lock Register. Once locked, the EXTSCN register can no longer be modified. Only a battery disconnect will clear this bit. VBAT powers this register.</description> 13955 <bitOffset>31</bitOffset> 13956 <bitWidth>1</bitWidth> 13957 <enumeratedValues> 13958 <enumeratedValue> 13959 <name>unlocked</name> 13960 <description>Unlocked.</description> 13961 <value>0</value> 13962 </enumeratedValue> 13963 <enumeratedValue> 13964 <name>locked</name> 13965 <description>Locked.</description> 13966 <value>1</value> 13967 </enumeratedValue> 13968 </enumeratedValues> 13969 </field> 13970 </fields> 13971 </register> 13972 <register> 13973 <name>INTSCN</name> 13974 <description>Internal Sensor Control Register.</description> 13975 <addressOffset>0x04</addressOffset> 13976 <resetMask>0x7F00FFF7</resetMask> 13977 <fields> 13978 <field> 13979 <name>SHIELD_EN</name> 13980 <description>Die Shield Enable.</description> 13981 <bitOffset>0</bitOffset> 13982 <bitWidth>1</bitWidth> 13983 <enumeratedValues> 13984 <enumeratedValue> 13985 <name>dis</name> 13986 <description>Disable.</description> 13987 <value>0</value> 13988 </enumeratedValue> 13989 <enumeratedValue> 13990 <name>en</name> 13991 <description>Enable.</description> 13992 <value>1</value> 13993 </enumeratedValue> 13994 </enumeratedValues> 13995 </field> 13996 <field> 13997 <name>TEMP_EN</name> 13998 <description>Temperature Sensor Enable.</description> 13999 <bitOffset>1</bitOffset> 14000 <bitWidth>1</bitWidth> 14001 <enumeratedValues> 14002 <enumeratedValue> 14003 <name>dis</name> 14004 <description>Disable.</description> 14005 <value>0</value> 14006 </enumeratedValue> 14007 <enumeratedValue> 14008 <name>en</name> 14009 <description>Enable.</description> 14010 <value>1</value> 14011 </enumeratedValue> 14012 </enumeratedValues> 14013 </field> 14014 <field> 14015 <name>VBAT_EN</name> 14016 <description>Battery Monitor Enable.</description> 14017 <bitOffset>2</bitOffset> 14018 <bitWidth>1</bitWidth> 14019 <enumeratedValues> 14020 <enumeratedValue> 14021 <name>dis</name> 14022 <description>Disable.</description> 14023 <value>0</value> 14024 </enumeratedValue> 14025 <enumeratedValue> 14026 <name>en</name> 14027 <description>Enable.</description> 14028 <value>1</value> 14029 </enumeratedValue> 14030 </enumeratedValues> 14031 </field> 14032 <field> 14033 <name>DFD_EN</name> 14034 <description>Digital Fault Dector Enable</description> 14035 <bitOffset>3</bitOffset> 14036 <bitWidth>1</bitWidth> 14037 </field> 14038 <field> 14039 <name>DFD_NMI</name> 14040 <description>Digital Fault NMI Enable</description> 14041 <bitOffset>4</bitOffset> 14042 <bitWidth>1</bitWidth> 14043 </field> 14044 <field> 14045 <name>DFD_STDBY</name> 14046 <description>Digital Fault Dector Stand by Enable</description> 14047 <bitOffset>8</bitOffset> 14048 <bitWidth>1</bitWidth> 14049 </field> 14050 <field> 14051 <name>PUF_TRIM_ERASE</name> 14052 <description>Erase puf trim Enable</description> 14053 <bitOffset>10</bitOffset> 14054 <bitWidth>1</bitWidth> 14055 </field> 14056 <field> 14057 <name>LOTEMP_SEL</name> 14058 <description>Low Temperature Detection Select.</description> 14059 <bitOffset>16</bitOffset> 14060 <bitWidth>1</bitWidth> 14061 <enumeratedValues> 14062 <enumeratedValue> 14063 <name>neg50C</name> 14064 <description>-50 degrees C.</description> 14065 <value>0</value> 14066 </enumeratedValue> 14067 <enumeratedValue> 14068 <name>neg30C</name> 14069 <description>-30 degrees C.</description> 14070 <value>1</value> 14071 </enumeratedValue> 14072 </enumeratedValues> 14073 </field> 14074 <field> 14075 <name>VCORELOEN</name> 14076 <description>VCORE Undervoltage Detect Enable.</description> 14077 <bitOffset>18</bitOffset> 14078 <bitWidth>1</bitWidth> 14079 <enumeratedValues> 14080 <enumeratedValue> 14081 <name>dis</name> 14082 <description>Disable.</description> 14083 <value>0</value> 14084 </enumeratedValue> 14085 <enumeratedValue> 14086 <name>en</name> 14087 <description>Enable.</description> 14088 <value>1</value> 14089 </enumeratedValue> 14090 </enumeratedValues> 14091 </field> 14092 <field> 14093 <name>VCOREHIEN</name> 14094 <description>VCORE Overvoltage Detect Enable.</description> 14095 <bitOffset>19</bitOffset> 14096 <bitWidth>1</bitWidth> 14097 <enumeratedValues> 14098 <enumeratedValue> 14099 <name>dis</name> 14100 <description>Disable.</description> 14101 <value>0</value> 14102 </enumeratedValue> 14103 <enumeratedValue> 14104 <name>en</name> 14105 <description>Enable.</description> 14106 <value>1</value> 14107 </enumeratedValue> 14108 </enumeratedValues> 14109 </field> 14110 <field> 14111 <name>VDDLOEN</name> 14112 <description>VDD Undervoltage Detect Enable.</description> 14113 <bitOffset>20</bitOffset> 14114 <bitWidth>1</bitWidth> 14115 <enumeratedValues> 14116 <enumeratedValue> 14117 <name>dis</name> 14118 <description>Disable.</description> 14119 <value>0</value> 14120 </enumeratedValue> 14121 <enumeratedValue> 14122 <name>en</name> 14123 <description>Enable.</description> 14124 <value>1</value> 14125 </enumeratedValue> 14126 </enumeratedValues> 14127 </field> 14128 <field> 14129 <name>VDDHIEN</name> 14130 <description>VDD Overvoltage Detect Enable.</description> 14131 <bitOffset>21</bitOffset> 14132 <bitWidth>1</bitWidth> 14133 <enumeratedValues> 14134 <enumeratedValue> 14135 <name>dis</name> 14136 <description>Disable.</description> 14137 <value>0</value> 14138 </enumeratedValue> 14139 <enumeratedValue> 14140 <name>en</name> 14141 <description>Enable.</description> 14142 <value>1</value> 14143 </enumeratedValue> 14144 </enumeratedValues> 14145 </field> 14146 <field> 14147 <name>VGLEN</name> 14148 <description>Voltage Glitch Detection Enable.</description> 14149 <bitOffset>22</bitOffset> 14150 <bitWidth>1</bitWidth> 14151 <enumeratedValues> 14152 <enumeratedValue> 14153 <name>dis</name> 14154 <description>Disable.</description> 14155 <value>0</value> 14156 </enumeratedValue> 14157 <enumeratedValue> 14158 <name>en</name> 14159 <description>Enable.</description> 14160 <value>1</value> 14161 </enumeratedValue> 14162 </enumeratedValues> 14163 </field> 14164 <field> 14165 <name>LOCK</name> 14166 <description>Lock Register. Once locked, the INTSCN register can no longer be modified. Only a battery disconnect will clear this bit. VBAT powers this register.</description> 14167 <bitOffset>31</bitOffset> 14168 <bitWidth>1</bitWidth> 14169 <enumeratedValues> 14170 <enumeratedValue> 14171 <name>unlocked</name> 14172 <description>Unlocked.</description> 14173 <value>0</value> 14174 </enumeratedValue> 14175 <enumeratedValue> 14176 <name>locked</name> 14177 <description>Locked.</description> 14178 <value>1</value> 14179 </enumeratedValue> 14180 </enumeratedValues> 14181 </field> 14182 </fields> 14183 </register> 14184 <register> 14185 <name>SECALM</name> 14186 <description>Security Alarm Register.</description> 14187 <addressOffset>0x08</addressOffset> 14188 <resetValue>0x00000000</resetValue> 14189 <resetMask>0x00000000</resetMask> 14190 <fields> 14191 <field> 14192 <name>DRS</name> 14193 <description>Destructive Reset Trigger. Setting this bit will generate a DRS. This bit is self-cleared by hardware.</description> 14194 <bitOffset>0</bitOffset> 14195 <bitWidth>1</bitWidth> 14196 <enumeratedValues> 14197 <enumeratedValue> 14198 <name>complete</name> 14199 <description>No operation/complete.</description> 14200 <value>0</value> 14201 </enumeratedValue> 14202 <enumeratedValue> 14203 <name>start</name> 14204 <description>Start operation.</description> 14205 <value>1</value> 14206 </enumeratedValue> 14207 </enumeratedValues> 14208 </field> 14209 <field> 14210 <name>KEYWIPE</name> 14211 <description>Key Wipe Trigger. Set to 1 to initiate a wipe of the AES key register. It does not reset the part, or log a timestamp. AES and DES registers are not affected by this bit. This bit is automatically cleared to 0 after the keys have been wiped.</description> 14212 <bitOffset>1</bitOffset> 14213 <bitWidth>1</bitWidth> 14214 <enumeratedValues> 14215 <enumeratedValue> 14216 <name>complete</name> 14217 <description>No operation/complete.</description> 14218 <value>0</value> 14219 </enumeratedValue> 14220 <enumeratedValue> 14221 <name>start</name> 14222 <description>Start operation.</description> 14223 <value>1</value> 14224 </enumeratedValue> 14225 </enumeratedValues> 14226 </field> 14227 <field> 14228 <name>SHIELDF</name> 14229 <description>Die Shield Flag.</description> 14230 <bitOffset>2</bitOffset> 14231 <bitWidth>1</bitWidth> 14232 <enumeratedValues> 14233 <enumeratedValue> 14234 <name>noEvent</name> 14235 <description>The event has not occurred.</description> 14236 <value>0</value> 14237 </enumeratedValue> 14238 <enumeratedValue> 14239 <name>occurred</name> 14240 <description>The event has occurred.</description> 14241 <value>1</value> 14242 </enumeratedValue> 14243 </enumeratedValues> 14244 </field> 14245 <field> 14246 <name>LOTEMP</name> 14247 <description>Low Temperature Detect.</description> 14248 <bitOffset>3</bitOffset> 14249 <bitWidth>1</bitWidth> 14250 <enumeratedValues> 14251 <enumeratedValue> 14252 <name>noEvent</name> 14253 <description>The event has not occurred.</description> 14254 <value>0</value> 14255 </enumeratedValue> 14256 <enumeratedValue> 14257 <name>occurred</name> 14258 <description>The event has occurred.</description> 14259 <value>1</value> 14260 </enumeratedValue> 14261 </enumeratedValues> 14262 </field> 14263 <field> 14264 <name>HITEMP</name> 14265 <description>High Temperature Detect.</description> 14266 <bitOffset>4</bitOffset> 14267 <bitWidth>1</bitWidth> 14268 <enumeratedValues> 14269 <enumeratedValue> 14270 <name>noEvent</name> 14271 <description>The event has not occurred.</description> 14272 <value>0</value> 14273 </enumeratedValue> 14274 <enumeratedValue> 14275 <name>occurred</name> 14276 <description>The event has occurred.</description> 14277 <value>1</value> 14278 </enumeratedValue> 14279 </enumeratedValues> 14280 </field> 14281 <field> 14282 <name>BATLO</name> 14283 <description>Battery Undervoltage Detect.</description> 14284 <bitOffset>5</bitOffset> 14285 <bitWidth>1</bitWidth> 14286 <enumeratedValues> 14287 <enumeratedValue> 14288 <name>noEvent</name> 14289 <description>The event has not occurred.</description> 14290 <value>0</value> 14291 </enumeratedValue> 14292 <enumeratedValue> 14293 <name>occurred</name> 14294 <description>The event has occurred.</description> 14295 <value>1</value> 14296 </enumeratedValue> 14297 </enumeratedValues> 14298 </field> 14299 <field> 14300 <name>BATHI</name> 14301 <description>Battery Overvoltage Detect.</description> 14302 <bitOffset>6</bitOffset> 14303 <bitWidth>1</bitWidth> 14304 <enumeratedValues> 14305 <enumeratedValue> 14306 <name>noEvent</name> 14307 <description>The event has not occurred.</description> 14308 <value>0</value> 14309 </enumeratedValue> 14310 <enumeratedValue> 14311 <name>occurred</name> 14312 <description>The event has occurred.</description> 14313 <value>1</value> 14314 </enumeratedValue> 14315 </enumeratedValues> 14316 </field> 14317 <field> 14318 <name>EXTF</name> 14319 <description>External Sensor Flag. This bit is set to 1 when any of the EXTSTAT bits are set.</description> 14320 <bitOffset>7</bitOffset> 14321 <bitWidth>1</bitWidth> 14322 <enumeratedValues> 14323 <enumeratedValue> 14324 <name>noEvent</name> 14325 <description>The event has not occurred.</description> 14326 <value>0</value> 14327 </enumeratedValue> 14328 <enumeratedValue> 14329 <name>occurred</name> 14330 <description>The event has occurred.</description> 14331 <value>1</value> 14332 </enumeratedValue> 14333 </enumeratedValues> 14334 </field> 14335 <field> 14336 <name>VDDLO</name> 14337 <description>VDD Undervoltage Detect Flag.</description> 14338 <bitOffset>8</bitOffset> 14339 <bitWidth>1</bitWidth> 14340 <enumeratedValues> 14341 <enumeratedValue> 14342 <name>noEvent</name> 14343 <description>The event has not occurred.</description> 14344 <value>0</value> 14345 </enumeratedValue> 14346 <enumeratedValue> 14347 <name>occurred</name> 14348 <description>The event has occurred.</description> 14349 <value>1</value> 14350 </enumeratedValue> 14351 </enumeratedValues> 14352 </field> 14353 <field> 14354 <name>VCORELO</name> 14355 <description>VCORE Undervoltage Detect Flag.</description> 14356 <bitOffset>9</bitOffset> 14357 <bitWidth>1</bitWidth> 14358 <enumeratedValues> 14359 <enumeratedValue> 14360 <name>noEvent</name> 14361 <description>The event has not occurred.</description> 14362 <value>0</value> 14363 </enumeratedValue> 14364 <enumeratedValue> 14365 <name>occurred</name> 14366 <description>The event has occurred.</description> 14367 <value>1</value> 14368 </enumeratedValue> 14369 </enumeratedValues> 14370 </field> 14371 <field> 14372 <name>VCOREHI</name> 14373 <description>VCORE Overvoltage Detect Flag.</description> 14374 <bitOffset>10</bitOffset> 14375 <bitWidth>1</bitWidth> 14376 <enumeratedValues> 14377 <enumeratedValue> 14378 <name>noEvent</name> 14379 <description>The event has not occurred.</description> 14380 <value>0</value> 14381 </enumeratedValue> 14382 <enumeratedValue> 14383 <name>occurred</name> 14384 <description>The event has occurred.</description> 14385 <value>1</value> 14386 </enumeratedValue> 14387 </enumeratedValues> 14388 </field> 14389 <field> 14390 <name>VDDHI</name> 14391 <description>VDD Overvoltage Flag.</description> 14392 <bitOffset>11</bitOffset> 14393 <bitWidth>1</bitWidth> 14394 <enumeratedValues> 14395 <enumeratedValue> 14396 <name>noEvent</name> 14397 <description>The event has not occurred.</description> 14398 <value>0</value> 14399 </enumeratedValue> 14400 <enumeratedValue> 14401 <name>occurred</name> 14402 <description>The event has occurred.</description> 14403 <value>1</value> 14404 </enumeratedValue> 14405 </enumeratedValues> 14406 </field> 14407 <field> 14408 <name>VGL</name> 14409 <description>Voltage Glitch Detection Flag.</description> 14410 <bitOffset>12</bitOffset> 14411 <bitWidth>1</bitWidth> 14412 <enumeratedValues> 14413 <enumeratedValue> 14414 <name>noEvent</name> 14415 <description>The event has not occurred.</description> 14416 <value>0</value> 14417 </enumeratedValue> 14418 <enumeratedValue> 14419 <name>occurred</name> 14420 <description>The event has occurred.</description> 14421 <value>1</value> 14422 </enumeratedValue> 14423 </enumeratedValues> 14424 </field> 14425 <field> 14426 <name>EXTSTAT0</name> 14427 <description>External Sensor 0 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.</description> 14428 <bitOffset>16</bitOffset> 14429 <bitWidth>1</bitWidth> 14430 <enumeratedValues> 14431 <enumeratedValue> 14432 <name>noEvent</name> 14433 <description>The event has not occurred.</description> 14434 <value>0</value> 14435 </enumeratedValue> 14436 <enumeratedValue> 14437 <name>occurred</name> 14438 <description>The event has occurred.</description> 14439 <value>1</value> 14440 </enumeratedValue> 14441 </enumeratedValues> 14442 </field> 14443 <field> 14444 <name>EXTSTAT1</name> 14445 <description>External Sensor 1 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.</description> 14446 <bitOffset>17</bitOffset> 14447 <bitWidth>1</bitWidth> 14448 <enumeratedValues> 14449 <enumeratedValue> 14450 <name>noEvent</name> 14451 <description>The event has not occurred.</description> 14452 <value>0</value> 14453 </enumeratedValue> 14454 <enumeratedValue> 14455 <name>occurred</name> 14456 <description>The event has occurred.</description> 14457 <value>1</value> 14458 </enumeratedValue> 14459 </enumeratedValues> 14460 </field> 14461 <field> 14462 <name>EXTSTAT2</name> 14463 <description>External Sensor 2 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.</description> 14464 <bitOffset>18</bitOffset> 14465 <bitWidth>1</bitWidth> 14466 <enumeratedValues> 14467 <enumeratedValue> 14468 <name>noEvent</name> 14469 <description>The event has not occurred.</description> 14470 <value>0</value> 14471 </enumeratedValue> 14472 <enumeratedValue> 14473 <name>occurred</name> 14474 <description>The event has occurred.</description> 14475 <value>1</value> 14476 </enumeratedValue> 14477 </enumeratedValues> 14478 </field> 14479 <field> 14480 <name>EXTSTAT3</name> 14481 <description>External Sensor 3 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.</description> 14482 <bitOffset>19</bitOffset> 14483 <bitWidth>1</bitWidth> 14484 <enumeratedValues> 14485 <enumeratedValue> 14486 <name>noEvent</name> 14487 <description>The event has not occurred.</description> 14488 <value>0</value> 14489 </enumeratedValue> 14490 <enumeratedValue> 14491 <name>occurred</name> 14492 <description>The event has occurred.</description> 14493 <value>1</value> 14494 </enumeratedValue> 14495 </enumeratedValues> 14496 </field> 14497 <field> 14498 <name>EXTSTAT4</name> 14499 <description>External Sensor 4 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.</description> 14500 <bitOffset>20</bitOffset> 14501 <bitWidth>1</bitWidth> 14502 <enumeratedValues> 14503 <enumeratedValue> 14504 <name>noEvent</name> 14505 <description>The event has not occurred.</description> 14506 <value>0</value> 14507 </enumeratedValue> 14508 <enumeratedValue> 14509 <name>occurred</name> 14510 <description>The event has occurred.</description> 14511 <value>1</value> 14512 </enumeratedValue> 14513 </enumeratedValues> 14514 </field> 14515 <field> 14516 <name>EXTSTAT5</name> 14517 <description>External Sensor 5 Detect. The tamper detect is only active when it is enabled. This bits needs to be cleared in software after a tamper event to re-arm the sensor.</description> 14518 <bitOffset>21</bitOffset> 14519 <bitWidth>1</bitWidth> 14520 <enumeratedValues> 14521 <enumeratedValue> 14522 <name>noEvent</name> 14523 <description>The event has not occurred.</description> 14524 <value>0</value> 14525 </enumeratedValue> 14526 <enumeratedValue> 14527 <name>occurred</name> 14528 <description>The event has occurred.</description> 14529 <value>1</value> 14530 </enumeratedValue> 14531 </enumeratedValues> 14532 </field> 14533 <field> 14534 <name>EXTSWARN0</name> 14535 <description>External Sensor 0 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.</description> 14536 <bitOffset>24</bitOffset> 14537 <bitWidth>1</bitWidth> 14538 <enumeratedValues> 14539 <enumeratedValue> 14540 <name>noEvent</name> 14541 <description>The event has not occurred.</description> 14542 <value>0</value> 14543 </enumeratedValue> 14544 <enumeratedValue> 14545 <name>occurred</name> 14546 <description>The event has occurred.</description> 14547 <value>1</value> 14548 </enumeratedValue> 14549 </enumeratedValues> 14550 </field> 14551 <field> 14552 <name>EXTSWARN1</name> 14553 <description>External Sensor 1 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.</description> 14554 <bitOffset>25</bitOffset> 14555 <bitWidth>1</bitWidth> 14556 <enumeratedValues> 14557 <enumeratedValue> 14558 <name>noEvent</name> 14559 <description>The event has not occurred.</description> 14560 <value>0</value> 14561 </enumeratedValue> 14562 <enumeratedValue> 14563 <name>occurred</name> 14564 <description>The event has occurred.</description> 14565 <value>1</value> 14566 </enumeratedValue> 14567 </enumeratedValues> 14568 </field> 14569 <field> 14570 <name>EXTSWARN2</name> 14571 <description>External Sensor 2 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.</description> 14572 <bitOffset>26</bitOffset> 14573 <bitWidth>1</bitWidth> 14574 <enumeratedValues> 14575 <enumeratedValue> 14576 <name>noEvent</name> 14577 <description>The event has not occurred.</description> 14578 <value>0</value> 14579 </enumeratedValue> 14580 <enumeratedValue> 14581 <name>occurred</name> 14582 <description>The event has occurred.</description> 14583 <value>1</value> 14584 </enumeratedValue> 14585 </enumeratedValues> 14586 </field> 14587 <field> 14588 <name>EXTSWARN3</name> 14589 <description>External Sensor 3 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.</description> 14590 <bitOffset>27</bitOffset> 14591 <bitWidth>1</bitWidth> 14592 <enumeratedValues> 14593 <enumeratedValue> 14594 <name>noEvent</name> 14595 <description>The event has not occurred.</description> 14596 <value>0</value> 14597 </enumeratedValue> 14598 <enumeratedValue> 14599 <name>occurred</name> 14600 <description>The event has occurred.</description> 14601 <value>1</value> 14602 </enumeratedValue> 14603 </enumeratedValues> 14604 </field> 14605 <field> 14606 <name>EXTSWARN4</name> 14607 <description>External Sensor 4 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.</description> 14608 <bitOffset>28</bitOffset> 14609 <bitWidth>1</bitWidth> 14610 <enumeratedValues> 14611 <enumeratedValue> 14612 <name>noEvent</name> 14613 <description>The event has not occurred.</description> 14614 <value>0</value> 14615 </enumeratedValue> 14616 <enumeratedValue> 14617 <name>occurred</name> 14618 <description>The event has occurred.</description> 14619 <value>1</value> 14620 </enumeratedValue> 14621 </enumeratedValues> 14622 </field> 14623 <field> 14624 <name>EXTSWARN5</name> 14625 <description>External Sensor 5 Warning Ready flag. The tamper detect warning flags are set, regardless of whether the external sensors are enabled.</description> 14626 <bitOffset>29</bitOffset> 14627 <bitWidth>1</bitWidth> 14628 <enumeratedValues> 14629 <enumeratedValue> 14630 <name>noEvent</name> 14631 <description>The event has not occurred.</description> 14632 <value>0</value> 14633 </enumeratedValue> 14634 <enumeratedValue> 14635 <name>occurred</name> 14636 <description>The event has occurred.</description> 14637 <value>1</value> 14638 </enumeratedValue> 14639 </enumeratedValues> 14640 </field> 14641 </fields> 14642 </register> 14643 <register> 14644 <name>SECDIAG</name> 14645 <description>Security Diagnostic Register.</description> 14646 <addressOffset>0x0C</addressOffset> 14647 <access>read-only</access> 14648 <resetValue>0x00000001</resetValue> 14649 <resetMask>0xFFC0FE02</resetMask> 14650 <fields> 14651 <field> 14652 <name>BORF</name> 14653 <description>Battery-On-Reset Flag. This bit is set once the back up battery is conneted.</description> 14654 <bitOffset>0</bitOffset> 14655 <bitWidth>1</bitWidth> 14656 <enumeratedValues> 14657 <enumeratedValue> 14658 <name>noEvent</name> 14659 <description>The event has not occurred.</description> 14660 <value>0</value> 14661 </enumeratedValue> 14662 <enumeratedValue> 14663 <name>occurred</name> 14664 <description>The event has occurred.</description> 14665 <value>1</value> 14666 </enumeratedValue> 14667 </enumeratedValues> 14668 </field> 14669 <field> 14670 <name>SHIELDF</name> 14671 <description>Die Shield Flag.</description> 14672 <bitOffset>2</bitOffset> 14673 <bitWidth>1</bitWidth> 14674 <enumeratedValues> 14675 <enumeratedValue> 14676 <name>noEvent</name> 14677 <description>The event has not occurred.</description> 14678 <value>0</value> 14679 </enumeratedValue> 14680 <enumeratedValue> 14681 <name>occurred</name> 14682 <description>The event has occurred.</description> 14683 <value>1</value> 14684 </enumeratedValue> 14685 </enumeratedValues> 14686 </field> 14687 <field> 14688 <name>LOTEMP</name> 14689 <description>Low Temperature Detect.</description> 14690 <bitOffset>3</bitOffset> 14691 <bitWidth>1</bitWidth> 14692 <enumeratedValues> 14693 <enumeratedValue> 14694 <name>noEvent</name> 14695 <description>The event has not occurred.</description> 14696 <value>0</value> 14697 </enumeratedValue> 14698 <enumeratedValue> 14699 <name>occurred</name> 14700 <description>The event has occurred.</description> 14701 <value>1</value> 14702 </enumeratedValue> 14703 </enumeratedValues> 14704 </field> 14705 <field> 14706 <name>HITEMP</name> 14707 <description>High Temperature Detect.</description> 14708 <bitOffset>4</bitOffset> 14709 <bitWidth>1</bitWidth> 14710 <enumeratedValues> 14711 <enumeratedValue> 14712 <name>noEvent</name> 14713 <description>The event has not occurred.</description> 14714 <value>0</value> 14715 </enumeratedValue> 14716 <enumeratedValue> 14717 <name>occurred</name> 14718 <description>The event has occurred.</description> 14719 <value>1</value> 14720 </enumeratedValue> 14721 </enumeratedValues> 14722 </field> 14723 <field> 14724 <name>BATLO</name> 14725 <description>Battery Undervoltage Detect.</description> 14726 <bitOffset>5</bitOffset> 14727 <bitWidth>1</bitWidth> 14728 <enumeratedValues> 14729 <enumeratedValue> 14730 <name>noEvent</name> 14731 <description>The event has not occurred.</description> 14732 <value>0</value> 14733 </enumeratedValue> 14734 <enumeratedValue> 14735 <name>occurred</name> 14736 <description>The event has occurred.</description> 14737 <value>1</value> 14738 </enumeratedValue> 14739 </enumeratedValues> 14740 </field> 14741 <field> 14742 <name>BATHI</name> 14743 <description>Battery Overvoltage Detect.</description> 14744 <bitOffset>6</bitOffset> 14745 <bitWidth>1</bitWidth> 14746 <enumeratedValues> 14747 <enumeratedValue> 14748 <name>noEvent</name> 14749 <description>The event has not occurred.</description> 14750 <value>0</value> 14751 </enumeratedValue> 14752 <enumeratedValue> 14753 <name>occurred</name> 14754 <description>The event has occurred.</description> 14755 <value>1</value> 14756 </enumeratedValue> 14757 </enumeratedValues> 14758 </field> 14759 <field> 14760 <name>DYNF</name> 14761 <description>Dynamic Sensor Flag. This bit is set to 1 when any of the EXTSTAT bits are set.</description> 14762 <bitOffset>7</bitOffset> 14763 <bitWidth>1</bitWidth> 14764 <enumeratedValues> 14765 <enumeratedValue> 14766 <name>noEvent</name> 14767 <description>The event has not occurred.</description> 14768 <value>0</value> 14769 </enumeratedValue> 14770 <enumeratedValue> 14771 <name>occurred</name> 14772 <description>The event has occurred.</description> 14773 <value>1</value> 14774 </enumeratedValue> 14775 </enumeratedValues> 14776 </field> 14777 <field> 14778 <name>AESKT</name> 14779 <description>AES Key Transfer. This bit is set to 1 when AES Key has been transferred from the TRNG to the battery backed AES key register. This bit can only be reset by a BOR.</description> 14780 <bitOffset>8</bitOffset> 14781 <bitWidth>1</bitWidth> 14782 <enumeratedValues> 14783 <enumeratedValue> 14784 <name>incomplete</name> 14785 <description>Key has not been transferred.</description> 14786 <value>0</value> 14787 </enumeratedValue> 14788 <enumeratedValue> 14789 <name>complete</name> 14790 <description>Key has been transferred.</description> 14791 <value>1</value> 14792 </enumeratedValue> 14793 </enumeratedValues> 14794 </field> 14795 <field> 14796 <name>EXTSTAT0</name> 14797 <description>External Sensor 0 Detect.</description> 14798 <bitOffset>16</bitOffset> 14799 <bitWidth>1</bitWidth> 14800 <enumeratedValues> 14801 <enumeratedValue> 14802 <name>noEvent</name> 14803 <description>The event has not occurred.</description> 14804 <value>0</value> 14805 </enumeratedValue> 14806 <enumeratedValue> 14807 <name>occurred</name> 14808 <description>The event has occurred.</description> 14809 <value>1</value> 14810 </enumeratedValue> 14811 </enumeratedValues> 14812 </field> 14813 <field> 14814 <name>EXTSTAT1</name> 14815 <description>External Sensor 1 Detect.</description> 14816 <bitOffset>17</bitOffset> 14817 <bitWidth>1</bitWidth> 14818 <enumeratedValues> 14819 <enumeratedValue> 14820 <name>noEvent</name> 14821 <description>The event has not occurred.</description> 14822 <value>0</value> 14823 </enumeratedValue> 14824 <enumeratedValue> 14825 <name>occurred</name> 14826 <description>The event has occurred.</description> 14827 <value>1</value> 14828 </enumeratedValue> 14829 </enumeratedValues> 14830 </field> 14831 <field> 14832 <name>EXTSTAT2</name> 14833 <description>External Sensor 2 Detect.</description> 14834 <bitOffset>18</bitOffset> 14835 <bitWidth>1</bitWidth> 14836 <enumeratedValues> 14837 <enumeratedValue> 14838 <name>noEvent</name> 14839 <description>The event has not occurred.</description> 14840 <value>0</value> 14841 </enumeratedValue> 14842 <enumeratedValue> 14843 <name>occurred</name> 14844 <description>The event has occurred.</description> 14845 <value>1</value> 14846 </enumeratedValue> 14847 </enumeratedValues> 14848 </field> 14849 <field> 14850 <name>EXTSTAT3</name> 14851 <description>External Sensor 3 Detect.</description> 14852 <bitOffset>19</bitOffset> 14853 <bitWidth>1</bitWidth> 14854 <enumeratedValues> 14855 <enumeratedValue> 14856 <name>noEvent</name> 14857 <description>The event has not occurred.</description> 14858 <value>0</value> 14859 </enumeratedValue> 14860 <enumeratedValue> 14861 <name>occurred</name> 14862 <description>The event has occurred.</description> 14863 <value>1</value> 14864 </enumeratedValue> 14865 </enumeratedValues> 14866 </field> 14867 <field> 14868 <name>EXTSTAT4</name> 14869 <description>External Sensor 4 Detect.</description> 14870 <bitOffset>20</bitOffset> 14871 <bitWidth>1</bitWidth> 14872 <enumeratedValues> 14873 <enumeratedValue> 14874 <name>noEvent</name> 14875 <description>The event has not occurred.</description> 14876 <value>0</value> 14877 </enumeratedValue> 14878 <enumeratedValue> 14879 <name>occurred</name> 14880 <description>The event has occurred.</description> 14881 <value>1</value> 14882 </enumeratedValue> 14883 </enumeratedValues> 14884 </field> 14885 <field> 14886 <name>EXTSTAT5</name> 14887 <description>External Sensor 5 Detect.</description> 14888 <bitOffset>21</bitOffset> 14889 <bitWidth>1</bitWidth> 14890 <enumeratedValues> 14891 <enumeratedValue> 14892 <name>noEvent</name> 14893 <description>The event has not occurred.</description> 14894 <value>0</value> 14895 </enumeratedValue> 14896 <enumeratedValue> 14897 <name>occurred</name> 14898 <description>The event has occurred.</description> 14899 <value>1</value> 14900 </enumeratedValue> 14901 </enumeratedValues> 14902 </field> 14903 </fields> 14904 </register> 14905 <register> 14906 <name>DLRTC</name> 14907 <description>DRS Log RTC Value. This register contains the 32 bit value in the RTC second register when the last DRS event occurred.</description> 14908 <addressOffset>0x10</addressOffset> 14909 <access>read-only</access> 14910 <resetMask>0x00000000</resetMask> 14911 <fields> 14912 <field> 14913 <name>DLRTC</name> 14914 <description>DRS Log RTC Value. This register contains the 32 bit value in the RTC second register when the last DRS event occured.</description> 14915 <bitOffset>0</bitOffset> 14916 <bitWidth>32</bitWidth> 14917 </field> 14918 </fields> 14919 </register> 14920 <register> 14921 <name>MEUCFG</name> 14922 <description>MEU Configuration</description> 14923 <addressOffset>0x24</addressOffset> 14924 <resetMask>0x00000000</resetMask> 14925 <fields> 14926 <field> 14927 <name>MEUCFG</name> 14928 <description>Configuration plain/encrypted area of the backed NVSRAM.</description> 14929 <bitOffset>0</bitOffset> 14930 <bitWidth>7</bitWidth> 14931 </field> 14932 </fields> 14933 </register> 14934 <register> 14935 <name>SECST</name> 14936 <description>Security Monitor Status Register.</description> 14937 <addressOffset>0x34</addressOffset> 14938 <access>read-only</access> 14939 <fields> 14940 <field> 14941 <name>EXTSRS</name> 14942 <description>External Sensor Control Register Status.</description> 14943 <bitOffset>0</bitOffset> 14944 <bitWidth>1</bitWidth> 14945 <enumeratedValues> 14946 <enumeratedValue> 14947 <name>allowed</name> 14948 <description>Access authorized.</description> 14949 <value>0</value> 14950 </enumeratedValue> 14951 <enumeratedValue> 14952 <name>notAllowed</name> 14953 <description>Access not authorized.</description> 14954 <value>1</value> 14955 </enumeratedValue> 14956 </enumeratedValues> 14957 </field> 14958 <field> 14959 <name>INTSRS</name> 14960 <description>Internal Sensor Control Register Status.</description> 14961 <bitOffset>1</bitOffset> 14962 <bitWidth>1</bitWidth> 14963 <enumeratedValues> 14964 <enumeratedValue> 14965 <name>allowed</name> 14966 <description>Access authorized.</description> 14967 <value>0</value> 14968 </enumeratedValue> 14969 <enumeratedValue> 14970 <name>notAllowed</name> 14971 <description>Access not authorized.</description> 14972 <value>1</value> 14973 </enumeratedValue> 14974 </enumeratedValues> 14975 </field> 14976 <field> 14977 <name>SECALRS</name> 14978 <description>Security Alarm Register Status.</description> 14979 <bitOffset>2</bitOffset> 14980 <bitWidth>1</bitWidth> 14981 <enumeratedValues> 14982 <enumeratedValue> 14983 <name>allowed</name> 14984 <description>Access authorized.</description> 14985 <value>0</value> 14986 </enumeratedValue> 14987 <enumeratedValue> 14988 <name>notAllowed</name> 14989 <description>Access not authorized.</description> 14990 <value>1</value> 14991 </enumeratedValue> 14992 </enumeratedValues> 14993 </field> 14994 </fields> 14995 </register> 14996 <register> 14997 <name>SDBE</name> 14998 <description>Security Monitor Self Destruct Byte.</description> 14999 <addressOffset>0x38</addressOffset> 15000 <fields> 15001 <field> 15002 <name>DBYTE</name> 15003 <description>Self Destruct Byte</description> 15004 <bitOffset>0</bitOffset> 15005 <bitWidth>8</bitWidth> 15006 </field> 15007 <field> 15008 <name>SBDEN</name> 15009 <description>Self-Destruct Byte ENable.</description> 15010 <bitOffset>31</bitOffset> 15011 <bitWidth>1</bitWidth> 15012 </field> 15013 </fields> 15014 </register> 15015 </registers> 15016 </peripheral> 15017<!--SMON The Security Monitor block used to monitor system threat conditions.--> 15018 <peripheral> 15019 <name>SPI0</name> 15020 <description>SPI peripheral.</description> 15021 <baseAddress>0x40046000</baseAddress> 15022 <addressBlock> 15023 <offset>0x00</offset> 15024 <size>0x1000</size> 15025 <usage>registers</usage> 15026 </addressBlock> 15027 <interrupt> 15028 <name>SPI0</name> 15029 <value>16</value> 15030 </interrupt> 15031 <registers> 15032 <register> 15033 <name>FIFO32</name> 15034 <description>Register for reading and writing the FIFO.</description> 15035 <addressOffset>0x00</addressOffset> 15036 <size>32</size> 15037 <access>read-write</access> 15038 <fields> 15039 <field> 15040 <name>DATA</name> 15041 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 15042 <bitOffset>0</bitOffset> 15043 <bitWidth>32</bitWidth> 15044 </field> 15045 </fields> 15046 </register> 15047 <register> 15048 <dim>2</dim> 15049 <dimIncrement>2</dimIncrement> 15050 <name>FIFO16[%s]</name> 15051 <description>Register for reading and writing the FIFO.</description> 15052 <alternateRegister>FIFO32</alternateRegister> 15053 <addressOffset>0x00</addressOffset> 15054 <size>16</size> 15055 <access>read-write</access> 15056 <fields> 15057 <field> 15058 <name>DATA</name> 15059 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 15060 <bitOffset>0</bitOffset> 15061 <bitWidth>16</bitWidth> 15062 </field> 15063 </fields> 15064 </register> 15065 <register> 15066 <dim>4</dim> 15067 <dimIncrement>1</dimIncrement> 15068 <name>FIFO8[%s]</name> 15069 <description>Register for reading and writing the FIFO.</description> 15070 <alternateRegister>FIFO32</alternateRegister> 15071 <addressOffset>0x00</addressOffset> 15072 <size>8</size> 15073 <access>read-write</access> 15074 <fields> 15075 <field> 15076 <name>DATA</name> 15077 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 15078 <bitOffset>0</bitOffset> 15079 <bitWidth>8</bitWidth> 15080 </field> 15081 </fields> 15082 </register> 15083 <register> 15084 <name>CTRL0</name> 15085 <description>Register for controlling SPI peripheral.</description> 15086 <addressOffset>0x04</addressOffset> 15087 <access>read-write</access> 15088 <fields> 15089 <field> 15090 <name>EN</name> 15091 <description>SPI Enable.</description> 15092 <bitOffset>0</bitOffset> 15093 <bitWidth>1</bitWidth> 15094 <enumeratedValues> 15095 <enumeratedValue> 15096 <name>dis</name> 15097 <description>SPI is disabled.</description> 15098 <value>0</value> 15099 </enumeratedValue> 15100 <enumeratedValue> 15101 <name>en</name> 15102 <description>SPI is enabled.</description> 15103 <value>1</value> 15104 </enumeratedValue> 15105 </enumeratedValues> 15106 </field> 15107 <field> 15108 <name>MST_MODE</name> 15109 <description>Master Mode Enable.</description> 15110 <bitOffset>1</bitOffset> 15111 <bitWidth>1</bitWidth> 15112 <enumeratedValues> 15113 <enumeratedValue> 15114 <name>dis</name> 15115 <description>SPI is Slave mode.</description> 15116 <value>0</value> 15117 </enumeratedValue> 15118 <enumeratedValue> 15119 <name>en</name> 15120 <description>SPI is Master mode.</description> 15121 <value>1</value> 15122 </enumeratedValue> 15123 </enumeratedValues> 15124 </field> 15125 <field> 15126 <name>SS_IO</name> 15127 <description>Slave Select 0, IO direction, to support Multi-Master mode,Slave Select 0 can be input in Master mode. This bit has no effect in slave mode.</description> 15128 <bitOffset>4</bitOffset> 15129 <bitWidth>1</bitWidth> 15130 <enumeratedValues> 15131 <enumeratedValue> 15132 <name>output</name> 15133 <description>Slave select 0 is output.</description> 15134 <value>0</value> 15135 </enumeratedValue> 15136 <enumeratedValue> 15137 <name>input</name> 15138 <description>Slave Select 0 is input, only valid if MMEN=1.</description> 15139 <value>1</value> 15140 </enumeratedValue> 15141 </enumeratedValues> 15142 </field> 15143 <field> 15144 <name>START</name> 15145 <description>Start Transmit.</description> 15146 <bitOffset>5</bitOffset> 15147 <bitWidth>1</bitWidth> 15148 <enumeratedValues> 15149 <enumeratedValue> 15150 <name>start</name> 15151 <description>Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction.</description> 15152 <value>1</value> 15153 </enumeratedValue> 15154 </enumeratedValues> 15155 </field> 15156 <field> 15157 <name>SS_CTRL</name> 15158 <description>Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction.</description> 15159 <bitOffset>8</bitOffset> 15160 <bitWidth>1</bitWidth> 15161 <enumeratedValues> 15162 <enumeratedValue> 15163 <name>DEASSERT</name> 15164 <description>SPI De-asserts Slave Select at the end of a transaction.</description> 15165 <value>0</value> 15166 </enumeratedValue> 15167 <enumeratedValue> 15168 <name>ASSERT</name> 15169 <description>SPI leaves Slave Select asserted at the end of a transaction.</description> 15170 <value>1</value> 15171 </enumeratedValue> 15172 </enumeratedValues> 15173 </field> 15174 <field> 15175 <name>SS_ACTIVE</name> 15176 <description>Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected.</description> 15177 <bitOffset>16</bitOffset> 15178 <bitWidth>4</bitWidth> 15179 <enumeratedValues> 15180 <enumeratedValue> 15181 <name>SS0</name> 15182 <description>SS0 is selected.</description> 15183 <value>0x1</value> 15184 </enumeratedValue> 15185 <enumeratedValue> 15186 <name>SS1</name> 15187 <description>SS1 is selected.</description> 15188 <value>0x2</value> 15189 </enumeratedValue> 15190 <enumeratedValue> 15191 <name>SS2</name> 15192 <description>SS2 is selected.</description> 15193 <value>0x4</value> 15194 </enumeratedValue> 15195 <enumeratedValue> 15196 <name>SS3</name> 15197 <description>SS3 is selected.</description> 15198 <value>0x8</value> 15199 </enumeratedValue> 15200 </enumeratedValues> 15201 </field> 15202 </fields> 15203 </register> 15204 <register> 15205 <name>CTRL1</name> 15206 <description>Register for controlling SPI peripheral.</description> 15207 <addressOffset>0x08</addressOffset> 15208 <access>read-write</access> 15209 <fields> 15210 <field> 15211 <name>TX_NUM_CHAR</name> 15212 <description>Nubmer of Characters to transmit.</description> 15213 <bitOffset>0</bitOffset> 15214 <bitWidth>16</bitWidth> 15215 </field> 15216 <field> 15217 <name>RX_NUM_CHAR</name> 15218 <description>Nubmer of Characters to receive.</description> 15219 <bitOffset>16</bitOffset> 15220 <bitWidth>16</bitWidth> 15221 </field> 15222 </fields> 15223 </register> 15224 <register> 15225 <name>CTRL2</name> 15226 <description>Register for controlling SPI peripheral.</description> 15227 <addressOffset>0x0C</addressOffset> 15228 <access>read-write</access> 15229 <fields> 15230 <field> 15231 <name>CLKPHA</name> 15232 <description>Clock Phase.</description> 15233 <bitOffset>0</bitOffset> 15234 <bitWidth>1</bitWidth> 15235 <enumeratedValues> 15236 <enumeratedValue> 15237 <name>Rising_Edge</name> 15238 <description>Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2 </description> 15239 <value>0</value> 15240 </enumeratedValue> 15241 <enumeratedValue> 15242 <name>Falling_Edge</name> 15243 <description>Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3</description> 15244 <value>1</value> 15245 </enumeratedValue> 15246 </enumeratedValues> 15247 </field> 15248 <field> 15249 <name>CLKPOL</name> 15250 <description>Clock Polarity.</description> 15251 <bitOffset>1</bitOffset> 15252 <bitWidth>1</bitWidth> 15253 <enumeratedValues> 15254 <enumeratedValue> 15255 <name>Normal</name> 15256 <description>Normal Clock. Use when in SPI Mode 0 and Mode 1</description> 15257 <value>0</value> 15258 </enumeratedValue> 15259 <enumeratedValue> 15260 <name>Inverted</name> 15261 <description>Inverted Clock. Use when in SPI Mode 2 and Mode 3</description> 15262 <value>1</value> 15263 </enumeratedValue> 15264 </enumeratedValues> 15265 </field> 15266 <field> 15267 <name>SCLK_FB_INV</name> 15268 <description>Clock Polarity.</description> 15269 <bitOffset>4</bitOffset> 15270 <bitWidth>1</bitWidth> 15271 <enumeratedValues> 15272 <enumeratedValue> 15273 <name>Normal</name> 15274 <description>Normal Clock. Use when in SPI Mode 0 and Mode 1</description> 15275 <value>0</value> 15276 </enumeratedValue> 15277 <enumeratedValue> 15278 <name>Inverted</name> 15279 <description>Inverted Clock. Use when in SPI Mode 2 and Mode 3</description> 15280 <value>1</value> 15281 </enumeratedValue> 15282 </enumeratedValues> 15283 </field> 15284 <field> 15285 <name>NUMBITS</name> 15286 <description>Number of Bits per character.</description> 15287 <bitOffset>8</bitOffset> 15288 <bitWidth>4</bitWidth> 15289 <enumeratedValues> 15290 <enumeratedValue> 15291 <name>16</name> 15292 <description>16 bits per character.</description> 15293 <value>0</value> 15294 </enumeratedValue> 15295 <enumeratedValue> 15296 <name>1</name> 15297 <description>1 bits per character.</description> 15298 <value>1</value> 15299 </enumeratedValue> 15300 <enumeratedValue> 15301 <name>2</name> 15302 <description>2 bits per character.</description> 15303 <value>2</value> 15304 </enumeratedValue> 15305 <enumeratedValue> 15306 <name>3</name> 15307 <description>3 bits per character.</description> 15308 <value>3</value> 15309 </enumeratedValue> 15310 <enumeratedValue> 15311 <name>4</name> 15312 <description>4 bits per character.</description> 15313 <value>4</value> 15314 </enumeratedValue> 15315 <enumeratedValue> 15316 <name>5</name> 15317 <description>5 bits per character.</description> 15318 <value>5</value> 15319 </enumeratedValue> 15320 <enumeratedValue> 15321 <name>6</name> 15322 <description>6 bits per character.</description> 15323 <value>6</value> 15324 </enumeratedValue> 15325 <enumeratedValue> 15326 <name>7</name> 15327 <description>7 bits per character.</description> 15328 <value>7</value> 15329 </enumeratedValue> 15330 <enumeratedValue> 15331 <name>8</name> 15332 <description>8 bits per character.</description> 15333 <value>8</value> 15334 </enumeratedValue> 15335 <enumeratedValue> 15336 <name>9</name> 15337 <description>9 bits per character.</description> 15338 <value>9</value> 15339 </enumeratedValue> 15340 <enumeratedValue> 15341 <name>10</name> 15342 <description>10 bits per character.</description> 15343 <value>10</value> 15344 </enumeratedValue> 15345 <enumeratedValue> 15346 <name>11</name> 15347 <description>11 bits per character.</description> 15348 <value>11</value> 15349 </enumeratedValue> 15350 <enumeratedValue> 15351 <name>12</name> 15352 <description>12 bits per character.</description> 15353 <value>12</value> 15354 </enumeratedValue> 15355 <enumeratedValue> 15356 <name>13</name> 15357 <description>13 bits per character.</description> 15358 <value>13</value> 15359 </enumeratedValue> 15360 <enumeratedValue> 15361 <name>14</name> 15362 <description>14 bits per character.</description> 15363 <value>14</value> 15364 </enumeratedValue> 15365 <enumeratedValue> 15366 <name>15</name> 15367 <description>15 bits per character.</description> 15368 <value>15</value> 15369 </enumeratedValue> 15370 </enumeratedValues> 15371 </field> 15372 <field> 15373 <name>DATA_WIDTH</name> 15374 <description>SPI Data width.</description> 15375 <bitOffset>12</bitOffset> 15376 <bitWidth>2</bitWidth> 15377 <enumeratedValues> 15378 <enumeratedValue> 15379 <name>Mono</name> 15380 <description>1 data pin.</description> 15381 <value>0</value> 15382 </enumeratedValue> 15383 <enumeratedValue> 15384 <name>Dual</name> 15385 <description>2 data pins.</description> 15386 <value>1</value> 15387 </enumeratedValue> 15388 <enumeratedValue> 15389 <name>Quad</name> 15390 <description>4 data pins.</description> 15391 <value>2</value> 15392 </enumeratedValue> 15393 </enumeratedValues> 15394 </field> 15395 <field> 15396 <name>THREE_WIRE</name> 15397 <description>Three Wire mode. MOSI/MISO pin (s) shared. Only Mono mode suports Four-Wire.</description> 15398 <bitOffset>15</bitOffset> 15399 <bitWidth>1</bitWidth> 15400 <enumeratedValues> 15401 <enumeratedValue> 15402 <name>dis</name> 15403 <description>Use four wire mode (Mono only).</description> 15404 <value>0</value> 15405 </enumeratedValue> 15406 <enumeratedValue> 15407 <name>en</name> 15408 <description>Use three wire mode.</description> 15409 <value>1</value> 15410 </enumeratedValue> 15411 </enumeratedValues> 15412 </field> 15413 <field> 15414 <name>SS_POL</name> 15415 <description>Slave Select Polarity, each Slave Select can have unique polarity.</description> 15416 <bitOffset>16</bitOffset> 15417 <bitWidth>8</bitWidth> 15418 <enumeratedValues> 15419 <enumeratedValue> 15420 <name>SS0_high</name> 15421 <description>SS0 active high.</description> 15422 <value>0x1</value> 15423 </enumeratedValue> 15424 <enumeratedValue> 15425 <name>SS1_high</name> 15426 <description>SS1 active high.</description> 15427 <value>0x2</value> 15428 </enumeratedValue> 15429 <enumeratedValue> 15430 <name>SS2_high</name> 15431 <description>SS2 active high.</description> 15432 <value>0x4</value> 15433 </enumeratedValue> 15434 <enumeratedValue> 15435 <name>SS3_high</name> 15436 <description>SS3 active high.</description> 15437 <value>0x8</value> 15438 </enumeratedValue> 15439 </enumeratedValues> 15440 </field> 15441 </fields> 15442 </register> 15443 <register> 15444 <name>SSTIME</name> 15445 <description>Register for controlling SPI peripheral/Slave Select Timing.</description> 15446 <addressOffset>0x10</addressOffset> 15447 <access>read-write</access> 15448 <fields> 15449 <field> 15450 <name>PRE</name> 15451 <description>Slave Select Pre delay 1.</description> 15452 <bitOffset>0</bitOffset> 15453 <bitWidth>8</bitWidth> 15454 <enumeratedValues> 15455 <enumeratedValue> 15456 <name>256</name> 15457 <description>256 system clocks between SS active and first serial clock edge.</description> 15458 <value>0</value> 15459 </enumeratedValue> 15460 </enumeratedValues> 15461 </field> 15462 <field> 15463 <name>POST</name> 15464 <description>Slave Select Post delay 2.</description> 15465 <bitOffset>8</bitOffset> 15466 <bitWidth>8</bitWidth> 15467 <enumeratedValues> 15468 <enumeratedValue> 15469 <name>256</name> 15470 <description>256 system clocks between last serial clock edge and SS inactive.</description> 15471 <value>0</value> 15472 </enumeratedValue> 15473 </enumeratedValues> 15474 </field> 15475 <field> 15476 <name>INACT</name> 15477 <description>Slave Select Inactive delay.</description> 15478 <bitOffset>16</bitOffset> 15479 <bitWidth>8</bitWidth> 15480 <enumeratedValues> 15481 <enumeratedValue> 15482 <name>256</name> 15483 <description>256 system clocks between transactions.</description> 15484 <value>0</value> 15485 </enumeratedValue> 15486 </enumeratedValues> 15487 </field> 15488 </fields> 15489 </register> 15490 <register> 15491 <name>CLKCTRL</name> 15492 <description>Register for controlling SPI clock rate.</description> 15493 <addressOffset>0x14</addressOffset> 15494 <access>read-write</access> 15495 <fields> 15496 <field> 15497 <name>LO</name> 15498 <description>Low duty cycle control. In timer mode, reload[7:0].</description> 15499 <bitOffset>0</bitOffset> 15500 <bitWidth>8</bitWidth> 15501 <enumeratedValues> 15502 <enumeratedValue> 15503 <name>Dis</name> 15504 <description>Duty cycle control of serial clock generation is disabled.</description> 15505 <value>0</value> 15506 </enumeratedValue> 15507 </enumeratedValues> 15508 </field> 15509 <field> 15510 <name>HI</name> 15511 <description>High duty cycle control. In timer mode, reload[15:8].</description> 15512 <bitOffset>8</bitOffset> 15513 <bitWidth>8</bitWidth> 15514 <enumeratedValues> 15515 <enumeratedValue> 15516 <name>Dis</name> 15517 <description>Duty cycle control of serial clock generation is disabled.</description> 15518 <value>0</value> 15519 </enumeratedValue> 15520 </enumeratedValues> 15521 </field> 15522 <field> 15523 <name>CLKDIV</name> 15524 <description>System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock.</description> 15525 <bitOffset>16</bitOffset> 15526 <bitWidth>4</bitWidth> 15527 </field> 15528 <field> 15529 <name>AFP_FCD</name> 15530 <description>AFP FCD.</description> 15531 <bitOffset>24</bitOffset> 15532 <bitWidth>3</bitWidth> 15533 </field> 15534 </fields> 15535 </register> 15536 <register> 15537 <name>DMA</name> 15538 <description>Register for controlling DMA.</description> 15539 <addressOffset>0x1C</addressOffset> 15540 <access>read-write</access> 15541 <fields> 15542 <field> 15543 <name>TX_THD_VAL</name> 15544 <description>Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered.</description> 15545 <bitOffset>0</bitOffset> 15546 <bitWidth>5</bitWidth> 15547 </field> 15548 <field> 15549 <name>TX_FIFO_EN</name> 15550 <description>Transmit FIFO enabled for SPI transactions.</description> 15551 <bitOffset>6</bitOffset> 15552 <bitWidth>1</bitWidth> 15553 <enumeratedValues> 15554 <enumeratedValue> 15555 <name>dis</name> 15556 <description>Transmit FIFO is not enabled.</description> 15557 <value>0</value> 15558 </enumeratedValue> 15559 <enumeratedValue> 15560 <name>en</name> 15561 <description>Transmit FIFO is enabled.</description> 15562 <value>1</value> 15563 </enumeratedValue> 15564 </enumeratedValues> 15565 </field> 15566 <field> 15567 <name>TX_FLUSH</name> 15568 <description>Clear TX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side.</description> 15569 <bitOffset>7</bitOffset> 15570 <bitWidth>1</bitWidth> 15571 <enumeratedValues> 15572 <enumeratedValue> 15573 <name>CLEAR</name> 15574 <description>Clear the Transmit FIFO, clears any pending TX FIFO status.</description> 15575 <value>1</value> 15576 </enumeratedValue> 15577 </enumeratedValues> 15578 </field> 15579 <field> 15580 <name>TX_LVL</name> 15581 <description>Count of entries in TX FIFO.</description> 15582 <bitOffset>8</bitOffset> 15583 <bitWidth>6</bitWidth> 15584 <access>read-only</access> 15585 </field> 15586 <field> 15587 <name>DMA_TX_EN</name> 15588 <description>TX DMA Enable.</description> 15589 <bitOffset>15</bitOffset> 15590 <bitWidth>1</bitWidth> 15591 <enumeratedValues> 15592 <enumeratedValue> 15593 <name>DIS</name> 15594 <description>TX DMA requests are disabled, andy pending DMA requests are cleared.</description> 15595 <value>0</value> 15596 </enumeratedValue> 15597 <enumeratedValue> 15598 <name>en</name> 15599 <description>TX DMA requests are enabled.</description> 15600 <value>1</value> 15601 </enumeratedValue> 15602 </enumeratedValues> 15603 </field> 15604 <field> 15605 <name>RX_THD_VAL</name> 15606 <description>Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered.</description> 15607 <bitOffset>16</bitOffset> 15608 <bitWidth>5</bitWidth> 15609 </field> 15610 <field> 15611 <name>RX_FIFO_EN</name> 15612 <description>Receive FIFO enabled for SPI transactions.</description> 15613 <bitOffset>22</bitOffset> 15614 <bitWidth>1</bitWidth> 15615 <enumeratedValues> 15616 <enumeratedValue> 15617 <name>DIS</name> 15618 <description>Receive FIFO is not enabled.</description> 15619 <value>0</value> 15620 </enumeratedValue> 15621 <enumeratedValue> 15622 <name>en</name> 15623 <description>Receive FIFO is enabled.</description> 15624 <value>1</value> 15625 </enumeratedValue> 15626 </enumeratedValues> 15627 </field> 15628 <field> 15629 <name>RX_FLUSH</name> 15630 <description>Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side.</description> 15631 <bitOffset>23</bitOffset> 15632 <bitWidth>1</bitWidth> 15633 <enumeratedValues> 15634 <enumeratedValue> 15635 <name>CLEAR</name> 15636 <description>Clear the Receive FIFO, clears any pending RX FIFO status.</description> 15637 <value>1</value> 15638 </enumeratedValue> 15639 </enumeratedValues> 15640 </field> 15641 <field> 15642 <name>RX_LVL</name> 15643 <description>Count of entries in RX FIFO.</description> 15644 <bitOffset>24</bitOffset> 15645 <bitWidth>6</bitWidth> 15646 <access>read-only</access> 15647 </field> 15648 <field> 15649 <name>DMA_RX_EN</name> 15650 <description>RX DMA Enable.</description> 15651 <bitOffset>31</bitOffset> 15652 <bitWidth>1</bitWidth> 15653 <enumeratedValues> 15654 <enumeratedValue> 15655 <name>dis</name> 15656 <description>RX DMA requests are disabled, any pending DMA requests are cleared.</description> 15657 <value>0</value> 15658 </enumeratedValue> 15659 <enumeratedValue> 15660 <name>en</name> 15661 <description>RX DMA requests are enabled.</description> 15662 <value>1</value> 15663 </enumeratedValue> 15664 </enumeratedValues> 15665 </field> 15666 </fields> 15667 </register> 15668 <register> 15669 <name>INTFL</name> 15670 <description>Register for reading and clearing interrupt flags. All bits are write 1 to clear.</description> 15671 <addressOffset>0x20</addressOffset> 15672 <access>read-write</access> 15673 <fields> 15674 <field> 15675 <name>TX_THD</name> 15676 <description>TX FIFO Threshold Crossed.</description> 15677 <bitOffset>0</bitOffset> 15678 <bitWidth>1</bitWidth> 15679 <enumeratedValues> 15680 <enumeratedValue> 15681 <name>clear</name> 15682 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 15683 <value>1</value> 15684 </enumeratedValue> 15685 </enumeratedValues> 15686 </field> 15687 <field> 15688 <name>TX_EM</name> 15689 <description>TX FIFO Empty.</description> 15690 <bitOffset>1</bitOffset> 15691 <bitWidth>1</bitWidth> 15692 <enumeratedValues> 15693 <enumeratedValue> 15694 <name>clear</name> 15695 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 15696 <value>1</value> 15697 </enumeratedValue> 15698 </enumeratedValues> 15699 </field> 15700 <field> 15701 <name>RX_THD</name> 15702 <description>RX FIFO Threshold Crossed.</description> 15703 <bitOffset>2</bitOffset> 15704 <bitWidth>1</bitWidth> 15705 <enumeratedValues> 15706 <enumeratedValue> 15707 <name>clear</name> 15708 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 15709 <value>1</value> 15710 </enumeratedValue> 15711 </enumeratedValues> 15712 </field> 15713 <field> 15714 <name>RX_FULL</name> 15715 <description>RX FIFO FULL.</description> 15716 <bitOffset>3</bitOffset> 15717 <bitWidth>1</bitWidth> 15718 <enumeratedValues> 15719 <enumeratedValue> 15720 <name>clear</name> 15721 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 15722 <value>1</value> 15723 </enumeratedValue> 15724 </enumeratedValues> 15725 </field> 15726 <field> 15727 <name>SSA</name> 15728 <description>Slave Select Asserted.</description> 15729 <bitOffset>4</bitOffset> 15730 <bitWidth>1</bitWidth> 15731 <enumeratedValues> 15732 <enumeratedValue> 15733 <name>clear</name> 15734 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 15735 <value>1</value> 15736 </enumeratedValue> 15737 </enumeratedValues> 15738 </field> 15739 <field> 15740 <name>SSD</name> 15741 <description>Slave Select Deasserted.</description> 15742 <bitOffset>5</bitOffset> 15743 <bitWidth>1</bitWidth> 15744 <enumeratedValues> 15745 <enumeratedValue> 15746 <name>clear</name> 15747 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 15748 <value>1</value> 15749 </enumeratedValue> 15750 </enumeratedValues> 15751 </field> 15752 <field> 15753 <name>FAULT</name> 15754 <description>Multi-Master Mode Fault.</description> 15755 <bitOffset>8</bitOffset> 15756 <bitWidth>1</bitWidth> 15757 <enumeratedValues> 15758 <enumeratedValue> 15759 <name>clear</name> 15760 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 15761 <value>1</value> 15762 </enumeratedValue> 15763 </enumeratedValues> 15764 </field> 15765 <field> 15766 <name>ABORT</name> 15767 <description>Slave Abort Detected.</description> 15768 <bitOffset>9</bitOffset> 15769 <bitWidth>1</bitWidth> 15770 <enumeratedValues> 15771 <enumeratedValue> 15772 <name>clear</name> 15773 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 15774 <value>1</value> 15775 </enumeratedValue> 15776 </enumeratedValues> 15777 </field> 15778 <field> 15779 <name>MST_DONE</name> 15780 <description>Master Done, set when SPI Master has completed any transactions.</description> 15781 <bitOffset>11</bitOffset> 15782 <bitWidth>1</bitWidth> 15783 <enumeratedValues> 15784 <enumeratedValue> 15785 <name>clear</name> 15786 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 15787 <value>1</value> 15788 </enumeratedValue> 15789 </enumeratedValues> 15790 </field> 15791 <field> 15792 <name>TX_OV</name> 15793 <description>Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO.</description> 15794 <bitOffset>12</bitOffset> 15795 <bitWidth>1</bitWidth> 15796 <enumeratedValues> 15797 <enumeratedValue> 15798 <name>clear</name> 15799 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 15800 <value>1</value> 15801 </enumeratedValue> 15802 </enumeratedValues> 15803 </field> 15804 <field> 15805 <name>TX_UN</name> 15806 <description>Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO.</description> 15807 <bitOffset>13</bitOffset> 15808 <bitWidth>1</bitWidth> 15809 <enumeratedValues> 15810 <enumeratedValue> 15811 <name>clear</name> 15812 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 15813 <value>1</value> 15814 </enumeratedValue> 15815 </enumeratedValues> 15816 </field> 15817 <field> 15818 <name>RX_OV</name> 15819 <description>Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO.</description> 15820 <bitOffset>14</bitOffset> 15821 <bitWidth>1</bitWidth> 15822 <enumeratedValues> 15823 <enumeratedValue> 15824 <name>clear</name> 15825 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 15826 <value>1</value> 15827 </enumeratedValue> 15828 </enumeratedValues> 15829 </field> 15830 <field> 15831 <name>RX_UN</name> 15832 <description>Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO.</description> 15833 <bitOffset>15</bitOffset> 15834 <bitWidth>1</bitWidth> 15835 <enumeratedValues> 15836 <enumeratedValue> 15837 <name>clear</name> 15838 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 15839 <value>1</value> 15840 </enumeratedValue> 15841 </enumeratedValues> 15842 </field> 15843 </fields> 15844 </register> 15845 <register> 15846 <name>INTEN</name> 15847 <description>Register for enabling interrupts.</description> 15848 <addressOffset>0x24</addressOffset> 15849 <access>read-write</access> 15850 <fields> 15851 <field> 15852 <name>TX_THD</name> 15853 <description>TX FIFO Threshold interrupt enable.</description> 15854 <bitOffset>0</bitOffset> 15855 <bitWidth>1</bitWidth> 15856 <enumeratedValues> 15857 <enumeratedValue> 15858 <name>dis</name> 15859 <description>Interrupt is disabled.</description> 15860 <value>0</value> 15861 </enumeratedValue> 15862 <enumeratedValue> 15863 <name>en</name> 15864 <description>Interrupt is enabled.</description> 15865 <value>1</value> 15866 </enumeratedValue> 15867 </enumeratedValues> 15868 </field> 15869 <field> 15870 <name>TX_EM</name> 15871 <description>TX FIFO Empty interrupt enable.</description> 15872 <bitOffset>1</bitOffset> 15873 <bitWidth>1</bitWidth> 15874 <enumeratedValues> 15875 <enumeratedValue> 15876 <name>dis</name> 15877 <description>Interrupt is disabled.</description> 15878 <value>0</value> 15879 </enumeratedValue> 15880 <enumeratedValue> 15881 <name>en</name> 15882 <description>Interrupt is enabled.</description> 15883 <value>1</value> 15884 </enumeratedValue> 15885 </enumeratedValues> 15886 </field> 15887 <field> 15888 <name>RX_THD</name> 15889 <description>RX FIFO Threshold Crossed interrupt enable.</description> 15890 <bitOffset>2</bitOffset> 15891 <bitWidth>1</bitWidth> 15892 <enumeratedValues> 15893 <enumeratedValue> 15894 <name>dis</name> 15895 <description>Interrupt is disabled.</description> 15896 <value>0</value> 15897 </enumeratedValue> 15898 <enumeratedValue> 15899 <name>en</name> 15900 <description>Interrupt is enabled.</description> 15901 <value>1</value> 15902 </enumeratedValue> 15903 </enumeratedValues> 15904 </field> 15905 <field> 15906 <name>RX_FULL</name> 15907 <description>RX FIFO FULL interrupt enable.</description> 15908 <bitOffset>3</bitOffset> 15909 <bitWidth>1</bitWidth> 15910 <enumeratedValues> 15911 <enumeratedValue> 15912 <name>dis</name> 15913 <description>Interrupt is disabled.</description> 15914 <value>0</value> 15915 </enumeratedValue> 15916 <enumeratedValue> 15917 <name>en</name> 15918 <description>Interrupt is enabled.</description> 15919 <value>1</value> 15920 </enumeratedValue> 15921 </enumeratedValues> 15922 </field> 15923 <field> 15924 <name>SSA</name> 15925 <description>Slave Select Asserted interrupt enable.</description> 15926 <bitOffset>4</bitOffset> 15927 <bitWidth>1</bitWidth> 15928 <enumeratedValues> 15929 <enumeratedValue> 15930 <name>dis</name> 15931 <description>Interrupt is disabled.</description> 15932 <value>0</value> 15933 </enumeratedValue> 15934 <enumeratedValue> 15935 <name>en</name> 15936 <description>Interrupt is enabled.</description> 15937 <value>1</value> 15938 </enumeratedValue> 15939 </enumeratedValues> 15940 </field> 15941 <field> 15942 <name>SSD</name> 15943 <description>Slave Select Deasserted interrupt enable.</description> 15944 <bitOffset>5</bitOffset> 15945 <bitWidth>1</bitWidth> 15946 <enumeratedValues> 15947 <enumeratedValue> 15948 <name>dis</name> 15949 <description>Interrupt is disabled.</description> 15950 <value>0</value> 15951 </enumeratedValue> 15952 <enumeratedValue> 15953 <name>en</name> 15954 <description>Interrupt is enabled.</description> 15955 <value>1</value> 15956 </enumeratedValue> 15957 </enumeratedValues> 15958 </field> 15959 <field> 15960 <name>FAULT</name> 15961 <description>Multi-Master Mode Fault interrupt enable.</description> 15962 <bitOffset>8</bitOffset> 15963 <bitWidth>1</bitWidth> 15964 <enumeratedValues> 15965 <enumeratedValue> 15966 <name>dis</name> 15967 <description>Interrupt is disabled.</description> 15968 <value>0</value> 15969 </enumeratedValue> 15970 <enumeratedValue> 15971 <name>en</name> 15972 <description>Interrupt is enabled.</description> 15973 <value>1</value> 15974 </enumeratedValue> 15975 </enumeratedValues> 15976 </field> 15977 <field> 15978 <name>ABORT</name> 15979 <description>Slave Abort Detected interrupt enable.</description> 15980 <bitOffset>9</bitOffset> 15981 <bitWidth>1</bitWidth> 15982 <enumeratedValues> 15983 <enumeratedValue> 15984 <name>dis</name> 15985 <description>Interrupt is disabled.</description> 15986 <value>0</value> 15987 </enumeratedValue> 15988 <enumeratedValue> 15989 <name>en</name> 15990 <description>Interrupt is enabled.</description> 15991 <value>1</value> 15992 </enumeratedValue> 15993 </enumeratedValues> 15994 </field> 15995 <field> 15996 <name>MST_DONE</name> 15997 <description>Master Done interrupt enable.</description> 15998 <bitOffset>11</bitOffset> 15999 <bitWidth>1</bitWidth> 16000 <enumeratedValues> 16001 <enumeratedValue> 16002 <name>dis</name> 16003 <description>Interrupt is disabled.</description> 16004 <value>0</value> 16005 </enumeratedValue> 16006 <enumeratedValue> 16007 <name>en</name> 16008 <description>Interrupt is enabled.</description> 16009 <value>1</value> 16010 </enumeratedValue> 16011 </enumeratedValues> 16012 </field> 16013 <field> 16014 <name>TX_OV</name> 16015 <description>Transmit FIFO Overrun interrupt enable.</description> 16016 <bitOffset>12</bitOffset> 16017 <bitWidth>1</bitWidth> 16018 <enumeratedValues> 16019 <enumeratedValue> 16020 <name>dis</name> 16021 <description>Interrupt is disabled.</description> 16022 <value>0</value> 16023 </enumeratedValue> 16024 <enumeratedValue> 16025 <name>en</name> 16026 <description>Interrupt is enabled.</description> 16027 <value>1</value> 16028 </enumeratedValue> 16029 </enumeratedValues> 16030 </field> 16031 <field> 16032 <name>TX_UN</name> 16033 <description>Transmit FIFO Underrun interrupt enable.</description> 16034 <bitOffset>13</bitOffset> 16035 <bitWidth>1</bitWidth> 16036 <enumeratedValues> 16037 <enumeratedValue> 16038 <name>dis</name> 16039 <description>Interrupt is disabled.</description> 16040 <value>0</value> 16041 </enumeratedValue> 16042 <enumeratedValue> 16043 <name>en</name> 16044 <description>Interrupt is enabled.</description> 16045 <value>1</value> 16046 </enumeratedValue> 16047 </enumeratedValues> 16048 </field> 16049 <field> 16050 <name>RX_OV</name> 16051 <description>Receive FIFO Overrun interrupt enable.</description> 16052 <bitOffset>14</bitOffset> 16053 <bitWidth>1</bitWidth> 16054 <enumeratedValues> 16055 <enumeratedValue> 16056 <name>dis</name> 16057 <description>Interrupt is disabled.</description> 16058 <value>0</value> 16059 </enumeratedValue> 16060 <enumeratedValue> 16061 <name>en</name> 16062 <description>Interrupt is enabled.</description> 16063 <value>1</value> 16064 </enumeratedValue> 16065 </enumeratedValues> 16066 </field> 16067 <field> 16068 <name>RX_UN</name> 16069 <description>Receive FIFO Underrun interrupt enable.</description> 16070 <bitOffset>15</bitOffset> 16071 <bitWidth>1</bitWidth> 16072 <enumeratedValues> 16073 <enumeratedValue> 16074 <name>dis</name> 16075 <description>Interrupt is disabled.</description> 16076 <value>0</value> 16077 </enumeratedValue> 16078 <enumeratedValue> 16079 <name>en</name> 16080 <description>Interrupt is enabled.</description> 16081 <value>1</value> 16082 </enumeratedValue> 16083 </enumeratedValues> 16084 </field> 16085 </fields> 16086 </register> 16087 <register> 16088 <name>WKFL</name> 16089 <description>Register for wake up flags. All bits in this register are write 1 to clear.</description> 16090 <addressOffset>0x28</addressOffset> 16091 <access>read-write</access> 16092 <fields> 16093 <field> 16094 <name>TX_THD</name> 16095 <description>Wake on TX FIFO Threshold Crossed.</description> 16096 <bitOffset>0</bitOffset> 16097 <bitWidth>1</bitWidth> 16098 <enumeratedValues> 16099 <enumeratedValue> 16100 <name>clear</name> 16101 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 16102 <value>1</value> 16103 </enumeratedValue> 16104 </enumeratedValues> 16105 </field> 16106 <field> 16107 <name>TX_EM</name> 16108 <description>Wake on TX FIFO Empty.</description> 16109 <bitOffset>1</bitOffset> 16110 <bitWidth>1</bitWidth> 16111 <enumeratedValues> 16112 <enumeratedValue> 16113 <name>clear</name> 16114 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 16115 <value>1</value> 16116 </enumeratedValue> 16117 </enumeratedValues> 16118 </field> 16119 <field> 16120 <name>RX_THD</name> 16121 <description>Wake on RX FIFO Threshold Crossed.</description> 16122 <bitOffset>2</bitOffset> 16123 <bitWidth>1</bitWidth> 16124 <enumeratedValues> 16125 <enumeratedValue> 16126 <name>clear</name> 16127 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 16128 <value>1</value> 16129 </enumeratedValue> 16130 </enumeratedValues> 16131 </field> 16132 <field> 16133 <name>RX_FULL</name> 16134 <description>Wake on RX FIFO Full.</description> 16135 <bitOffset>3</bitOffset> 16136 <bitWidth>1</bitWidth> 16137 <enumeratedValues> 16138 <enumeratedValue> 16139 <name>clear</name> 16140 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 16141 <value>1</value> 16142 </enumeratedValue> 16143 </enumeratedValues> 16144 </field> 16145 </fields> 16146 </register> 16147 <register> 16148 <name>WKEN</name> 16149 <description>Register for wake up enable.</description> 16150 <addressOffset>0x2C</addressOffset> 16151 <access>read-write</access> 16152 <fields> 16153 <field> 16154 <name>TX_THD</name> 16155 <description>Wake on TX FIFO Threshold Crossed Enable.</description> 16156 <bitOffset>0</bitOffset> 16157 <bitWidth>1</bitWidth> 16158 <enumeratedValues> 16159 <enumeratedValue> 16160 <name>dis</name> 16161 <description>Wakeup source disabled.</description> 16162 <value>0</value> 16163 </enumeratedValue> 16164 <enumeratedValue> 16165 <name>en</name> 16166 <description>Wakeup source enabled.</description> 16167 <value>1</value> 16168 </enumeratedValue> 16169 </enumeratedValues> 16170 </field> 16171 <field> 16172 <name>TX_EM</name> 16173 <description>Wake on TX FIFO Empty Enable.</description> 16174 <bitOffset>1</bitOffset> 16175 <bitWidth>1</bitWidth> 16176 <enumeratedValues> 16177 <enumeratedValue> 16178 <name>dis</name> 16179 <description>Wakeup source disabled.</description> 16180 <value>0</value> 16181 </enumeratedValue> 16182 <enumeratedValue> 16183 <name>en</name> 16184 <description>Wakeup source enabled.</description> 16185 <value>1</value> 16186 </enumeratedValue> 16187 </enumeratedValues> 16188 </field> 16189 <field> 16190 <name>RX_THD</name> 16191 <description>Wake on RX FIFO Threshold Crossed Enable.</description> 16192 <bitOffset>2</bitOffset> 16193 <bitWidth>1</bitWidth> 16194 <enumeratedValues> 16195 <enumeratedValue> 16196 <name>dis</name> 16197 <description>Wakeup source disabled.</description> 16198 <value>0</value> 16199 </enumeratedValue> 16200 <enumeratedValue> 16201 <name>en</name> 16202 <description>Wakeup source enabled.</description> 16203 <value>1</value> 16204 </enumeratedValue> 16205 </enumeratedValues> 16206 </field> 16207 <field> 16208 <name>RX_FULL</name> 16209 <description>Wake on RX FIFO Full Enable.</description> 16210 <bitOffset>3</bitOffset> 16211 <bitWidth>1</bitWidth> 16212 <enumeratedValues> 16213 <enumeratedValue> 16214 <name>dis</name> 16215 <description>Wakeup source disabled.</description> 16216 <value>0</value> 16217 </enumeratedValue> 16218 <enumeratedValue> 16219 <name>en</name> 16220 <description>Wakeup source enabled.</description> 16221 <value>1</value> 16222 </enumeratedValue> 16223 </enumeratedValues> 16224 </field> 16225 </fields> 16226 </register> 16227 <register> 16228 <name>STAT</name> 16229 <description>SPI Status register.</description> 16230 <addressOffset>0x30</addressOffset> 16231 <access>read-only</access> 16232 <fields> 16233 <field> 16234 <name>BUSY</name> 16235 <description>SPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. </description> 16236 <bitOffset>0</bitOffset> 16237 <bitWidth>1</bitWidth> 16238 <enumeratedValues> 16239 <enumeratedValue> 16240 <name>not</name> 16241 <description>SPI not active.</description> 16242 <value>0</value> 16243 </enumeratedValue> 16244 <enumeratedValue> 16245 <name>active</name> 16246 <description>SPI active.</description> 16247 <value>1</value> 16248 </enumeratedValue> 16249 </enumeratedValues> 16250 </field> 16251 </fields> 16252 </register> 16253 </registers> 16254 </peripheral> 16255<!--SPI0 SPI peripheral.--> 16256 <peripheral derivedFrom="SPI0"> 16257 <name>SPI1</name> 16258 <description>SPI peripheral. 1</description> 16259 <baseAddress>0x400BE000</baseAddress> 16260 <interrupt> 16261 <name>SPI1</name> 16262 <description>SPI1 IRQ</description> 16263 <value>17</value> 16264 </interrupt> 16265 </peripheral> 16266<!--SPI1 SPI peripheral. 1--> 16267 <peripheral derivedFrom="SPI0"> 16268 <name>SPI2</name> 16269 <description>SPI peripheral. 2</description> 16270 <baseAddress>0x400BE400</baseAddress> 16271 <interrupt> 16272 <name>SPI2</name> 16273 <description>SPI2 IRQ</description> 16274 <value>18</value> 16275 </interrupt> 16276 </peripheral> 16277<!--SPI2 SPI peripheral. 2--> 16278 <peripheral> 16279 <name>SPIXR</name> 16280 <description>SPIXR peripheral.</description> 16281 <baseAddress>0x4003A000</baseAddress> 16282 <addressBlock> 16283 <offset>0x00</offset> 16284 <size>0x1000</size> 16285 <usage>registers</usage> 16286 </addressBlock> 16287 <registers> 16288 <register> 16289 <name>DATA32</name> 16290 <description>Register for reading and writing the FIFO.</description> 16291 <addressOffset>0x00</addressOffset> 16292 <size>32</size> 16293 <access>read-write</access> 16294 <fields> 16295 <field> 16296 <name>DATA</name> 16297 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 16298 <bitOffset>0</bitOffset> 16299 <bitWidth>32</bitWidth> 16300 </field> 16301 </fields> 16302 </register> 16303 <register> 16304 <dim>2</dim> 16305 <dimIncrement>2</dimIncrement> 16306 <name>DATA16[%s]</name> 16307 <description>Register for reading and writing the FIFO.</description> 16308 <alternateRegister>DATA32</alternateRegister> 16309 <addressOffset>0x00</addressOffset> 16310 <size>16</size> 16311 <access>read-write</access> 16312 <fields> 16313 <field> 16314 <name>DATA</name> 16315 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 16316 <bitOffset>0</bitOffset> 16317 <bitWidth>16</bitWidth> 16318 </field> 16319 </fields> 16320 </register> 16321 <register> 16322 <dim>4</dim> 16323 <dimIncrement>1</dimIncrement> 16324 <name>DATA8[%s]</name> 16325 <description>Register for reading and writing the FIFO.</description> 16326 <alternateRegister>DATA32</alternateRegister> 16327 <addressOffset>0x00</addressOffset> 16328 <size>8</size> 16329 <access>read-write</access> 16330 <fields> 16331 <field> 16332 <name>DATA</name> 16333 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 16334 <bitOffset>0</bitOffset> 16335 <bitWidth>8</bitWidth> 16336 </field> 16337 </fields> 16338 </register> 16339 <register> 16340 <name>CTRL0</name> 16341 <description>Register for controlling SPI peripheral.</description> 16342 <addressOffset>0x04</addressOffset> 16343 <access>read-write</access> 16344 <fields> 16345 <field> 16346 <name>EN</name> 16347 <description>SPI Enable.</description> 16348 <bitOffset>0</bitOffset> 16349 <bitWidth>1</bitWidth> 16350 <enumeratedValues> 16351 <enumeratedValue> 16352 <name>dis</name> 16353 <description>SPI is disabled.</description> 16354 <value>0</value> 16355 </enumeratedValue> 16356 <enumeratedValue> 16357 <name>en</name> 16358 <description>SPI is enabled.</description> 16359 <value>1</value> 16360 </enumeratedValue> 16361 </enumeratedValues> 16362 </field> 16363 <field> 16364 <name>MSTR_EN</name> 16365 <description>Master Mode Enable.</description> 16366 <bitOffset>1</bitOffset> 16367 <bitWidth>1</bitWidth> 16368 <enumeratedValues> 16369 <enumeratedValue> 16370 <name>dis</name> 16371 <description>SPI is Slave mode.</description> 16372 <value>0</value> 16373 </enumeratedValue> 16374 <enumeratedValue> 16375 <name>en</name> 16376 <description>SPI is Master mode.</description> 16377 <value>1</value> 16378 </enumeratedValue> 16379 </enumeratedValues> 16380 </field> 16381 <field> 16382 <name>SSIO</name> 16383 <description>Slave Select 0, IO direction, to support Multi-Master mode, 16384 Slave Select 0 can be input in Master mode. This bit has no 16385 effect in slave mode.</description> 16386 <bitOffset>4</bitOffset> 16387 <bitWidth>1</bitWidth> 16388 <enumeratedValues> 16389 <enumeratedValue> 16390 <name>output</name> 16391 <description>Slave select 0 is output.</description> 16392 <value>0</value> 16393 </enumeratedValue> 16394 <enumeratedValue> 16395 <name>input</name> 16396 <description>Slave Select 0 is input, only valid if MMEN=1.</description> 16397 <value>1</value> 16398 </enumeratedValue> 16399 </enumeratedValues> 16400 </field> 16401 <field> 16402 <name>TX_START</name> 16403 <description>Start Transmit.</description> 16404 <bitOffset>5</bitOffset> 16405 <bitWidth>1</bitWidth> 16406 <enumeratedValues> 16407 <enumeratedValue> 16408 <name>start</name> 16409 <description>Master Initiates a transaction, this bit is 16410 self clearing when transactions are done. If 16411 a transaction completes, and the TX FIFO 16412 is empty, the Master halts, if a transaction 16413 completes, and the TX FIFO is not empty, 16414 the Master initiates another transaction.</description> 16415 <value>1</value> 16416 </enumeratedValue> 16417 </enumeratedValues> 16418 </field> 16419 <field> 16420 <name>SS_CTRL</name> 16421 <description>Slave Select Control.</description> 16422 <bitOffset>8</bitOffset> 16423 <bitWidth>1</bitWidth> 16424 <enumeratedValues> 16425 <enumeratedValue> 16426 <name>deassert</name> 16427 <description>SPI de-asserts Slave Select at the end of a transaction.</description> 16428 <value>0</value> 16429 </enumeratedValue> 16430 <enumeratedValue> 16431 <name>assert</name> 16432 <description>SPI leaves Slave Select asserted at the end of a transaction.</description> 16433 <value>1</value> 16434 </enumeratedValue> 16435 </enumeratedValues> 16436 </field> 16437 <field> 16438 <name>SS</name> 16439 <description>Slave Select, when in Master mode selects which Slave devices are 16440 selected. More than one Slave device can be selected.</description> 16441 <bitOffset>16</bitOffset> 16442 <bitWidth>1</bitWidth> 16443 <enumeratedValues> 16444 <enumeratedValue> 16445 <name>SS0</name> 16446 <description>Slave Select 0</description> 16447 <value>1</value> 16448 </enumeratedValue> 16449 </enumeratedValues> 16450 </field> 16451 </fields> 16452 </register> 16453 <register> 16454 <name>CTRL1</name> 16455 <description>Register for controlling SPI peripheral.</description> 16456 <addressOffset>0x08</addressOffset> 16457 <access>read-write</access> 16458 <fields> 16459 <field> 16460 <name>TX_NUM_CHAR</name> 16461 <description>Nubmer of Characters to transmit.</description> 16462 <bitOffset>0</bitOffset> 16463 <bitWidth>16</bitWidth> 16464 </field> 16465 <field> 16466 <name>RX_NUM_CHAR</name> 16467 <description>Nubmer of Characters to receive.</description> 16468 <bitOffset>16</bitOffset> 16469 <bitWidth>16</bitWidth> 16470 </field> 16471 </fields> 16472 </register> 16473 <register> 16474 <name>CTRL2</name> 16475 <description>Register for controlling SPI peripheral.</description> 16476 <addressOffset>0x0C</addressOffset> 16477 <access>read-write</access> 16478 <fields> 16479 <field> 16480 <name>CPHA</name> 16481 <description>Clock Phase.</description> 16482 <bitOffset>0</bitOffset> 16483 <bitWidth>1</bitWidth> 16484 </field> 16485 <field> 16486 <name>CPOL</name> 16487 <description>Clock Polarity.</description> 16488 <bitOffset>1</bitOffset> 16489 <bitWidth>1</bitWidth> 16490 </field> 16491 <field> 16492 <name>SCLK_FB_INV</name> 16493 <description>Invert SCLK Feedback in Master Mode.</description> 16494 <bitOffset>4</bitOffset> 16495 <bitWidth>1</bitWidth> 16496 <enumeratedValues> 16497 <enumeratedValue> 16498 <name>NON_INV</name> 16499 <description>SCLK is not inverted to Line Receiver.</description> 16500 <value>0</value> 16501 </enumeratedValue> 16502 <enumeratedValue> 16503 <name>INV</name> 16504 <description>SCLK is inverted to Line Receiver.</description> 16505 <value>1</value> 16506 </enumeratedValue> 16507 </enumeratedValues> 16508 </field> 16509 <field> 16510 <name>NUMBITS</name> 16511 <description>Number of Bits per character.</description> 16512 <bitOffset>8</bitOffset> 16513 <bitWidth>4</bitWidth> 16514 <enumeratedValues> 16515 <enumeratedValue> 16516 <name>0</name> 16517 <description>16 bits per character.</description> 16518 <value>0</value> 16519 </enumeratedValue> 16520 </enumeratedValues> 16521 </field> 16522 <field> 16523 <name>DATA_WIDTH</name> 16524 <description>SPI Data width.</description> 16525 <bitOffset>12</bitOffset> 16526 <bitWidth>2</bitWidth> 16527 <enumeratedValues> 16528 <enumeratedValue> 16529 <name>Mono</name> 16530 <description>1 data pin.</description> 16531 <value>0</value> 16532 </enumeratedValue> 16533 <enumeratedValue> 16534 <name>Dual</name> 16535 <description>2 data pins.</description> 16536 <value>1</value> 16537 </enumeratedValue> 16538 <enumeratedValue> 16539 <name>Quad</name> 16540 <description>4 data pins.</description> 16541 <value>2</value> 16542 </enumeratedValue> 16543 </enumeratedValues> 16544 </field> 16545 <field> 16546 <name>THREE_WIRE</name> 16547 <description>Three Wire mode. MOSI/MISO pin (s) shared. Only Mono mode suports Four-Wire.</description> 16548 <bitOffset>15</bitOffset> 16549 <bitWidth>1</bitWidth> 16550 <enumeratedValues> 16551 <enumeratedValue> 16552 <name>dis</name> 16553 <description>Use four wire mode (Mono only).</description> 16554 <value>0</value> 16555 </enumeratedValue> 16556 <enumeratedValue> 16557 <name>en</name> 16558 <description>Use three wire mode.</description> 16559 <value>1</value> 16560 </enumeratedValue> 16561 </enumeratedValues> 16562 </field> 16563 <field> 16564 <name>SSPOL</name> 16565 <description>Slave Select Polarity</description> 16566 <bitOffset>16</bitOffset> 16567 <bitWidth>1</bitWidth> 16568 </field> 16569 </fields> 16570 </register> 16571 <register> 16572 <name>CTRL3</name> 16573 <description>Register for controlling SPI peripheral.</description> 16574 <addressOffset>0x10</addressOffset> 16575 <access>read-write</access> 16576 <fields> 16577 <field> 16578 <name>SSACT1</name> 16579 <description>Slave Select Action delay 1.</description> 16580 <bitOffset>0</bitOffset> 16581 <bitWidth>8</bitWidth> 16582 <enumeratedValues> 16583 <enumeratedValue> 16584 <name>256</name> 16585 <description>256 system clocks between SS active and first serial clock edge.</description> 16586 <value>0</value> 16587 </enumeratedValue> 16588 </enumeratedValues> 16589 </field> 16590 <field> 16591 <name>SSACT2</name> 16592 <description>Slave Select Action delay 2.</description> 16593 <bitOffset>8</bitOffset> 16594 <bitWidth>8</bitWidth> 16595 <enumeratedValues> 16596 <enumeratedValue> 16597 <name>256</name> 16598 <description>256 system clocks between last serial clock edge and SS inactive.</description> 16599 <value>0</value> 16600 </enumeratedValue> 16601 </enumeratedValues> 16602 </field> 16603 <field> 16604 <name>SSIACT</name> 16605 <description>Slave Select Inactive delay.</description> 16606 <bitOffset>16</bitOffset> 16607 <bitWidth>8</bitWidth> 16608 <enumeratedValues> 16609 <enumeratedValue> 16610 <name>256</name> 16611 <description>256 system clocks between transactions.</description> 16612 <value>0</value> 16613 </enumeratedValue> 16614 </enumeratedValues> 16615 </field> 16616 </fields> 16617 </register> 16618 <register> 16619 <name>BRGCTRL</name> 16620 <description>Register for controlling SPI clock rate.</description> 16621 <addressOffset>0x14</addressOffset> 16622 <access>read-write</access> 16623 <fields> 16624 <field> 16625 <name>LOW</name> 16626 <description>Low duty cycle control. In timer mode, reload[7:0].</description> 16627 <bitOffset>0</bitOffset> 16628 <bitWidth>8</bitWidth> 16629 <enumeratedValues> 16630 <enumeratedValue> 16631 <name>Dis</name> 16632 <description>Duty cycle control of serial clock generation is disabled.</description> 16633 <value>0</value> 16634 </enumeratedValue> 16635 </enumeratedValues> 16636 </field> 16637 <field> 16638 <name>HIGH</name> 16639 <description>High duty cycle control. In timer mode, reload[15:8].</description> 16640 <bitOffset>8</bitOffset> 16641 <bitWidth>8</bitWidth> 16642 <enumeratedValues> 16643 <enumeratedValue> 16644 <name>Dis</name> 16645 <description>Duty cycle control of serial clock generation is disabled.</description> 16646 <value>0</value> 16647 </enumeratedValue> 16648 </enumeratedValues> 16649 </field> 16650 <field> 16651 <name>SCALE</name> 16652 <description>System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock.</description> 16653 <bitOffset>16</bitOffset> 16654 <bitWidth>4</bitWidth> 16655 </field> 16656 </fields> 16657 </register> 16658 <register> 16659 <name>DMA</name> 16660 <description>Register for controlling DMA.</description> 16661 <addressOffset>0x1C</addressOffset> 16662 <access>read-write</access> 16663 <fields> 16664 <field> 16665 <name>TX_FIFO_LVL</name> 16666 <description>Transmit FIFO level that will trigger a DMA request, also level for 16667 threshold status. When TX FIFO has fewer than this many bytes, the 16668 associated events and conditions are triggered.</description> 16669 <bitOffset>0</bitOffset> 16670 <bitWidth>6</bitWidth> 16671 </field> 16672 <field> 16673 <name>TX_FIFO_EN</name> 16674 <description>Transmit FIFO enabled for SPI transactions.</description> 16675 <bitOffset>6</bitOffset> 16676 <bitWidth>1</bitWidth> 16677 <enumeratedValues> 16678 <enumeratedValue> 16679 <name>dis</name> 16680 <description>Transmit FIFO is not enabled.</description> 16681 <value>0</value> 16682 </enumeratedValue> 16683 <enumeratedValue> 16684 <name>en</name> 16685 <description>Transmit FIFO is enabled.</description> 16686 <value>1</value> 16687 </enumeratedValue> 16688 </enumeratedValues> 16689 </field> 16690 <field> 16691 <name>TX_FIFO_CLEAR</name> 16692 <description>Clear TX FIFO, clear is accomplished by resetting the read and write 16693 pointers. This should be done when FIFO is not being accessed on the SPI side. 16694 </description> 16695 <bitOffset>7</bitOffset> 16696 <bitWidth>1</bitWidth> 16697 <enumeratedValues> 16698 <enumeratedValue> 16699 <name>CLEAR</name> 16700 <description>Clear the Transmit FIFO, clears any pending TX FIFO status.</description> 16701 <value>1</value> 16702 </enumeratedValue> 16703 </enumeratedValues> 16704 </field> 16705 <field> 16706 <name>TX_FIFO_CNT</name> 16707 <description>Count of entries in TX FIFO.</description> 16708 <bitOffset>8</bitOffset> 16709 <bitWidth>5</bitWidth> 16710 </field> 16711 <field> 16712 <name>DMA_TX_EN</name> 16713 <description>TX DMA Enable.</description> 16714 <bitOffset>15</bitOffset> 16715 <bitWidth>1</bitWidth> 16716 <enumeratedValues> 16717 <enumeratedValue> 16718 <name>DIS</name> 16719 <description>TX DMA requests are disabled, andy pending DMA requests are cleared.</description> 16720 <value>0</value> 16721 </enumeratedValue> 16722 <enumeratedValue> 16723 <name>en</name> 16724 <description>TX DMA requests are enabled.</description> 16725 <value>1</value> 16726 </enumeratedValue> 16727 </enumeratedValues> 16728 </field> 16729 <field> 16730 <name>RX_FIFO_LVL</name> 16731 <description>Receive FIFO level that will trigger a DMA request, also level for 16732 threshold status. When RX FIFO has more than this many bytes, the 16733 associated events and conditions are triggered.</description> 16734 <bitOffset>16</bitOffset> 16735 <bitWidth>6</bitWidth> 16736 </field> 16737 <field> 16738 <name>RX_FIFO_EN</name> 16739 <description>Receive FIFO enabled for SPI transactions.</description> 16740 <bitOffset>22</bitOffset> 16741 <bitWidth>1</bitWidth> 16742 <enumeratedValues> 16743 <enumeratedValue> 16744 <name>DIS</name> 16745 <description>Receive FIFO is not enabled.</description> 16746 <value>0</value> 16747 </enumeratedValue> 16748 <enumeratedValue> 16749 <name>en</name> 16750 <description>Receive FIFO is enabled.</description> 16751 <value>1</value> 16752 </enumeratedValue> 16753 </enumeratedValues> 16754 </field> 16755 <field> 16756 <name>RX_FIFO_CLR</name> 16757 <description>Clear RX FIFO, clear is accomplished by resetting the read and write 16758 pointers. This should be done when FIFO is not being accessed on the SPI side.</description> 16759 <bitOffset>23</bitOffset> 16760 <bitWidth>1</bitWidth> 16761 <enumeratedValues> 16762 <enumeratedValue> 16763 <name>CLEAR</name> 16764 <description>Clear the Receive FIFIO, clears any pending RX FIFO status.</description> 16765 <value>1</value> 16766 </enumeratedValue> 16767 </enumeratedValues> 16768 </field> 16769 <field> 16770 <name>RX_FIFO_CNT</name> 16771 <description>Count of entries in RX FIFO.</description> 16772 <bitOffset>24</bitOffset> 16773 <bitWidth>6</bitWidth> 16774 </field> 16775 <field> 16776 <name>DMA_RX_EN</name> 16777 <description>RX DMA Enable.</description> 16778 <bitOffset>31</bitOffset> 16779 <bitWidth>1</bitWidth> 16780 <enumeratedValues> 16781 <enumeratedValue> 16782 <name>dis</name> 16783 <description>RX DMA requests are disabled, any pending DMA requests are cleared.</description> 16784 <value>0</value> 16785 </enumeratedValue> 16786 <enumeratedValue> 16787 <name>en</name> 16788 <description>RX DMA requests are enabled.</description> 16789 <value>1</value> 16790 </enumeratedValue> 16791 </enumeratedValues> 16792 </field> 16793 </fields> 16794 </register> 16795 <register> 16796 <name>INTFL</name> 16797 <description>Register for reading and clearing interrupt flags. All bits are write 1 to clear.</description> 16798 <addressOffset>0x20</addressOffset> 16799 <access>read-write</access> 16800 <fields> 16801 <field> 16802 <name>TX_THRESH</name> 16803 <description>TX FIFO Threshold Crossed.</description> 16804 <bitOffset>0</bitOffset> 16805 <bitWidth>1</bitWidth> 16806 <enumeratedValues> 16807 <enumeratedValue> 16808 <name>clear</name> 16809 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 16810 <value>1</value> 16811 </enumeratedValue> 16812 </enumeratedValues> 16813 </field> 16814 <field> 16815 <name>TX_EMPTY</name> 16816 <description>TX FIFO Empty.</description> 16817 <bitOffset>1</bitOffset> 16818 <bitWidth>1</bitWidth> 16819 <enumeratedValues> 16820 <enumeratedValue> 16821 <name>clear</name> 16822 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 16823 <value>1</value> 16824 </enumeratedValue> 16825 </enumeratedValues> 16826 </field> 16827 <field> 16828 <name>RX_THRESH</name> 16829 <description>RX FIFO Threshold Crossed.</description> 16830 <bitOffset>2</bitOffset> 16831 <bitWidth>1</bitWidth> 16832 <enumeratedValues> 16833 <enumeratedValue> 16834 <name>clear</name> 16835 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 16836 <value>1</value> 16837 </enumeratedValue> 16838 </enumeratedValues> 16839 </field> 16840 <field> 16841 <name>RX_FULL</name> 16842 <description>RX FIFO FULL.</description> 16843 <bitOffset>3</bitOffset> 16844 <bitWidth>1</bitWidth> 16845 <enumeratedValues> 16846 <enumeratedValue> 16847 <name>clear</name> 16848 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 16849 <value>1</value> 16850 </enumeratedValue> 16851 </enumeratedValues> 16852 </field> 16853 <field> 16854 <name>SSA</name> 16855 <description>Slave Select Asserted.</description> 16856 <bitOffset>4</bitOffset> 16857 <bitWidth>1</bitWidth> 16858 <enumeratedValues> 16859 <enumeratedValue> 16860 <name>clear</name> 16861 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 16862 <value>1</value> 16863 </enumeratedValue> 16864 </enumeratedValues> 16865 </field> 16866 <field> 16867 <name>SSD</name> 16868 <description>Slave Select Deasserted.</description> 16869 <bitOffset>5</bitOffset> 16870 <bitWidth>1</bitWidth> 16871 <enumeratedValues> 16872 <enumeratedValue> 16873 <name>clear</name> 16874 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 16875 <value>1</value> 16876 </enumeratedValue> 16877 </enumeratedValues> 16878 </field> 16879 <field> 16880 <name>FAULT</name> 16881 <description>Multi-Master Mode Fault.</description> 16882 <bitOffset>8</bitOffset> 16883 <bitWidth>1</bitWidth> 16884 <enumeratedValues> 16885 <enumeratedValue> 16886 <name>clear</name> 16887 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 16888 <value>1</value> 16889 </enumeratedValue> 16890 </enumeratedValues> 16891 </field> 16892 <field> 16893 <name>ABORT</name> 16894 <description>Slave Abort Detected.</description> 16895 <bitOffset>9</bitOffset> 16896 <bitWidth>1</bitWidth> 16897 <enumeratedValues> 16898 <enumeratedValue> 16899 <name>clear</name> 16900 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 16901 <value>1</value> 16902 </enumeratedValue> 16903 </enumeratedValues> 16904 </field> 16905 <field> 16906 <name>M_DONE</name> 16907 <description>Master Done, set when SPI Master has completed any transactions.</description> 16908 <bitOffset>11</bitOffset> 16909 <bitWidth>1</bitWidth> 16910 <enumeratedValues> 16911 <enumeratedValue> 16912 <name>clear</name> 16913 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 16914 <value>1</value> 16915 </enumeratedValue> 16916 </enumeratedValues> 16917 </field> 16918 <field> 16919 <name>TX_OVR</name> 16920 <description>Transmit FIFO Overrun, set when the AMBA side attempts to write data 16921 to a full transmit FIFO.</description> 16922 <bitOffset>12</bitOffset> 16923 <bitWidth>1</bitWidth> 16924 <enumeratedValues> 16925 <enumeratedValue> 16926 <name>clear</name> 16927 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 16928 <value>1</value> 16929 </enumeratedValue> 16930 </enumeratedValues> 16931 </field> 16932 <field> 16933 <name>TX_UND</name> 16934 <description>Transmit FIFO Underrun, set when the SPI side attempts to read data 16935 from an empty transmit FIFO.</description> 16936 <bitOffset>13</bitOffset> 16937 <bitWidth>1</bitWidth> 16938 <enumeratedValues> 16939 <enumeratedValue> 16940 <name>clear</name> 16941 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 16942 <value>1</value> 16943 </enumeratedValue> 16944 </enumeratedValues> 16945 </field> 16946 <field> 16947 <name>RX_OVR</name> 16948 <description>Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO.</description> 16949 <bitOffset>14</bitOffset> 16950 <bitWidth>1</bitWidth> 16951 <enumeratedValues> 16952 <enumeratedValue> 16953 <name>clear</name> 16954 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 16955 <value>1</value> 16956 </enumeratedValue> 16957 </enumeratedValues> 16958 </field> 16959 <field> 16960 <name>RX_UND</name> 16961 <description>Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO.</description> 16962 <bitOffset>15</bitOffset> 16963 <bitWidth>1</bitWidth> 16964 <enumeratedValues> 16965 <enumeratedValue> 16966 <name>clear</name> 16967 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 16968 <value>1</value> 16969 </enumeratedValue> 16970 </enumeratedValues> 16971 </field> 16972 </fields> 16973 </register> 16974 <register> 16975 <name>INTEN</name> 16976 <description>Register for enabling interrupts.</description> 16977 <addressOffset>0x24</addressOffset> 16978 <access>read-write</access> 16979 <fields> 16980 <field> 16981 <name>TX_THRESH</name> 16982 <description>TX FIFO Threshold interrupt enable.</description> 16983 <bitOffset>0</bitOffset> 16984 <bitWidth>1</bitWidth> 16985 <enumeratedValues> 16986 <enumeratedValue> 16987 <name>dis</name> 16988 <description>Interrupt is disabled.</description> 16989 <value>0</value> 16990 </enumeratedValue> 16991 <enumeratedValue> 16992 <name>en</name> 16993 <description>Interrupt is enabled.</description> 16994 <value>1</value> 16995 </enumeratedValue> 16996 </enumeratedValues> 16997 </field> 16998 <field> 16999 <name>TX_EMPTY</name> 17000 <description>TX FIFO Empty interrupt enable.</description> 17001 <bitOffset>1</bitOffset> 17002 <bitWidth>1</bitWidth> 17003 <enumeratedValues> 17004 <enumeratedValue> 17005 <name>dis</name> 17006 <description>Interrupt is disabled.</description> 17007 <value>0</value> 17008 </enumeratedValue> 17009 <enumeratedValue> 17010 <name>en</name> 17011 <description>Interrupt is enabled.</description> 17012 <value>1</value> 17013 </enumeratedValue> 17014 </enumeratedValues> 17015 </field> 17016 <field> 17017 <name>RX_THRESH</name> 17018 <description>RX FIFO Threshold Crossed interrupt enable.</description> 17019 <bitOffset>2</bitOffset> 17020 <bitWidth>1</bitWidth> 17021 <enumeratedValues> 17022 <enumeratedValue> 17023 <name>dis</name> 17024 <description>Interrupt is disabled.</description> 17025 <value>0</value> 17026 </enumeratedValue> 17027 <enumeratedValue> 17028 <name>en</name> 17029 <description>Interrupt is enabled.</description> 17030 <value>1</value> 17031 </enumeratedValue> 17032 </enumeratedValues> 17033 </field> 17034 <field> 17035 <name>RX_FULL</name> 17036 <description>RX FIFO FULL interrupt enable.</description> 17037 <bitOffset>3</bitOffset> 17038 <bitWidth>1</bitWidth> 17039 <enumeratedValues> 17040 <enumeratedValue> 17041 <name>dis</name> 17042 <description>Interrupt is disabled.</description> 17043 <value>0</value> 17044 </enumeratedValue> 17045 <enumeratedValue> 17046 <name>en</name> 17047 <description>Interrupt is enabled.</description> 17048 <value>1</value> 17049 </enumeratedValue> 17050 </enumeratedValues> 17051 </field> 17052 <field> 17053 <name>SSA</name> 17054 <description>Slave Select Asserted interrupt enable.</description> 17055 <bitOffset>4</bitOffset> 17056 <bitWidth>1</bitWidth> 17057 <enumeratedValues> 17058 <enumeratedValue> 17059 <name>dis</name> 17060 <description>Interrupt is disabled.</description> 17061 <value>0</value> 17062 </enumeratedValue> 17063 <enumeratedValue> 17064 <name>en</name> 17065 <description>Interrupt is enabled.</description> 17066 <value>1</value> 17067 </enumeratedValue> 17068 </enumeratedValues> 17069 </field> 17070 <field> 17071 <name>SSD</name> 17072 <description>Slave Select Deasserted interrupt enable.</description> 17073 <bitOffset>5</bitOffset> 17074 <bitWidth>1</bitWidth> 17075 <enumeratedValues> 17076 <enumeratedValue> 17077 <name>dis</name> 17078 <description>Interrupt is disabled.</description> 17079 <value>0</value> 17080 </enumeratedValue> 17081 <enumeratedValue> 17082 <name>en</name> 17083 <description>Interrupt is enabled.</description> 17084 <value>1</value> 17085 </enumeratedValue> 17086 </enumeratedValues> 17087 </field> 17088 <field> 17089 <name>FAULT</name> 17090 <description>Multi-Master Mode Fault interrupt enable.</description> 17091 <bitOffset>8</bitOffset> 17092 <bitWidth>1</bitWidth> 17093 <enumeratedValues> 17094 <enumeratedValue> 17095 <name>dis</name> 17096 <description>Interrupt is disabled.</description> 17097 <value>0</value> 17098 </enumeratedValue> 17099 <enumeratedValue> 17100 <name>en</name> 17101 <description>Interrupt is enabled.</description> 17102 <value>1</value> 17103 </enumeratedValue> 17104 </enumeratedValues> 17105 </field> 17106 <field> 17107 <name>ABORT</name> 17108 <description>Slave Abort Detected interrupt enable.</description> 17109 <bitOffset>9</bitOffset> 17110 <bitWidth>1</bitWidth> 17111 <enumeratedValues> 17112 <enumeratedValue> 17113 <name>dis</name> 17114 <description>Interrupt is disabled.</description> 17115 <value>0</value> 17116 </enumeratedValue> 17117 <enumeratedValue> 17118 <name>en</name> 17119 <description>Interrupt is enabled.</description> 17120 <value>1</value> 17121 </enumeratedValue> 17122 </enumeratedValues> 17123 </field> 17124 <field> 17125 <name>M_DONE</name> 17126 <description>Master Done interrupt enable.</description> 17127 <bitOffset>11</bitOffset> 17128 <bitWidth>1</bitWidth> 17129 <enumeratedValues> 17130 <enumeratedValue> 17131 <name>dis</name> 17132 <description>Interrupt is disabled.</description> 17133 <value>0</value> 17134 </enumeratedValue> 17135 <enumeratedValue> 17136 <name>en</name> 17137 <description>Interrupt is enabled.</description> 17138 <value>1</value> 17139 </enumeratedValue> 17140 </enumeratedValues> 17141 </field> 17142 <field> 17143 <name>TX_OVR</name> 17144 <description>Transmit FIFO Overrun interrupt enable.</description> 17145 <bitOffset>12</bitOffset> 17146 <bitWidth>1</bitWidth> 17147 <enumeratedValues> 17148 <enumeratedValue> 17149 <name>dis</name> 17150 <description>Interrupt is disabled.</description> 17151 <value>0</value> 17152 </enumeratedValue> 17153 <enumeratedValue> 17154 <name>en</name> 17155 <description>Interrupt is enabled.</description> 17156 <value>1</value> 17157 </enumeratedValue> 17158 </enumeratedValues> 17159 </field> 17160 <field> 17161 <name>TX_UND</name> 17162 <description>Transmit FIFO Underrun interrupt enable.</description> 17163 <bitOffset>13</bitOffset> 17164 <bitWidth>1</bitWidth> 17165 <enumeratedValues> 17166 <enumeratedValue> 17167 <name>dis</name> 17168 <description>Interrupt is disabled.</description> 17169 <value>0</value> 17170 </enumeratedValue> 17171 <enumeratedValue> 17172 <name>en</name> 17173 <description>Interrupt is enabled.</description> 17174 <value>1</value> 17175 </enumeratedValue> 17176 </enumeratedValues> 17177 </field> 17178 <field> 17179 <name>RX_OVR</name> 17180 <description>Receive FIFO Overrun interrupt enable.</description> 17181 <bitOffset>14</bitOffset> 17182 <bitWidth>1</bitWidth> 17183 <enumeratedValues> 17184 <enumeratedValue> 17185 <name>dis</name> 17186 <description>Interrupt is disabled.</description> 17187 <value>0</value> 17188 </enumeratedValue> 17189 <enumeratedValue> 17190 <name>en</name> 17191 <description>Interrupt is enabled.</description> 17192 <value>1</value> 17193 </enumeratedValue> 17194 </enumeratedValues> 17195 </field> 17196 <field> 17197 <name>RX_UND</name> 17198 <description>Receive FIFO Underrun interrupt enable.</description> 17199 <bitOffset>15</bitOffset> 17200 <bitWidth>1</bitWidth> 17201 <enumeratedValues> 17202 <enumeratedValue> 17203 <name>dis</name> 17204 <description>Interrupt is disabled.</description> 17205 <value>0</value> 17206 </enumeratedValue> 17207 <enumeratedValue> 17208 <name>en</name> 17209 <description>Interrupt is enabled.</description> 17210 <value>1</value> 17211 </enumeratedValue> 17212 </enumeratedValues> 17213 </field> 17214 </fields> 17215 </register> 17216 <register> 17217 <name>WKFL</name> 17218 <description>Register for wake up flags. All bits in this register are write 1 to clear.</description> 17219 <addressOffset>0x28</addressOffset> 17220 <access>read-write</access> 17221 <fields> 17222 <field> 17223 <name>TX_THRESH</name> 17224 <description>Wake on TX FIFO Threshold Crossed.</description> 17225 <bitOffset>0</bitOffset> 17226 <bitWidth>1</bitWidth> 17227 <enumeratedValues> 17228 <enumeratedValue> 17229 <name>clear</name> 17230 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 17231 <value>1</value> 17232 </enumeratedValue> 17233 </enumeratedValues> 17234 </field> 17235 <field> 17236 <name>TX_EM</name> 17237 <description>Wake on TX FIFO Empty.</description> 17238 <bitOffset>1</bitOffset> 17239 <bitWidth>1</bitWidth> 17240 <enumeratedValues> 17241 <enumeratedValue> 17242 <name>clear</name> 17243 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 17244 <value>1</value> 17245 </enumeratedValue> 17246 </enumeratedValues> 17247 </field> 17248 <field> 17249 <name>RX_THRESH</name> 17250 <description>Wake on RX FIFO Threshold Crossed.</description> 17251 <bitOffset>2</bitOffset> 17252 <bitWidth>1</bitWidth> 17253 <enumeratedValues> 17254 <enumeratedValue> 17255 <name>clear</name> 17256 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 17257 <value>1</value> 17258 </enumeratedValue> 17259 </enumeratedValues> 17260 </field> 17261 <field> 17262 <name>RX_FULL</name> 17263 <description>Wake on RX FIFO Full.</description> 17264 <bitOffset>3</bitOffset> 17265 <bitWidth>1</bitWidth> 17266 <enumeratedValues> 17267 <enumeratedValue> 17268 <name>clear</name> 17269 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 17270 <value>1</value> 17271 </enumeratedValue> 17272 </enumeratedValues> 17273 </field> 17274 </fields> 17275 </register> 17276 <register> 17277 <name>WKEN</name> 17278 <description>Register for wake up enable.</description> 17279 <addressOffset>0x2C</addressOffset> 17280 <access>read-write</access> 17281 <fields> 17282 <field> 17283 <name>TX_THRESH</name> 17284 <description>Wake on TX FIFO Threshold Crossed Enable.</description> 17285 <bitOffset>0</bitOffset> 17286 <bitWidth>1</bitWidth> 17287 <enumeratedValues> 17288 <enumeratedValue> 17289 <name>dis</name> 17290 <description>Wakeup source disabled.</description> 17291 <value>0</value> 17292 </enumeratedValue> 17293 <enumeratedValue> 17294 <name>en</name> 17295 <description>Wakeup source enabled.</description> 17296 <value>1</value> 17297 </enumeratedValue> 17298 </enumeratedValues> 17299 </field> 17300 <field> 17301 <name>TX_EM</name> 17302 <description>Wake on TX FIFO Empty Enable.</description> 17303 <bitOffset>1</bitOffset> 17304 <bitWidth>1</bitWidth> 17305 <enumeratedValues> 17306 <enumeratedValue> 17307 <name>dis</name> 17308 <description>Wakeup source disabled.</description> 17309 <value>0</value> 17310 </enumeratedValue> 17311 <enumeratedValue> 17312 <name>en</name> 17313 <description>Wakeup source enabled.</description> 17314 <value>1</value> 17315 </enumeratedValue> 17316 </enumeratedValues> 17317 </field> 17318 <field> 17319 <name>RX_THRESH</name> 17320 <description>Wake on RX FIFO Threshold Crossed Enable.</description> 17321 <bitOffset>2</bitOffset> 17322 <bitWidth>1</bitWidth> 17323 <enumeratedValues> 17324 <enumeratedValue> 17325 <name>dis</name> 17326 <description>Wakeup source disabled.</description> 17327 <value>0</value> 17328 </enumeratedValue> 17329 <enumeratedValue> 17330 <name>en</name> 17331 <description>Wakeup source enabled.</description> 17332 <value>1</value> 17333 </enumeratedValue> 17334 </enumeratedValues> 17335 </field> 17336 <field> 17337 <name>RX_FULL</name> 17338 <description>Wake on RX FIFO Full Enable.</description> 17339 <bitOffset>3</bitOffset> 17340 <bitWidth>1</bitWidth> 17341 <enumeratedValues> 17342 <enumeratedValue> 17343 <name>dis</name> 17344 <description>Wakeup source disabled.</description> 17345 <value>0</value> 17346 </enumeratedValue> 17347 <enumeratedValue> 17348 <name>en</name> 17349 <description>Wakeup source enabled.</description> 17350 <value>1</value> 17351 </enumeratedValue> 17352 </enumeratedValues> 17353 </field> 17354 </fields> 17355 </register> 17356 <register> 17357 <name>STAT</name> 17358 <description>SPI Status register.</description> 17359 <addressOffset>0x30</addressOffset> 17360 <access>read-only</access> 17361 <fields> 17362 <field> 17363 <name>BUSY</name> 17364 <description>SPI active status. In Master mode, set when transaction starts, 17365 cleared when last bit of last character is acted upon and Slave Select 17366 de-assertion would occur. In Slave mode, set when Slave Select is 17367 asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. 17368 </description> 17369 <bitOffset>0</bitOffset> 17370 <bitWidth>1</bitWidth> 17371 <enumeratedValues> 17372 <enumeratedValue> 17373 <name>not</name> 17374 <description>SPI not active.</description> 17375 <value>0</value> 17376 </enumeratedValue> 17377 <enumeratedValue> 17378 <name>active</name> 17379 <description>SPI active.</description> 17380 <value>1</value> 17381 </enumeratedValue> 17382 </enumeratedValues> 17383 </field> 17384 </fields> 17385 </register> 17386 <register> 17387 <name>XMEMCTRL</name> 17388 <description>Register to control external memory.</description> 17389 <addressOffset>0x34</addressOffset> 17390 <access>read-write</access> 17391 <fields> 17392 <field> 17393 <name>RD_CMD</name> 17394 <description>Read command.</description> 17395 <bitOffset>0</bitOffset> 17396 <bitWidth>8</bitWidth> 17397 </field> 17398 <field> 17399 <name>WR_CMD</name> 17400 <description>Write command.</description> 17401 <bitOffset>8</bitOffset> 17402 <bitWidth>8</bitWidth> 17403 </field> 17404 <field> 17405 <name>DUMMY_CLK</name> 17406 <description>Dummy clocks.</description> 17407 <bitOffset>16</bitOffset> 17408 <bitWidth>8</bitWidth> 17409 </field> 17410 <field> 17411 <name>XMEM_EN</name> 17412 <description>XMEM enable.</description> 17413 <bitOffset>31</bitOffset> 17414 <bitWidth>1</bitWidth> 17415 </field> 17416 </fields> 17417 </register> 17418 </registers> 17419 </peripheral> 17420<!--SPIXR SPIXR peripheral.--> 17421 <peripheral> 17422 <name>SPIXFC</name> 17423 <description>SPI XiP Flash Configuration Controller</description> 17424 <baseAddress>0x40027000</baseAddress> 17425 <addressBlock> 17426 <offset>0</offset> 17427 <size>0x1000</size> 17428 <usage>registers</usage> 17429 </addressBlock> 17430 <interrupt> 17431 <name>SPIXFC</name> 17432 <description>SPIXFC IRQ</description> 17433 <value>38</value> 17434 </interrupt> 17435 <registers> 17436 <register> 17437 <name>CTRL0</name> 17438 <description>Control Register.</description> 17439 <addressOffset>0x00</addressOffset> 17440 <fields> 17441 <field> 17442 <name>SSEL</name> 17443 <description>Slaves Select.</description> 17444 <bitOffset>0</bitOffset> 17445 <bitWidth>3</bitWidth> 17446 <enumeratedValues> 17447 <enumeratedValue> 17448 <name>Slave_0</name> 17449 <description>Slave 0 is selected.</description> 17450 <value>0</value> 17451 </enumeratedValue> 17452 <enumeratedValue> 17453 <name>Slave_1</name> 17454 <description>Slave 1 is selected.</description> 17455 <value>1</value> 17456 </enumeratedValue> 17457 </enumeratedValues> 17458 </field> 17459 <field> 17460 <name>THREE_WIRE</name> 17461 <description>Three Wire Mode.</description> 17462 <bitOffset>3</bitOffset> 17463 <bitWidth>1</bitWidth> 17464 </field> 17465 <field> 17466 <name>MODE</name> 17467 <description>Defines SPI Mode, Only valid values are 0 and 3.</description> 17468 <bitOffset>4</bitOffset> 17469 <bitWidth>2</bitWidth> 17470 <enumeratedValues> 17471 <enumeratedValue> 17472 <name>SPI_Mode_0</name> 17473 <description>SPIX Mode 0. CLK Polarity = 0, CLK Phase = 0.</description> 17474 <value>0</value> 17475 </enumeratedValue> 17476 <enumeratedValue> 17477 <name>SPI_Mode_3</name> 17478 <description>SPIX Mode 3. CLK Polarity = 1, CLK Phase = 1.</description> 17479 <value>3</value> 17480 </enumeratedValue> 17481 </enumeratedValues> 17482 </field> 17483 <field> 17484 <name>PGSZ</name> 17485 <description>Page Size.</description> 17486 <bitOffset>6</bitOffset> 17487 <bitWidth>2</bitWidth> 17488 <enumeratedValues> 17489 <enumeratedValue> 17490 <name>4_bytes</name> 17491 <description>4 bytes.</description> 17492 <value>0</value> 17493 </enumeratedValue> 17494 <enumeratedValue> 17495 <name>8_bytes</name> 17496 <description>8 bytes.</description> 17497 <value>1</value> 17498 </enumeratedValue> 17499 <enumeratedValue> 17500 <name>16_bytes</name> 17501 <description>16 bytes.</description> 17502 <value>2</value> 17503 </enumeratedValue> 17504 <enumeratedValue> 17505 <name>32_bytes</name> 17506 <description>32 bytes.</description> 17507 <value>3</value> 17508 </enumeratedValue> 17509 </enumeratedValues> 17510 </field> 17511 <field> 17512 <name>HICLK</name> 17513 <description>SCLK High Clocks. Number of system clocks that SCLK will be high when SCLK pulses are generated. 0 Correspond to 16 system clocks and, all other values defines the number of system clock taht SCLK will be held high.</description> 17514 <bitOffset>8</bitOffset> 17515 <bitWidth>4</bitWidth> 17516 <enumeratedValues> 17517 <enumeratedValue> 17518 <name>16_SCLK</name> 17519 <description>16 system clocks.</description> 17520 <value>0</value> 17521 </enumeratedValue> 17522 </enumeratedValues> 17523 </field> 17524 <field> 17525 <name>LOCLK</name> 17526 <description>SCLK low Clocks. Number of system clocks that SCLK will be low when SCLK pulses are generated. 0 correspond to 16 system clocks and, all other values defines the number of system clock taht SCLK will be held low.</description> 17527 <bitOffset>12</bitOffset> 17528 <bitWidth>4</bitWidth> 17529 <enumeratedValues> 17530 <enumeratedValue> 17531 <name>16_SCLK</name> 17532 <description>16 system clocks.</description> 17533 <value>0</value> 17534 </enumeratedValue> 17535 </enumeratedValues> 17536 </field> 17537 <field> 17538 <name>SSACT</name> 17539 <description>Slaves Select Activate Timing.</description> 17540 <bitOffset>16</bitOffset> 17541 <bitWidth>2</bitWidth> 17542 <enumeratedValues> 17543 <enumeratedValue> 17544 <name>0_CLKS</name> 17545 <description>0 sytem clocks.</description> 17546 <value>0</value> 17547 </enumeratedValue> 17548 <enumeratedValue> 17549 <name>2_CLKS</name> 17550 <description>2 sytem clocks.</description> 17551 <value>1</value> 17552 </enumeratedValue> 17553 <enumeratedValue> 17554 <name>4_CLKS</name> 17555 <description>4 sytem clocks.</description> 17556 <value>2</value> 17557 </enumeratedValue> 17558 <enumeratedValue> 17559 <name>8_CLKS</name> 17560 <description>8 sytem clocks.</description> 17561 <value>3</value> 17562 </enumeratedValue> 17563 </enumeratedValues> 17564 </field> 17565 <field> 17566 <name>SSIACT</name> 17567 <description>Slaves Select Inactive Timing.</description> 17568 <bitOffset>18</bitOffset> 17569 <bitWidth>2</bitWidth> 17570 <enumeratedValues> 17571 <enumeratedValue> 17572 <name>4_CLKS</name> 17573 <description>4 sytem clocks.</description> 17574 <value>0</value> 17575 </enumeratedValue> 17576 <enumeratedValue> 17577 <name>6_CLKS</name> 17578 <description>6 sytem clocks.</description> 17579 <value>1</value> 17580 </enumeratedValue> 17581 <enumeratedValue> 17582 <name>8_CLKS</name> 17583 <description>8 sytem clocks.</description> 17584 <value>2</value> 17585 </enumeratedValue> 17586 <enumeratedValue> 17587 <name>12_CLKS</name> 17588 <description>12 sytem clocks.</description> 17589 <value>3</value> 17590 </enumeratedValue> 17591 </enumeratedValues> 17592 </field> 17593 <field> 17594 <name>IOSMPL</name> 17595 <description>Sample Delay</description> 17596 <bitOffset>20</bitOffset> 17597 <bitWidth>4</bitWidth> 17598 </field> 17599 </fields> 17600 </register> 17601 <register> 17602 <name>SSPOL</name> 17603 <description>SPIX Controller Slave Select Polarity Register.</description> 17604 <addressOffset>0x04</addressOffset> 17605 <fields> 17606 <field> 17607 <name>SS_POL</name> 17608 <description>Slave Select Polarity.</description> 17609 <bitOffset>0</bitOffset> 17610 <bitWidth>1</bitWidth> 17611 <enumeratedValues> 17612 <enumeratedValue> 17613 <name>lo</name> 17614 <description>Active Low.</description> 17615 <value>0</value> 17616 </enumeratedValue> 17617 <enumeratedValue> 17618 <name>hi</name> 17619 <description>Active High.</description> 17620 <value>1</value> 17621 </enumeratedValue> 17622 </enumeratedValues> 17623 </field> 17624 <field> 17625 <name>FC_POL</name> 17626 <description>FC Polarity.</description> 17627 <bitOffset>8</bitOffset> 17628 <bitWidth>1</bitWidth> 17629 <enumeratedValues> 17630 <enumeratedValue> 17631 <name>lo</name> 17632 <description>Active Low.</description> 17633 <value>0</value> 17634 </enumeratedValue> 17635 <enumeratedValue> 17636 <name>hi</name> 17637 <description>Active High.</description> 17638 <value>1</value> 17639 </enumeratedValue> 17640 </enumeratedValues> 17641 </field> 17642 </fields> 17643 </register> 17644 <register> 17645 <name>CTRL1</name> 17646 <description>SPIX Controller General Controller Register.</description> 17647 <addressOffset>0x08</addressOffset> 17648 <fields> 17649 <field> 17650 <name>EN</name> 17651 <description>SPI Master enable.</description> 17652 <bitOffset>0</bitOffset> 17653 <bitWidth>1</bitWidth> 17654 <enumeratedValues> 17655 <enumeratedValue> 17656 <name>dis</name> 17657 <description>Disable SPI Master, putting a reset state.</description> 17658 <value>0</value> 17659 </enumeratedValue> 17660 <enumeratedValue> 17661 <name>en</name> 17662 <description>Enable SPI Master for processing transactions.</description> 17663 <value>1</value> 17664 </enumeratedValue> 17665 </enumeratedValues> 17666 </field> 17667 <field> 17668 <name>TX_FIFO_EN</name> 17669 <description>Transaction FIFO Enable.</description> 17670 <bitOffset>1</bitOffset> 17671 <bitWidth>1</bitWidth> 17672 <enumeratedValues> 17673 <enumeratedValue> 17674 <name>dis_txfifo</name> 17675 <description>Disable Transaction FIFO.</description> 17676 <value>0</value> 17677 </enumeratedValue> 17678 <enumeratedValue> 17679 <name>en_txfifo</name> 17680 <description>Enable Transaction FIFO.</description> 17681 <value>1</value> 17682 </enumeratedValue> 17683 </enumeratedValues> 17684 </field> 17685 <field> 17686 <name>RX_FIFO_EN</name> 17687 <description>Result FIFO Enable.</description> 17688 <bitOffset>2</bitOffset> 17689 <bitWidth>1</bitWidth> 17690 <enumeratedValues> 17691 <enumeratedValue> 17692 <name>DIS_RXFIFO</name> 17693 <description>Disable Result FIFO.</description> 17694 <value>0</value> 17695 </enumeratedValue> 17696 <enumeratedValue> 17697 <name>EN_RXFIFO</name> 17698 <description>Enable Result FIFO.</description> 17699 <value>1</value> 17700 </enumeratedValue> 17701 </enumeratedValues> 17702 </field> 17703 <field> 17704 <name>BBMODE</name> 17705 <description>Bit-Bang Mode.</description> 17706 <bitOffset>3</bitOffset> 17707 <bitWidth>1</bitWidth> 17708 <enumeratedValues> 17709 <enumeratedValue> 17710 <name>dis</name> 17711 <description>Disable Bit-Bang Mode.</description> 17712 <value>0</value> 17713 </enumeratedValue> 17714 <enumeratedValue> 17715 <name>en</name> 17716 <description>Enable Bit-Bang Mode.</description> 17717 <value>1</value> 17718 </enumeratedValue> 17719 </enumeratedValues> 17720 </field> 17721 <field> 17722 <name>SSDR</name> 17723 <description>This bits reflects the state of the currently selected slave select.</description> 17724 <bitOffset>4</bitOffset> 17725 <bitWidth>1</bitWidth> 17726 <enumeratedValues> 17727 <enumeratedValue> 17728 <name>output0</name> 17729 <description>Selected Slave select output = 0.</description> 17730 <value>0</value> 17731 </enumeratedValue> 17732 <enumeratedValue> 17733 <name>output1</name> 17734 <description>Selected Slave select output = 1.</description> 17735 <value>1</value> 17736 </enumeratedValue> 17737 </enumeratedValues> 17738 </field> 17739 <field> 17740 <name>FCDR</name> 17741 <description>This bits reflects the state of the selected FC.</description> 17742 <bitOffset>5</bitOffset> 17743 <bitWidth>1</bitWidth> 17744 </field> 17745 <field> 17746 <name>SCLKDR</name> 17747 <description>SCLK Drive and State.</description> 17748 <bitOffset>6</bitOffset> 17749 <bitWidth>1</bitWidth> 17750 <enumeratedValues> 17751 <enumeratedValue> 17752 <name>SCLK_0</name> 17753 <description>SCLK is 0.</description> 17754 <value>0</value> 17755 </enumeratedValue> 17756 <enumeratedValue> 17757 <name>SCLK_1</name> 17758 <description>SCLK is 1.</description> 17759 <value>1</value> 17760 </enumeratedValue> 17761 </enumeratedValues> 17762 </field> 17763 <field> 17764 <name>SDIO_DATA_IN</name> 17765 <description>SDIO Input Data Value.</description> 17766 <bitOffset>8</bitOffset> 17767 <bitWidth>4</bitWidth> 17768 <enumeratedValues> 17769 <enumeratedValue> 17770 <name>SDIO0</name> 17771 <description>SDIO[0]</description> 17772 <value>0</value> 17773 </enumeratedValue> 17774 <enumeratedValue> 17775 <name>SDIO1</name> 17776 <description>SDIO[1]</description> 17777 <value>1</value> 17778 </enumeratedValue> 17779 <enumeratedValue> 17780 <name>SDIO2</name> 17781 <description>SDIO[2]</description> 17782 <value>2</value> 17783 </enumeratedValue> 17784 <enumeratedValue> 17785 <name>SDIO3</name> 17786 <description>SDIO[3]</description> 17787 <value>3</value> 17788 </enumeratedValue> 17789 </enumeratedValues> 17790 </field> 17791 <field> 17792 <name>BB_DATA_OUT</name> 17793 <description>No description available.</description> 17794 <bitOffset>12</bitOffset> 17795 <bitWidth>4</bitWidth> 17796 <enumeratedValues> 17797 <enumeratedValue> 17798 <name>SDIO0</name> 17799 <description>SDIO[0]</description> 17800 <value>0</value> 17801 </enumeratedValue> 17802 <enumeratedValue> 17803 <name>SDIO1</name> 17804 <description>SDIO[1]</description> 17805 <value>1</value> 17806 </enumeratedValue> 17807 <enumeratedValue> 17808 <name>SDIO2</name> 17809 <description>SDIO[2]</description> 17810 <value>2</value> 17811 </enumeratedValue> 17812 <enumeratedValue> 17813 <name>SDIO3</name> 17814 <description>SDIO[3]</description> 17815 <value>3</value> 17816 </enumeratedValue> 17817 </enumeratedValues> 17818 </field> 17819 <field> 17820 <name>BB_DATA_OUT_EN</name> 17821 <description>Bit Bang SDIO Output Enable.</description> 17822 <bitOffset>16</bitOffset> 17823 <bitWidth>4</bitWidth> 17824 <enumeratedValues> 17825 <enumeratedValue> 17826 <name>SDIO0</name> 17827 <description>SDIO[0]</description> 17828 <value>0</value> 17829 </enumeratedValue> 17830 <enumeratedValue> 17831 <name>SDIO1</name> 17832 <description>SDIO[1]</description> 17833 <value>1</value> 17834 </enumeratedValue> 17835 <enumeratedValue> 17836 <name>SDIO2</name> 17837 <description>SDIO[2]</description> 17838 <value>2</value> 17839 </enumeratedValue> 17840 <enumeratedValue> 17841 <name>SDIO3</name> 17842 <description>SDIO[3]</description> 17843 <value>3</value> 17844 </enumeratedValue> 17845 </enumeratedValues> 17846 </field> 17847 <field> 17848 <name>SIMPLE</name> 17849 <description>Simple Mode Enable.</description> 17850 <bitOffset>20</bitOffset> 17851 <bitWidth>1</bitWidth> 17852 </field> 17853 <field> 17854 <name>SIMPLE_RX</name> 17855 <description>Simple Receive Enable.</description> 17856 <bitOffset>21</bitOffset> 17857 <bitWidth>1</bitWidth> 17858 </field> 17859 <field> 17860 <name>SIMPLE_SS</name> 17861 <description>Simple Mode Slave Select.</description> 17862 <bitOffset>22</bitOffset> 17863 <bitWidth>1</bitWidth> 17864 </field> 17865 <field> 17866 <name>SCLK_FB</name> 17867 <description>Enable SCLK Feedback Mode.</description> 17868 <bitOffset>24</bitOffset> 17869 <bitWidth>1</bitWidth> 17870 <enumeratedValues> 17871 <enumeratedValue> 17872 <name>Dis</name> 17873 <value>0</value> 17874 </enumeratedValue> 17875 <enumeratedValue> 17876 <name>En</name> 17877 <value>1</value> 17878 </enumeratedValue> 17879 </enumeratedValues> 17880 </field> 17881 <field> 17882 <name>SCLK_FB_INV</name> 17883 <description>SCK Invert.</description> 17884 <bitOffset>25</bitOffset> 17885 <bitWidth>1</bitWidth> 17886 </field> 17887 </fields> 17888 </register> 17889 <register> 17890 <name>CTRL2</name> 17891 <description>SPIX Controller FIFO Control and Status Register.</description> 17892 <addressOffset>0x0C</addressOffset> 17893 <fields> 17894 <field> 17895 <name>TX_AE_LVL</name> 17896 <description>Transaction FIFO Almost Empty Level.</description> 17897 <bitOffset>0</bitOffset> 17898 <bitWidth>4</bitWidth> 17899 </field> 17900 <field> 17901 <name>TX_CNT</name> 17902 <description>Transaction FIFO Used.</description> 17903 <bitOffset>8</bitOffset> 17904 <bitWidth>5</bitWidth> 17905 </field> 17906 <field> 17907 <name>RX_AF_LVL</name> 17908 <description>Results FIFO Almost Full Level.</description> 17909 <bitOffset>16</bitOffset> 17910 <bitWidth>5</bitWidth> 17911 </field> 17912 <field> 17913 <name>RX_CNT</name> 17914 <description>Result FIFO Used.</description> 17915 <bitOffset>24</bitOffset> 17916 <bitWidth>6</bitWidth> 17917 </field> 17918 </fields> 17919 </register> 17920 <register> 17921 <name>CTRL3</name> 17922 <description>SPIX Controller Special Control Register.</description> 17923 <addressOffset>0x10</addressOffset> 17924 <fields> 17925 <field> 17926 <name>SAMPLE</name> 17927 <description>Setting this bit to a 1 enables the ability to drive SDIO outputs prior to the assertion of Slave Select. This bit must 17928 only be set when the SPIXF bus is idle and the transaction FIFO is empty. This bit is automatically cleared by hardware after the 17929 next slave select assertion.</description> 17930 <bitOffset>0</bitOffset> 17931 <bitWidth>1</bitWidth> 17932 </field> 17933 <field> 17934 <name>MISO_FC_EN</name> 17935 <description>MISO FC Enable.</description> 17936 <bitOffset>1</bitOffset> 17937 <bitWidth>1</bitWidth> 17938 </field> 17939 <field> 17940 <name>SDIO_OUT</name> 17941 <description>SDIO Output Value Sample Mode</description> 17942 <bitOffset>4</bitOffset> 17943 <bitWidth>4</bitWidth> 17944 </field> 17945 <field> 17946 <name>SDIO_OUT_EN</name> 17947 <description>SDIO Output Enable Sample Mode</description> 17948 <bitOffset>8</bitOffset> 17949 <bitWidth>4</bitWidth> 17950 </field> 17951 <field> 17952 <name>SCLKINH3</name> 17953 <description>SCLK Inhibit Mode3. In SPI Mode 3, some SPI flash read timing diagrams show the last SCLK going low prior to de-assertion. The default is to support this additional falling edge of clock. When this bit is set and the device is in SPI Mode 3, the SPI clock is held high while Slave Select is de-asserted. This is to support some SPI flash write timing diagrams.</description> 17954 <bitOffset>16</bitOffset> 17955 <bitWidth>1</bitWidth> 17956 <enumeratedValues> 17957 <enumeratedValue> 17958 <name>EN</name> 17959 <description>Allow trailing SCLK low pulse prior to Slave Select de-assertion.</description> 17960 <value>0</value> 17961 </enumeratedValue> 17962 <enumeratedValue> 17963 <name>DIS</name> 17964 <description>Inhibit trailing SCLK low pulse prior to Slave Select de-assertion.</description> 17965 <value>1</value> 17966 </enumeratedValue> 17967 </enumeratedValues> 17968 </field> 17969 </fields> 17970 </register> 17971 <register> 17972 <name>INTFL</name> 17973 <description>SPIX Controller Interrupt Status Register.</description> 17974 <addressOffset>0x14</addressOffset> 17975 <fields> 17976 <field> 17977 <name>TX_STALLED</name> 17978 <description>Transaction Stalled Interrupt Flag.</description> 17979 <bitOffset>0</bitOffset> 17980 <bitWidth>1</bitWidth> 17981 <enumeratedValues> 17982 <enumeratedValue> 17983 <name>CLR</name> 17984 <description>Normal FIFO Transaction.</description> 17985 <value>0</value> 17986 </enumeratedValue> 17987 <enumeratedValue> 17988 <name>SET</name> 17989 <description>Stalled FIFO Transaction.</description> 17990 <value>1</value> 17991 </enumeratedValue> 17992 </enumeratedValues> 17993 </field> 17994 <field> 17995 <name>RX_STALLED</name> 17996 <description>Results Stalled Interrupt Flag.</description> 17997 <bitOffset>1</bitOffset> 17998 <bitWidth>1</bitWidth> 17999 <enumeratedValues> 18000 <enumeratedValue> 18001 <name>CLR</name> 18002 <description>Normal FIFO Operation.</description> 18003 <value>0</value> 18004 </enumeratedValue> 18005 <enumeratedValue> 18006 <name>SET</name> 18007 <description>Stalled FIFO.</description> 18008 <value>1</value> 18009 </enumeratedValue> 18010 </enumeratedValues> 18011 </field> 18012 <field> 18013 <name>TX_RDY</name> 18014 <description>Transaction Ready Interrupt Status.</description> 18015 <bitOffset>2</bitOffset> 18016 <bitWidth>1</bitWidth> 18017 <enumeratedValues> 18018 <enumeratedValue> 18019 <name>CLR</name> 18020 <description>FIFO Transaction not ready.</description> 18021 <value>0</value> 18022 </enumeratedValue> 18023 <enumeratedValue> 18024 <name>SET</name> 18025 <description>FIFO Transaction ready.</description> 18026 <value>1</value> 18027 </enumeratedValue> 18028 </enumeratedValues> 18029 </field> 18030 <field> 18031 <name>RX_DONE</name> 18032 <description>Results Done Interrupt Status.</description> 18033 <bitOffset>3</bitOffset> 18034 <bitWidth>1</bitWidth> 18035 <enumeratedValues> 18036 <enumeratedValue> 18037 <name>CLR</name> 18038 <description>Results FIFO ready.</description> 18039 <value>0</value> 18040 </enumeratedValue> 18041 <enumeratedValue> 18042 <name>SET</name> 18043 <description>Results FIFO Not ready.</description> 18044 <value>1</value> 18045 </enumeratedValue> 18046 </enumeratedValues> 18047 </field> 18048 <field> 18049 <name>TX_FIFO_AE</name> 18050 <description>Transaction FIFO Almost Empty Flag.</description> 18051 <bitOffset>4</bitOffset> 18052 <bitWidth>1</bitWidth> 18053 <enumeratedValues> 18054 <enumeratedValue> 18055 <name>CLR</name> 18056 <description>Transaction FIFO not Almost Empty.</description> 18057 <value>0</value> 18058 </enumeratedValue> 18059 <enumeratedValue> 18060 <name>SET</name> 18061 <description>Transaction FIFO Almost Empty.</description> 18062 <value>1</value> 18063 </enumeratedValue> 18064 </enumeratedValues> 18065 </field> 18066 <field> 18067 <name>RX_FIFO_AF</name> 18068 <description>Results FIFO Almost Full Flag.</description> 18069 <bitOffset>5</bitOffset> 18070 <bitWidth>1</bitWidth> 18071 <enumeratedValues> 18072 <enumeratedValue> 18073 <name>CLR</name> 18074 <description>Results FIFO level below the Almost Full level.</description> 18075 <value>0</value> 18076 </enumeratedValue> 18077 <enumeratedValue> 18078 <name>SET</name> 18079 <description>Results FIFO level at Almost Full level.</description> 18080 <value>1</value> 18081 </enumeratedValue> 18082 </enumeratedValues> 18083 </field> 18084 </fields> 18085 </register> 18086 <register> 18087 <name>INTEN</name> 18088 <description>SPIX Controller Interrupt Enable Register.</description> 18089 <addressOffset>0x18</addressOffset> 18090 <fields> 18091 <field> 18092 <name>TX_STALLED</name> 18093 <description>Transaction Stalled Interrupt Enable.</description> 18094 <bitOffset>0</bitOffset> 18095 <bitWidth>1</bitWidth> 18096 <enumeratedValues> 18097 <enumeratedValue> 18098 <name>EN</name> 18099 <description>Disable Transaction Stalled Interrupt.</description> 18100 <value>0</value> 18101 </enumeratedValue> 18102 <enumeratedValue> 18103 <name>DIS</name> 18104 <description>Enable Transaction Stalled Interrupt.</description> 18105 <value>1</value> 18106 </enumeratedValue> 18107 </enumeratedValues> 18108 </field> 18109 <field> 18110 <name>RX_STALLED</name> 18111 <description>Results Stalled Interrupt Enable.</description> 18112 <bitOffset>1</bitOffset> 18113 <bitWidth>1</bitWidth> 18114 <enumeratedValues> 18115 <enumeratedValue> 18116 <name>EN</name> 18117 <description>Disable Results Stalled Interrupt.</description> 18118 <value>0</value> 18119 </enumeratedValue> 18120 <enumeratedValue> 18121 <name>DIS</name> 18122 <description>Enable Results Stalled Interrupt.</description> 18123 <value>1</value> 18124 </enumeratedValue> 18125 </enumeratedValues> 18126 </field> 18127 <field> 18128 <name>TX_RDY</name> 18129 <description>Transaction Ready Interrupt Enable.</description> 18130 <bitOffset>2</bitOffset> 18131 <bitWidth>1</bitWidth> 18132 <enumeratedValues> 18133 <enumeratedValue> 18134 <name>EN</name> 18135 <description>Disable FIFO Transaction Ready Interrupt.</description> 18136 <value>0</value> 18137 </enumeratedValue> 18138 <enumeratedValue> 18139 <name>DIS</name> 18140 <description>Enable FIFO Transaction Ready Interrupt.</description> 18141 <value>1</value> 18142 </enumeratedValue> 18143 </enumeratedValues> 18144 </field> 18145 <field> 18146 <name>RX_DONE</name> 18147 <description>Results Done Interrupt Enable.</description> 18148 <bitOffset>3</bitOffset> 18149 <bitWidth>1</bitWidth> 18150 <enumeratedValues> 18151 <enumeratedValue> 18152 <name>EN</name> 18153 <description>Disable Results Done Interrupt.</description> 18154 <value>0</value> 18155 </enumeratedValue> 18156 <enumeratedValue> 18157 <name>DIS</name> 18158 <description>Enable Results Done Interrupt.</description> 18159 <value>1</value> 18160 </enumeratedValue> 18161 </enumeratedValues> 18162 </field> 18163 <field> 18164 <name>TX_FIFO_AE</name> 18165 <description>Transaction FIFO Almost Empty Interrupt Enable.</description> 18166 <bitOffset>4</bitOffset> 18167 <bitWidth>1</bitWidth> 18168 <enumeratedValues> 18169 <enumeratedValue> 18170 <name>EN</name> 18171 <description>Disable Transaction FIFO Almost Empty Interrupt.</description> 18172 <value>0</value> 18173 </enumeratedValue> 18174 <enumeratedValue> 18175 <name>DIS</name> 18176 <description>Enable Transaction FIFO Almost Empty Interrupt.</description> 18177 <value>1</value> 18178 </enumeratedValue> 18179 </enumeratedValues> 18180 </field> 18181 <field> 18182 <name>RX_FIFO_AF</name> 18183 <description>Results FIFO Almost Full Interrupt Enable.</description> 18184 <bitOffset>5</bitOffset> 18185 <bitWidth>1</bitWidth> 18186 <enumeratedValues> 18187 <enumeratedValue> 18188 <name>EN</name> 18189 <description>Disable Results FIFO Almost Full Interrupt.</description> 18190 <value>0</value> 18191 </enumeratedValue> 18192 <enumeratedValue> 18193 <name>DIS</name> 18194 <description>Enable Results FIFO Almost Full Interrupt.</description> 18195 <value>1</value> 18196 </enumeratedValue> 18197 </enumeratedValues> 18198 </field> 18199 </fields> 18200 </register> 18201 <register> 18202 <name>SIMPLE_HEADER</name> 18203 <description>Simple Header</description> 18204 <addressOffset>0x1C</addressOffset> 18205 <fields> 18206 <field> 18207 <name>TX_BIDIR</name> 18208 <description>TX Bdirectional Header.</description> 18209 <bitOffset>0</bitOffset> 18210 <bitWidth>14</bitWidth> 18211 </field> 18212 <field> 18213 <name>RX_ONLY</name> 18214 <description>RX Only Header.</description> 18215 <bitOffset>16</bitOffset> 18216 <bitWidth>14</bitWidth> 18217 </field> 18218 </fields> 18219 </register> 18220 </registers> 18221 </peripheral> 18222<!--SPIXFC SPI XiP Flash Configuration Controller--> 18223 <peripheral> 18224 <name>SPIXFC_FIFO</name> 18225 <description>SPI XiP Master Controller FIFO.</description> 18226 <baseAddress>0x400BC000</baseAddress> 18227 <addressBlock> 18228 <offset>0</offset> 18229 <size>0x1000</size> 18230 <usage>registers</usage> 18231 </addressBlock> 18232 <registers> 18233 <register> 18234 <name>TX_8</name> 18235 <description>SPI TX FIFO 8-Bit Write</description> 18236 <addressOffset>0x00</addressOffset> 18237 <size>8</size> 18238 <dataType>uint8_t</dataType> 18239 </register> 18240 <register> 18241 <name>TX_16</name> 18242 <description>SPI TX FIFO 16-Bit Write</description> 18243 <alternateRegister>TX_8</alternateRegister> 18244 <addressOffset>0x00</addressOffset> 18245 <size>16</size> 18246 <dataType>uint16_t</dataType> 18247 </register> 18248 <register> 18249 <name>TX_32</name> 18250 <description>SPI TX FIFO 32-Bit Write</description> 18251 <alternateRegister>TX_8</alternateRegister> 18252 <addressOffset>0x00</addressOffset> 18253 <size>32</size> 18254 <dataType>uint32_t</dataType> 18255 </register> 18256 <register> 18257 <name>RX_8</name> 18258 <description>SPI RX FIFO 8-Bit Access</description> 18259 <addressOffset>0x04</addressOffset> 18260 <size>8</size> 18261 <dataType>uint8_t</dataType> 18262 </register> 18263 <register> 18264 <name>RX_16</name> 18265 <description>SPI RX FIFO 16-Bit Access</description> 18266 <alternateRegister>RX_8</alternateRegister> 18267 <addressOffset>0x04</addressOffset> 18268 <size>16</size> 18269 <dataType>uint16_t</dataType> 18270 </register> 18271 <register> 18272 <name>RX_32</name> 18273 <description>SPI RX FIFO 32-Bit Access</description> 18274 <alternateRegister>RX_8</alternateRegister> 18275 <addressOffset>0x04</addressOffset> 18276 <size>32</size> 18277 <dataType>uint32_t</dataType> 18278 </register> 18279 </registers> 18280 </peripheral> 18281<!--SPIXFC_FIFO SPI XiP Master Controller FIFO.--> 18282 <peripheral> 18283 <name>SPIXFM</name> 18284 <description>SPIXF Master</description> 18285 <baseAddress>0x40026000</baseAddress> 18286 <addressBlock> 18287 <offset>0x00</offset> 18288 <size>0x1000</size> 18289 <usage>registers</usage> 18290 </addressBlock> 18291 <registers> 18292 <register> 18293 <name>CTRL</name> 18294 <description>SPIX Control Register.</description> 18295 <addressOffset>0x00</addressOffset> 18296 <fields> 18297 <field> 18298 <name>MODE</name> 18299 <description>Defines SPI Mode, Only valid values are 0 and 3.</description> 18300 <bitOffset>0</bitOffset> 18301 <bitWidth>2</bitWidth> 18302 <enumeratedValues> 18303 <enumeratedValue> 18304 <name>SCLK_HI_SAMPLE_RISING</name> 18305 <description>Description not available.</description> 18306 <value>0</value> 18307 </enumeratedValue> 18308 <enumeratedValue> 18309 <name>SCLK_LO_SAMPLE_FAILLING</name> 18310 <description>Description not available.</description> 18311 <value>3</value> 18312 </enumeratedValue> 18313 </enumeratedValues> 18314 </field> 18315 <field> 18316 <name>SSPOL</name> 18317 <description>Slave Select Polarity.</description> 18318 <bitOffset>2</bitOffset> 18319 <bitWidth>1</bitWidth> 18320 <enumeratedValues> 18321 <enumeratedValue> 18322 <name>ACTIVE_HIGH</name> 18323 <description>Slave Select is Active High.</description> 18324 <value>0</value> 18325 </enumeratedValue> 18326 <enumeratedValue> 18327 <name>ACTIVE_LOW</name> 18328 <description>Slave Select is Active Low.</description> 18329 <value>1</value> 18330 </enumeratedValue> 18331 </enumeratedValues> 18332 </field> 18333 <field> 18334 <name>SSEL</name> 18335 <description>Slave Select. Only valid value is zero.</description> 18336 <bitOffset>4</bitOffset> 18337 <bitWidth>3</bitWidth> 18338 </field> 18339 <field> 18340 <name>LOCLK</name> 18341 <description>Number of system clocks that SCLK will be low when SCLK pulses are generated.</description> 18342 <bitOffset>8</bitOffset> 18343 <bitWidth>4</bitWidth> 18344 </field> 18345 <field> 18346 <name>HICLK</name> 18347 <description>Number of system clocks that SCLK will be high when SCLK pulses are generated.</description> 18348 <bitOffset>12</bitOffset> 18349 <bitWidth>4</bitWidth> 18350 </field> 18351 <field> 18352 <name>SSACT</name> 18353 <description>Slave Select Active Timing.</description> 18354 <bitOffset>16</bitOffset> 18355 <bitWidth>2</bitWidth> 18356 <enumeratedValues> 18357 <enumeratedValue> 18358 <name>off</name> 18359 <description>0 system clocks.</description> 18360 <value>0</value> 18361 </enumeratedValue> 18362 <enumeratedValue> 18363 <name>for_2_mod_clk</name> 18364 <description>2 System clocks.</description> 18365 <value>1</value> 18366 </enumeratedValue> 18367 <enumeratedValue> 18368 <name>for_4_mod_clk</name> 18369 <description>4 System clocks.</description> 18370 <value>2</value> 18371 </enumeratedValue> 18372 <enumeratedValue> 18373 <name>for_8_mod_clk</name> 18374 <description>8 System clocks.</description> 18375 <value>3</value> 18376 </enumeratedValue> 18377 </enumeratedValues> 18378 </field> 18379 <field> 18380 <name>SSIACT</name> 18381 <description>Slave Select Inactive Timing.</description> 18382 <bitOffset>18</bitOffset> 18383 <bitWidth>2</bitWidth> 18384 <enumeratedValues> 18385 <enumeratedValue> 18386 <name>for_1_mod_clk</name> 18387 <description>1 system clocks.</description> 18388 <value>0</value> 18389 </enumeratedValue> 18390 <enumeratedValue> 18391 <name>for_3_mod_clk</name> 18392 <description>3 System clocks.</description> 18393 <value>1</value> 18394 </enumeratedValue> 18395 <enumeratedValue> 18396 <name>for_5_mod_clk</name> 18397 <description>5 System clocks.</description> 18398 <value>2</value> 18399 </enumeratedValue> 18400 <enumeratedValue> 18401 <name>for_9_mod_clk</name> 18402 <description>9 System clocks.</description> 18403 <value>3</value> 18404 </enumeratedValue> 18405 </enumeratedValues> 18406 </field> 18407 </fields> 18408 </register> 18409 <register> 18410 <name>FETCHCTRL</name> 18411 <description>SPIX Fetch Control Register.</description> 18412 <addressOffset>0x04</addressOffset> 18413 <fields> 18414 <field> 18415 <name>CMDVAL</name> 18416 <description>Command Value sent to target to initiate fetching from SPI flash.</description> 18417 <bitOffset>0</bitOffset> 18418 <bitWidth>8</bitWidth> 18419 </field> 18420 <field> 18421 <name>CMDWTH</name> 18422 <description>Command Width. Number of data I/O used to send commands.</description> 18423 <bitOffset>8</bitOffset> 18424 <bitWidth>2</bitWidth> 18425 <enumeratedValues> 18426 <enumeratedValue> 18427 <name>Single</name> 18428 <description>Single SDIO.</description> 18429 <value>0</value> 18430 </enumeratedValue> 18431 <enumeratedValue> 18432 <name>Dual_IO</name> 18433 <description>Dual SDIO.</description> 18434 <value>1</value> 18435 </enumeratedValue> 18436 <enumeratedValue> 18437 <name>Quad_IO</name> 18438 <description>Quad SDIO.</description> 18439 <value>2</value> 18440 </enumeratedValue> 18441 <enumeratedValue> 18442 <name>Invalid</name> 18443 <description>Invalid.</description> 18444 <value>3</value> 18445 </enumeratedValue> 18446 </enumeratedValues> 18447 </field> 18448 <field> 18449 <name>ADDR_WIDTH</name> 18450 <description>Address Width. Number of data I/O used to send address, and mode/dummy clocks.</description> 18451 <bitOffset>10</bitOffset> 18452 <bitWidth>2</bitWidth> 18453 <enumeratedValues> 18454 <enumeratedValue> 18455 <name>Single</name> 18456 <description>Single SDIO.</description> 18457 <value>0</value> 18458 </enumeratedValue> 18459 <enumeratedValue> 18460 <name>Dual_IO</name> 18461 <description>Dual SDIO.</description> 18462 <value>1</value> 18463 </enumeratedValue> 18464 <enumeratedValue> 18465 <name>Quad_IO</name> 18466 <description>Quad SDIO.</description> 18467 <value>2</value> 18468 </enumeratedValue> 18469 <enumeratedValue> 18470 <name>Invalid</name> 18471 <description>Invalid.</description> 18472 <value>3</value> 18473 </enumeratedValue> 18474 </enumeratedValues> 18475 </field> 18476 <field> 18477 <name>DATA_WIDTH</name> 18478 <description>Data Width. Number of data I/O used to receive data.</description> 18479 <bitOffset>12</bitOffset> 18480 <bitWidth>2</bitWidth> 18481 <enumeratedValues> 18482 <enumeratedValue> 18483 <name>Single</name> 18484 <description>Single SDIO.</description> 18485 <value>0</value> 18486 </enumeratedValue> 18487 <enumeratedValue> 18488 <name>Dual_IO</name> 18489 <description>Dual SDIO.</description> 18490 <value>1</value> 18491 </enumeratedValue> 18492 <enumeratedValue> 18493 <name>Quad_IO</name> 18494 <description>Quad SDIO.</description> 18495 <value>2</value> 18496 </enumeratedValue> 18497 <enumeratedValue> 18498 <name>Invalid</name> 18499 <description>Invalid.</description> 18500 <value>3</value> 18501 </enumeratedValue> 18502 </enumeratedValues> 18503 </field> 18504 <field> 18505 <name>4BADDR</name> 18506 <description>Four Byte Address Mode. Enables 4-byte Flash Address Mode.</description> 18507 <bitOffset>16</bitOffset> 18508 <bitWidth>1</bitWidth> 18509 <enumeratedValues> 18510 <enumeratedValue> 18511 <name>3</name> 18512 <description>3 Byte Address Mode.</description> 18513 <value>0</value> 18514 </enumeratedValue> 18515 <enumeratedValue> 18516 <name>4</name> 18517 <description>4 Byte Address Mode.</description> 18518 <value>1</value> 18519 </enumeratedValue> 18520 </enumeratedValues> 18521 </field> 18522 </fields> 18523 </register> 18524 <register> 18525 <name>MODECTRL</name> 18526 <description>SPIX Mode Control Register.</description> 18527 <addressOffset>0x08</addressOffset> 18528 <fields> 18529 <field> 18530 <name>MDCLK</name> 18531 <description>Mode Clocks. Number of SPI clocks needed during mode/dummy phase of fetch.</description> 18532 <bitOffset>0</bitOffset> 18533 <bitWidth>4</bitWidth> 18534 </field> 18535 <field> 18536 <name>NOCMD</name> 18537 <description>No Command Mode.</description> 18538 <bitOffset>8</bitOffset> 18539 <bitWidth>1</bitWidth> 18540 <enumeratedValues> 18541 <enumeratedValue> 18542 <name>always</name> 18543 <description>Send read command every time SPI transaction is initiated.</description> 18544 <value>0</value> 18545 </enumeratedValue> 18546 <enumeratedValue> 18547 <name>once</name> 18548 <description>Send read command only once. NO read command in subsequent SPI transactions.</description> 18549 <value>1</value> 18550 </enumeratedValue> 18551 </enumeratedValues> 18552 </field> 18553 <field> 18554 <name>EXIT_NOCMD</name> 18555 <description>Mode Send.</description> 18556 <bitOffset>9</bitOffset> 18557 <bitWidth>1</bitWidth> 18558 </field> 18559 </fields> 18560 </register> 18561 <register> 18562 <name>MODEDATA</name> 18563 <description>SPIX Mode Data Register.</description> 18564 <addressOffset>0x0C</addressOffset> 18565 <fields> 18566 <field> 18567 <name>MDDATA</name> 18568 <description>Mode Data. Specifies the data to send with the Dummy/Mode clocks.</description> 18569 <bitOffset>0</bitOffset> 18570 <bitWidth>16</bitWidth> 18571 </field> 18572 <field> 18573 <name>MDOUT_EN</name> 18574 <description>Mode Output Enable. Output enable state for each corresponding data bit in MD_DATA. 0: output enable off, I/O is tristate and 1: Output enable on, I/O is driving MD_DATA.</description> 18575 <bitOffset>16</bitOffset> 18576 <bitWidth>16</bitWidth> 18577 </field> 18578 </fields> 18579 </register> 18580 <register> 18581 <name>FBCTRL</name> 18582 <description>SPIX Feedback Control Register.</description> 18583 <addressOffset>0x10</addressOffset> 18584 <fields> 18585 <field> 18586 <name>FB_EN</name> 18587 <description>Enable SCLK feedback mode.</description> 18588 <bitOffset>0</bitOffset> 18589 <bitWidth>1</bitWidth> 18590 <enumeratedValues> 18591 <enumeratedValue> 18592 <name>dis</name> 18593 <description>Disable SCLK feedback mode.</description> 18594 <value>0</value> 18595 </enumeratedValue> 18596 <enumeratedValue> 18597 <name>en</name> 18598 <description>Enable SCLK feedback mode.</description> 18599 <value>1</value> 18600 </enumeratedValue> 18601 </enumeratedValues> 18602 </field> 18603 <field> 18604 <name>INVERT</name> 18605 <description>Invert SCLK in feedback mode.</description> 18606 <bitOffset>1</bitOffset> 18607 <bitWidth>1</bitWidth> 18608 <enumeratedValues> 18609 <enumeratedValue> 18610 <name>dis</name> 18611 <description>Disable Invert SCLK feedback mode.</description> 18612 <value>0</value> 18613 </enumeratedValue> 18614 <enumeratedValue> 18615 <name>en</name> 18616 <description>Enable Invert SCLK feedback mode.</description> 18617 <value>1</value> 18618 </enumeratedValue> 18619 </enumeratedValues> 18620 </field> 18621 </fields> 18622 </register> 18623 <register> 18624 <name>IOCTRL</name> 18625 <description>SPIX IO Control Register.</description> 18626 <addressOffset>0x1C</addressOffset> 18627 <fields> 18628 <field> 18629 <name>SCLK_DS</name> 18630 <description>SCLK drive Strength. This bit controls the drive strength on the SCLK pin.</description> 18631 <bitOffset>0</bitOffset> 18632 <bitWidth>1</bitWidth> 18633 <enumeratedValues> 18634 <enumeratedValue> 18635 <name>Low</name> 18636 <description>Low drive strength.</description> 18637 <value>0</value> 18638 </enumeratedValue> 18639 <enumeratedValue> 18640 <name>High</name> 18641 <description>High drive strength.</description> 18642 <value>1</value> 18643 </enumeratedValue> 18644 </enumeratedValues> 18645 </field> 18646 <field> 18647 <name>SS_DS</name> 18648 <description>Slave Select Drive Strength. This bit controls the drive strength on the dedicated slave select pin.</description> 18649 <bitOffset>1</bitOffset> 18650 <bitWidth>1</bitWidth> 18651 <enumeratedValues> 18652 <enumeratedValue> 18653 <name>Low</name> 18654 <description>Low drive strength.</description> 18655 <value>0</value> 18656 </enumeratedValue> 18657 <enumeratedValue> 18658 <name>High</name> 18659 <description>High drive strength.</description> 18660 <value>1</value> 18661 </enumeratedValue> 18662 </enumeratedValues> 18663 </field> 18664 <field> 18665 <name>SDIO_DS</name> 18666 <description>SDIO Drive Strength. This bit controls the drive strength of all SDIO pins.</description> 18667 <bitOffset>2</bitOffset> 18668 <bitWidth>1</bitWidth> 18669 <enumeratedValues> 18670 <enumeratedValue> 18671 <name>Low</name> 18672 <description>Low drive strength.</description> 18673 <value>0</value> 18674 </enumeratedValue> 18675 <enumeratedValue> 18676 <name>High</name> 18677 <description>High drive strength.</description> 18678 <value>1</value> 18679 </enumeratedValue> 18680 </enumeratedValues> 18681 </field> 18682 <field> 18683 <name>PADCTRL</name> 18684 <description>IO Pullup/Pulldown Control. These bits control the pullups and pulldowns associated with all SPI XiP SDIO pins.</description> 18685 <bitOffset>3</bitOffset> 18686 <bitWidth>2</bitWidth> 18687 <enumeratedValues> 18688 <enumeratedValue> 18689 <name>tri_state</name> 18690 <description>Tristate.</description> 18691 <value>0</value> 18692 </enumeratedValue> 18693 <enumeratedValue> 18694 <name>Pull_Up</name> 18695 <description>Pull-Up.</description> 18696 <value>1</value> 18697 </enumeratedValue> 18698 <enumeratedValue> 18699 <name>Pull_down</name> 18700 <description>Pull-Down.</description> 18701 <value>2</value> 18702 </enumeratedValue> 18703 </enumeratedValues> 18704 </field> 18705 </fields> 18706 </register> 18707 <register> 18708 <name>MEMSECCTRL</name> 18709 <description>SPIX Memory Security Control Register.</description> 18710 <addressOffset>0x20</addressOffset> 18711 <fields> 18712 <field> 18713 <name>DEC_EN</name> 18714 <description>Decryption Enable.</description> 18715 <bitOffset>0</bitOffset> 18716 <bitWidth>1</bitWidth> 18717 <enumeratedValues> 18718 <enumeratedValue> 18719 <name>dis</name> 18720 <description>Disable decryption of SPIX data.</description> 18721 <value>0</value> 18722 </enumeratedValue> 18723 <enumeratedValue> 18724 <name>en</name> 18725 <description>Enable decryption of SPIX data.</description> 18726 <value>1</value> 18727 </enumeratedValue> 18728 </enumeratedValues> 18729 </field> 18730 <field> 18731 <name>AUTH_DISABLE</name> 18732 <description>Integrity Enable.</description> 18733 <bitOffset>1</bitOffset> 18734 <bitWidth>1</bitWidth> 18735 <enumeratedValues> 18736 <enumeratedValue> 18737 <name>en</name> 18738 <description>Integrity checking enabled.</description> 18739 <value>0</value> 18740 </enumeratedValue> 18741 <enumeratedValue> 18742 <name>dis</name> 18743 <description>Integrity checking disabled.</description> 18744 <value>1</value> 18745 </enumeratedValue> 18746 </enumeratedValues> 18747 </field> 18748 <field> 18749 <name>CNTOPT_EN</name> 18750 <description>Enable counters optimization (when authentication is enabled).</description> 18751 <bitOffset>2</bitOffset> 18752 <bitWidth>1</bitWidth> 18753 <enumeratedValues> 18754 <enumeratedValue> 18755 <name>dis</name> 18756 <description>Disable counter optimization.</description> 18757 <value>0</value> 18758 </enumeratedValue> 18759 <enumeratedValue> 18760 <name>en</name> 18761 <description>Enable counter optimization.</description> 18762 <value>1</value> 18763 </enumeratedValue> 18764 </enumeratedValues> 18765 </field> 18766 <field> 18767 <name>INTERL_DIS</name> 18768 <description>Disable authenticity interleaving (when authentication is enabled)</description> 18769 <bitOffset>3</bitOffset> 18770 <bitWidth>1</bitWidth> 18771 <enumeratedValues> 18772 <enumeratedValue> 18773 <name>dis</name> 18774 <description>Disable interleaving of SPIX data.</description> 18775 <value>1</value> 18776 </enumeratedValue> 18777 <enumeratedValue> 18778 <name>en</name> 18779 <description>Enable interleaving of SPIX data.</description> 18780 <value>0</value> 18781 </enumeratedValue> 18782 </enumeratedValues> 18783 </field> 18784 <field> 18785 <name>AUTHERR_FL</name> 18786 <description>Authentication Error Flag Bit.</description> 18787 <bitOffset>4</bitOffset> 18788 <bitWidth>1</bitWidth> 18789 </field> 18790 </fields> 18791 </register> 18792 <register> 18793 <name>BUSIDLE</name> 18794 <description>Bus Idle</description> 18795 <addressOffset>0x24</addressOffset> 18796 <fields> 18797 <field> 18798 <name>BUSIDLE</name> 18799 <description>A 16-bit timer will be triggered for each external access. The timer will be 18800 restarted if another access is performed before the timer expires. When the 18801 timer expires, slave select will be deactivated.</description> 18802 <bitOffset>0</bitOffset> 18803 <bitWidth>16</bitWidth> 18804 </field> 18805 </fields> 18806 </register> 18807 <register> 18808 <name>AUTHOFFSET</name> 18809 <description>Auth Offset</description> 18810 <addressOffset>0x28</addressOffset> 18811 </register> 18812 </registers> 18813 </peripheral> 18814<!--SPIXFM SPIXF Master--> 18815 <peripheral> 18816 <name>TMR</name> 18817 <description>Low-Power Configurable Timer</description> 18818 <baseAddress>0x40010000</baseAddress> 18819 <addressBlock> 18820 <offset>0x00</offset> 18821 <size>0x1000</size> 18822 <usage>registers</usage> 18823 </addressBlock> 18824 <interrupt> 18825 <name>TMR</name> 18826 <value>5</value> 18827 </interrupt> 18828 <registers> 18829 <register> 18830 <name>CNT</name> 18831 <description>Timer Counter Register.</description> 18832 <addressOffset>0x00</addressOffset> 18833 <access>read-write</access> 18834 <fields> 18835 <field> 18836 <name>COUNT</name> 18837 <description>The current count value for the timer. This field increments as the timer counts.</description> 18838 <bitOffset>0</bitOffset> 18839 <bitWidth>32</bitWidth> 18840 </field> 18841 </fields> 18842 </register> 18843 <register> 18844 <name>CMP</name> 18845 <description>Timer Compare Register.</description> 18846 <addressOffset>0x04</addressOffset> 18847 <access>read-write</access> 18848 <fields> 18849 <field> 18850 <name>COMPARE</name> 18851 <description>The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer.</description> 18852 <bitOffset>0</bitOffset> 18853 <bitWidth>32</bitWidth> 18854 </field> 18855 </fields> 18856 </register> 18857 <register> 18858 <name>PWM</name> 18859 <description>Timer PWM Register.</description> 18860 <addressOffset>0x08</addressOffset> 18861 <access>read-write</access> 18862 <fields> 18863 <field> 18864 <name>PWM</name> 18865 <description>Timer PWM Match: 18866 In PWM Mode, this field sets the count value for the first transition period of the PWM cycle. At the end of the cycle where CNT equals PWM, the PWM output transitions to the second period of the PWM cycle. The second PWM period count is stored in the CMP register. The value set for PWM must me less than the value set in CMP for PWM mode operation. Timer Capture Value: 18867 In Capture, Compare, and Capture/Compare modes, this field is used to store the CNT value when a Capture, Compare, or Capture/Compare event occurs.</description> 18868 <bitOffset>0</bitOffset> 18869 <bitWidth>32</bitWidth> 18870 </field> 18871 </fields> 18872 </register> 18873 <register> 18874 <name>INTFL</name> 18875 <description>Timer Interrupt Status Register.</description> 18876 <addressOffset>0x0C</addressOffset> 18877 <access>read-write</access> 18878 <fields> 18879 <field> 18880 <name>IRQ_A</name> 18881 <description>Interrupt Flag for Timer A.</description> 18882 <bitOffset>0</bitOffset> 18883 <bitWidth>1</bitWidth> 18884 </field> 18885 <field> 18886 <name>WRDONE_A</name> 18887 <description>Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain.</description> 18888 <bitOffset>8</bitOffset> 18889 <bitWidth>1</bitWidth> 18890 </field> 18891 <field> 18892 <name>WR_DIS_A</name> 18893 <description>Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration.</description> 18894 <bitOffset>9</bitOffset> 18895 <bitWidth>1</bitWidth> 18896 </field> 18897 <field> 18898 <name>IRQ_B</name> 18899 <description>Interrupt Flag for Timer B.</description> 18900 <bitOffset>16</bitOffset> 18901 <bitWidth>1</bitWidth> 18902 </field> 18903 <field> 18904 <name>WRDONE_B</name> 18905 <description>Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain.</description> 18906 <bitOffset>24</bitOffset> 18907 <bitWidth>1</bitWidth> 18908 </field> 18909 <field> 18910 <name>WR_DIS_B</name> 18911 <description>Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration.</description> 18912 <bitOffset>25</bitOffset> 18913 <bitWidth>1</bitWidth> 18914 </field> 18915 </fields> 18916 </register> 18917 <register> 18918 <name>CTRL0</name> 18919 <description>Timer Control Register.</description> 18920 <addressOffset>0x10</addressOffset> 18921 <access>read-write</access> 18922 <fields> 18923 <field> 18924 <name>MODE_A</name> 18925 <description>Mode Select for Timer A</description> 18926 <bitOffset>0</bitOffset> 18927 <bitWidth>4</bitWidth> 18928 <enumeratedValues> 18929 <enumeratedValue> 18930 <name>ONE_SHOT</name> 18931 <description>One-Shot Mode</description> 18932 <value>0</value> 18933 </enumeratedValue> 18934 <enumeratedValue> 18935 <name>CONTINUOUS</name> 18936 <description>Continuous Mode</description> 18937 <value>1</value> 18938 </enumeratedValue> 18939 <enumeratedValue> 18940 <name>COUNTER</name> 18941 <description>Counter Mode</description> 18942 <value>2</value> 18943 </enumeratedValue> 18944 <enumeratedValue> 18945 <name>PWM</name> 18946 <description>PWM Mode</description> 18947 <value>3</value> 18948 </enumeratedValue> 18949 <enumeratedValue> 18950 <name>CAPTURE</name> 18951 <description>Capture Mode</description> 18952 <value>4</value> 18953 </enumeratedValue> 18954 <enumeratedValue> 18955 <name>COMPARE</name> 18956 <description>Compare Mode</description> 18957 <value>5</value> 18958 </enumeratedValue> 18959 <enumeratedValue> 18960 <name>GATED</name> 18961 <description>Gated Mode</description> 18962 <value>6</value> 18963 </enumeratedValue> 18964 <enumeratedValue> 18965 <name>CAPCOMP</name> 18966 <description>Capture/Compare Mode</description> 18967 <value>7</value> 18968 </enumeratedValue> 18969 <enumeratedValue> 18970 <name>DUAL_EDGE</name> 18971 <description>Dual Edge Capture Mode</description> 18972 <value>8</value> 18973 </enumeratedValue> 18974 <enumeratedValue> 18975 <name>IGATED</name> 18976 <description>Inactive Gated Mode</description> 18977 <value>14</value> 18978 </enumeratedValue> 18979 </enumeratedValues> 18980 </field> 18981 <field> 18982 <name>CLKDIV_A</name> 18983 <description>Clock Divider Select for Timer A</description> 18984 <bitOffset>4</bitOffset> 18985 <bitWidth>4</bitWidth> 18986 <enumeratedValues> 18987 <enumeratedValue> 18988 <name>DIV_BY_1</name> 18989 <description>Prescaler Divide-By-1</description> 18990 <value>0</value> 18991 </enumeratedValue> 18992 <enumeratedValue> 18993 <name>DIV_BY_2</name> 18994 <description>Prescaler Divide-By-2</description> 18995 <value>1</value> 18996 </enumeratedValue> 18997 <enumeratedValue> 18998 <name>DIV_BY_4</name> 18999 <description>Prescaler Divide-By-4</description> 19000 <value>2</value> 19001 </enumeratedValue> 19002 <enumeratedValue> 19003 <name>DIV_BY_8</name> 19004 <description>Prescaler Divide-By-8</description> 19005 <value>3</value> 19006 </enumeratedValue> 19007 <enumeratedValue> 19008 <name>DIV_BY_16</name> 19009 <description>Prescaler Divide-By-16</description> 19010 <value>4</value> 19011 </enumeratedValue> 19012 <enumeratedValue> 19013 <name>DIV_BY_32</name> 19014 <description>Prescaler Divide-By-32</description> 19015 <value>5</value> 19016 </enumeratedValue> 19017 <enumeratedValue> 19018 <name>DIV_BY_64</name> 19019 <description>Prescaler Divide-By-64</description> 19020 <value>6</value> 19021 </enumeratedValue> 19022 <enumeratedValue> 19023 <name>DIV_BY_128</name> 19024 <description>Prescaler Divide-By-128</description> 19025 <value>7</value> 19026 </enumeratedValue> 19027 <enumeratedValue> 19028 <name>DIV_BY_256</name> 19029 <description>Prescaler Divide-By-256</description> 19030 <value>8</value> 19031 </enumeratedValue> 19032 <enumeratedValue> 19033 <name>DIV_BY_512</name> 19034 <description>Prescaler Divide-By-512</description> 19035 <value>9</value> 19036 </enumeratedValue> 19037 <enumeratedValue> 19038 <name>DIV_BY_1024</name> 19039 <description>Prescaler Divide-By-1024</description> 19040 <value>10</value> 19041 </enumeratedValue> 19042 <enumeratedValue> 19043 <name>DIV_BY_2048</name> 19044 <description>Prescaler Divide-By-2048</description> 19045 <value>11</value> 19046 </enumeratedValue> 19047 <enumeratedValue> 19048 <name>DIV_BY_4096</name> 19049 <description>TBD</description> 19050 <value>12</value> 19051 </enumeratedValue> 19052 </enumeratedValues> 19053 </field> 19054 <field> 19055 <name>POL_A</name> 19056 <description>Timer Polarity for Timer A</description> 19057 <bitOffset>8</bitOffset> 19058 <bitWidth>1</bitWidth> 19059 </field> 19060 <field> 19061 <name>PWMSYNC_A</name> 19062 <description>PWM Synchronization Mode for Timer A</description> 19063 <bitOffset>9</bitOffset> 19064 <bitWidth>1</bitWidth> 19065 </field> 19066 <field> 19067 <name>NOLHPOL_A</name> 19068 <description>PWM Phase A (Non-Overlapping High) Polarity for Timer A</description> 19069 <bitOffset>10</bitOffset> 19070 <bitWidth>1</bitWidth> 19071 </field> 19072 <field> 19073 <name>NOLLPOL_A</name> 19074 <description>PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A</description> 19075 <bitOffset>11</bitOffset> 19076 <bitWidth>1</bitWidth> 19077 </field> 19078 <field> 19079 <name>PWMCKBD_A</name> 19080 <description>PWM Phase A-Prime Output Disable for Timer A</description> 19081 <bitOffset>12</bitOffset> 19082 <bitWidth>1</bitWidth> 19083 </field> 19084 <field> 19085 <name>RST_A</name> 19086 <description>Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears.</description> 19087 <bitOffset>13</bitOffset> 19088 <bitWidth>1</bitWidth> 19089 </field> 19090 <field> 19091 <name>CLKEN_A</name> 19092 <description>Write 1 to Enable CLK_TMR for Timer A</description> 19093 <bitOffset>14</bitOffset> 19094 <bitWidth>1</bitWidth> 19095 </field> 19096 <field> 19097 <name>EN_A</name> 19098 <description>Enable for Timer A</description> 19099 <bitOffset>15</bitOffset> 19100 <bitWidth>1</bitWidth> 19101 </field> 19102 <field> 19103 <name>MODE_B</name> 19104 <description>Mode Select for Timer B</description> 19105 <bitOffset>16</bitOffset> 19106 <bitWidth>4</bitWidth> 19107 <enumeratedValues> 19108 <enumeratedValue> 19109 <name>ONE_SHOT</name> 19110 <description>One-Shot Mode</description> 19111 <value>0</value> 19112 </enumeratedValue> 19113 <enumeratedValue> 19114 <name>CONTINUOUS</name> 19115 <description>Continuous Mode</description> 19116 <value>1</value> 19117 </enumeratedValue> 19118 <enumeratedValue> 19119 <name>COUNTER</name> 19120 <description>Counter Mode</description> 19121 <value>2</value> 19122 </enumeratedValue> 19123 <enumeratedValue> 19124 <name>PWM</name> 19125 <description>PWM Mode</description> 19126 <value>3</value> 19127 </enumeratedValue> 19128 <enumeratedValue> 19129 <name>CAPTURE</name> 19130 <description>Capture Mode</description> 19131 <value>4</value> 19132 </enumeratedValue> 19133 <enumeratedValue> 19134 <name>COMPARE</name> 19135 <description>Compare Mode</description> 19136 <value>5</value> 19137 </enumeratedValue> 19138 <enumeratedValue> 19139 <name>GATED</name> 19140 <description>Gated Mode</description> 19141 <value>6</value> 19142 </enumeratedValue> 19143 <enumeratedValue> 19144 <name>CAPCOMP</name> 19145 <description>Capture/Compare Mode</description> 19146 <value>7</value> 19147 </enumeratedValue> 19148 <enumeratedValue> 19149 <name>DUAL_EDGE</name> 19150 <description>Dual Edge Capture Mode</description> 19151 <value>8</value> 19152 </enumeratedValue> 19153 <enumeratedValue> 19154 <name>IGATED</name> 19155 <description>Inactive Gated Mode</description> 19156 <value>14</value> 19157 </enumeratedValue> 19158 </enumeratedValues> 19159 </field> 19160 <field> 19161 <name>CLKDIV_B</name> 19162 <description>Clock Divider Select for Timer B</description> 19163 <bitOffset>20</bitOffset> 19164 <bitWidth>4</bitWidth> 19165 <enumeratedValues> 19166 <enumeratedValue> 19167 <name>DIV_BY_1</name> 19168 <description>Prescaler Divide-By-1</description> 19169 <value>0</value> 19170 </enumeratedValue> 19171 <enumeratedValue> 19172 <name>DIV_BY_2</name> 19173 <description>Prescaler Divide-By-2</description> 19174 <value>1</value> 19175 </enumeratedValue> 19176 <enumeratedValue> 19177 <name>DIV_BY_4</name> 19178 <description>Prescaler Divide-By-4</description> 19179 <value>2</value> 19180 </enumeratedValue> 19181 <enumeratedValue> 19182 <name>DIV_BY_8</name> 19183 <description>Prescaler Divide-By-8</description> 19184 <value>3</value> 19185 </enumeratedValue> 19186 <enumeratedValue> 19187 <name>DIV_BY_16</name> 19188 <description>Prescaler Divide-By-16</description> 19189 <value>4</value> 19190 </enumeratedValue> 19191 <enumeratedValue> 19192 <name>DIV_BY_32</name> 19193 <description>Prescaler Divide-By-32</description> 19194 <value>5</value> 19195 </enumeratedValue> 19196 <enumeratedValue> 19197 <name>DIV_BY_64</name> 19198 <description>Prescaler Divide-By-64</description> 19199 <value>6</value> 19200 </enumeratedValue> 19201 <enumeratedValue> 19202 <name>DIV_BY_128</name> 19203 <description>Prescaler Divide-By-128</description> 19204 <value>7</value> 19205 </enumeratedValue> 19206 <enumeratedValue> 19207 <name>DIV_BY_256</name> 19208 <description>Prescaler Divide-By-256</description> 19209 <value>8</value> 19210 </enumeratedValue> 19211 <enumeratedValue> 19212 <name>DIV_BY_512</name> 19213 <description>Prescaler Divide-By-512</description> 19214 <value>9</value> 19215 </enumeratedValue> 19216 <enumeratedValue> 19217 <name>DIV_BY_1024</name> 19218 <description>Prescaler Divide-By-1024</description> 19219 <value>10</value> 19220 </enumeratedValue> 19221 <enumeratedValue> 19222 <name>DIV_BY_2048</name> 19223 <description>Prescaler Divide-By-2048</description> 19224 <value>11</value> 19225 </enumeratedValue> 19226 <enumeratedValue> 19227 <name>DIV_BY_4096</name> 19228 <description>TBD</description> 19229 <value>12</value> 19230 </enumeratedValue> 19231 </enumeratedValues> 19232 </field> 19233 <field> 19234 <name>POL_B</name> 19235 <description>Timer Polarity for Timer B</description> 19236 <bitOffset>24</bitOffset> 19237 <bitWidth>1</bitWidth> 19238 </field> 19239 <field> 19240 <name>PWMSYNC_B</name> 19241 <description>PWM Synchronization Mode for Timer B</description> 19242 <bitOffset>25</bitOffset> 19243 <bitWidth>1</bitWidth> 19244 </field> 19245 <field> 19246 <name>NOLHPOL_B</name> 19247 <description>PWM Phase A (Non-Overlapping High) Polarity for Timer B</description> 19248 <bitOffset>26</bitOffset> 19249 <bitWidth>1</bitWidth> 19250 </field> 19251 <field> 19252 <name>NOLLPOL_B</name> 19253 <description>PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B</description> 19254 <bitOffset>27</bitOffset> 19255 <bitWidth>1</bitWidth> 19256 </field> 19257 <field> 19258 <name>PWMCKBD_B</name> 19259 <description>PWM Phase A-Prime Output Disable for Timer B</description> 19260 <bitOffset>28</bitOffset> 19261 <bitWidth>1</bitWidth> 19262 </field> 19263 <field> 19264 <name>RST_B</name> 19265 <description>Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears.</description> 19266 <bitOffset>29</bitOffset> 19267 <bitWidth>1</bitWidth> 19268 </field> 19269 <field> 19270 <name>CLKEN_B</name> 19271 <description>Write 1 to Enable CLK_TMR for Timer B</description> 19272 <bitOffset>30</bitOffset> 19273 <bitWidth>1</bitWidth> 19274 </field> 19275 <field> 19276 <name>EN_B</name> 19277 <description>Enable for Timer B</description> 19278 <bitOffset>31</bitOffset> 19279 <bitWidth>1</bitWidth> 19280 </field> 19281 </fields> 19282 </register> 19283 <register> 19284 <name>NOLCMP</name> 19285 <description>Timer Non-Overlapping Compare Register.</description> 19286 <addressOffset>0x14</addressOffset> 19287 <access>read-write</access> 19288 <fields> 19289 <field> 19290 <name>LO_A</name> 19291 <description>Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime.</description> 19292 <bitOffset>0</bitOffset> 19293 <bitWidth>8</bitWidth> 19294 </field> 19295 <field> 19296 <name>HI_A</name> 19297 <description>Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A.</description> 19298 <bitOffset>8</bitOffset> 19299 <bitWidth>8</bitWidth> 19300 </field> 19301 <field> 19302 <name>LO_B</name> 19303 <description>Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime.</description> 19304 <bitOffset>16</bitOffset> 19305 <bitWidth>8</bitWidth> 19306 </field> 19307 <field> 19308 <name>HI_B</name> 19309 <description>Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A.</description> 19310 <bitOffset>24</bitOffset> 19311 <bitWidth>8</bitWidth> 19312 </field> 19313 </fields> 19314 </register> 19315 <register> 19316 <name>CTRL1</name> 19317 <description>Timer Configuration Register.</description> 19318 <addressOffset>0x18</addressOffset> 19319 <access>read-write</access> 19320 <fields> 19321 <field> 19322 <name>CLKSEL_A</name> 19323 <description>Timer Clock Select for Timer A</description> 19324 <bitOffset>0</bitOffset> 19325 <bitWidth>2</bitWidth> 19326 </field> 19327 <field> 19328 <name>CLKEN_A</name> 19329 <description>Timer A Enable Status</description> 19330 <bitOffset>2</bitOffset> 19331 <bitWidth>1</bitWidth> 19332 </field> 19333 <field> 19334 <name>CLKRDY_A</name> 19335 <description>CLK_TMR Ready Flag for Timer A</description> 19336 <bitOffset>3</bitOffset> 19337 <bitWidth>1</bitWidth> 19338 </field> 19339 <field> 19340 <name>EVENT_SEL_A</name> 19341 <description>Event Select for Timer A</description> 19342 <bitOffset>4</bitOffset> 19343 <bitWidth>3</bitWidth> 19344 </field> 19345 <field> 19346 <name>NEGTRIG_A</name> 19347 <description>Negative Edge Trigger for Event for Timer A</description> 19348 <bitOffset>7</bitOffset> 19349 <bitWidth>1</bitWidth> 19350 </field> 19351 <field> 19352 <name>IE_A</name> 19353 <description>Interrupt Enable for Timer A</description> 19354 <bitOffset>8</bitOffset> 19355 <bitWidth>1</bitWidth> 19356 </field> 19357 <field> 19358 <name>CAPEVENT_SEL_A</name> 19359 <description>Capture Event Select for Timer A</description> 19360 <bitOffset>9</bitOffset> 19361 <bitWidth>2</bitWidth> 19362 </field> 19363 <field> 19364 <name>SW_CAPEVENT_A</name> 19365 <description>Software Capture Event for Timer A</description> 19366 <bitOffset>11</bitOffset> 19367 <bitWidth>1</bitWidth> 19368 </field> 19369 <field> 19370 <name>WE_A</name> 19371 <description>Wake-Up Enable for Timer A</description> 19372 <bitOffset>12</bitOffset> 19373 <bitWidth>1</bitWidth> 19374 </field> 19375 <field> 19376 <name>OUTEN_A</name> 19377 <description>OUT_OE_O Enable for Modes 0, 1,and 5 for Timer A</description> 19378 <bitOffset>13</bitOffset> 19379 <bitWidth>1</bitWidth> 19380 </field> 19381 <field> 19382 <name>OUTBEN_A</name> 19383 <description>PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A</description> 19384 <bitOffset>14</bitOffset> 19385 <bitWidth>1</bitWidth> 19386 </field> 19387 <field> 19388 <name>CLKSEL_B</name> 19389 <description>Timer Clock Select for Timer B</description> 19390 <bitOffset>16</bitOffset> 19391 <bitWidth>2</bitWidth> 19392 </field> 19393 <field> 19394 <name>CLKEN_B</name> 19395 <description>Timer B Enable Status</description> 19396 <bitOffset>18</bitOffset> 19397 <bitWidth>1</bitWidth> 19398 </field> 19399 <field> 19400 <name>CLKRDY_B</name> 19401 <description>CLK_TMR Ready Flag for Timer B</description> 19402 <bitOffset>19</bitOffset> 19403 <bitWidth>1</bitWidth> 19404 </field> 19405 <field> 19406 <name>EVENT_SEL_B</name> 19407 <description>Event Select for Timer B</description> 19408 <bitOffset>20</bitOffset> 19409 <bitWidth>3</bitWidth> 19410 </field> 19411 <field> 19412 <name>NEGTRIG_B</name> 19413 <description>Negative Edge Trigger for Event for Timer B</description> 19414 <bitOffset>23</bitOffset> 19415 <bitWidth>1</bitWidth> 19416 </field> 19417 <field> 19418 <name>IE_B</name> 19419 <description>Interrupt Enable for Timer B</description> 19420 <bitOffset>24</bitOffset> 19421 <bitWidth>1</bitWidth> 19422 </field> 19423 <field> 19424 <name>CAPEVENT_SEL_B</name> 19425 <description>Capture Event Select for Timer B</description> 19426 <bitOffset>25</bitOffset> 19427 <bitWidth>2</bitWidth> 19428 </field> 19429 <field> 19430 <name>SW_CAPEVENT_B</name> 19431 <description>Software Capture Event for Timer B</description> 19432 <bitOffset>27</bitOffset> 19433 <bitWidth>1</bitWidth> 19434 </field> 19435 <field> 19436 <name>WE_B</name> 19437 <description>Wake-Up Enable for Timer B</description> 19438 <bitOffset>28</bitOffset> 19439 <bitWidth>1</bitWidth> 19440 </field> 19441 <field> 19442 <name>CASCADE</name> 19443 <description>Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1.</description> 19444 <bitOffset>31</bitOffset> 19445 <bitWidth>1</bitWidth> 19446 </field> 19447 </fields> 19448 </register> 19449 <register> 19450 <name>WKFL</name> 19451 <description>Timer Wakeup Status Register.</description> 19452 <addressOffset>0x1C</addressOffset> 19453 <access>read-write</access> 19454 <fields> 19455 <field> 19456 <name>A</name> 19457 <description>Wake-Up Flag for Timer A</description> 19458 <bitOffset>0</bitOffset> 19459 <bitWidth>1</bitWidth> 19460 </field> 19461 <field> 19462 <name>B</name> 19463 <description>Wake-Up Flag for Timer B</description> 19464 <bitOffset>16</bitOffset> 19465 <bitWidth>1</bitWidth> 19466 </field> 19467 </fields> 19468 </register> 19469 </registers> 19470 </peripheral> 19471<!--TMR Low-Power Configurable Timer--> 19472 <peripheral derivedFrom="TMR"> 19473 <name>TMR1</name> 19474 <description>Low-Power Configurable Timer 1</description> 19475 <baseAddress>0x40011000</baseAddress> 19476 <interrupt> 19477 <name>TMR1</name> 19478 <description>TMR1 IRQ</description> 19479 <value>6</value> 19480 </interrupt> 19481 </peripheral> 19482<!--TMR1 Low-Power Configurable Timer 1--> 19483 <peripheral derivedFrom="TMR"> 19484 <name>TMR2</name> 19485 <description>Low-Power Configurable Timer 2</description> 19486 <baseAddress>0x40012000</baseAddress> 19487 <interrupt> 19488 <name>TMR2</name> 19489 <description>TMR2 IRQ</description> 19490 <value>7</value> 19491 </interrupt> 19492 </peripheral> 19493<!--TMR2 Low-Power Configurable Timer 2--> 19494 <peripheral derivedFrom="TMR"> 19495 <name>TMR3</name> 19496 <description>Low-Power Configurable Timer 3</description> 19497 <baseAddress>0x40013000</baseAddress> 19498 <interrupt> 19499 <name>TMR3</name> 19500 <description>TMR3 IRQ</description> 19501 <value>8</value> 19502 </interrupt> 19503 </peripheral> 19504<!--TMR3 Low-Power Configurable Timer 3--> 19505 <peripheral derivedFrom="TMR"> 19506 <name>TMR4</name> 19507 <description>Low-Power Configurable Timer 4</description> 19508 <baseAddress>0x40080C00</baseAddress> 19509 <interrupt> 19510 <name>TMR4</name> 19511 <description>TMR4 IRQ</description> 19512 <value>9</value> 19513 </interrupt> 19514 </peripheral> 19515<!--TMR4 Low-Power Configurable Timer 4--> 19516 <peripheral derivedFrom="TMR"> 19517 <name>TMR5</name> 19518 <description>Low-Power Configurable Timer 5</description> 19519 <baseAddress>0x40081000</baseAddress> 19520 <interrupt> 19521 <name>TMR5</name> 19522 <description>TMR5 IRQ</description> 19523 <value>10</value> 19524 </interrupt> 19525 </peripheral> 19526<!--TMR5 Low-Power Configurable Timer 5--> 19527 <peripheral> 19528 <name>TRIMSIR</name> 19529 <description>Trim System Initilazation Registers</description> 19530 <baseAddress>0x40005400</baseAddress> 19531 <addressBlock> 19532 <offset>0x00</offset> 19533 <size>0x400</size> 19534 <usage>registers</usage> 19535 </addressBlock> 19536 <registers> 19537 <register> 19538 <name>RTC</name> 19539 <description>RTC Trim System Initialization Register.</description> 19540 <addressOffset>0x08</addressOffset> 19541 <fields> 19542 <field> 19543 <name>RTCX1</name> 19544 <description>RTC X1 Trim.</description> 19545 <bitOffset>16</bitOffset> 19546 <bitWidth>5</bitWidth> 19547 </field> 19548 <field> 19549 <name>RTCX2</name> 19550 <description>RTC X2 Trim.</description> 19551 <bitOffset>21</bitOffset> 19552 <bitWidth>5</bitWidth> 19553 </field> 19554 <field> 19555 <name>LOCK</name> 19556 <description>Lock.</description> 19557 <bitOffset>31</bitOffset> 19558 <bitWidth>1</bitWidth> 19559 </field> 19560 </fields> 19561 </register> 19562 </registers> 19563 </peripheral> 19564<!--TRIMSIR Trim System Initilazation Registers--> 19565 <peripheral> 19566 <name>TRNG</name> 19567 <description>Random Number Generator.</description> 19568 <baseAddress>0x4004D000</baseAddress> 19569 <addressBlock> 19570 <offset>0x00</offset> 19571 <size>0x1000</size> 19572 <usage>registers</usage> 19573 </addressBlock> 19574 <interrupt> 19575 <name>TRNG</name> 19576 <description>TRNG interrupt.</description> 19577 <value>4</value> 19578 </interrupt> 19579 <registers> 19580 <register> 19581 <name>CTRL</name> 19582 <description>TRNG Control Register.</description> 19583 <addressOffset>0x00</addressOffset> 19584 <resetValue>0x00000003</resetValue> 19585 <fields> 19586 <field> 19587 <name>RND_IE</name> 19588 <description>To enable IRQ generation when a new 32-bit Random number is ready.</description> 19589 <bitOffset>1</bitOffset> 19590 <bitWidth>1</bitWidth> 19591 <enumeratedValues> 19592 <enumeratedValue> 19593 <name>disable</name> 19594 <description>Disable</description> 19595 <value>0</value> 19596 </enumeratedValue> 19597 <enumeratedValue> 19598 <name>enable</name> 19599 <description>Enable</description> 19600 <value>1</value> 19601 </enumeratedValue> 19602 </enumeratedValues> 19603 </field> 19604 <field> 19605 <name>KEYGEN</name> 19606 <description>AES Key Generate. When enabled, the key for securing NVSRAM is generated and transferred to the secure key register automatically without user visibility or intervention. This bit is cleared by hardware once the key has been transferred to the secure key register.</description> 19607 <bitOffset>3</bitOffset> 19608 <bitWidth>1</bitWidth> 19609 </field> 19610 <field> 19611 <name>KEYWIPE</name> 19612 <description>To wipe the Battery Backed key.</description> 19613 <bitOffset>15</bitOffset> 19614 <bitWidth>1</bitWidth> 19615 </field> 19616 </fields> 19617 </register> 19618 <register> 19619 <name>STATUS</name> 19620 <description>Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000.</description> 19621 <addressOffset>0x04</addressOffset> 19622 <fields> 19623 <field> 19624 <name>RDY</name> 19625 <description>32-bit random data is ready to read from TRNG_DATA register. Reading TRNG_DATA when RND_RDY=0 will return all 0's. IRQ is generated when RND_RDY=1 if TRNG_CN.RND_IRQ_EN=1.</description> 19626 <bitOffset>0</bitOffset> 19627 <bitWidth>1</bitWidth> 19628 <enumeratedValues> 19629 <enumeratedValue> 19630 <name>Busy</name> 19631 <description>TRNG Busy</description> 19632 <value>0</value> 19633 </enumeratedValue> 19634 <enumeratedValue> 19635 <name>Ready</name> 19636 <description>32 bit random data is ready</description> 19637 <value>1</value> 19638 </enumeratedValue> 19639 </enumeratedValues> 19640 </field> 19641 </fields> 19642 </register> 19643 <register> 19644 <name>DATA</name> 19645 <description>Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000.</description> 19646 <addressOffset>0x08</addressOffset> 19647 <access>read-only</access> 19648 <fields> 19649 <field> 19650 <name>DATA</name> 19651 <description>Data. The content of this register is valid only when RNG_IS =1. When TNRG is disabled, read returns 0x0000 0000.</description> 19652 <bitOffset>0</bitOffset> 19653 <bitWidth>32</bitWidth> 19654 </field> 19655 </fields> 19656 </register> 19657 </registers> 19658 </peripheral> 19659<!--TRNG Random Number Generator.--> 19660 <peripheral> 19661 <name>UART</name> 19662 <description>UART Low Power Registers</description> 19663 <baseAddress>0x40042000</baseAddress> 19664 <addressBlock> 19665 <offset>0x00</offset> 19666 <size>0x1000</size> 19667 <usage>registers</usage> 19668 </addressBlock> 19669 <registers> 19670 <register> 19671 <name>CTRL</name> 19672 <description>Control register</description> 19673 <addressOffset>0x0000</addressOffset> 19674 <fields> 19675 <field> 19676 <name>RX_THD_VAL</name> 19677 <description>This field specifies the depth of receive FIFO for interrupt generation (value 0 and > 16 are ignored) </description> 19678 <bitOffset>0</bitOffset> 19679 <bitWidth>4</bitWidth> 19680 </field> 19681 <field> 19682 <name>PAR_EN</name> 19683 <description>Parity Enable</description> 19684 <bitOffset>4</bitOffset> 19685 <bitWidth>1</bitWidth> 19686 </field> 19687 <field> 19688 <name>PAR_EO</name> 19689 <description>when PAREN=1 selects odd or even parity odd is 1 even is 0</description> 19690 <bitOffset>5</bitOffset> 19691 <bitWidth>1</bitWidth> 19692 </field> 19693 <field> 19694 <name>PAR_MD</name> 19695 <description>Selects parity based on 1s or 0s count (when PAREN=1) </description> 19696 <bitOffset>6</bitOffset> 19697 <bitWidth>1</bitWidth> 19698 </field> 19699 <field> 19700 <name>CTS_DIS</name> 19701 <description>CTS Sampling Disable </description> 19702 <bitOffset>7</bitOffset> 19703 <bitWidth>1</bitWidth> 19704 </field> 19705 <field> 19706 <name>TX_FLUSH</name> 19707 <description>Flushes the TX FIFO buffer. This bit is automatically cleared by hardware when flush is completed.</description> 19708 <bitOffset>8</bitOffset> 19709 <bitWidth>1</bitWidth> 19710 </field> 19711 <field> 19712 <name>RX_FLUSH</name> 19713 <description>Flushes the RX FIFO buffer. This bit is automatically cleared by hardware when flush is completed.</description> 19714 <bitOffset>9</bitOffset> 19715 <bitWidth>1</bitWidth> 19716 </field> 19717 <field> 19718 <name>CHAR_SIZE</name> 19719 <description>Selects UART character size</description> 19720 <bitOffset>10</bitOffset> 19721 <bitWidth>2</bitWidth> 19722 <enumeratedValues> 19723 <enumeratedValue> 19724 <name>5bits</name> 19725 <description>5 bits</description> 19726 <value>0</value> 19727 </enumeratedValue> 19728 <enumeratedValue> 19729 <name>6bits</name> 19730 <description>6 bits</description> 19731 <value>1</value> 19732 </enumeratedValue> 19733 <enumeratedValue> 19734 <name>7bits</name> 19735 <description>7 bits</description> 19736 <value>2</value> 19737 </enumeratedValue> 19738 <enumeratedValue> 19739 <name>8bits</name> 19740 <description>8 bits</description> 19741 <value>3</value> 19742 </enumeratedValue> 19743 </enumeratedValues> 19744 </field> 19745 <field> 19746 <name>STOPBITS</name> 19747 <description>Selects the number of stop bits that will be generated</description> 19748 <bitOffset>12</bitOffset> 19749 <bitWidth>1</bitWidth> 19750 </field> 19751 <field> 19752 <name>HFC_EN</name> 19753 <description>Enables/disables hardware flow control</description> 19754 <bitOffset>13</bitOffset> 19755 <bitWidth>1</bitWidth> 19756 </field> 19757 <field> 19758 <name>RTSDC</name> 19759 <description>Hardware Flow Control RTS Mode</description> 19760 <bitOffset>14</bitOffset> 19761 <bitWidth>1</bitWidth> 19762 </field> 19763 <field> 19764 <name>BCLKEN</name> 19765 <description>Baud clock enable</description> 19766 <bitOffset>15</bitOffset> 19767 <bitWidth>1</bitWidth> 19768 </field> 19769 <field> 19770 <name>BCLKSRC</name> 19771 <description>To select the UART clock source for the UART engine (except APB registers). Secondary clock (used for baud rate generator) can be asynchronous from APB clock.</description> 19772 <bitOffset>16</bitOffset> 19773 <bitWidth>2</bitWidth> 19774 <enumeratedValues> 19775 <enumeratedValue> 19776 <name>Peripheral_Clock</name> 19777 <description>apb clock</description> 19778 <value>0</value> 19779 </enumeratedValue> 19780 <enumeratedValue> 19781 <name>External_Clock</name> 19782 <description>Clock 1</description> 19783 <value>1</value> 19784 </enumeratedValue> 19785 <enumeratedValue> 19786 <name>CLK2</name> 19787 <description>Clock 2</description> 19788 <value>2</value> 19789 </enumeratedValue> 19790 <enumeratedValue> 19791 <name>CLK3</name> 19792 <description>Clock 3</description> 19793 <value>3</value> 19794 </enumeratedValue> 19795 </enumeratedValues> 19796 </field> 19797 <field> 19798 <name>DPFE_EN</name> 19799 <description>Data/Parity bit frame error detection enable</description> 19800 <bitOffset>18</bitOffset> 19801 <bitWidth>1</bitWidth> 19802 </field> 19803 <field> 19804 <name>BCLKRDY</name> 19805 <description>Baud clock Ready read only bit</description> 19806 <bitOffset>19</bitOffset> 19807 <bitWidth>1</bitWidth> 19808 </field> 19809 <field> 19810 <name>UCAGM</name> 19811 <description>UART Clock Auto Gating mode</description> 19812 <bitOffset>20</bitOffset> 19813 <bitWidth>1</bitWidth> 19814 </field> 19815 <field> 19816 <name>FDM</name> 19817 <description>Fractional Division Mode</description> 19818 <bitOffset>21</bitOffset> 19819 <bitWidth>1</bitWidth> 19820 </field> 19821 <field> 19822 <name>DESM</name> 19823 <description>RX Dual Edge Sampling Mode</description> 19824 <bitOffset>22</bitOffset> 19825 <bitWidth>1</bitWidth> 19826 </field> 19827 </fields> 19828 </register> 19829 <register> 19830 <name>STATUS</name> 19831 <description>Status register</description> 19832 <addressOffset>0x0004</addressOffset> 19833 <access>read-only</access> 19834 <fields> 19835 <field> 19836 <name>TX_BUSY</name> 19837 <description>Read-only flag indicating the UART transmit status</description> 19838 <bitOffset>0</bitOffset> 19839 <bitWidth>1</bitWidth> 19840 </field> 19841 <field> 19842 <name>RX_BUSY</name> 19843 <description>Read-only flag indicating the UART receiver status</description> 19844 <bitOffset>1</bitOffset> 19845 <bitWidth>1</bitWidth> 19846 </field> 19847 <field> 19848 <name>RX_EM</name> 19849 <description>Read-only flag indicating the RX FIFO state</description> 19850 <bitOffset>4</bitOffset> 19851 <bitWidth>1</bitWidth> 19852 </field> 19853 <field> 19854 <name>RX_FULL</name> 19855 <description>Read-only flag indicating the RX FIFO state</description> 19856 <bitOffset>5</bitOffset> 19857 <bitWidth>1</bitWidth> 19858 </field> 19859 <field> 19860 <name>TX_EM</name> 19861 <description>Read-only flag indicating the TX FIFO state</description> 19862 <bitOffset>6</bitOffset> 19863 <bitWidth>1</bitWidth> 19864 </field> 19865 <field> 19866 <name>TX_FULL</name> 19867 <description>Read-only flag indicating the TX FIFO state</description> 19868 <bitOffset>7</bitOffset> 19869 <bitWidth>1</bitWidth> 19870 </field> 19871 <field> 19872 <name>RX_LVL</name> 19873 <description>Indicates the number of bytes currently in the RX FIFO (0-RX FIFO_ELTS) </description> 19874 <bitOffset>8</bitOffset> 19875 <bitWidth>4</bitWidth> 19876 </field> 19877 <field> 19878 <name>TX_LVL</name> 19879 <description>Indicates the number of bytes currently in the TX FIFO (0-TX FIFO_ELTS) </description> 19880 <bitOffset>12</bitOffset> 19881 <bitWidth>4</bitWidth> 19882 </field> 19883 </fields> 19884 </register> 19885 <register> 19886 <name>INT_EN</name> 19887 <description>Interrupt Enable control register</description> 19888 <addressOffset>0x0008</addressOffset> 19889 <fields> 19890 <field> 19891 <name>RX_FERR</name> 19892 <description>Enable Interrupt For RX Frame Error</description> 19893 <bitOffset>0</bitOffset> 19894 <bitWidth>1</bitWidth> 19895 </field> 19896 <field> 19897 <name>RX_PAR</name> 19898 <description>Enable Interrupt For RX Parity Error</description> 19899 <bitOffset>1</bitOffset> 19900 <bitWidth>1</bitWidth> 19901 </field> 19902 <field> 19903 <name>CTS_EV</name> 19904 <description>Enable Interrupt For CTS signal change Error</description> 19905 <bitOffset>2</bitOffset> 19906 <bitWidth>1</bitWidth> 19907 </field> 19908 <field> 19909 <name>RX_OV</name> 19910 <description>Enable Interrupt For RX FIFO Overrun Error</description> 19911 <bitOffset>3</bitOffset> 19912 <bitWidth>1</bitWidth> 19913 </field> 19914 <field> 19915 <name>RX_THD</name> 19916 <description>Enable Interrupt For RX FIFO reaches the number of bytes configured by RXTHD</description> 19917 <bitOffset>4</bitOffset> 19918 <bitWidth>1</bitWidth> 19919 </field> 19920 <field> 19921 <name>TX_OB</name> 19922 <description>Enable Interrupt For TX FIFO has one byte remaining</description> 19923 <bitOffset>5</bitOffset> 19924 <bitWidth>1</bitWidth> 19925 </field> 19926 <field> 19927 <name>TX_HE</name> 19928 <description>Enable Interrupt For TX FIFO has half empty</description> 19929 <bitOffset>6</bitOffset> 19930 <bitWidth>1</bitWidth> 19931 </field> 19932 </fields> 19933 </register> 19934 <register> 19935 <name>INT_FL</name> 19936 <description>Interrupt status flags Control register</description> 19937 <addressOffset>0x000C</addressOffset> 19938 <fields> 19939 <field> 19940 <name>RX_FERR</name> 19941 <description>Flag for RX Frame Error Interrupt.</description> 19942 <bitOffset>0</bitOffset> 19943 <bitWidth>1</bitWidth> 19944 </field> 19945 <field> 19946 <name>RX_PAR</name> 19947 <description>Flag for RX Parity Error interrupt</description> 19948 <bitOffset>1</bitOffset> 19949 <bitWidth>1</bitWidth> 19950 </field> 19951 <field> 19952 <name>CTS_EV</name> 19953 <description>Flag for CTS signal change interrupt (hardware flow control disabled) </description> 19954 <bitOffset>2</bitOffset> 19955 <bitWidth>1</bitWidth> 19956 </field> 19957 <field> 19958 <name>RX_OV</name> 19959 <description>Flag for RX FIFO Overrun interrupt</description> 19960 <bitOffset>3</bitOffset> 19961 <bitWidth>1</bitWidth> 19962 </field> 19963 <field> 19964 <name>RX_THD</name> 19965 <description>Flag for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field</description> 19966 <bitOffset>4</bitOffset> 19967 <bitWidth>1</bitWidth> 19968 </field> 19969 <field> 19970 <name>TX_OB</name> 19971 <description>Flag for interrupt when TX FIFO has one byte remaining</description> 19972 <bitOffset>5</bitOffset> 19973 <bitWidth>1</bitWidth> 19974 </field> 19975 <field> 19976 <name>TX_HE</name> 19977 <description>Flag for interrupt when TX FIFO is half empty</description> 19978 <bitOffset>6</bitOffset> 19979 <bitWidth>1</bitWidth> 19980 </field> 19981 </fields> 19982 </register> 19983 <register> 19984 <name>CLKDIV</name> 19985 <description>Clock Divider register</description> 19986 <addressOffset>0x0010</addressOffset> 19987 <fields> 19988 <field> 19989 <name>CLKDIV</name> 19990 <description>Baud rate divisor value</description> 19991 <bitOffset>0</bitOffset> 19992 <bitWidth>20</bitWidth> 19993 </field> 19994 </fields> 19995 </register> 19996 <register> 19997 <name>OSR</name> 19998 <description>Over Sampling Rate register</description> 19999 <addressOffset>0x0014</addressOffset> 20000 <fields> 20001 <field> 20002 <name>OSR</name> 20003 <description>OSR</description> 20004 <bitOffset>0</bitOffset> 20005 <bitWidth>3</bitWidth> 20006 </field> 20007 </fields> 20008 </register> 20009 <register> 20010 <name>TXPEEK</name> 20011 <description>TX FIFO Output Peek register</description> 20012 <addressOffset>0x0018</addressOffset> 20013 <fields> 20014 <field> 20015 <name>DATA</name> 20016 <description>Read TX FIFO next data. Reading from this field does not affect the contents of TX FIFO. Note that the parity bit is available from this field.</description> 20017 <bitOffset>0</bitOffset> 20018 <bitWidth>8</bitWidth> 20019 </field> 20020 </fields> 20021 </register> 20022 <register> 20023 <name>PNR</name> 20024 <description> Pin register</description> 20025 <addressOffset>0x001C</addressOffset> 20026 <fields> 20027 <field> 20028 <name>CTS</name> 20029 <description>Current sampled value of CTS IO</description> 20030 <bitOffset>0</bitOffset> 20031 <bitWidth>1</bitWidth> 20032 <access>read-only</access> 20033 </field> 20034 <field> 20035 <name>RTS</name> 20036 <description>This bit controls the value to apply on the RTS IO. If set to 1, the RTS IO is set to high level. If set to 0, the RTS IO is set to low level.</description> 20037 <bitOffset>1</bitOffset> 20038 <bitWidth>1</bitWidth> 20039 </field> 20040 </fields> 20041 </register> 20042 <register> 20043 <name>FIFO</name> 20044 <description>FIFO Read/Write register</description> 20045 <addressOffset>0x0020</addressOffset> 20046 <fields> 20047 <field> 20048 <name>DATA</name> 20049 <description>Load/unload location for TX and RX FIFO buffers.</description> 20050 <bitOffset>0</bitOffset> 20051 <bitWidth>8</bitWidth> 20052 </field> 20053 <field> 20054 <name>RX_PAR</name> 20055 <description>Parity error flag for next byte to be read from FIFO.</description> 20056 <bitOffset>8</bitOffset> 20057 <bitWidth>1</bitWidth> 20058 </field> 20059 </fields> 20060 </register> 20061 <register> 20062 <name>DMA</name> 20063 <description>DMA Configuration register</description> 20064 <addressOffset>0x0030</addressOffset> 20065 <fields> 20066 <field> 20067 <name>TX_THD_VAL</name> 20068 <description>TX FIFO Level DMA Trigger If the TX FIFO level is less than this value, then the TX FIFO DMA interface will send a signal to system DMA to notify that TX FIFO is ready to receive data from memory.</description> 20069 <bitOffset>0</bitOffset> 20070 <bitWidth>4</bitWidth> 20071 </field> 20072 <field> 20073 <name>TX_EN</name> 20074 <description>TX DMA channel enable</description> 20075 <bitOffset>4</bitOffset> 20076 <bitWidth>1</bitWidth> 20077 </field> 20078 <field> 20079 <name>RX_THD_VAL</name> 20080 <description>Rx FIFO Level DMA Trigger If the RX FIFO level is greater than this value, then the RX FIFO DMA interface will send a signal to the system DMA to notify that RX FIFO has characters to transfer to memory.</description> 20081 <bitOffset>5</bitOffset> 20082 <bitWidth>4</bitWidth> 20083 </field> 20084 <field> 20085 <name>RX_EN</name> 20086 <description>RX DMA channel enable</description> 20087 <bitOffset>9</bitOffset> 20088 <bitWidth>1</bitWidth> 20089 </field> 20090 </fields> 20091 </register> 20092 <register> 20093 <name>WKEN</name> 20094 <description>Wake up enable Control register</description> 20095 <addressOffset>0x0034</addressOffset> 20096 <fields> 20097 <field> 20098 <name>RX_NE</name> 20099 <description>Wake-Up Enable for RX FIFO Not Empty</description> 20100 <bitOffset>0</bitOffset> 20101 <bitWidth>1</bitWidth> 20102 </field> 20103 <field> 20104 <name>RX_FULL</name> 20105 <description>Wake-Up Enable for RX FIFO Full</description> 20106 <bitOffset>1</bitOffset> 20107 <bitWidth>1</bitWidth> 20108 </field> 20109 <field> 20110 <name>RX_THD</name> 20111 <description>Wake-Up Enable for RX FIFO Threshold Met</description> 20112 <bitOffset>2</bitOffset> 20113 <bitWidth>1</bitWidth> 20114 </field> 20115 </fields> 20116 </register> 20117 <register> 20118 <name>WKFL</name> 20119 <description>Wake up Flags register</description> 20120 <addressOffset>0x0038</addressOffset> 20121 <fields> 20122 <field> 20123 <name>RX_NE</name> 20124 <description>Wake-Up Flag for RX FIFO Not Empty</description> 20125 <bitOffset>0</bitOffset> 20126 <bitWidth>1</bitWidth> 20127 </field> 20128 <field> 20129 <name>RX_FULL</name> 20130 <description>Wake-Up Flag for RX FIFO Full</description> 20131 <bitOffset>1</bitOffset> 20132 <bitWidth>1</bitWidth> 20133 </field> 20134 <field> 20135 <name>RX_THD</name> 20136 <description>Wake-Up Flag for RX FIFO Threshold Met</description> 20137 <bitOffset>2</bitOffset> 20138 <bitWidth>1</bitWidth> 20139 </field> 20140 </fields> 20141 </register> 20142 </registers> 20143 </peripheral> 20144<!--UART UART Low Power Registers--> 20145 <peripheral derivedFrom="UART"> 20146 <name>UART1</name> 20147 <description>UART Low Power Registers 1</description> 20148 <baseAddress>0x40043000</baseAddress> 20149 </peripheral> 20150<!--UART1 UART Low Power Registers 1--> 20151 <peripheral derivedFrom="UART"> 20152 <name>UART2</name> 20153 <description>UART Low Power Registers 2</description> 20154 <baseAddress>0x40044000</baseAddress> 20155 </peripheral> 20156<!--UART2 UART Low Power Registers 2--> 20157 <peripheral derivedFrom="UART"> 20158 <name>UART3</name> 20159 <description>UART Low Power Registers 3</description> 20160 <baseAddress>0x40081400</baseAddress> 20161 </peripheral> 20162<!--UART3 UART Low Power Registers 3--> 20163 <peripheral> 20164 <name>USBHS</name> 20165 <description>USB 2.0 High-speed Controller.</description> 20166 <baseAddress>0x400B1000</baseAddress> 20167 <addressBlock> 20168 <offset>0</offset> 20169 <size>0x1000</size> 20170 <usage>registers</usage> 20171 </addressBlock> 20172 <interrupt> 20173 <name>USB</name> 20174 <value>2</value> 20175 </interrupt> 20176 <registers> 20177 <register> 20178 <name>FADDR</name> 20179 <description>Function address register.</description> 20180 <addressOffset>0x00</addressOffset> 20181 <size>8</size> 20182 <resetMask>0x00</resetMask> 20183 <fields> 20184 <field> 20185 <name>ADDR</name> 20186 <description>Function address for this controller.</description> 20187 <bitOffset>0</bitOffset> 20188 <bitWidth>7</bitWidth> 20189 <access>read-write</access> 20190 </field> 20191 <field> 20192 <name>UPDATE</name> 20193 <description>Set when ADDR is written, cleared when new address takes effect.</description> 20194 <bitOffset>7</bitOffset> 20195 <bitWidth>1</bitWidth> 20196 <access>read-only</access> 20197 </field> 20198 </fields> 20199 </register> 20200 <register> 20201 <name>POWER</name> 20202 <description>Power management register.</description> 20203 <addressOffset>0x01</addressOffset> 20204 <size>8</size> 20205 <fields> 20206 <field> 20207 <name>EN_SUSPENDM</name> 20208 <description>Enable SUSPENDM signal.</description> 20209 <bitOffset>0</bitOffset> 20210 <bitWidth>1</bitWidth> 20211 <access>read-write</access> 20212 </field> 20213 <field> 20214 <name>SUSPEND</name> 20215 <description>Suspend mode detected.</description> 20216 <bitOffset>1</bitOffset> 20217 <bitWidth>1</bitWidth> 20218 <access>read-only</access> 20219 </field> 20220 <field> 20221 <name>RESUME</name> 20222 <description>Generate resume signaling.</description> 20223 <bitOffset>2</bitOffset> 20224 <bitWidth>1</bitWidth> 20225 <access>read-write</access> 20226 </field> 20227 <field> 20228 <name>RESET</name> 20229 <description>Bus reset detected.</description> 20230 <bitOffset>3</bitOffset> 20231 <bitWidth>1</bitWidth> 20232 <access>read-only</access> 20233 </field> 20234 <field> 20235 <name>HS_MODE</name> 20236 <description>High-speed mode detected.</description> 20237 <bitOffset>4</bitOffset> 20238 <bitWidth>1</bitWidth> 20239 <access>read-only</access> 20240 </field> 20241 <field> 20242 <name>HS_ENABLE</name> 20243 <description>High-speed mode enable.</description> 20244 <bitOffset>5</bitOffset> 20245 <bitWidth>1</bitWidth> 20246 <access>read-write</access> 20247 </field> 20248 <field> 20249 <name>SOFTCONN</name> 20250 <description>Softconn.</description> 20251 <bitOffset>6</bitOffset> 20252 <bitWidth>1</bitWidth> 20253 <access>read-write</access> 20254 </field> 20255 <field> 20256 <name>ISO_UPDATE</name> 20257 <description>Wait for SOF during Isochronous xfers.</description> 20258 <bitOffset>7</bitOffset> 20259 <bitWidth>1</bitWidth> 20260 <access>read-write</access> 20261 </field> 20262 </fields> 20263 </register> 20264 <register> 20265 <name>INTRIN</name> 20266 <description>Interrupt register for EP0 and IN EP1-15.</description> 20267 <addressOffset>0x02</addressOffset> 20268 <size>16</size> 20269 <fields> 20270 <field> 20271 <name>EP15_IN_INT</name> 20272 <description>Endpoint 15 interrupt.</description> 20273 <bitOffset>15</bitOffset> 20274 <bitWidth>1</bitWidth> 20275 <access>read-only</access> 20276 </field> 20277 <field> 20278 <name>EP14_IN_INT</name> 20279 <description>Endpoint 14 interrupt.</description> 20280 <bitOffset>14</bitOffset> 20281 <bitWidth>1</bitWidth> 20282 <access>read-only</access> 20283 </field> 20284 <field> 20285 <name>EP13_IN_INT</name> 20286 <description>Endpoint 13 interrupt.</description> 20287 <bitOffset>13</bitOffset> 20288 <bitWidth>1</bitWidth> 20289 <access>read-only</access> 20290 </field> 20291 <field> 20292 <name>EP12_IN_INT</name> 20293 <description>Endpoint 12 interrupt.</description> 20294 <bitOffset>12</bitOffset> 20295 <bitWidth>1</bitWidth> 20296 <access>read-only</access> 20297 </field> 20298 <field> 20299 <name>EP11_IN_INT</name> 20300 <description>Endpoint 11 interrupt.</description> 20301 <bitOffset>11</bitOffset> 20302 <bitWidth>1</bitWidth> 20303 <access>read-only</access> 20304 </field> 20305 <field> 20306 <name>EP10_IN_INT</name> 20307 <description>Endpoint 10 interrupt.</description> 20308 <bitOffset>10</bitOffset> 20309 <bitWidth>1</bitWidth> 20310 <access>read-only</access> 20311 </field> 20312 <field> 20313 <name>EP9_IN_INT</name> 20314 <description>Endpoint 9 interrupt.</description> 20315 <bitOffset>9</bitOffset> 20316 <bitWidth>1</bitWidth> 20317 <access>read-only</access> 20318 </field> 20319 <field> 20320 <name>EP8_IN_INT</name> 20321 <description>Endpoint 8 interrupt.</description> 20322 <bitOffset>8</bitOffset> 20323 <bitWidth>1</bitWidth> 20324 <access>read-only</access> 20325 </field> 20326 <field> 20327 <name>EP7_IN_INT</name> 20328 <description>Endpoint 7 interrupt.</description> 20329 <bitOffset>7</bitOffset> 20330 <bitWidth>1</bitWidth> 20331 <access>read-only</access> 20332 </field> 20333 <field> 20334 <name>EP6_IN_INT</name> 20335 <description>Endpoint 6 interrupt.</description> 20336 <bitOffset>6</bitOffset> 20337 <bitWidth>1</bitWidth> 20338 <access>read-only</access> 20339 </field> 20340 <field> 20341 <name>EP5_IN_INT</name> 20342 <description>Endpoint 5 interrupt.</description> 20343 <bitOffset>5</bitOffset> 20344 <bitWidth>1</bitWidth> 20345 <access>read-only</access> 20346 </field> 20347 <field> 20348 <name>EP4_IN_INT</name> 20349 <description>Endpoint 4 interrupt.</description> 20350 <bitOffset>4</bitOffset> 20351 <bitWidth>1</bitWidth> 20352 <access>read-only</access> 20353 </field> 20354 <field> 20355 <name>EP3_IN_INT</name> 20356 <description>Endpoint 3 interrupt.</description> 20357 <bitOffset>3</bitOffset> 20358 <bitWidth>1</bitWidth> 20359 <access>read-only</access> 20360 </field> 20361 <field> 20362 <name>EP2_IN_INT</name> 20363 <description>Endpoint 2 interrupt.</description> 20364 <bitOffset>2</bitOffset> 20365 <bitWidth>1</bitWidth> 20366 <access>read-only</access> 20367 </field> 20368 <field> 20369 <name>EP1_IN_INT</name> 20370 <description>Endpoint 1 interrupt.</description> 20371 <bitOffset>1</bitOffset> 20372 <bitWidth>1</bitWidth> 20373 <access>read-only</access> 20374 </field> 20375 <field> 20376 <name>EP0_IN_INT</name> 20377 <description>Endpoint 0 interrupt.</description> 20378 <bitOffset>0</bitOffset> 20379 <bitWidth>1</bitWidth> 20380 <access>read-only</access> 20381 </field> 20382 </fields> 20383 </register> 20384 <register> 20385 <name>INTROUT</name> 20386 <description>Interrupt register for OUT EP 1-15.</description> 20387 <addressOffset>0x04</addressOffset> 20388 <size>16</size> 20389 <fields> 20390 <field> 20391 <name>EP15_OUT_INT</name> 20392 <description>Endpoint 15 interrupt.</description> 20393 <bitOffset>15</bitOffset> 20394 <bitWidth>1</bitWidth> 20395 <access>read-only</access> 20396 </field> 20397 <field> 20398 <name>EP14_OUT_INT</name> 20399 <description>Endpoint 14 interrupt.</description> 20400 <bitOffset>14</bitOffset> 20401 <bitWidth>1</bitWidth> 20402 <access>read-only</access> 20403 </field> 20404 <field> 20405 <name>EP13_OUT_INT</name> 20406 <description>Endpoint 13 interrupt.</description> 20407 <bitOffset>13</bitOffset> 20408 <bitWidth>1</bitWidth> 20409 <access>read-only</access> 20410 </field> 20411 <field> 20412 <name>EP12_OUT_INT</name> 20413 <description>Endpoint 12 interrupt.</description> 20414 <bitOffset>12</bitOffset> 20415 <bitWidth>1</bitWidth> 20416 <access>read-only</access> 20417 </field> 20418 <field> 20419 <name>EP11_OUT_INT</name> 20420 <description>Endpoint 11 interrupt.</description> 20421 <bitOffset>11</bitOffset> 20422 <bitWidth>1</bitWidth> 20423 <access>read-only</access> 20424 </field> 20425 <field> 20426 <name>EP10_OUT_INT</name> 20427 <description>Endpoint 10 interrupt.</description> 20428 <bitOffset>10</bitOffset> 20429 <bitWidth>1</bitWidth> 20430 <access>read-only</access> 20431 </field> 20432 <field> 20433 <name>EP9_OUT_INT</name> 20434 <description>Endpoint 9 interrupt.</description> 20435 <bitOffset>9</bitOffset> 20436 <bitWidth>1</bitWidth> 20437 <access>read-only</access> 20438 </field> 20439 <field> 20440 <name>EP8_OUT_INT</name> 20441 <description>Endpoint 8 interrupt.</description> 20442 <bitOffset>8</bitOffset> 20443 <bitWidth>1</bitWidth> 20444 <access>read-only</access> 20445 </field> 20446 <field> 20447 <name>EP7_OUT_INT</name> 20448 <description>Endpoint 7 interrupt.</description> 20449 <bitOffset>7</bitOffset> 20450 <bitWidth>1</bitWidth> 20451 <access>read-only</access> 20452 </field> 20453 <field> 20454 <name>EP6_OUT_INT</name> 20455 <description>Endpoint 6 interrupt.</description> 20456 <bitOffset>6</bitOffset> 20457 <bitWidth>1</bitWidth> 20458 <access>read-only</access> 20459 </field> 20460 <field> 20461 <name>EP5_OUT_INT</name> 20462 <description>Endpoint 5 interrupt.</description> 20463 <bitOffset>5</bitOffset> 20464 <bitWidth>1</bitWidth> 20465 <access>read-only</access> 20466 </field> 20467 <field> 20468 <name>EP4_OUT_INT</name> 20469 <description>Endpoint 4 interrupt.</description> 20470 <bitOffset>4</bitOffset> 20471 <bitWidth>1</bitWidth> 20472 <access>read-only</access> 20473 </field> 20474 <field> 20475 <name>EP3_OUT_INT</name> 20476 <description>Endpoint 3 interrupt.</description> 20477 <bitOffset>3</bitOffset> 20478 <bitWidth>1</bitWidth> 20479 <access>read-only</access> 20480 </field> 20481 <field> 20482 <name>EP2_OUT_INT</name> 20483 <description>Endpoint 2 interrupt.</description> 20484 <bitOffset>2</bitOffset> 20485 <bitWidth>1</bitWidth> 20486 <access>read-only</access> 20487 </field> 20488 <field> 20489 <name>EP1_OUT_INT</name> 20490 <description>Endpoint 1 interrupt.</description> 20491 <bitOffset>1</bitOffset> 20492 <bitWidth>1</bitWidth> 20493 <access>read-only</access> 20494 </field> 20495 </fields> 20496 </register> 20497 <register> 20498 <name>INTRINEN</name> 20499 <description>Interrupt enable for EP 0 and IN EP 1-15.</description> 20500 <addressOffset>0x06</addressOffset> 20501 <size>16</size> 20502 <fields> 20503 <field> 20504 <name>EP15_IN_INT_EN</name> 20505 <description>Endpoint 15 interrupt enable.</description> 20506 <bitOffset>15</bitOffset> 20507 <bitWidth>1</bitWidth> 20508 <access>read-write</access> 20509 </field> 20510 <field> 20511 <name>EP14_IN_INT_EN</name> 20512 <description>Endpoint 14 interrupt enable.</description> 20513 <bitOffset>14</bitOffset> 20514 <bitWidth>1</bitWidth> 20515 <access>read-write</access> 20516 </field> 20517 <field> 20518 <name>EP13_IN_INT_EN</name> 20519 <description>Endpoint 13 interrupt enable.</description> 20520 <bitOffset>13</bitOffset> 20521 <bitWidth>1</bitWidth> 20522 <access>read-write</access> 20523 </field> 20524 <field> 20525 <name>EP12_IN_INT_EN</name> 20526 <description>Endpoint 12 interrupt enable.</description> 20527 <bitOffset>12</bitOffset> 20528 <bitWidth>1</bitWidth> 20529 <access>read-write</access> 20530 </field> 20531 <field> 20532 <name>EP11_IN_INT_EN</name> 20533 <description>Endpoint 11 interrupt enable.</description> 20534 <bitOffset>11</bitOffset> 20535 <bitWidth>1</bitWidth> 20536 <access>read-write</access> 20537 </field> 20538 <field> 20539 <name>EP10_IN_INT_EN</name> 20540 <description>Endpoint 10 interrupt enable.</description> 20541 <bitOffset>10</bitOffset> 20542 <bitWidth>1</bitWidth> 20543 <access>read-write</access> 20544 </field> 20545 <field> 20546 <name>EP9_IN_INT_EN</name> 20547 <description>Endpoint 9 interrupt enable.</description> 20548 <bitOffset>9</bitOffset> 20549 <bitWidth>1</bitWidth> 20550 <access>read-write</access> 20551 </field> 20552 <field> 20553 <name>EP8_IN_INT_EN</name> 20554 <description>Endpoint 8 interrupt enable.</description> 20555 <bitOffset>8</bitOffset> 20556 <bitWidth>1</bitWidth> 20557 <access>read-write</access> 20558 </field> 20559 <field> 20560 <name>EP7_IN_INT_EN</name> 20561 <description>Endpoint 7 interrupt enable.</description> 20562 <bitOffset>7</bitOffset> 20563 <bitWidth>1</bitWidth> 20564 <access>read-write</access> 20565 </field> 20566 <field> 20567 <name>EP6_IN_INT_EN</name> 20568 <description>Endpoint 6 interrupt enable.</description> 20569 <bitOffset>6</bitOffset> 20570 <bitWidth>1</bitWidth> 20571 <access>read-write</access> 20572 </field> 20573 <field> 20574 <name>EP5_IN_INT_EN</name> 20575 <description>Endpoint 5 interrupt enable.</description> 20576 <bitOffset>5</bitOffset> 20577 <bitWidth>1</bitWidth> 20578 <access>read-write</access> 20579 </field> 20580 <field> 20581 <name>EP4_IN_INT_EN</name> 20582 <description>Endpoint 4 interrupt enable.</description> 20583 <bitOffset>4</bitOffset> 20584 <bitWidth>1</bitWidth> 20585 <access>read-write</access> 20586 </field> 20587 <field> 20588 <name>EP3_IN_INT_EN</name> 20589 <description>Endpoint 3 interrupt enable.</description> 20590 <bitOffset>3</bitOffset> 20591 <bitWidth>1</bitWidth> 20592 <access>read-write</access> 20593 </field> 20594 <field> 20595 <name>EP2_IN_INT_EN</name> 20596 <description>Endpoint 2 interrupt enable.</description> 20597 <bitOffset>2</bitOffset> 20598 <bitWidth>1</bitWidth> 20599 <access>read-write</access> 20600 </field> 20601 <field> 20602 <name>EP1_IN_INT_EN</name> 20603 <description>Endpoint 1 interrupt enable.</description> 20604 <bitOffset>1</bitOffset> 20605 <bitWidth>1</bitWidth> 20606 <access>read-write</access> 20607 </field> 20608 <field> 20609 <name>EP0_INT_EN</name> 20610 <description>Endpoint 0 interrupt enable.</description> 20611 <bitOffset>0</bitOffset> 20612 <bitWidth>1</bitWidth> 20613 <access>read-write</access> 20614 </field> 20615 </fields> 20616 </register> 20617 <register> 20618 <name>INTROUTEN</name> 20619 <description>Interrupt enable for OUT EP 1-15.</description> 20620 <addressOffset>0x08</addressOffset> 20621 <size>16</size> 20622 <fields> 20623 <field> 20624 <name>EP15_OUT_INT_EN</name> 20625 <description>Endpoint 15 interrupt.</description> 20626 <bitOffset>15</bitOffset> 20627 <bitWidth>1</bitWidth> 20628 <access>read-write</access> 20629 </field> 20630 <field> 20631 <name>EP14_OUT_INT_EN</name> 20632 <description>Endpoint 14 interrupt.</description> 20633 <bitOffset>14</bitOffset> 20634 <bitWidth>1</bitWidth> 20635 <access>read-write</access> 20636 </field> 20637 <field> 20638 <name>EP13_OUT_INT_EN</name> 20639 <description>Endpoint 13 interrupt.</description> 20640 <bitOffset>13</bitOffset> 20641 <bitWidth>1</bitWidth> 20642 <access>read-write</access> 20643 </field> 20644 <field> 20645 <name>EP12_OUT_INT_EN</name> 20646 <description>Endpoint 12 interrupt.</description> 20647 <bitOffset>12</bitOffset> 20648 <bitWidth>1</bitWidth> 20649 <access>read-write</access> 20650 </field> 20651 <field> 20652 <name>EP11_OUT_INT_EN</name> 20653 <description>Endpoint 11 interrupt.</description> 20654 <bitOffset>11</bitOffset> 20655 <bitWidth>1</bitWidth> 20656 <access>read-write</access> 20657 </field> 20658 <field> 20659 <name>EP10_OUT_INT_EN</name> 20660 <description>Endpoint 10 interrupt.</description> 20661 <bitOffset>10</bitOffset> 20662 <bitWidth>1</bitWidth> 20663 <access>read-write</access> 20664 </field> 20665 <field> 20666 <name>EP9_OUT_INT_EN</name> 20667 <description>Endpoint 9 interrupt.</description> 20668 <bitOffset>9</bitOffset> 20669 <bitWidth>1</bitWidth> 20670 <access>read-write</access> 20671 </field> 20672 <field> 20673 <name>EP8_OUT_INT_EN</name> 20674 <description>Endpoint 8 interrupt.</description> 20675 <bitOffset>8</bitOffset> 20676 <bitWidth>1</bitWidth> 20677 <access>read-write</access> 20678 </field> 20679 <field> 20680 <name>EP7_OUT_INT_EN</name> 20681 <description>Endpoint 7 interrupt.</description> 20682 <bitOffset>7</bitOffset> 20683 <bitWidth>1</bitWidth> 20684 <access>read-write</access> 20685 </field> 20686 <field> 20687 <name>EP6_OUT_INT_EN</name> 20688 <description>Endpoint 6 interrupt.</description> 20689 <bitOffset>6</bitOffset> 20690 <bitWidth>1</bitWidth> 20691 <access>read-write</access> 20692 </field> 20693 <field> 20694 <name>EP5_OUT_INT_EN</name> 20695 <description>Endpoint 5 interrupt.</description> 20696 <bitOffset>5</bitOffset> 20697 <bitWidth>1</bitWidth> 20698 <access>read-write</access> 20699 </field> 20700 <field> 20701 <name>EP4_OUT_INT_EN</name> 20702 <description>Endpoint 4 interrupt.</description> 20703 <bitOffset>4</bitOffset> 20704 <bitWidth>1</bitWidth> 20705 <access>read-write</access> 20706 </field> 20707 <field> 20708 <name>EP3_OUT_INT_EN</name> 20709 <description>Endpoint 3 interrupt.</description> 20710 <bitOffset>3</bitOffset> 20711 <bitWidth>1</bitWidth> 20712 <access>read-write</access> 20713 </field> 20714 <field> 20715 <name>EP2_OUT_INT_EN</name> 20716 <description>Endpoint 2 interrupt.</description> 20717 <bitOffset>2</bitOffset> 20718 <bitWidth>1</bitWidth> 20719 <access>read-write</access> 20720 </field> 20721 <field> 20722 <name>EP1_OUT_INT_EN</name> 20723 <description>Endpoint 1 interrupt.</description> 20724 <bitOffset>1</bitOffset> 20725 <bitWidth>1</bitWidth> 20726 <access>read-write</access> 20727 </field> 20728 </fields> 20729 </register> 20730 <register> 20731 <name>INTRUSB</name> 20732 <description>Interrupt register for common USB interrupts.</description> 20733 <addressOffset>0x0A</addressOffset> 20734 <size>8</size> 20735 <fields> 20736 <field> 20737 <name>SOF_INT</name> 20738 <description>Start of Frame.</description> 20739 <bitOffset>3</bitOffset> 20740 <bitWidth>1</bitWidth> 20741 <access>read-only</access> 20742 </field> 20743 <field> 20744 <name>RESET_INT</name> 20745 <description>Bus reset detected.</description> 20746 <bitOffset>2</bitOffset> 20747 <bitWidth>1</bitWidth> 20748 <access>read-only</access> 20749 </field> 20750 <field> 20751 <name>RESUME_INT</name> 20752 <description>Resume detected.</description> 20753 <bitOffset>1</bitOffset> 20754 <bitWidth>1</bitWidth> 20755 <access>read-only</access> 20756 </field> 20757 <field> 20758 <name>SUSPEND_INT</name> 20759 <description>Suspend detected.</description> 20760 <bitOffset>0</bitOffset> 20761 <bitWidth>1</bitWidth> 20762 <access>read-only</access> 20763 </field> 20764 </fields> 20765 </register> 20766 <register> 20767 <name>INTRUSBEN</name> 20768 <description>Interrupt enable for common USB interrupts.</description> 20769 <addressOffset>0x0B</addressOffset> 20770 <size>8</size> 20771 <fields> 20772 <field> 20773 <name>SOF_INT_EN</name> 20774 <description>Start of Frame.</description> 20775 <bitOffset>3</bitOffset> 20776 <bitWidth>1</bitWidth> 20777 <access>read-write</access> 20778 </field> 20779 <field> 20780 <name>RESET_INT_EN</name> 20781 <description>Bus reset detected.</description> 20782 <bitOffset>2</bitOffset> 20783 <bitWidth>1</bitWidth> 20784 <access>read-write</access> 20785 </field> 20786 <field> 20787 <name>RESUME_INT_EN</name> 20788 <description>Resume detected.</description> 20789 <bitOffset>1</bitOffset> 20790 <bitWidth>1</bitWidth> 20791 <access>read-write</access> 20792 </field> 20793 <field> 20794 <name>SUSPEND_INT_EN</name> 20795 <description>Suspend detected.</description> 20796 <bitOffset>0</bitOffset> 20797 <bitWidth>1</bitWidth> 20798 <access>read-write</access> 20799 </field> 20800 </fields> 20801 </register> 20802 <register> 20803 <name>FRAME</name> 20804 <description>Frame number.</description> 20805 <addressOffset>0x0C</addressOffset> 20806 <size>16</size> 20807 <fields> 20808 <field> 20809 <name>FRAMENUM</name> 20810 <description>Read the last received frame number, that is the 11-bit frame number received in the SOF packet.</description> 20811 <bitOffset>0</bitOffset> 20812 <bitWidth>11</bitWidth> 20813 <access>read-only</access> 20814 </field> 20815 </fields> 20816 </register> 20817 <register> 20818 <name>INDEX</name> 20819 <description>Index for banked registers.</description> 20820 <addressOffset>0x0E</addressOffset> 20821 <size>8</size> 20822 <fields> 20823 <field> 20824 <name>INDEX</name> 20825 <description>Index Register Access Selector. </description> 20826 <bitOffset>0</bitOffset> 20827 <bitWidth>4</bitWidth> 20828 <access>read-write</access> 20829 </field> 20830 </fields> 20831 </register> 20832 <register> 20833 <name>TESTMODE</name> 20834 <description>USB 2.0 test mode enable register.</description> 20835 <addressOffset>0x0F</addressOffset> 20836 <size>8</size> 20837 <fields> 20838 <field> 20839 <name>FORCE_FS</name> 20840 <description>Force USB to Full-speed after reset.</description> 20841 <bitOffset>5</bitOffset> 20842 <bitWidth>1</bitWidth> 20843 <access>read-write</access> 20844 </field> 20845 <field> 20846 <name>FORCE_HS</name> 20847 <description>Force USB to High-speed after reset.</description> 20848 <bitOffset>4</bitOffset> 20849 <bitWidth>1</bitWidth> 20850 <access>read-write</access> 20851 </field> 20852 <field> 20853 <name>TEST_PKT</name> 20854 <description>Transmit fixed test packet.</description> 20855 <bitOffset>3</bitOffset> 20856 <bitWidth>1</bitWidth> 20857 <access>read-write</access> 20858 </field> 20859 <field> 20860 <name>TEST_K</name> 20861 <description>Force USB to continuous K state.</description> 20862 <bitOffset>2</bitOffset> 20863 <bitWidth>1</bitWidth> 20864 <access>read-write</access> 20865 </field> 20866 <field> 20867 <name>TEST_J</name> 20868 <description>Force USB to continuous J state.</description> 20869 <bitOffset>1</bitOffset> 20870 <bitWidth>1</bitWidth> 20871 <access>read-write</access> 20872 </field> 20873 <field> 20874 <name>TEST_SE0_NAK</name> 20875 <description>Respond to any valid IN token with NAK.</description> 20876 <bitOffset>0</bitOffset> 20877 <bitWidth>1</bitWidth> 20878 <access>read-write</access> 20879 </field> 20880 </fields> 20881 </register> 20882 <register> 20883 <name>INMAXP</name> 20884 <description>Maximum packet size for INx endpoint (x == INDEX).</description> 20885 <addressOffset>0x10</addressOffset> 20886 <size>16</size> 20887 <fields> 20888 <field> 20889 <name>MAXPACKETSIZE</name> 20890 <description>Maximum Packet Size in a Single Transaction. That is the maximum packet size in bytes, that is transmitted for each microframe. The maximum value is 1024, subject to the limitations of the endpoint type set in USB 2.0 Specification, Chapter 9</description> 20891 <bitOffset>0</bitOffset> 20892 <bitWidth>11</bitWidth> 20893 </field> 20894 <field> 20895 <name>NUMPACKMINUS1</name> 20896 <description>Number of Split Packets - 1. Defines the maximum number of packets minus 1 that a USB payload can be split into. THis must be an exact multiple of maxpacketsize. Only applicable for HS High-Bandwidth isochronous endpoints and Bulk endpoints. Ignored in all other cases. </description> 20897 <bitOffset>11</bitOffset> 20898 <bitWidth>5</bitWidth> 20899 </field> 20900 </fields> 20901 </register> 20902 <register> 20903 <name>CSR0</name> 20904 <description>Control status register for EP 0 (when INDEX == 0).</description> 20905 <addressOffset>0x12</addressOffset> 20906 <size>8</size> 20907 <fields> 20908 <field> 20909 <name>SERV_SETUP_END</name> 20910 <description>Clear EP0 Setup End Bit. Write a 1 to clear the setupend bit. Automatically cleared after being set </description> 20911 <bitOffset>7</bitOffset> 20912 <bitWidth>1</bitWidth> 20913 <access>read-write</access> 20914 </field> 20915 <field> 20916 <name>SERV_OUTPKTRDY</name> 20917 <description>Clear EP0 Out Packet Ready Bit. Write a 1 to clear the outpktrdy bit. Automatically cleared after being set.</description> 20918 <bitOffset>6</bitOffset> 20919 <bitWidth>1</bitWidth> 20920 <access>read-write</access> 20921 </field> 20922 <field> 20923 <name>SEND_STALL</name> 20924 <description>Send EP0 STALL Handshake. Write a 1 to this bit to terminate the current control transaction by sneding a STALL handshake. Automatically cleared after being set. </description> 20925 <bitOffset>5</bitOffset> 20926 <bitWidth>1</bitWidth> 20927 <access>read-write</access> 20928 </field> 20929 <field> 20930 <name>SETUP_END</name> 20931 <description>Read Setup End Status. Automatically set when a contorl transaction ends before the dataend bit has been set by fimrware. An interrupt is generated when this bit is set. Write 1 to servicedsetupend to clear.</description> 20932 <bitOffset>4</bitOffset> 20933 <bitWidth>1</bitWidth> 20934 <access>read-only</access> 20935 </field> 20936 <field> 20937 <name>DATA_END</name> 20938 <description>Control Transaction Data End. Write a 1 to this bit after firmware completes any of the following three transactions: 1. set inpktrdy = 1 for the last data packet. 2. Set inpktrdy =1 for a zero-length data packet. 3. Clear outpktrdy = 0 after unloading the last data packet. </description> 20939 <bitOffset>3</bitOffset> 20940 <bitWidth>1</bitWidth> 20941 <access>read-write</access> 20942 </field> 20943 <field> 20944 <name>SENT_STALL</name> 20945 <description> Read EP0 STALL Handshake Sent Status Automatically set when a STALL handshake is transmitted. Write a 0 to clear. </description> 20946 <bitOffset>2</bitOffset> 20947 <bitWidth>1</bitWidth> 20948 <access>read-write</access> 20949 </field> 20950 <field> 20951 <name>INPKTRDY</name> 20952 <description>EP0 IN Packet Ready 1: Write a 1 after writing a data packet to the IN FIFO. Automatically cleared when the data packet is transmitted. An interrupt is generated when this bit is cleared. </description> 20953 <bitOffset>1</bitOffset> 20954 <bitWidth>1</bitWidth> 20955 <access>read-write</access> 20956 </field> 20957 <field> 20958 <name>OUTPKTRDY</name> 20959 <description>EP0 OUT Packet Ready Status Automatically set when a data packet is received in the OUT FIFO. An interrupt is generated when this bit is set. Write a 1 to the servicedoutpktrdy bit (above) to clear after the packet is unloaded from the OUT FIFO. </description> 20960 <bitOffset>0</bitOffset> 20961 <bitWidth>1</bitWidth> 20962 <access>read-only</access> 20963 </field> 20964 </fields> 20965 </register> 20966 <register> 20967 <name>INCSRL</name> 20968 <description>Control status lower register for INx endpoint (x == INDEX).</description> 20969 <alternateRegister>CSR0</alternateRegister> 20970 <addressOffset>0x12</addressOffset> 20971 <size>8</size> 20972 <fields> 20973 <field> 20974 <name>INCOMPTX</name> 20975 <description>Read Incomplete Split Transfer Error Status High-bandwidth isochronous transfers: Automatically set when a payload is split into multiple packets but insufficient IN tokens were received to send all packets. The current packets is flushed from the IN FIFO. Write 0 to clear.</description> 20976 <bitOffset>7</bitOffset> 20977 <bitWidth>1</bitWidth> 20978 <access>read-write</access> 20979 </field> 20980 <field> 20981 <name>CLRDATATOG</name> 20982 <description>Write 1 to clear IN endpoint data-toggle to 0.</description> 20983 <bitOffset>6</bitOffset> 20984 <bitWidth>1</bitWidth> 20985 <access>read-write</access> 20986 </field> 20987 <field> 20988 <name>SENTSTALL</name> 20989 <description>Read STALL Handshake Sent Status Automatically set when a STALL handshake is transmitted, at which time the IN FIFO is flushed, and inpktrdy is cleared. Write 0 to clear.</description> 20990 <bitOffset>5</bitOffset> 20991 <bitWidth>1</bitWidth> 20992 <access>read-write</access> 20993 </field> 20994 <field> 20995 <name>SENDSTALL</name> 20996 <description>Send STALL Handshake.</description> 20997 <bitOffset>4</bitOffset> 20998 <bitWidth>1</bitWidth> 20999 <access>read-only</access> 21000 <enumeratedValues> 21001 <enumeratedValue> 21002 <name>terminate</name> 21003 <description>Terminate STALL handhsake</description> 21004 <value>0</value> 21005 </enumeratedValue> 21006 <enumeratedValue> 21007 <name>respond</name> 21008 <description>Respond to an IN token with a STALL handshake</description> 21009 <value>1</value> 21010 </enumeratedValue> 21011 </enumeratedValues> 21012 </field> 21013 <field> 21014 <name>FLUSHFIFO</name> 21015 <description>Flush Next Packet from IN FIFO. Write 1 to clear</description> 21016 <bitOffset>3</bitOffset> 21017 <bitWidth>1</bitWidth> 21018 <access>read-write</access> 21019 </field> 21020 <field> 21021 <name>UNDERRUN</name> 21022 <description>Read IN FIFO Underrun Error Status Isochronous Mode: Automatically set if the IN FIFO is empty. Write 0 to clear</description> 21023 <bitOffset>2</bitOffset> 21024 <bitWidth>1</bitWidth> 21025 <access>read-write</access> 21026 </field> 21027 <field> 21028 <name>FIFONOTEMPTY</name> 21029 <description>Read FIFO Not Empty Status. Automatically set when there is at least one packet in the IN FIFO. Write a 0 to clear. </description> 21030 <bitOffset>1</bitOffset> 21031 <bitWidth>1</bitWidth> 21032 <access>read-write</access> 21033 </field> 21034 <field> 21035 <name>INPKTRDY</name> 21036 <description>IN Packet Ready. Write a 1 to clear </description> 21037 <bitOffset>0</bitOffset> 21038 <bitWidth>1</bitWidth> 21039 <access>read-only</access> 21040 </field> 21041 </fields> 21042 </register> 21043 <register> 21044 <name>INCSRU</name> 21045 <description>Control status upper register for INx endpoint (x == INDEX).</description> 21046 <addressOffset>0x13</addressOffset> 21047 <size>8</size> 21048 <fields> 21049 <field> 21050 <name>AUTOSET</name> 21051 <description>Auto Set inpktrdy. </description> 21052 <bitOffset>7</bitOffset> 21053 <bitWidth>1</bitWidth> 21054 <access>read-write</access> 21055 <enumeratedValues> 21056 <enumeratedValue> 21057 <name>set</name> 21058 <description>USBHS_INCSRL_inpktrdy must be set by firmware.</description> 21059 <value>0</value> 21060 </enumeratedValue> 21061 <enumeratedValue> 21062 <name>auto</name> 21063 <description>USBHS_INCSRL_inpktrdy is automatically set. </description> 21064 <value>1</value> 21065 </enumeratedValue> 21066 </enumeratedValues> 21067 </field> 21068 <field> 21069 <name>ISO</name> 21070 <description>Isochronous Transfer Enable</description> 21071 <bitOffset>6</bitOffset> 21072 <bitWidth>1</bitWidth> 21073 <access>read-write</access> 21074 <enumeratedValues> 21075 <enumeratedValue> 21076 <name>interrupt</name> 21077 <description>Enable IN Bulk and IN interrupt transfers.</description> 21078 <value>0</value> 21079 </enumeratedValue> 21080 <enumeratedValue> 21081 <name>isochronous</name> 21082 <description>Enable IN Isochronous transfers. </description> 21083 <value>1</value> 21084 </enumeratedValue> 21085 </enumeratedValues> 21086 </field> 21087 <field> 21088 <name>MODE</name> 21089 <description> Endpoint Direction Mode.</description> 21090 <bitOffset>5</bitOffset> 21091 <bitWidth>1</bitWidth> 21092 <access>read-write</access> 21093 <enumeratedValues> 21094 <enumeratedValue> 21095 <name>out</name> 21096 <description>Endpoint direction is OUT.</description> 21097 <value>0</value> 21098 </enumeratedValue> 21099 <enumeratedValue> 21100 <name>in</name> 21101 <description>Endpoint direction is IN. </description> 21102 <value>1</value> 21103 </enumeratedValue> 21104 </enumeratedValues> 21105 </field> 21106 <field> 21107 <name>FRCDATATOG</name> 21108 <description> Force In Data - Toggle</description> 21109 <bitOffset>3</bitOffset> 21110 <bitWidth>1</bitWidth> 21111 <access>read-write</access> 21112 <enumeratedValues> 21113 <enumeratedValue> 21114 <name>received</name> 21115 <description>Toggle data-toglge only when an ACK is received.</description> 21116 <value>0</value> 21117 </enumeratedValue> 21118 <enumeratedValue> 21119 <name>dontcare</name> 21120 <description>Toggle data-toggle regardless of ACK. </description> 21121 <value>1</value> 21122 </enumeratedValue> 21123 </enumeratedValues> 21124 </field> 21125 <field> 21126 <name>DPKTBUFDIS</name> 21127 <description> Double Packet Buffering Disable </description> 21128 <bitOffset>1</bitOffset> 21129 <bitWidth>1</bitWidth> 21130 <access>read-write</access> 21131 <enumeratedValues> 21132 <enumeratedValue> 21133 <name>en</name> 21134 <description>Enable Double packet buffering.</description> 21135 <value>0</value> 21136 </enumeratedValue> 21137 <enumeratedValue> 21138 <name>dis</name> 21139 <description>Disable Double Packet Buffering.</description> 21140 <value>1</value> 21141 </enumeratedValue> 21142 </enumeratedValues> 21143 </field> 21144 </fields> 21145 </register> 21146 <register> 21147 <name>OUTMAXP</name> 21148 <description>Maximum packet size for OUTx endpoint (x == INDEX).</description> 21149 <addressOffset>0x14</addressOffset> 21150 <size>16</size> 21151 <fields> 21152 <field> 21153 <name>NUMPACKMINUS1</name> 21154 <description>Number of Split Packets -1. Defines the maximum number of packets - 1 that a usb payload is combined into. The value must be exact multiple of maxpacketsize. </description> 21155 <bitOffset>11</bitOffset> 21156 <bitWidth>5</bitWidth> 21157 </field> 21158 <field> 21159 <name>MAXPACKETSIZE</name> 21160 <description>Maximum Packet in a Single Transaction. This is the maximum packet size, in bytes, that is transmitted for each microframe. The maximum value is 1024, subject to the limitations for the endpoint type set in USB2.0 spesification, chapter 9.</description> 21161 <bitOffset>0</bitOffset> 21162 <bitWidth>11</bitWidth> 21163 </field> 21164 </fields> 21165 </register> 21166 <register> 21167 <name>OUTCSRL</name> 21168 <description>Control status lower register for OUTx endpoint (x == INDEX).</description> 21169 <addressOffset>0x16</addressOffset> 21170 <size>8</size> 21171 <fields> 21172 <field> 21173 <name>CLRDATATOG</name> 21174 <bitOffset>7</bitOffset> 21175 <bitWidth>1</bitWidth> 21176 <access>read-write</access> 21177 </field> 21178 <field> 21179 <name>SENTSTALL</name> 21180 <bitOffset>6</bitOffset> 21181 <bitWidth>1</bitWidth> 21182 <access>read-write</access> 21183 </field> 21184 <field> 21185 <name>SENDSTALL</name> 21186 <bitOffset>5</bitOffset> 21187 <bitWidth>1</bitWidth> 21188 <access>read-write</access> 21189 </field> 21190 <field> 21191 <name>FLUSHFIFO</name> 21192 <bitOffset>4</bitOffset> 21193 <bitWidth>1</bitWidth> 21194 <access>read-write</access> 21195 </field> 21196 <field> 21197 <name>DATAERROR</name> 21198 <bitOffset>3</bitOffset> 21199 <bitWidth>1</bitWidth> 21200 <access>read-only</access> 21201 </field> 21202 <field> 21203 <name>OVERRUN</name> 21204 <bitOffset>2</bitOffset> 21205 <bitWidth>1</bitWidth> 21206 <access>read-write</access> 21207 </field> 21208 <field> 21209 <name>FIFOFULL</name> 21210 <bitOffset>1</bitOffset> 21211 <bitWidth>1</bitWidth> 21212 <access>read-only</access> 21213 </field> 21214 <field> 21215 <name>OUTPKTRDY</name> 21216 <bitOffset>0</bitOffset> 21217 <bitWidth>1</bitWidth> 21218 <access>read-write</access> 21219 </field> 21220 </fields> 21221 </register> 21222 <register> 21223 <name>OUTCSRU</name> 21224 <description>Control status upper register for OUTx endpoint (x == INDEX).</description> 21225 <addressOffset>0x17</addressOffset> 21226 <size>8</size> 21227 <fields> 21228 <field> 21229 <name>AUTOCLEAR</name> 21230 <bitOffset>7</bitOffset> 21231 <bitWidth>1</bitWidth> 21232 <access>read-write</access> 21233 </field> 21234 <field> 21235 <name>ISO</name> 21236 <bitOffset>6</bitOffset> 21237 <bitWidth>1</bitWidth> 21238 <access>read-write</access> 21239 </field> 21240 <field> 21241 <name>DISNYET</name> 21242 <bitOffset>4</bitOffset> 21243 <bitWidth>1</bitWidth> 21244 <access>read-write</access> 21245 </field> 21246 <field> 21247 <name>DPKTBUFDIS</name> 21248 <bitOffset>1</bitOffset> 21249 <bitWidth>1</bitWidth> 21250 <access>read-write</access> 21251 </field> 21252 <field> 21253 <name>INCOMPRX</name> 21254 <bitOffset>0</bitOffset> 21255 <bitWidth>1</bitWidth> 21256 <access>read-only</access> 21257 </field> 21258 </fields> 21259 </register> 21260 <register> 21261 <name>COUNT0</name> 21262 <description>Number of received bytes in EP 0 FIFO (INDEX == 0).</description> 21263 <addressOffset>0x18</addressOffset> 21264 <size>16</size> 21265 <fields> 21266 <field> 21267 <name>COUNT0</name> 21268 <description>Read Number of Data Bytes in the Endpoint 0 FIFO. Returns the number of data bytes in the endpoint 0 FIFO. This value changes as contents of the FIFO change. The value is only valued when USBHS_OUTSCRL_outpktrdy = 1 </description> 21269 <bitOffset>0</bitOffset> 21270 <bitWidth>7</bitWidth> 21271 <access>read-only</access> 21272 </field> 21273 </fields> 21274 </register> 21275 <register> 21276 <name>OUTCOUNT</name> 21277 <description>Number of received bytes in OUT EPx FIFO (x == INDEX).</description> 21278 <alternateRegister>COUNT0</alternateRegister> 21279 <addressOffset>0x18</addressOffset> 21280 <size>16</size> 21281 <fields> 21282 <field> 21283 <name>OUTCOUNT</name> 21284 <description>Read Number of Data Bytes in OUT FIFO. Returns the number of data bytes in the packet that are read next in the OUT FIFO. </description> 21285 <bitOffset>0</bitOffset> 21286 <bitWidth>13</bitWidth> 21287 <access>read-only</access> 21288 </field> 21289 </fields> 21290 </register> 21291 <register> 21292 <name>FIFO0</name> 21293 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 21294 <addressOffset>0x20</addressOffset> 21295 <fields> 21296 <field> 21297 <name>USBHS_FIFO0</name> 21298 <description>USBHS Endpoint FIFO Read/Write Register.</description> 21299 <bitOffset>0</bitOffset> 21300 <bitWidth>32</bitWidth> 21301 </field> 21302 </fields> 21303 </register> 21304 <register> 21305 <name>FIFO1</name> 21306 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 21307 <addressOffset>0x24</addressOffset> 21308 <fields> 21309 <field> 21310 <name>USBHS_FIFO1</name> 21311 <description>USBHS Endpoint FIFO Read/Write Register.</description> 21312 <bitOffset>0</bitOffset> 21313 <bitWidth>32</bitWidth> 21314 </field> 21315 </fields> 21316 </register> 21317 <register> 21318 <name>FIFO2</name> 21319 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 21320 <addressOffset>0x28</addressOffset> 21321 <fields> 21322 <field> 21323 <name>USBHS_FIFO2</name> 21324 <description>USBHS Endpoint FIFO Read/Write Register.</description> 21325 <bitOffset>0</bitOffset> 21326 <bitWidth>32</bitWidth> 21327 </field> 21328 </fields> 21329 </register> 21330 <register> 21331 <name>FIFO3</name> 21332 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 21333 <addressOffset>0x2c</addressOffset> 21334 <fields> 21335 <field> 21336 <name>USBHS_FIFO3</name> 21337 <description>USBHS Endpoint FIFO Read/Write Register.</description> 21338 <bitOffset>0</bitOffset> 21339 <bitWidth>32</bitWidth> 21340 </field> 21341 </fields> 21342 </register> 21343 <register> 21344 <name>FIFO4</name> 21345 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 21346 <addressOffset>0x30</addressOffset> 21347 <fields> 21348 <field> 21349 <name>USBHS_FIFO4</name> 21350 <description>USBHS Endpoint FIFO Read/Write Register.</description> 21351 <bitOffset>0</bitOffset> 21352 <bitWidth>32</bitWidth> 21353 </field> 21354 </fields> 21355 </register> 21356 <register> 21357 <name>FIFO5</name> 21358 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 21359 <addressOffset>0x34</addressOffset> 21360 <fields> 21361 <field> 21362 <name>USBHS_FIFO5</name> 21363 <description>USBHS Endpoint FIFO Read/Write Register.</description> 21364 <bitOffset>0</bitOffset> 21365 <bitWidth>32</bitWidth> 21366 </field> 21367 </fields> 21368 </register> 21369 <register> 21370 <name>FIFO6</name> 21371 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 21372 <addressOffset>0x38</addressOffset> 21373 <fields> 21374 <field> 21375 <name>USBHS_FIFO6</name> 21376 <description>USBHS Endpoint FIFO Read/Write Register.</description> 21377 <bitOffset>0</bitOffset> 21378 <bitWidth>32</bitWidth> 21379 </field> 21380 </fields> 21381 </register> 21382 <register> 21383 <name>FIFO7</name> 21384 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 21385 <addressOffset>0x3c</addressOffset> 21386 <fields> 21387 <field> 21388 <name>USBHS_FIFO7</name> 21389 <description>USBHS Endpoint FIFO Read/Write Register.</description> 21390 <bitOffset>0</bitOffset> 21391 <bitWidth>32</bitWidth> 21392 </field> 21393 </fields> 21394 </register> 21395 <register> 21396 <name>FIFO8</name> 21397 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 21398 <addressOffset>0x40</addressOffset> 21399 <fields> 21400 <field> 21401 <name>USBHS_FIFO8</name> 21402 <description>USBHS Endpoint FIFO Read/Write Register.</description> 21403 <bitOffset>0</bitOffset> 21404 <bitWidth>32</bitWidth> 21405 </field> 21406 </fields> 21407 </register> 21408 <register> 21409 <name>FIFO9</name> 21410 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 21411 <addressOffset>0x44</addressOffset> 21412 <fields> 21413 <field> 21414 <name>USBHS_FIFO9</name> 21415 <description>USBHS Endpoint FIFO Read/Write Register.</description> 21416 <bitOffset>0</bitOffset> 21417 <bitWidth>32</bitWidth> 21418 </field> 21419 </fields> 21420 </register> 21421 <register> 21422 <name>FIFO10</name> 21423 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 21424 <addressOffset>0x48</addressOffset> 21425 <fields> 21426 <field> 21427 <name>USBHS_FIFO10</name> 21428 <description>USBHS Endpoint FIFO Read/Write Register.</description> 21429 <bitOffset>0</bitOffset> 21430 <bitWidth>32</bitWidth> 21431 </field> 21432 </fields> 21433 </register> 21434 <register> 21435 <name>FIFO11</name> 21436 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 21437 <addressOffset>0x4c</addressOffset> 21438 <fields> 21439 <field> 21440 <name>USBHS_FIFO11</name> 21441 <description>USBHS Endpoint FIFO Read/Write Register.</description> 21442 <bitOffset>0</bitOffset> 21443 <bitWidth>32</bitWidth> 21444 </field> 21445 </fields> 21446 </register> 21447 <register> 21448 <name>FIFO12</name> 21449 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 21450 <addressOffset>0x50</addressOffset> 21451 <fields> 21452 <field> 21453 <name>USBHS_FIFO12</name> 21454 <description>USBHS Endpoint FIFO Read/Write Register.</description> 21455 <bitOffset>0</bitOffset> 21456 <bitWidth>32</bitWidth> 21457 </field> 21458 </fields> 21459 </register> 21460 <register> 21461 <name>FIFO13</name> 21462 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 21463 <addressOffset>0x54</addressOffset> 21464 <fields> 21465 <field> 21466 <name>USBHS_FIFO13</name> 21467 <description>USBHS Endpoint FIFO Read/Write Register.</description> 21468 <bitOffset>0</bitOffset> 21469 <bitWidth>32</bitWidth> 21470 </field> 21471 </fields> 21472 </register> 21473 <register> 21474 <name>FIFO14</name> 21475 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 21476 <addressOffset>0x58</addressOffset> 21477 <fields> 21478 <field> 21479 <name>USBHS_FIFO14</name> 21480 <description>USBHS Endpoint FIFO Read/Write Register.</description> 21481 <bitOffset>0</bitOffset> 21482 <bitWidth>32</bitWidth> 21483 </field> 21484 </fields> 21485 </register> 21486 <register> 21487 <name>FIFO15</name> 21488 <description>Read for OUT data FIFO, write for IN data FIFO.</description> 21489 <addressOffset>0x5c</addressOffset> 21490 <fields> 21491 <field> 21492 <name>USBHS_FIFO15</name> 21493 <description>USBHS Endpoint FIFO Read/Write Register.</description> 21494 <bitOffset>0</bitOffset> 21495 <bitWidth>32</bitWidth> 21496 </field> 21497 </fields> 21498 </register> 21499 <register> 21500 <name>HWVERS</name> 21501 <description>HWVERS</description> 21502 <addressOffset>0x6c</addressOffset> 21503 <size>16</size> 21504 <fields> 21505 <field> 21506 <name>USBHS_HWVERS</name> 21507 <description>USBHS Register.</description> 21508 <bitOffset>0</bitOffset> 21509 <bitWidth>16</bitWidth> 21510 </field> 21511 </fields> 21512 </register> 21513 <register> 21514 <name>EPINFO</name> 21515 <description>Endpoint hardware information.</description> 21516 <addressOffset>0x78</addressOffset> 21517 <size>8</size> 21518 <fields> 21519 <field> 21520 <name>OUTENDPOINTS</name> 21521 <bitOffset>4</bitOffset> 21522 <bitWidth>4</bitWidth> 21523 <access>read-only</access> 21524 </field> 21525 <field> 21526 <name>INTENDPOINTS</name> 21527 <bitOffset>0</bitOffset> 21528 <bitWidth>4</bitWidth> 21529 <access>read-only</access> 21530 </field> 21531 </fields> 21532 </register> 21533 <register> 21534 <name>RAMINFO</name> 21535 <description>RAM width information.</description> 21536 <addressOffset>0x79</addressOffset> 21537 <size>8</size> 21538 <fields> 21539 <field> 21540 <name>RAMBITS</name> 21541 <bitOffset>0</bitOffset> 21542 <bitWidth>4</bitWidth> 21543 <access>read-only</access> 21544 </field> 21545 </fields> 21546 </register> 21547 <register> 21548 <name>SOFTRESET</name> 21549 <description>Software reset register.</description> 21550 <addressOffset>0x7A</addressOffset> 21551 <size>8</size> 21552 <fields> 21553 <field> 21554 <name>RSTXS</name> 21555 <bitOffset>1</bitOffset> 21556 <bitWidth>1</bitWidth> 21557 <access>read-write</access> 21558 </field> 21559 <field> 21560 <name>RSTS</name> 21561 <bitOffset>0</bitOffset> 21562 <bitWidth>1</bitWidth> 21563 <access>read-write</access> 21564 </field> 21565 </fields> 21566 </register> 21567 <register> 21568 <name>CTUCH</name> 21569 <description>Chirp timeout timer setting.</description> 21570 <addressOffset>0x80</addressOffset> 21571 <size>16</size> 21572 <fields> 21573 <field> 21574 <name>C_T_UCH</name> 21575 <description>HS Chirp Timeout Clock Cycles. This configures the chirp timeout used by this device to negotiate a HS connection with a FS Host. </description> 21576 <bitOffset>0</bitOffset> 21577 <bitWidth>16</bitWidth> 21578 </field> 21579 </fields> 21580 </register> 21581 <register> 21582 <name>CTHSRTN</name> 21583 <description>Sets delay between HS resume to UTM normal operating mode.</description> 21584 <addressOffset>0x82</addressOffset> 21585 <size>16</size> 21586 <fields> 21587 <field> 21588 <name>C_T_HSTRN</name> 21589 <description>High Speed Resume Delay Clock Cycles. This configures the delay from when the RESUME state on the bus ends, the when the USBHS resumes normal operation.</description> 21590 <bitOffset>0</bitOffset> 21591 <bitWidth>16</bitWidth> 21592 </field> 21593 </fields> 21594 </register> 21595 <register> 21596 <name>MXM_USB_REG_00</name> 21597 <description>MXM_USB_REG_00</description> 21598 <addressOffset>0x400</addressOffset> 21599 </register> 21600 <register> 21601 <name>M31_PHY_UTMI_RESET</name> 21602 <description>M31_PHY_UTMI_RESET</description> 21603 <addressOffset>0x404</addressOffset> 21604 </register> 21605 <register> 21606 <name>M31_PHY_UTMI_VCONTROL</name> 21607 <description>M31_PHY_UTMI_VCONTROL</description> 21608 <addressOffset>0x408</addressOffset> 21609 </register> 21610 <register> 21611 <name>M31_PHY_CLK_EN</name> 21612 <description>M31_PHY_CLK_EN</description> 21613 <addressOffset>0x40C</addressOffset> 21614 </register> 21615 <register> 21616 <name>M31_PHY_PONRST</name> 21617 <description>M31_PHY_PONRST</description> 21618 <addressOffset>0x410</addressOffset> 21619 </register> 21620 <register> 21621 <name>M31_PHY_NONCRY_RSTB</name> 21622 <description>M31_PHY_NONCRY_RSTB</description> 21623 <addressOffset>0x414</addressOffset> 21624 </register> 21625 <register> 21626 <name>M31_PHY_NONCRY_EN</name> 21627 <description>M31_PHY_NONCRY_EN</description> 21628 <addressOffset>0x418</addressOffset> 21629 </register> 21630 <register> 21631 <name>M31_PHY_U2_COMPLIANCE_EN</name> 21632 <description>M31_PHY_U2_COMPLIANCE_EN</description> 21633 <addressOffset>0x420</addressOffset> 21634 </register> 21635 <register> 21636 <name>M31_PHY_U2_COMPLIANCE_DAC_ADJ</name> 21637 <description>M31_PHY_U2_COMPLIANCE_DAC_ADJ</description> 21638 <addressOffset>0x424</addressOffset> 21639 </register> 21640 <register> 21641 <name>M31_PHY_U2_COMPLIANCE_DAC_ADJ_EN</name> 21642 <description>M31_PHY_U2_COMPLIANCE_DAC_ADJ_EN</description> 21643 <addressOffset>0x428</addressOffset> 21644 </register> 21645 <register> 21646 <name>M31_PHY_CLK_RDY</name> 21647 <description>M31_PHY_CLK_RDY</description> 21648 <addressOffset>0x42C</addressOffset> 21649 </register> 21650 <register> 21651 <name>M31_PHY_PLL_EN</name> 21652 <description>M31_PHY_PLL_EN</description> 21653 <addressOffset>0x430</addressOffset> 21654 </register> 21655 <register> 21656 <name>M31_PHY_BIST_OK</name> 21657 <description>M31_PHY_BIST_OK</description> 21658 <addressOffset>0x434</addressOffset> 21659 </register> 21660 <register> 21661 <name>M31_PHY_DATA_OE</name> 21662 <description>M31_PHY_DATA_OE</description> 21663 <addressOffset>0x438</addressOffset> 21664 </register> 21665 <register> 21666 <name>M31_PHY_OSCOUTEN</name> 21667 <description>M31_PHY_OSCOUTEN</description> 21668 <addressOffset>0x43C</addressOffset> 21669 </register> 21670 <register> 21671 <name>M31_PHY_LPM_ALIVE</name> 21672 <description>M31_PHY_LPM_ALIVE</description> 21673 <addressOffset>0x440</addressOffset> 21674 </register> 21675 <register> 21676 <name>M31_PHY_HS_BIST_MODE</name> 21677 <description>M31_PHY_HS_BIST_MODE</description> 21678 <addressOffset>0x444</addressOffset> 21679 </register> 21680 <register> 21681 <name>M31_PHY_CORECLKIN</name> 21682 <description>M31_PHY_CORECLKIN</description> 21683 <addressOffset>0x448</addressOffset> 21684 </register> 21685 <register> 21686 <name>M31_PHY_XTLSEL</name> 21687 <description>M31_PHY_XTLSEL</description> 21688 <addressOffset>0x44C</addressOffset> 21689 </register> 21690 <register> 21691 <name>M31_PHY_LS_EN</name> 21692 <description>M31_PHY_LS_EN</description> 21693 <addressOffset>0x450</addressOffset> 21694 </register> 21695 <register> 21696 <name>M31_PHY_DEBUG_SEL</name> 21697 <description>M31_PHY_DEBUG_SEL</description> 21698 <addressOffset>0x454</addressOffset> 21699 </register> 21700 <register> 21701 <name>M31_PHY_DEBUG_OUT</name> 21702 <description>M31_PHY_DEBUG_OUT</description> 21703 <addressOffset>0x458</addressOffset> 21704 </register> 21705 <register> 21706 <name>M31_PHY_OUTCLKSEL</name> 21707 <description>M31_PHY_OUTCLKSEL</description> 21708 <addressOffset>0x45C</addressOffset> 21709 </register> 21710 <register> 21711 <name>M31_PHY_XCFGI_31_0</name> 21712 <description>M31_PHY_XCFGI_31_0</description> 21713 <addressOffset>0x460</addressOffset> 21714 </register> 21715 <register> 21716 <name>M31_PHY_XCFGI_63_32</name> 21717 <description>M31_PHY_XCFGI_63_32</description> 21718 <addressOffset>0x464</addressOffset> 21719 </register> 21720 <register> 21721 <name>M31_PHY_XCFGI_95_64</name> 21722 <description>M31_PHY_XCFGI_95_64</description> 21723 <addressOffset>0x468</addressOffset> 21724 </register> 21725 <register> 21726 <name>M31_PHY_XCFGI_127_96</name> 21727 <description>M31_PHY_XCFGI_127_96</description> 21728 <addressOffset>0x46C</addressOffset> 21729 </register> 21730 <register> 21731 <name>M31_PHY_XCFGI_137_128</name> 21732 <description>M31_PHY_XCFGI_137_128</description> 21733 <addressOffset>0x470</addressOffset> 21734 </register> 21735 <register> 21736 <name>M31_PHY_XCFG_HS_COARSE_TUNE_NUM</name> 21737 <description>M31_PHY_XCFG_HS_COARSE_TUNE_NUM</description> 21738 <addressOffset>0x474</addressOffset> 21739 </register> 21740 <register> 21741 <name>M31_PHY_XCFG_HS_FINE_TUNE_NUM</name> 21742 <description>M31_PHY_XCFG_HS_FINE_TUNE_NUM</description> 21743 <addressOffset>0x478</addressOffset> 21744 </register> 21745 <register> 21746 <name>M31_PHY_XCFG_FS_COARSE_TUNE_NUM</name> 21747 <description>M31_PHY_XCFG_FS_COARSE_TUNE_NUM</description> 21748 <addressOffset>0x47C</addressOffset> 21749 </register> 21750 <register> 21751 <name>M31_PHY_XCFG_FS_FINE_TUNE_NUM</name> 21752 <description>M31_PHY_XCFG_FS_FINE_TUNE_NUM</description> 21753 <addressOffset>0x480</addressOffset> 21754 </register> 21755 <register> 21756 <name>M31_PHY_XCFG_LOCK_RANGE_MAX</name> 21757 <description>M31_PHY_XCFG_LOCK_RANGE_MAX</description> 21758 <addressOffset>0x484</addressOffset> 21759 </register> 21760 <register> 21761 <name>M31_PHY_XCFGI_LOCK_RANGE_MIN</name> 21762 <description>M31_PHY_XCFGI_LOCK_RANGE_MIN</description> 21763 <addressOffset>0x488</addressOffset> 21764 </register> 21765 <register> 21766 <name>M31_PHY_XCFG_OB_RSEL</name> 21767 <description>M31_PHY_XCFG_OB_RSEL</description> 21768 <addressOffset>0x48C</addressOffset> 21769 </register> 21770 <register> 21771 <name>M31_PHY_XCFG_OC_RSEL</name> 21772 <description>M31_PHY_XCFG_OC_RSEL</description> 21773 <addressOffset>0x490</addressOffset> 21774 </register> 21775 <register> 21776 <name>M31_PHY_XCFGO</name> 21777 <description>M31_PHY_XCFGO</description> 21778 <addressOffset>0x494</addressOffset> 21779 </register> 21780 <register> 21781 <name>MXM_INT</name> 21782 <description>USB Added Maxim Interrupt Flag Register.</description> 21783 <addressOffset>0x498</addressOffset> 21784 <fields> 21785 <field> 21786 <name>VBUS</name> 21787 <description>VBUS</description> 21788 <bitOffset>0</bitOffset> 21789 <bitWidth>1</bitWidth> 21790 </field> 21791 <field> 21792 <name>NOVBUS</name> 21793 <description>NOVBUS</description> 21794 <bitOffset>1</bitOffset> 21795 <bitWidth>1</bitWidth> 21796 </field> 21797 </fields> 21798 </register> 21799 <register> 21800 <name>MXM_INT_EN</name> 21801 <description>USB Added Maxim Interrupt Enable Register.</description> 21802 <addressOffset>0x49C</addressOffset> 21803 <fields> 21804 <field> 21805 <name>VBUS</name> 21806 <description>VBUS</description> 21807 <bitOffset>0</bitOffset> 21808 <bitWidth>1</bitWidth> 21809 </field> 21810 <field> 21811 <name>NOVBUS</name> 21812 <description>NOVBUS</description> 21813 <bitOffset>1</bitOffset> 21814 <bitWidth>1</bitWidth> 21815 </field> 21816 </fields> 21817 </register> 21818 <register> 21819 <name>MXM_SUSPEND</name> 21820 <description>USB Added Maxim Suspend Register.</description> 21821 <addressOffset>0x4A0</addressOffset> 21822 <fields> 21823 <field> 21824 <name>SEL</name> 21825 <description>Suspend register</description> 21826 <bitOffset>0</bitOffset> 21827 <bitWidth>1</bitWidth> 21828 </field> 21829 </fields> 21830 </register> 21831 <register> 21832 <name>MXM_REG_A4</name> 21833 <description>USB Added Maxim Power Status Register</description> 21834 <addressOffset>0x4A4</addressOffset> 21835 <fields> 21836 <field> 21837 <name>VRST_VDDB_N_A</name> 21838 <description>VRST_VDDB_N_A</description> 21839 <bitOffset>0</bitOffset> 21840 <bitWidth>1</bitWidth> 21841 </field> 21842 </fields> 21843 </register> 21844 </registers> 21845 </peripheral> 21846<!--USBHS USB 2.0 High-speed Controller.--> 21847 <peripheral> 21848 <name>WDT</name> 21849 <description>Windowed Watchdog Timer</description> 21850 <baseAddress>0x40003000</baseAddress> 21851 <addressBlock> 21852 <offset>0x00</offset> 21853 <size>0x0400</size> 21854 <usage>registers</usage> 21855 </addressBlock> 21856 <interrupt> 21857 <name>WWDT</name> 21858 <value>1</value> 21859 </interrupt> 21860 <registers> 21861 <register> 21862 <name>CTRL</name> 21863 <description>Watchdog Timer Control Register.</description> 21864 <addressOffset>0x00</addressOffset> 21865 <access>read-write</access> 21866 <fields> 21867 <field> 21868 <name>INT_LATE_VAL</name> 21869 <description>Windowed Watchdog Interrupt Upper Limit. Sets the number of WDTCLK cycles until a windowed watchdog timer interrupt is generated (if enabled) if the CPU does not write the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset.</description> 21870 <bitOffset>0</bitOffset> 21871 <bitWidth>4</bitWidth> 21872 <enumeratedValues> 21873 <enumeratedValue> 21874 <name>wdt2pow31</name> 21875 <description>2**31 clock cycles.</description> 21876 <value>0</value> 21877 </enumeratedValue> 21878 <enumeratedValue> 21879 <name>wdt2pow30</name> 21880 <description>2**30 clock cycles.</description> 21881 <value>1</value> 21882 </enumeratedValue> 21883 <enumeratedValue> 21884 <name>wdt2pow29</name> 21885 <description>2**29 clock cycles.</description> 21886 <value>2</value> 21887 </enumeratedValue> 21888 <enumeratedValue> 21889 <name>wdt2pow28</name> 21890 <description>2**28 clock cycles.</description> 21891 <value>3</value> 21892 </enumeratedValue> 21893 <enumeratedValue> 21894 <name>wdt2pow27</name> 21895 <description>2^27 clock cycles.</description> 21896 <value>4</value> 21897 </enumeratedValue> 21898 <enumeratedValue> 21899 <name>wdt2pow26</name> 21900 <description>2**26 clock cycles.</description> 21901 <value>5</value> 21902 </enumeratedValue> 21903 <enumeratedValue> 21904 <name>wdt2pow25</name> 21905 <description>2**25 clock cycles.</description> 21906 <value>6</value> 21907 </enumeratedValue> 21908 <enumeratedValue> 21909 <name>wdt2pow24</name> 21910 <description>2**24 clock cycles.</description> 21911 <value>7</value> 21912 </enumeratedValue> 21913 <enumeratedValue> 21914 <name>wdt2pow23</name> 21915 <description>2**23 clock cycles.</description> 21916 <value>8</value> 21917 </enumeratedValue> 21918 <enumeratedValue> 21919 <name>wdt2pow22</name> 21920 <description>2**22 clock cycles.</description> 21921 <value>9</value> 21922 </enumeratedValue> 21923 <enumeratedValue> 21924 <name>wdt2pow21</name> 21925 <description>2**21 clock cycles.</description> 21926 <value>10</value> 21927 </enumeratedValue> 21928 <enumeratedValue> 21929 <name>wdt2pow20</name> 21930 <description>2**20 clock cycles.</description> 21931 <value>11</value> 21932 </enumeratedValue> 21933 <enumeratedValue> 21934 <name>wdt2pow19</name> 21935 <description>2**19 clock cycles.</description> 21936 <value>12</value> 21937 </enumeratedValue> 21938 <enumeratedValue> 21939 <name>wdt2pow18</name> 21940 <description>2**18 clock cycles.</description> 21941 <value>13</value> 21942 </enumeratedValue> 21943 <enumeratedValue> 21944 <name>wdt2pow17</name> 21945 <description>2**17 clock cycles.</description> 21946 <value>14</value> 21947 </enumeratedValue> 21948 <enumeratedValue> 21949 <name>wdt2pow16</name> 21950 <description>2**16 clock cycles.</description> 21951 <value>15</value> 21952 </enumeratedValue> 21953 </enumeratedValues> 21954 </field> 21955 <field> 21956 <name>RST_LATE_VAL</name> 21957 <description>Windowed Watchdog Reset Upper Limit. Sets the number of WDTCLK cycles until a system reset occurs (if enabled) if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset.</description> 21958 <bitOffset>4</bitOffset> 21959 <bitWidth>4</bitWidth> 21960 <enumeratedValues> 21961 <enumeratedValue> 21962 <name>wdt2pow31</name> 21963 <description>2**31 clock cycles.</description> 21964 <value>0</value> 21965 </enumeratedValue> 21966 <enumeratedValue> 21967 <name>wdt2pow30</name> 21968 <description>2**30 clock cycles.</description> 21969 <value>1</value> 21970 </enumeratedValue> 21971 <enumeratedValue> 21972 <name>wdt2pow29</name> 21973 <description>2**29 clock cycles.</description> 21974 <value>2</value> 21975 </enumeratedValue> 21976 <enumeratedValue> 21977 <name>wdt2pow28</name> 21978 <description>2**28 clock cycles.</description> 21979 <value>3</value> 21980 </enumeratedValue> 21981 <enumeratedValue> 21982 <name>wdt2pow27</name> 21983 <description>2^27 clock cycles.</description> 21984 <value>4</value> 21985 </enumeratedValue> 21986 <enumeratedValue> 21987 <name>wdt2pow26</name> 21988 <description>2**26 clock cycles.</description> 21989 <value>5</value> 21990 </enumeratedValue> 21991 <enumeratedValue> 21992 <name>wdt2pow25</name> 21993 <description>2**25 clock cycles.</description> 21994 <value>6</value> 21995 </enumeratedValue> 21996 <enumeratedValue> 21997 <name>wdt2pow24</name> 21998 <description>2**24 clock cycles.</description> 21999 <value>7</value> 22000 </enumeratedValue> 22001 <enumeratedValue> 22002 <name>wdt2pow23</name> 22003 <description>2**23 clock cycles.</description> 22004 <value>8</value> 22005 </enumeratedValue> 22006 <enumeratedValue> 22007 <name>wdt2pow22</name> 22008 <description>2**22 clock cycles.</description> 22009 <value>9</value> 22010 </enumeratedValue> 22011 <enumeratedValue> 22012 <name>wdt2pow21</name> 22013 <description>2**21 clock cycles.</description> 22014 <value>10</value> 22015 </enumeratedValue> 22016 <enumeratedValue> 22017 <name>wdt2pow20</name> 22018 <description>2**20 clock cycles.</description> 22019 <value>11</value> 22020 </enumeratedValue> 22021 <enumeratedValue> 22022 <name>wdt2pow19</name> 22023 <description>2**19 clock cycles.</description> 22024 <value>12</value> 22025 </enumeratedValue> 22026 <enumeratedValue> 22027 <name>wdt2pow18</name> 22028 <description>2**18 clock cycles.</description> 22029 <value>13</value> 22030 </enumeratedValue> 22031 <enumeratedValue> 22032 <name>wdt2pow17</name> 22033 <description>2**17 clock cycles.</description> 22034 <value>14</value> 22035 </enumeratedValue> 22036 <enumeratedValue> 22037 <name>wdt2pow16</name> 22038 <description>2**16 clock cycles.</description> 22039 <value>15</value> 22040 </enumeratedValue> 22041 </enumeratedValues> 22042 </field> 22043 <field> 22044 <name>EN</name> 22045 <description>Windowed Watchdog Timer Enable.</description> 22046 <bitOffset>8</bitOffset> 22047 <bitWidth>1</bitWidth> 22048 <enumeratedValues> 22049 <enumeratedValue> 22050 <name>dis</name> 22051 <description>Disable.</description> 22052 <value>0</value> 22053 </enumeratedValue> 22054 <enumeratedValue> 22055 <name>en</name> 22056 <description>Enable.</description> 22057 <value>1</value> 22058 </enumeratedValue> 22059 </enumeratedValues> 22060 </field> 22061 <field> 22062 <name>INT_LATE</name> 22063 <description>Windowed Watchdog Timer Interrupt Flag Too Late.</description> 22064 <bitOffset>9</bitOffset> 22065 <bitWidth>1</bitWidth> 22066 <enumeratedValues> 22067 <usage>read-write</usage> 22068 <enumeratedValue> 22069 <name>inactive</name> 22070 <description>No interrupt is pending.</description> 22071 <value>0</value> 22072 </enumeratedValue> 22073 <enumeratedValue> 22074 <name>pending</name> 22075 <description>An interrupt is pending.</description> 22076 <value>1</value> 22077 </enumeratedValue> 22078 </enumeratedValues> 22079 </field> 22080 <field> 22081 <name>WDT_INT_EN</name> 22082 <description>Windowed Watchdog Timer Interrupt Enable.</description> 22083 <bitOffset>10</bitOffset> 22084 <bitWidth>1</bitWidth> 22085 <enumeratedValues> 22086 <enumeratedValue> 22087 <name>dis</name> 22088 <description>Disable.</description> 22089 <value>0</value> 22090 </enumeratedValue> 22091 <enumeratedValue> 22092 <name>en</name> 22093 <description>Enable.</description> 22094 <value>1</value> 22095 </enumeratedValue> 22096 </enumeratedValues> 22097 </field> 22098 <field> 22099 <name>WDT_RST_EN</name> 22100 <description>Windowed Watchdog Timer Reset Enable.</description> 22101 <bitOffset>11</bitOffset> 22102 <bitWidth>1</bitWidth> 22103 <enumeratedValues> 22104 <enumeratedValue> 22105 <name>dis</name> 22106 <description>Disable.</description> 22107 <value>0</value> 22108 </enumeratedValue> 22109 <enumeratedValue> 22110 <name>en</name> 22111 <description>Enable.</description> 22112 <value>1</value> 22113 </enumeratedValue> 22114 </enumeratedValues> 22115 </field> 22116 <field> 22117 <name>INT_EARLY</name> 22118 <description>Windowed Watchdog Timer Interrupt Flag Too Soon.</description> 22119 <bitOffset>12</bitOffset> 22120 <bitWidth>1</bitWidth> 22121 <enumeratedValues> 22122 <usage>read-write</usage> 22123 <enumeratedValue> 22124 <name>inactive</name> 22125 <description>No interrupt is pending.</description> 22126 <value>0</value> 22127 </enumeratedValue> 22128 <enumeratedValue> 22129 <name>pending</name> 22130 <description>An interrupt is pending.</description> 22131 <value>1</value> 22132 </enumeratedValue> 22133 </enumeratedValues> 22134 </field> 22135 <field> 22136 <name>INT_EARLY_VAL</name> 22137 <description>Windowed Watchdog Interrupt Lower Limit. Sets the number of WDTCLK cycles that establishes the lower boundary of the watchdog window. A windowed watchdog timer interrupt is generated (if enabled) if the CPU writes the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset.</description> 22138 <bitOffset>16</bitOffset> 22139 <bitWidth>4</bitWidth> 22140 <enumeratedValues> 22141 <enumeratedValue> 22142 <name>wdt2pow31</name> 22143 <description>2**31 clock cycles.</description> 22144 <value>0</value> 22145 </enumeratedValue> 22146 <enumeratedValue> 22147 <name>wdt2pow30</name> 22148 <description>2**30 clock cycles.</description> 22149 <value>1</value> 22150 </enumeratedValue> 22151 <enumeratedValue> 22152 <name>wdt2pow29</name> 22153 <description>2**29 clock cycles.</description> 22154 <value>2</value> 22155 </enumeratedValue> 22156 <enumeratedValue> 22157 <name>wdt2pow28</name> 22158 <description>2**28 clock cycles.</description> 22159 <value>3</value> 22160 </enumeratedValue> 22161 <enumeratedValue> 22162 <name>wdt2pow27</name> 22163 <description>2^27 clock cycles.</description> 22164 <value>4</value> 22165 </enumeratedValue> 22166 <enumeratedValue> 22167 <name>wdt2pow26</name> 22168 <description>2**26 clock cycles.</description> 22169 <value>5</value> 22170 </enumeratedValue> 22171 <enumeratedValue> 22172 <name>wdt2pow25</name> 22173 <description>2**25 clock cycles.</description> 22174 <value>6</value> 22175 </enumeratedValue> 22176 <enumeratedValue> 22177 <name>wdt2pow24</name> 22178 <description>2**24 clock cycles.</description> 22179 <value>7</value> 22180 </enumeratedValue> 22181 <enumeratedValue> 22182 <name>wdt2pow23</name> 22183 <description>2**23 clock cycles.</description> 22184 <value>8</value> 22185 </enumeratedValue> 22186 <enumeratedValue> 22187 <name>wdt2pow22</name> 22188 <description>2**22 clock cycles.</description> 22189 <value>9</value> 22190 </enumeratedValue> 22191 <enumeratedValue> 22192 <name>wdt2pow21</name> 22193 <description>2**21 clock cycles.</description> 22194 <value>10</value> 22195 </enumeratedValue> 22196 <enumeratedValue> 22197 <name>wdt2pow20</name> 22198 <description>2**20 clock cycles.</description> 22199 <value>11</value> 22200 </enumeratedValue> 22201 <enumeratedValue> 22202 <name>wdt2pow19</name> 22203 <description>2**19 clock cycles.</description> 22204 <value>12</value> 22205 </enumeratedValue> 22206 <enumeratedValue> 22207 <name>wdt2pow18</name> 22208 <description>2**18 clock cycles.</description> 22209 <value>13</value> 22210 </enumeratedValue> 22211 <enumeratedValue> 22212 <name>wdt2pow17</name> 22213 <description>2**17 clock cycles.</description> 22214 <value>14</value> 22215 </enumeratedValue> 22216 <enumeratedValue> 22217 <name>wdt2pow16</name> 22218 <description>2**16 clock cycles.</description> 22219 <value>15</value> 22220 </enumeratedValue> 22221 </enumeratedValues> 22222 </field> 22223 <field> 22224 <name>RST_EARLY_VAL</name> 22225 <description>Windowed Watchdog Reset Lower Limit. Sets the number of WDTCLK cycles that establishes the lower boundary of the watchdog window. A system reset occurs (if enabled) if the CPU writes the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset.</description> 22226 <bitOffset>20</bitOffset> 22227 <bitWidth>4</bitWidth> 22228 <enumeratedValues> 22229 <enumeratedValue> 22230 <name>wdt2pow31</name> 22231 <description>2**31 clock cycles.</description> 22232 <value>0</value> 22233 </enumeratedValue> 22234 <enumeratedValue> 22235 <name>wdt2pow30</name> 22236 <description>2**30 clock cycles.</description> 22237 <value>1</value> 22238 </enumeratedValue> 22239 <enumeratedValue> 22240 <name>wdt2pow29</name> 22241 <description>2**29 clock cycles.</description> 22242 <value>2</value> 22243 </enumeratedValue> 22244 <enumeratedValue> 22245 <name>wdt2pow28</name> 22246 <description>2**28 clock cycles.</description> 22247 <value>3</value> 22248 </enumeratedValue> 22249 <enumeratedValue> 22250 <name>wdt2pow27</name> 22251 <description>2^27 clock cycles.</description> 22252 <value>4</value> 22253 </enumeratedValue> 22254 <enumeratedValue> 22255 <name>wdt2pow26</name> 22256 <description>2**26 clock cycles.</description> 22257 <value>5</value> 22258 </enumeratedValue> 22259 <enumeratedValue> 22260 <name>wdt2pow25</name> 22261 <description>2**25 clock cycles.</description> 22262 <value>6</value> 22263 </enumeratedValue> 22264 <enumeratedValue> 22265 <name>wdt2pow24</name> 22266 <description>2**24 clock cycles.</description> 22267 <value>7</value> 22268 </enumeratedValue> 22269 <enumeratedValue> 22270 <name>wdt2pow23</name> 22271 <description>2**23 clock cycles.</description> 22272 <value>8</value> 22273 </enumeratedValue> 22274 <enumeratedValue> 22275 <name>wdt2pow22</name> 22276 <description>2**22 clock cycles.</description> 22277 <value>9</value> 22278 </enumeratedValue> 22279 <enumeratedValue> 22280 <name>wdt2pow21</name> 22281 <description>2**21 clock cycles.</description> 22282 <value>10</value> 22283 </enumeratedValue> 22284 <enumeratedValue> 22285 <name>wdt2pow20</name> 22286 <description>2**20 clock cycles.</description> 22287 <value>11</value> 22288 </enumeratedValue> 22289 <enumeratedValue> 22290 <name>wdt2pow19</name> 22291 <description>2**19 clock cycles.</description> 22292 <value>12</value> 22293 </enumeratedValue> 22294 <enumeratedValue> 22295 <name>wdt2pow18</name> 22296 <description>2**18 clock cycles.</description> 22297 <value>13</value> 22298 </enumeratedValue> 22299 <enumeratedValue> 22300 <name>wdt2pow17</name> 22301 <description>2**17 clock cycles.</description> 22302 <value>14</value> 22303 </enumeratedValue> 22304 <enumeratedValue> 22305 <name>wdt2pow16</name> 22306 <description>2**16 clock cycles.</description> 22307 <value>15</value> 22308 </enumeratedValue> 22309 </enumeratedValues> 22310 </field> 22311 <field> 22312 <name>CLKRDY_IE</name> 22313 <description>Switch Ready Interrupt Enable. Fires an interrupt when it is safe to swithc the clock.</description> 22314 <bitOffset>27</bitOffset> 22315 <bitWidth>1</bitWidth> 22316 </field> 22317 <field> 22318 <name>CLKRDY</name> 22319 <description>Clock Status.</description> 22320 <bitOffset>28</bitOffset> 22321 <bitWidth>1</bitWidth> 22322 </field> 22323 <field> 22324 <name>WIN_EN</name> 22325 <description>Enables the Windowed Watchdog Function.</description> 22326 <bitOffset>29</bitOffset> 22327 <bitWidth>1</bitWidth> 22328 <enumeratedValues> 22329 <enumeratedValue> 22330 <name>dis</name> 22331 <description>Windowed Mode Disabled (i.e. Compatibility Mode).</description> 22332 <value>0</value> 22333 </enumeratedValue> 22334 <enumeratedValue> 22335 <name>en</name> 22336 <description>Windowed Mode Enabled.</description> 22337 <value>1</value> 22338 </enumeratedValue> 22339 </enumeratedValues> 22340 </field> 22341 <field> 22342 <name>RST_EARLY</name> 22343 <description>Windowed Watchdog Timer Reset Flag Too Soon.</description> 22344 <bitOffset>30</bitOffset> 22345 <bitWidth>1</bitWidth> 22346 <enumeratedValues> 22347 <usage>read-write</usage> 22348 <enumeratedValue> 22349 <name>noEvent</name> 22350 <description>The event has not occurred.</description> 22351 <value>0</value> 22352 </enumeratedValue> 22353 <enumeratedValue> 22354 <name>occurred</name> 22355 <description>The event has occurred.</description> 22356 <value>1</value> 22357 </enumeratedValue> 22358 </enumeratedValues> 22359 </field> 22360 <field> 22361 <name>RST_LATE</name> 22362 <description>Windowed Watchdog Timer Reset Flag Too Late.</description> 22363 <bitOffset>31</bitOffset> 22364 <bitWidth>1</bitWidth> 22365 <enumeratedValues> 22366 <usage>read-write</usage> 22367 <enumeratedValue> 22368 <name>noEvent</name> 22369 <description>The event has not occurred.</description> 22370 <value>0</value> 22371 </enumeratedValue> 22372 <enumeratedValue> 22373 <name>occurred</name> 22374 <description>The event has occurred.</description> 22375 <value>1</value> 22376 </enumeratedValue> 22377 </enumeratedValues> 22378 </field> 22379 </fields> 22380 </register> 22381 <register> 22382 <name>RST</name> 22383 <description>Windowed Watchdog Timer Reset Register.</description> 22384 <addressOffset>0x04</addressOffset> 22385 <access>write-only</access> 22386 <fields> 22387 <field> 22388 <name>RESET</name> 22389 <description>Writing the watchdog counter 'reset sequence' to this register resets the watchdog counter. If the watchdog count exceeds INT_PERIOD_UPPER_LIMIT then a watchdog interrupt will occur, if enabled. If the watchdog count exceeds RST_PERIOD_UPPER_LIMIT then a watchdog reset will occur, if enabled.</description> 22390 <bitOffset>0</bitOffset> 22391 <bitWidth>8</bitWidth> 22392 <enumeratedValues> 22393 <enumeratedValue> 22394 <name>seq0</name> 22395 <description>The first value to be written to reset the WDT.</description> 22396 <value>0x000000A5</value> 22397 </enumeratedValue> 22398 <enumeratedValue> 22399 <name>seq1</name> 22400 <description>The second value to be written to reset the WDT.</description> 22401 <value>0x0000005A</value> 22402 </enumeratedValue> 22403 </enumeratedValues> 22404 </field> 22405 </fields> 22406 </register> 22407 <register> 22408 <name>CLKSEL</name> 22409 <description>Windowed Watchdog Timer Clock Select Register.</description> 22410 <addressOffset>0x08</addressOffset> 22411 <access>read-write</access> 22412 <fields> 22413 <field> 22414 <name>SOURCE</name> 22415 <description>WWDT Clock Selection Register.</description> 22416 <bitOffset>0</bitOffset> 22417 <bitWidth>3</bitWidth> 22418 </field> 22419 </fields> 22420 </register> 22421 <register> 22422 <name>CNT</name> 22423 <description>Windowed Watchdog Timer Count Register.</description> 22424 <addressOffset>0x0C</addressOffset> 22425 <access>read-only</access> 22426 <fields> 22427 <field> 22428 <name>COUNT</name> 22429 <description>Current Value of the Windowed Watchdog Timer Counter.</description> 22430 <bitOffset>0</bitOffset> 22431 <bitWidth>32</bitWidth> 22432 </field> 22433 </fields> 22434 </register> 22435 </registers> 22436 </peripheral> 22437<!--WDT Windowed Watchdog Timer--> 22438 <peripheral derivedFrom="WDT"> 22439 <name>WDT1</name> 22440 <description>Windowed Watchdog Timer 1</description> 22441 <baseAddress>0x40080800</baseAddress> 22442 <interrupt> 22443 <name>WDT1</name> 22444 <description>WDT1 IRQ</description> 22445 <value>57</value> 22446 </interrupt> 22447 </peripheral> 22448<!--WDT1 Windowed Watchdog Timer 1--> 22449 <peripheral> 22450 <name>WUT</name> 22451 <description>Wake Up Timer</description> 22452 <baseAddress>0x40006400</baseAddress> 22453 <addressBlock> 22454 <offset>0x00</offset> 22455 <size>0x0400</size> 22456 <usage>registers</usage> 22457 </addressBlock> 22458 <interrupt> 22459 <name>WUT</name> 22460 <value>53</value> 22461 </interrupt> 22462 <registers> 22463 <register> 22464 <name>CNT</name> 22465 <description>Wakeup Timer Count Register</description> 22466 <addressOffset>0x0000</addressOffset> 22467 <access>read-write</access> 22468 <fields> 22469 <field> 22470 <name>COUNT</name> 22471 <description>Timer Count Value. </description> 22472 <bitOffset>0</bitOffset> 22473 <bitWidth>32</bitWidth> 22474 </field> 22475 </fields> 22476 </register> 22477 <register> 22478 <name>CMP</name> 22479 <description>Wakeup Timer Compare Register</description> 22480 <addressOffset>0x0004</addressOffset> 22481 <access>read-write</access> 22482 <fields> 22483 <field> 22484 <name>COMPARE</name> 22485 <description>Timer Compare Value.</description> 22486 <bitOffset>0</bitOffset> 22487 <bitWidth>32</bitWidth> 22488 </field> 22489 </fields> 22490 </register> 22491 <register> 22492 <name>INTFL</name> 22493 <description>Wakeup Timer Interrupt Register</description> 22494 <addressOffset>0x000C</addressOffset> 22495 <access>read-write</access> 22496 <fields> 22497 <field> 22498 <name>IRQ_CLR</name> 22499 <description>Timer Interrupt.</description> 22500 <bitOffset>0</bitOffset> 22501 <bitWidth>1</bitWidth> 22502 </field> 22503 </fields> 22504 </register> 22505 <register> 22506 <name>CTRL</name> 22507 <description>Wakeup Timer Control Register</description> 22508 <addressOffset>0x0010</addressOffset> 22509 <access>read-write</access> 22510 <fields> 22511 <field> 22512 <name>TMODE</name> 22513 <description>Timer Mode Select.</description> 22514 <bitOffset>0</bitOffset> 22515 <bitWidth>3</bitWidth> 22516 <enumeratedValues> 22517 <enumeratedValue> 22518 <name>oneShot</name> 22519 <description>One Shot Mode.</description> 22520 <value>0</value> 22521 </enumeratedValue> 22522 <enumeratedValue> 22523 <name>continuous</name> 22524 <description>Continuous Mode.</description> 22525 <value>1</value> 22526 </enumeratedValue> 22527 <enumeratedValue> 22528 <name>counter</name> 22529 <description>Counter Mode.</description> 22530 <value>2</value> 22531 </enumeratedValue> 22532 <enumeratedValue> 22533 <name>pwm</name> 22534 <description>PWM Mode.</description> 22535 <value>3</value> 22536 </enumeratedValue> 22537 <enumeratedValue> 22538 <name>capture</name> 22539 <description>Capture Mode.</description> 22540 <value>4</value> 22541 </enumeratedValue> 22542 <enumeratedValue> 22543 <name>compare</name> 22544 <description>Compare Mode.</description> 22545 <value>5</value> 22546 </enumeratedValue> 22547 <enumeratedValue> 22548 <name>gated</name> 22549 <description>Gated Mode.</description> 22550 <value>6</value> 22551 </enumeratedValue> 22552 <enumeratedValue> 22553 <name>captureCompare</name> 22554 <description>Capture/Compare Mode.</description> 22555 <value>7</value> 22556 </enumeratedValue> 22557 </enumeratedValues> 22558 </field> 22559 <field> 22560 <name>PRES</name> 22561 <description>Timer Prescaler Select.</description> 22562 <bitOffset>3</bitOffset> 22563 <bitWidth>3</bitWidth> 22564 <enumeratedValues> 22565 <enumeratedValue> 22566 <name>DIV1</name> 22567 <value>0</value> 22568 </enumeratedValue> 22569 <enumeratedValue> 22570 <name>DIV2</name> 22571 <value>1</value> 22572 </enumeratedValue> 22573 <enumeratedValue> 22574 <name>DIV4</name> 22575 <value>2</value> 22576 </enumeratedValue> 22577 <enumeratedValue> 22578 <name>DIV8</name> 22579 <value>3</value> 22580 </enumeratedValue> 22581 <enumeratedValue> 22582 <name>DIV16</name> 22583 <value>4</value> 22584 </enumeratedValue> 22585 <enumeratedValue> 22586 <name>DIV32</name> 22587 <value>5</value> 22588 </enumeratedValue> 22589 <enumeratedValue> 22590 <name>DIV64</name> 22591 <value>6</value> 22592 </enumeratedValue> 22593 <enumeratedValue> 22594 <name>DIV128</name> 22595 <value>7</value> 22596 </enumeratedValue> 22597 <enumeratedValue> 22598 <name>DIV256</name> 22599 <value>0</value> 22600 </enumeratedValue> 22601 <enumeratedValue> 22602 <name>DIV512</name> 22603 <value>2</value> 22604 </enumeratedValue> 22605 <enumeratedValue> 22606 <name>DIV1024</name> 22607 <value>3</value> 22608 </enumeratedValue> 22609 <enumeratedValue> 22610 <name>DIV2048</name> 22611 <value>4</value> 22612 </enumeratedValue> 22613 <enumeratedValue> 22614 <name>DIV4096</name> 22615 <value>5</value> 22616 </enumeratedValue> 22617 </enumeratedValues> 22618 </field> 22619 <field> 22620 <name>TPOL</name> 22621 <description>Timer Polarity.</description> 22622 <bitOffset>6</bitOffset> 22623 <bitWidth>1</bitWidth> 22624 </field> 22625 <field> 22626 <name>TEN</name> 22627 <description>Timer Enable.</description> 22628 <bitOffset>7</bitOffset> 22629 <bitWidth>1</bitWidth> 22630 <enumeratedValues> 22631 <enumeratedValue> 22632 <name>timer_dis</name> 22633 <value>0</value> 22634 </enumeratedValue> 22635 <enumeratedValue> 22636 <name>timer_en</name> 22637 <value>1</value> 22638 </enumeratedValue> 22639 </enumeratedValues> 22640 </field> 22641 <field> 22642 <name>PRES3</name> 22643 <description>Timer Prescaler Select.</description> 22644 <bitOffset>8</bitOffset> 22645 <bitWidth>1</bitWidth> 22646 <enumeratedValues> 22647 <enumeratedValue> 22648 <name>pres3_1</name> 22649 <value>0</value> 22650 </enumeratedValue> 22651 <enumeratedValue> 22652 <name>pres3_2</name> 22653 <value>0</value> 22654 </enumeratedValue> 22655 <enumeratedValue> 22656 <name>pres3_4</name> 22657 <value>0</value> 22658 </enumeratedValue> 22659 <enumeratedValue> 22660 <name>pres3_8</name> 22661 <value>0</value> 22662 </enumeratedValue> 22663 <enumeratedValue> 22664 <name>pres3_16</name> 22665 <value>0</value> 22666 </enumeratedValue> 22667 <enumeratedValue> 22668 <name>pres3_32</name> 22669 <value>0</value> 22670 </enumeratedValue> 22671 <enumeratedValue> 22672 <name>pres3_64</name> 22673 <value>0</value> 22674 </enumeratedValue> 22675 <enumeratedValue> 22676 <name>pres3_128</name> 22677 <value>0</value> 22678 </enumeratedValue> 22679 <enumeratedValue> 22680 <name>pres3_256</name> 22681 <value>1</value> 22682 </enumeratedValue> 22683 <enumeratedValue> 22684 <name>pres3_512</name> 22685 <value>1</value> 22686 </enumeratedValue> 22687 <enumeratedValue> 22688 <name>pres3_1024</name> 22689 <value>1</value> 22690 </enumeratedValue> 22691 <enumeratedValue> 22692 <name>pres3_2048</name> 22693 <value>1</value> 22694 </enumeratedValue> 22695 <enumeratedValue> 22696 <name>pres3_4096</name> 22697 <value>1</value> 22698 </enumeratedValue> 22699 </enumeratedValues> 22700 </field> 22701 </fields> 22702 </register> 22703 <register> 22704 <name>NOLCMP</name> 22705 <description>Non Overlaping Compare Register</description> 22706 <addressOffset>0x0014</addressOffset> 22707 <access>read-write</access> 22708 <fields> 22709 <field> 22710 <name>NOLLCMP</name> 22711 <description>Non Overlaping Low Compare.</description> 22712 <bitOffset>0</bitOffset> 22713 <bitWidth>8</bitWidth> 22714 </field> 22715 <field> 22716 <name>NOLHCMP</name> 22717 <description>Non Overlaping High Compare.</description> 22718 <bitOffset>8</bitOffset> 22719 <bitWidth>8</bitWidth> 22720 </field> 22721 </fields> 22722 </register> 22723 <register> 22724 <name>PRESET</name> 22725 <description>Preset register.</description> 22726 <addressOffset>0x18</addressOffset> 22727 <fields> 22728 <field> 22729 <name>PRESET</name> 22730 <description>Preset Value.</description> 22731 <bitOffset>0</bitOffset> 22732 <bitWidth>32</bitWidth> 22733 </field> 22734 </fields> 22735 </register> 22736 <register> 22737 <name>RELOAD</name> 22738 <description>Reload register.</description> 22739 <addressOffset>0x1C</addressOffset> 22740 <fields> 22741 <field> 22742 <name>RELOAD</name> 22743 <description>Reload Value.</description> 22744 <bitOffset>0</bitOffset> 22745 <bitWidth>32</bitWidth> 22746 </field> 22747 </fields> 22748 </register> 22749 <register> 22750 <name>SNAPSHOT</name> 22751 <description>Snapshot register.</description> 22752 <addressOffset>0x20</addressOffset> 22753 <fields> 22754 <field> 22755 <name>SNAPSHOT</name> 22756 <description>Snapshot Value.</description> 22757 <bitOffset>0</bitOffset> 22758 <bitWidth>32</bitWidth> 22759 </field> 22760 </fields> 22761 </register> 22762 </registers> 22763 </peripheral> 22764<!--WUT Wake Up Timer--> 22765 <peripheral derivedFrom="WUT"> 22766 <name>WUT1</name> 22767 <description>Wake Up Timer 1</description> 22768 <baseAddress>0x40006600</baseAddress> 22769 <interrupt> 22770 <name>WUT1</name> 22771 <description>WUT1 IRQ</description> 22772 <value>109</value> 22773 </interrupt> 22774 </peripheral> 22775<!--WUT1 Wake Up Timer 1--> 22776 </peripherals> 22777</device> 22778
