1 /** 2 * @file lpgcr_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the LPGCR Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup lpgcr_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_LPGCR_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_LPGCR_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup lpgcr 67 * @defgroup lpgcr_registers LPGCR_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the LPGCR Peripheral Module. 69 * @details Low Power Global Control. 70 */ 71 72 /** 73 * @ingroup lpgcr_registers 74 * Structure type to access the LPGCR Registers. 75 */ 76 typedef struct { 77 __R uint32_t rsv_0x0_0x7[2]; 78 __IO uint32_t rst; /**< <tt>\b 0x08:</tt> LPGCR RST Register */ 79 __IO uint32_t pclkdis; /**< <tt>\b 0x0C:</tt> LPGCR PCLKDIS Register */ 80 } mxc_lpgcr_regs_t; 81 82 /* Register offsets for module LPGCR */ 83 /** 84 * @ingroup lpgcr_registers 85 * @defgroup LPGCR_Register_Offsets Register Offsets 86 * @brief LPGCR Peripheral Register Offsets from the LPGCR Base Peripheral Address. 87 * @{ 88 */ 89 #define MXC_R_LPGCR_RST ((uint32_t)0x00000008UL) /**< Offset from LPGCR Base Address: <tt> 0x0008</tt> */ 90 #define MXC_R_LPGCR_PCLKDIS ((uint32_t)0x0000000CUL) /**< Offset from LPGCR Base Address: <tt> 0x000C</tt> */ 91 /**@} end of group lpgcr_registers */ 92 93 /** 94 * @ingroup lpgcr_registers 95 * @defgroup LPGCR_RST LPGCR_RST 96 * @brief Low Power Reset Register. 97 * @{ 98 */ 99 #define MXC_F_LPGCR_RST_GPIO3_POS 0 /**< RST_GPIO3 Position */ 100 #define MXC_F_LPGCR_RST_GPIO3 ((uint32_t)(0x1UL << MXC_F_LPGCR_RST_GPIO3_POS)) /**< RST_GPIO3 Mask */ 101 102 #define MXC_F_LPGCR_RST_WDT1_POS 1 /**< RST_WDT1 Position */ 103 #define MXC_F_LPGCR_RST_WDT1 ((uint32_t)(0x1UL << MXC_F_LPGCR_RST_WDT1_POS)) /**< RST_WDT1 Mask */ 104 105 #define MXC_F_LPGCR_RST_TMR4_POS 2 /**< RST_TMR4 Position */ 106 #define MXC_F_LPGCR_RST_TMR4 ((uint32_t)(0x1UL << MXC_F_LPGCR_RST_TMR4_POS)) /**< RST_TMR4 Mask */ 107 108 #define MXC_F_LPGCR_RST_TMR5_POS 3 /**< RST_TMR5 Position */ 109 #define MXC_F_LPGCR_RST_TMR5 ((uint32_t)(0x1UL << MXC_F_LPGCR_RST_TMR5_POS)) /**< RST_TMR5 Mask */ 110 111 #define MXC_F_LPGCR_RST_UART3_POS 4 /**< RST_UART3 Position */ 112 #define MXC_F_LPGCR_RST_UART3 ((uint32_t)(0x1UL << MXC_F_LPGCR_RST_UART3_POS)) /**< RST_UART3 Mask */ 113 114 #define MXC_F_LPGCR_RST_LPCOMP_POS 6 /**< RST_LPCOMP Position */ 115 #define MXC_F_LPGCR_RST_LPCOMP ((uint32_t)(0x1UL << MXC_F_LPGCR_RST_LPCOMP_POS)) /**< RST_LPCOMP Mask */ 116 117 /**@} end of group LPGCR_RST_Register */ 118 119 /** 120 * @ingroup lpgcr_registers 121 * @defgroup LPGCR_PCLKDIS LPGCR_PCLKDIS 122 * @brief Low Power Peripheral Clock Disable Register. 123 * @{ 124 */ 125 #define MXC_F_LPGCR_PCLKDIS_GPIO3_POS 0 /**< PCLKDIS_GPIO3 Position */ 126 #define MXC_F_LPGCR_PCLKDIS_GPIO3 ((uint32_t)(0x1UL << MXC_F_LPGCR_PCLKDIS_GPIO3_POS)) /**< PCLKDIS_GPIO3 Mask */ 127 128 #define MXC_F_LPGCR_PCLKDIS_WDT1_POS 1 /**< PCLKDIS_WDT1 Position */ 129 #define MXC_F_LPGCR_PCLKDIS_WDT1 ((uint32_t)(0x1UL << MXC_F_LPGCR_PCLKDIS_WDT1_POS)) /**< PCLKDIS_WDT1 Mask */ 130 131 #define MXC_F_LPGCR_PCLKDIS_TMR4_POS 2 /**< PCLKDIS_TMR4 Position */ 132 #define MXC_F_LPGCR_PCLKDIS_TMR4 ((uint32_t)(0x1UL << MXC_F_LPGCR_PCLKDIS_TMR4_POS)) /**< PCLKDIS_TMR4 Mask */ 133 134 #define MXC_F_LPGCR_PCLKDIS_TMR5_POS 3 /**< PCLKDIS_TMR5 Position */ 135 #define MXC_F_LPGCR_PCLKDIS_TMR5 ((uint32_t)(0x1UL << MXC_F_LPGCR_PCLKDIS_TMR5_POS)) /**< PCLKDIS_TMR5 Mask */ 136 137 #define MXC_F_LPGCR_PCLKDIS_UART3_POS 4 /**< PCLKDIS_UART3 Position */ 138 #define MXC_F_LPGCR_PCLKDIS_UART3 ((uint32_t)(0x1UL << MXC_F_LPGCR_PCLKDIS_UART3_POS)) /**< PCLKDIS_UART3 Mask */ 139 140 #define MXC_F_LPGCR_PCLKDIS_LPCOMP_POS 6 /**< PCLKDIS_LPCOMP Position */ 141 #define MXC_F_LPGCR_PCLKDIS_LPCOMP ((uint32_t)(0x1UL << MXC_F_LPGCR_PCLKDIS_LPCOMP_POS)) /**< PCLKDIS_LPCOMP Mask */ 142 143 /**@} end of group LPGCR_PCLKDIS_Register */ 144 145 #ifdef __cplusplus 146 } 147 #endif 148 149 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_LPGCR_REGS_H_ 150
