1 /** 2 * @file hpb_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the HPB Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup hpb_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_HPB_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_HPB_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup hpb 67 * @defgroup hpb_registers HPB_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the HPB Peripheral Module. 69 * @details HyperBus Memory Controller Registers 70 */ 71 72 /** 73 * @ingroup hpb_registers 74 * Structure type to access the HPB Registers. 75 */ 76 typedef struct { 77 __IO uint32_t stat; /**< <tt>\b 0x0000:</tt> HPB STAT Register */ 78 __IO uint32_t inten; /**< <tt>\b 0x0004:</tt> HPB INTEN Register */ 79 __IO uint32_t intfl; /**< <tt>\b 0x0008:</tt> HPB INTFL Register */ 80 __R uint32_t rsv_0xc; 81 __IO uint32_t membaddr[2]; /**< <tt>\b 0x0010:</tt> HPB MEMBADDR Register */ 82 __R uint32_t rsv_0x18_0x1f[2]; 83 __IO uint32_t memctrl[2]; /**< <tt>\b 0x0020:</tt> HPB MEMCTRL Register */ 84 __R uint32_t rsv_0x28_0x2f[2]; 85 __IO uint32_t memtim[2]; /**< <tt>\b 0x0030:</tt> HPB MEMTIM Register */ 86 } mxc_hpb_regs_t; 87 88 /* Register offsets for module HPB */ 89 /** 90 * @ingroup hpb_registers 91 * @defgroup HPB_Register_Offsets Register Offsets 92 * @brief HPB Peripheral Register Offsets from the HPB Base Peripheral Address. 93 * @{ 94 */ 95 #define MXC_R_HPB_STAT ((uint32_t)0x00000000UL) /**< Offset from HPB Base Address: <tt> 0x0000</tt> */ 96 #define MXC_R_HPB_INTEN ((uint32_t)0x00000004UL) /**< Offset from HPB Base Address: <tt> 0x0004</tt> */ 97 #define MXC_R_HPB_INTFL ((uint32_t)0x00000008UL) /**< Offset from HPB Base Address: <tt> 0x0008</tt> */ 98 #define MXC_R_HPB_MEMBADDR ((uint32_t)0x00000010UL) /**< Offset from HPB Base Address: <tt> 0x0010</tt> */ 99 #define MXC_R_HPB_MEMCTRL ((uint32_t)0x00000020UL) /**< Offset from HPB Base Address: <tt> 0x0020</tt> */ 100 #define MXC_R_HPB_MEMTIM ((uint32_t)0x00000030UL) /**< Offset from HPB Base Address: <tt> 0x0030</tt> */ 101 /**@} end of group hpb_registers */ 102 103 /** 104 * @ingroup hpb_registers 105 * @defgroup HPB_STAT HPB_STAT 106 * @brief Hyperbus Status Register. 107 * @{ 108 */ 109 #define MXC_F_HPB_STAT_RDTXN_POS 0 /**< STAT_RDTXN Position */ 110 #define MXC_F_HPB_STAT_RDTXN ((uint32_t)(0x1UL << MXC_F_HPB_STAT_RDTXN_POS)) /**< STAT_RDTXN Mask */ 111 112 #define MXC_F_HPB_STAT_RDADDRERR_POS 8 /**< STAT_RDADDRERR Position */ 113 #define MXC_F_HPB_STAT_RDADDRERR ((uint32_t)(0x1UL << MXC_F_HPB_STAT_RDADDRERR_POS)) /**< STAT_RDADDRERR Mask */ 114 115 #define MXC_F_HPB_STAT_RDSLVST_POS 9 /**< STAT_RDSLVST Position */ 116 #define MXC_F_HPB_STAT_RDSLVST ((uint32_t)(0x1UL << MXC_F_HPB_STAT_RDSLVST_POS)) /**< STAT_RDSLVST Mask */ 117 118 #define MXC_F_HPB_STAT_RDRSTERR_POS 10 /**< STAT_RDRSTERR Position */ 119 #define MXC_F_HPB_STAT_RDRSTERR ((uint32_t)(0x1UL << MXC_F_HPB_STAT_RDRSTERR_POS)) /**< STAT_RDRSTERR Mask */ 120 121 #define MXC_F_HPB_STAT_RDSTALL_POS 11 /**< STAT_RDSTALL Position */ 122 #define MXC_F_HPB_STAT_RDSTALL ((uint32_t)(0x1UL << MXC_F_HPB_STAT_RDSTALL_POS)) /**< STAT_RDSTALL Mask */ 123 124 #define MXC_F_HPB_STAT_WRTXN_POS 16 /**< STAT_WRTXN Position */ 125 #define MXC_F_HPB_STAT_WRTXN ((uint32_t)(0x1UL << MXC_F_HPB_STAT_WRTXN_POS)) /**< STAT_WRTXN Mask */ 126 127 #define MXC_F_HPB_STAT_WRADDRERR_POS 24 /**< STAT_WRADDRERR Position */ 128 #define MXC_F_HPB_STAT_WRADDRERR ((uint32_t)(0x1UL << MXC_F_HPB_STAT_WRADDRERR_POS)) /**< STAT_WRADDRERR Mask */ 129 130 #define MXC_F_HPB_STAT_WRRSTERR_POS 26 /**< STAT_WRRSTERR Position */ 131 #define MXC_F_HPB_STAT_WRRSTERR ((uint32_t)(0x1UL << MXC_F_HPB_STAT_WRRSTERR_POS)) /**< STAT_WRRSTERR Mask */ 132 133 /**@} end of group HPB_STAT_Register */ 134 135 /** 136 * @ingroup hpb_registers 137 * @defgroup HPB_INTEN HPB_INTEN 138 * @brief Hyperbus Interrupt Enable Register. 139 * @{ 140 */ 141 #define MXC_F_HPB_INTEN_MEM_POS 0 /**< INTEN_MEM Position */ 142 #define MXC_F_HPB_INTEN_MEM ((uint32_t)(0x1UL << MXC_F_HPB_INTEN_MEM_POS)) /**< INTEN_MEM Mask */ 143 144 #define MXC_F_HPB_INTEN_ERR_POS 1 /**< INTEN_ERR Position */ 145 #define MXC_F_HPB_INTEN_ERR ((uint32_t)(0x1UL << MXC_F_HPB_INTEN_ERR_POS)) /**< INTEN_ERR Mask */ 146 147 /**@} end of group HPB_INTEN_Register */ 148 149 /** 150 * @ingroup hpb_registers 151 * @defgroup HPB_INTFL HPB_INTFL 152 * @brief Hyperbus Interrupt Flag Register. 153 * @{ 154 */ 155 #define MXC_F_HPB_INTFL_MEM_POS 0 /**< INTFL_MEM Position */ 156 #define MXC_F_HPB_INTFL_MEM ((uint32_t)(0x1UL << MXC_F_HPB_INTFL_MEM_POS)) /**< INTFL_MEM Mask */ 157 158 #define MXC_F_HPB_INTFL_ERR_POS 1 /**< INTFL_ERR Position */ 159 #define MXC_F_HPB_INTFL_ERR ((uint32_t)(0x1UL << MXC_F_HPB_INTFL_ERR_POS)) /**< INTFL_ERR Mask */ 160 161 /**@} end of group HPB_INTFL_Register */ 162 163 /** 164 * @ingroup hpb_registers 165 * @defgroup HPB_MEMBADDR HPB_MEMBADDR 166 * @brief Hyperbus Memory Base Address Register. 167 * @{ 168 */ 169 #define MXC_F_HPB_MEMBADDR_ADDR_POS 0 /**< MEMBADDR_ADDR Position */ 170 #define MXC_F_HPB_MEMBADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_HPB_MEMBADDR_ADDR_POS)) /**< MEMBADDR_ADDR Mask */ 171 172 /**@} end of group HPB_MEMBADDR_Register */ 173 174 /** 175 * @ingroup hpb_registers 176 * @defgroup HPB_MEMCTRL HPB_MEMCTRL 177 * @brief Hyperbus Memory Control Register. 178 * @{ 179 */ 180 #define MXC_F_HPB_MEMCTRL_WRAPSIZE_POS 0 /**< MEMCTRL_WRAPSIZE Position */ 181 #define MXC_F_HPB_MEMCTRL_WRAPSIZE ((uint32_t)(0x3UL << MXC_F_HPB_MEMCTRL_WRAPSIZE_POS)) /**< MEMCTRL_WRAPSIZE Mask */ 182 #define MXC_V_HPB_MEMCTRL_WRAPSIZE_64B ((uint32_t)0x1UL) /**< MEMCTRL_WRAPSIZE_64B Value */ 183 #define MXC_S_HPB_MEMCTRL_WRAPSIZE_64B (MXC_V_HPB_MEMCTRL_WRAPSIZE_64B << MXC_F_HPB_MEMCTRL_WRAPSIZE_POS) /**< MEMCTRL_WRAPSIZE_64B Setting */ 184 #define MXC_V_HPB_MEMCTRL_WRAPSIZE_16B ((uint32_t)0x2UL) /**< MEMCTRL_WRAPSIZE_16B Value */ 185 #define MXC_S_HPB_MEMCTRL_WRAPSIZE_16B (MXC_V_HPB_MEMCTRL_WRAPSIZE_16B << MXC_F_HPB_MEMCTRL_WRAPSIZE_POS) /**< MEMCTRL_WRAPSIZE_16B Setting */ 186 #define MXC_V_HPB_MEMCTRL_WRAPSIZE_32B ((uint32_t)0x3UL) /**< MEMCTRL_WRAPSIZE_32B Value */ 187 #define MXC_S_HPB_MEMCTRL_WRAPSIZE_32B (MXC_V_HPB_MEMCTRL_WRAPSIZE_32B << MXC_F_HPB_MEMCTRL_WRAPSIZE_POS) /**< MEMCTRL_WRAPSIZE_32B Setting */ 188 189 #define MXC_F_HPB_MEMCTRL_DEVTYPE_POS 3 /**< MEMCTRL_DEVTYPE Position */ 190 #define MXC_F_HPB_MEMCTRL_DEVTYPE ((uint32_t)(0x3UL << MXC_F_HPB_MEMCTRL_DEVTYPE_POS)) /**< MEMCTRL_DEVTYPE Mask */ 191 #define MXC_V_HPB_MEMCTRL_DEVTYPE_HYPERFLASH ((uint32_t)0x0UL) /**< MEMCTRL_DEVTYPE_HYPERFLASH Value */ 192 #define MXC_S_HPB_MEMCTRL_DEVTYPE_HYPERFLASH (MXC_V_HPB_MEMCTRL_DEVTYPE_HYPERFLASH << MXC_F_HPB_MEMCTRL_DEVTYPE_POS) /**< MEMCTRL_DEVTYPE_HYPERFLASH Setting */ 193 #define MXC_V_HPB_MEMCTRL_DEVTYPE_XCCELA_PSRAM ((uint32_t)0x1UL) /**< MEMCTRL_DEVTYPE_XCCELA_PSRAM Value */ 194 #define MXC_S_HPB_MEMCTRL_DEVTYPE_XCCELA_PSRAM (MXC_V_HPB_MEMCTRL_DEVTYPE_XCCELA_PSRAM << MXC_F_HPB_MEMCTRL_DEVTYPE_POS) /**< MEMCTRL_DEVTYPE_XCCELA_PSRAM Setting */ 195 #define MXC_V_HPB_MEMCTRL_DEVTYPE_HYPERRAM ((uint32_t)0x2UL) /**< MEMCTRL_DEVTYPE_HYPERRAM Value */ 196 #define MXC_S_HPB_MEMCTRL_DEVTYPE_HYPERRAM (MXC_V_HPB_MEMCTRL_DEVTYPE_HYPERRAM << MXC_F_HPB_MEMCTRL_DEVTYPE_POS) /**< MEMCTRL_DEVTYPE_HYPERRAM Setting */ 197 198 #define MXC_F_HPB_MEMCTRL_CRT_POS 5 /**< MEMCTRL_CRT Position */ 199 #define MXC_F_HPB_MEMCTRL_CRT ((uint32_t)(0x1UL << MXC_F_HPB_MEMCTRL_CRT_POS)) /**< MEMCTRL_CRT Mask */ 200 201 #define MXC_F_HPB_MEMCTRL_RDLAT_EN_POS 6 /**< MEMCTRL_RDLAT_EN Position */ 202 #define MXC_F_HPB_MEMCTRL_RDLAT_EN ((uint32_t)(0x1UL << MXC_F_HPB_MEMCTRL_RDLAT_EN_POS)) /**< MEMCTRL_RDLAT_EN Mask */ 203 204 #define MXC_F_HPB_MEMCTRL_HSE_POS 7 /**< MEMCTRL_HSE Position */ 205 #define MXC_F_HPB_MEMCTRL_HSE ((uint32_t)(0x1UL << MXC_F_HPB_MEMCTRL_HSE_POS)) /**< MEMCTRL_HSE Mask */ 206 207 #define MXC_F_HPB_MEMCTRL_MAXLEN_POS 18 /**< MEMCTRL_MAXLEN Position */ 208 #define MXC_F_HPB_MEMCTRL_MAXLEN ((uint32_t)(0x1FFUL << MXC_F_HPB_MEMCTRL_MAXLEN_POS)) /**< MEMCTRL_MAXLEN Mask */ 209 210 #define MXC_F_HPB_MEMCTRL_MAX_EN_POS 31 /**< MEMCTRL_MAX_EN Position */ 211 #define MXC_F_HPB_MEMCTRL_MAX_EN ((uint32_t)(0x1UL << MXC_F_HPB_MEMCTRL_MAX_EN_POS)) /**< MEMCTRL_MAX_EN Mask */ 212 213 /**@} end of group HPB_MEMCTRL_Register */ 214 215 /** 216 * @ingroup hpb_registers 217 * @defgroup HPB_MEMTIM HPB_MEMTIM 218 * @brief Hyperbus Memory Timing Register. 219 * @{ 220 */ 221 #define MXC_F_HPB_MEMTIM_LAT_POS 0 /**< MEMTIM_LAT Position */ 222 #define MXC_F_HPB_MEMTIM_LAT ((uint32_t)(0xFUL << MXC_F_HPB_MEMTIM_LAT_POS)) /**< MEMTIM_LAT Mask */ 223 #define MXC_V_HPB_MEMTIM_LAT_5CLK ((uint32_t)0x0UL) /**< MEMTIM_LAT_5CLK Value */ 224 #define MXC_S_HPB_MEMTIM_LAT_5CLK (MXC_V_HPB_MEMTIM_LAT_5CLK << MXC_F_HPB_MEMTIM_LAT_POS) /**< MEMTIM_LAT_5CLK Setting */ 225 #define MXC_V_HPB_MEMTIM_LAT_6CLK ((uint32_t)0x1UL) /**< MEMTIM_LAT_6CLK Value */ 226 #define MXC_S_HPB_MEMTIM_LAT_6CLK (MXC_V_HPB_MEMTIM_LAT_6CLK << MXC_F_HPB_MEMTIM_LAT_POS) /**< MEMTIM_LAT_6CLK Setting */ 227 #define MXC_V_HPB_MEMTIM_LAT_3CLK ((uint32_t)0xEUL) /**< MEMTIM_LAT_3CLK Value */ 228 #define MXC_S_HPB_MEMTIM_LAT_3CLK (MXC_V_HPB_MEMTIM_LAT_3CLK << MXC_F_HPB_MEMTIM_LAT_POS) /**< MEMTIM_LAT_3CLK Setting */ 229 #define MXC_V_HPB_MEMTIM_LAT_4CLK ((uint32_t)0xFUL) /**< MEMTIM_LAT_4CLK Value */ 230 #define MXC_S_HPB_MEMTIM_LAT_4CLK (MXC_V_HPB_MEMTIM_LAT_4CLK << MXC_F_HPB_MEMTIM_LAT_POS) /**< MEMTIM_LAT_4CLK Setting */ 231 232 #define MXC_F_HPB_MEMTIM_WRCSHD_POS 8 /**< MEMTIM_WRCSHD Position */ 233 #define MXC_F_HPB_MEMTIM_WRCSHD ((uint32_t)(0xFUL << MXC_F_HPB_MEMTIM_WRCSHD_POS)) /**< MEMTIM_WRCSHD Mask */ 234 235 #define MXC_F_HPB_MEMTIM_RDCSHD_POS 12 /**< MEMTIM_RDCSHD Position */ 236 #define MXC_F_HPB_MEMTIM_RDCSHD ((uint32_t)(0xFUL << MXC_F_HPB_MEMTIM_RDCSHD_POS)) /**< MEMTIM_RDCSHD Mask */ 237 238 #define MXC_F_HPB_MEMTIM_WRCSST_POS 16 /**< MEMTIM_WRCSST Position */ 239 #define MXC_F_HPB_MEMTIM_WRCSST ((uint32_t)(0xFUL << MXC_F_HPB_MEMTIM_WRCSST_POS)) /**< MEMTIM_WRCSST Mask */ 240 241 #define MXC_F_HPB_MEMTIM_RDCSST_POS 20 /**< MEMTIM_RDCSST Position */ 242 #define MXC_F_HPB_MEMTIM_RDCSST ((uint32_t)(0xFUL << MXC_F_HPB_MEMTIM_RDCSST_POS)) /**< MEMTIM_RDCSST Mask */ 243 244 #define MXC_F_HPB_MEMTIM_WRCSHI_POS 24 /**< MEMTIM_WRCSHI Position */ 245 #define MXC_F_HPB_MEMTIM_WRCSHI ((uint32_t)(0xFUL << MXC_F_HPB_MEMTIM_WRCSHI_POS)) /**< MEMTIM_WRCSHI Mask */ 246 247 #define MXC_F_HPB_MEMTIM_RDCSHI_POS 28 /**< MEMTIM_RDCSHI Position */ 248 #define MXC_F_HPB_MEMTIM_RDCSHI ((uint32_t)(0xFUL << MXC_F_HPB_MEMTIM_RDCSHI_POS)) /**< MEMTIM_RDCSHI Mask */ 249 250 /**@} end of group HPB_MEMTIM_Register */ 251 252 #ifdef __cplusplus 253 } 254 #endif 255 256 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_HPB_REGS_H_ 257
