1 /** 2 * @file fcr_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the FCR Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup fcr_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_FCR_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_FCR_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup fcr 67 * @defgroup fcr_registers FCR_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the FCR Peripheral Module. 69 * @details Function Control Register. 70 */ 71 72 /** 73 * @ingroup fcr_registers 74 * Structure type to access the FCR Registers. 75 */ 76 typedef struct { 77 __IO uint32_t fctrl0; /**< <tt>\b 0x00:</tt> FCR FCTRL0 Register */ 78 __IO uint32_t autocal0; /**< <tt>\b 0x04:</tt> FCR AUTOCAL0 Register */ 79 __IO uint32_t autocal1; /**< <tt>\b 0x08:</tt> FCR AUTOCAL1 Register */ 80 __IO uint32_t autocal2; /**< <tt>\b 0x0C:</tt> FCR AUTOCAL2 Register */ 81 __IO uint32_t urvbootaddr; /**< <tt>\b 0x10:</tt> FCR URVBOOTADDR Register */ 82 __IO uint32_t urvctrl; /**< <tt>\b 0x14:</tt> FCR URVCTRL Register */ 83 __IO uint32_t xo32mks; /**< <tt>\b 0x18:</tt> FCR XO32MKS Register */ 84 __IO uint32_t sarbufcn; /**< <tt>\b 0x1C:</tt> FCR SARBUFCN Register */ 85 __IO uint32_t ts0; /**< <tt>\b 0x20:</tt> FCR TS0 Register */ 86 __IO uint32_t ts1; /**< <tt>\b 0x24:</tt> FCR TS1 Register */ 87 __IO uint32_t adcreftrim0; /**< <tt>\b 0x28:</tt> FCR ADCREFTRIM0 Register */ 88 __IO uint32_t adcreftrim1; /**< <tt>\b 0x2C:</tt> FCR ADCREFTRIM1 Register */ 89 __IO uint32_t adcreftrim2; /**< <tt>\b 0x30:</tt> FCR ADCREFTRIM2 Register */ 90 } mxc_fcr_regs_t; 91 92 /* Register offsets for module FCR */ 93 /** 94 * @ingroup fcr_registers 95 * @defgroup FCR_Register_Offsets Register Offsets 96 * @brief FCR Peripheral Register Offsets from the FCR Base Peripheral Address. 97 * @{ 98 */ 99 #define MXC_R_FCR_FCTRL0 ((uint32_t)0x00000000UL) /**< Offset from FCR Base Address: <tt> 0x0000</tt> */ 100 #define MXC_R_FCR_AUTOCAL0 ((uint32_t)0x00000004UL) /**< Offset from FCR Base Address: <tt> 0x0004</tt> */ 101 #define MXC_R_FCR_AUTOCAL1 ((uint32_t)0x00000008UL) /**< Offset from FCR Base Address: <tt> 0x0008</tt> */ 102 #define MXC_R_FCR_AUTOCAL2 ((uint32_t)0x0000000CUL) /**< Offset from FCR Base Address: <tt> 0x000C</tt> */ 103 #define MXC_R_FCR_URVBOOTADDR ((uint32_t)0x00000010UL) /**< Offset from FCR Base Address: <tt> 0x0010</tt> */ 104 #define MXC_R_FCR_URVCTRL ((uint32_t)0x00000014UL) /**< Offset from FCR Base Address: <tt> 0x0014</tt> */ 105 #define MXC_R_FCR_XO32MKS ((uint32_t)0x00000018UL) /**< Offset from FCR Base Address: <tt> 0x0018</tt> */ 106 #define MXC_R_FCR_SARBUFCN ((uint32_t)0x0000001CUL) /**< Offset from FCR Base Address: <tt> 0x001C</tt> */ 107 #define MXC_R_FCR_TS0 ((uint32_t)0x00000020UL) /**< Offset from FCR Base Address: <tt> 0x0020</tt> */ 108 #define MXC_R_FCR_TS1 ((uint32_t)0x00000024UL) /**< Offset from FCR Base Address: <tt> 0x0024</tt> */ 109 #define MXC_R_FCR_ADCREFTRIM0 ((uint32_t)0x00000028UL) /**< Offset from FCR Base Address: <tt> 0x0028</tt> */ 110 #define MXC_R_FCR_ADCREFTRIM1 ((uint32_t)0x0000002CUL) /**< Offset from FCR Base Address: <tt> 0x002C</tt> */ 111 #define MXC_R_FCR_ADCREFTRIM2 ((uint32_t)0x00000030UL) /**< Offset from FCR Base Address: <tt> 0x0030</tt> */ 112 /**@} end of group fcr_registers */ 113 114 /** 115 * @ingroup fcr_registers 116 * @defgroup FCR_FCTRL0 FCR_FCTRL0 117 * @brief Function Control 0. 118 * @{ 119 */ 120 #define MXC_F_FCR_FCTRL0_RDSGCSEL_POS 0 /**< FCTRL0_RDSGCSEL Position */ 121 #define MXC_F_FCR_FCTRL0_RDSGCSEL ((uint32_t)(0x3FUL << MXC_F_FCR_FCTRL0_RDSGCSEL_POS)) /**< FCTRL0_RDSGCSEL Mask */ 122 123 #define MXC_F_FCR_FCTRL0_RDSGCSET_POS 6 /**< FCTRL0_RDSGCSET Position */ 124 #define MXC_F_FCR_FCTRL0_RDSGCSET ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_RDSGCSET_POS)) /**< FCTRL0_RDSGCSET Mask */ 125 126 #define MXC_F_FCR_FCTRL0_HYPERCGDLY_POS 8 /**< FCTRL0_HYPERCGDLY Position */ 127 #define MXC_F_FCR_FCTRL0_HYPERCGDLY ((uint32_t)(0x3FUL << MXC_F_FCR_FCTRL0_HYPERCGDLY_POS)) /**< FCTRL0_HYPERCGDLY Mask */ 128 129 #define MXC_F_FCR_FCTRL0_USBCLKSEL_POS 16 /**< FCTRL0_USBCLKSEL Position */ 130 #define MXC_F_FCR_FCTRL0_USBCLKSEL ((uint32_t)(0x3UL << MXC_F_FCR_FCTRL0_USBCLKSEL_POS)) /**< FCTRL0_USBCLKSEL Mask */ 131 132 #define MXC_F_FCR_FCTRL0_I2C0DGEN0_POS 20 /**< FCTRL0_I2C0DGEN0 Position */ 133 #define MXC_F_FCR_FCTRL0_I2C0DGEN0 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0DGEN0_POS)) /**< FCTRL0_I2C0DGEN0 Mask */ 134 135 #define MXC_F_FCR_FCTRL0_I2C0DGEN1_POS 21 /**< FCTRL0_I2C0DGEN1 Position */ 136 #define MXC_F_FCR_FCTRL0_I2C0DGEN1 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0DGEN1_POS)) /**< FCTRL0_I2C0DGEN1 Mask */ 137 138 #define MXC_F_FCR_FCTRL0_I2C1DGEN0_POS 22 /**< FCTRL0_I2C1DGEN0 Position */ 139 #define MXC_F_FCR_FCTRL0_I2C1DGEN0 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1DGEN0_POS)) /**< FCTRL0_I2C1DGEN0 Mask */ 140 141 #define MXC_F_FCR_FCTRL0_I2C1DGEN1_POS 23 /**< FCTRL0_I2C1DGEN1 Position */ 142 #define MXC_F_FCR_FCTRL0_I2C1DGEN1 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1DGEN1_POS)) /**< FCTRL0_I2C1DGEN1 Mask */ 143 144 #define MXC_F_FCR_FCTRL0_I2C2DGEN0_POS 24 /**< FCTRL0_I2C2DGEN0 Position */ 145 #define MXC_F_FCR_FCTRL0_I2C2DGEN0 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2DGEN0_POS)) /**< FCTRL0_I2C2DGEN0 Mask */ 146 147 #define MXC_F_FCR_FCTRL0_I2C2DGEN1_POS 25 /**< FCTRL0_I2C2DGEN1 Position */ 148 #define MXC_F_FCR_FCTRL0_I2C2DGEN1 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2DGEN1_POS)) /**< FCTRL0_I2C2DGEN1 Mask */ 149 150 /**@} end of group FCR_FCTRL0_Register */ 151 152 /** 153 * @ingroup fcr_registers 154 * @defgroup FCR_AUTOCAL0 FCR_AUTOCAL0 155 * @brief Automatic Calibration 0. 156 * @{ 157 */ 158 #define MXC_F_FCR_AUTOCAL0_ACEN_POS 0 /**< AUTOCAL0_ACEN Position */ 159 #define MXC_F_FCR_AUTOCAL0_ACEN ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_ACEN_POS)) /**< AUTOCAL0_ACEN Mask */ 160 161 #define MXC_F_FCR_AUTOCAL0_ACRUN_POS 1 /**< AUTOCAL0_ACRUN Position */ 162 #define MXC_F_FCR_AUTOCAL0_ACRUN ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_ACRUN_POS)) /**< AUTOCAL0_ACRUN Mask */ 163 164 #define MXC_F_FCR_AUTOCAL0_LDTRM_POS 2 /**< AUTOCAL0_LDTRM Position */ 165 #define MXC_F_FCR_AUTOCAL0_LDTRM ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_LDTRM_POS)) /**< AUTOCAL0_LDTRM Mask */ 166 167 #define MXC_F_FCR_AUTOCAL0_GAININV_POS 3 /**< AUTOCAL0_GAININV Position */ 168 #define MXC_F_FCR_AUTOCAL0_GAININV ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_GAININV_POS)) /**< AUTOCAL0_GAININV Mask */ 169 170 #define MXC_F_FCR_AUTOCAL0_ATOMIC_POS 4 /**< AUTOCAL0_ATOMIC Position */ 171 #define MXC_F_FCR_AUTOCAL0_ATOMIC ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_ATOMIC_POS)) /**< AUTOCAL0_ATOMIC Mask */ 172 173 #define MXC_F_FCR_AUTOCAL0_MU_POS 8 /**< AUTOCAL0_MU Position */ 174 #define MXC_F_FCR_AUTOCAL0_MU ((uint32_t)(0xFFFUL << MXC_F_FCR_AUTOCAL0_MU_POS)) /**< AUTOCAL0_MU Mask */ 175 176 #define MXC_F_FCR_AUTOCAL0_HIRC96MACTMROUT_POS 23 /**< AUTOCAL0_HIRC96MACTMROUT Position */ 177 #define MXC_F_FCR_AUTOCAL0_HIRC96MACTMROUT ((uint32_t)(0x1FFUL << MXC_F_FCR_AUTOCAL0_HIRC96MACTMROUT_POS)) /**< AUTOCAL0_HIRC96MACTMROUT Mask */ 178 179 /**@} end of group FCR_AUTOCAL0_Register */ 180 181 /** 182 * @ingroup fcr_registers 183 * @defgroup FCR_AUTOCAL1 FCR_AUTOCAL1 184 * @brief Automatic Calibration 1. 185 * @{ 186 */ 187 #define MXC_F_FCR_AUTOCAL1_INITTRM_POS 0 /**< AUTOCAL1_INITTRM Position */ 188 #define MXC_F_FCR_AUTOCAL1_INITTRM ((uint32_t)(0x1FFUL << MXC_F_FCR_AUTOCAL1_INITTRM_POS)) /**< AUTOCAL1_INITTRM Mask */ 189 190 /**@} end of group FCR_AUTOCAL1_Register */ 191 192 /** 193 * @ingroup fcr_registers 194 * @defgroup FCR_AUTOCAL2 FCR_AUTOCAL2 195 * @brief Automatic Calibration 2 196 * @{ 197 */ 198 #define MXC_F_FCR_AUTOCAL2_DONECNT_POS 0 /**< AUTOCAL2_DONECNT Position */ 199 #define MXC_F_FCR_AUTOCAL2_DONECNT ((uint32_t)(0xFFUL << MXC_F_FCR_AUTOCAL2_DONECNT_POS)) /**< AUTOCAL2_DONECNT Mask */ 200 201 #define MXC_F_FCR_AUTOCAL2_ACDIV_POS 8 /**< AUTOCAL2_ACDIV Position */ 202 #define MXC_F_FCR_AUTOCAL2_ACDIV ((uint32_t)(0x1FFFUL << MXC_F_FCR_AUTOCAL2_ACDIV_POS)) /**< AUTOCAL2_ACDIV Mask */ 203 204 /**@} end of group FCR_AUTOCAL2_Register */ 205 206 /** 207 * @ingroup fcr_registers 208 * @defgroup FCR_URVCTRL FCR_URVCTRL 209 * @brief RISC-V Control Register. 210 * @{ 211 */ 212 #define MXC_F_FCR_URVCTRL_MEMSEL_POS 0 /**< URVCTRL_MEMSEL Position */ 213 #define MXC_F_FCR_URVCTRL_MEMSEL ((uint32_t)(0x1UL << MXC_F_FCR_URVCTRL_MEMSEL_POS)) /**< URVCTRL_MEMSEL Mask */ 214 215 #define MXC_F_FCR_URVCTRL_IFLUSHEN_POS 1 /**< URVCTRL_IFLUSHEN Position */ 216 #define MXC_F_FCR_URVCTRL_IFLUSHEN ((uint32_t)(0x1UL << MXC_F_FCR_URVCTRL_IFLUSHEN_POS)) /**< URVCTRL_IFLUSHEN Mask */ 217 218 /**@} end of group FCR_URVCTRL_Register */ 219 220 /** 221 * @ingroup fcr_registers 222 * @defgroup FCR_XO32MKS FCR_XO32MKS 223 * @brief RISC-V Control Register. 224 * @{ 225 */ 226 #define MXC_F_FCR_XO32MKS_CLK_POS 0 /**< XO32MKS_CLK Position */ 227 #define MXC_F_FCR_XO32MKS_CLK ((uint32_t)(0x7FUL << MXC_F_FCR_XO32MKS_CLK_POS)) /**< XO32MKS_CLK Mask */ 228 229 #define MXC_F_FCR_XO32MKS_EN_POS 7 /**< XO32MKS_EN Position */ 230 #define MXC_F_FCR_XO32MKS_EN ((uint32_t)(0x1UL << MXC_F_FCR_XO32MKS_EN_POS)) /**< XO32MKS_EN Mask */ 231 232 #define MXC_F_FCR_XO32MKS_DRIVER_POS 8 /**< XO32MKS_DRIVER Position */ 233 #define MXC_F_FCR_XO32MKS_DRIVER ((uint32_t)(0x7UL << MXC_F_FCR_XO32MKS_DRIVER_POS)) /**< XO32MKS_DRIVER Mask */ 234 235 #define MXC_F_FCR_XO32MKS_PULSE_POS 11 /**< XO32MKS_PULSE Position */ 236 #define MXC_F_FCR_XO32MKS_PULSE ((uint32_t)(0x1UL << MXC_F_FCR_XO32MKS_PULSE_POS)) /**< XO32MKS_PULSE Mask */ 237 238 #define MXC_F_FCR_XO32MKS_CLKSEL_POS 12 /**< XO32MKS_CLKSEL Position */ 239 #define MXC_F_FCR_XO32MKS_CLKSEL ((uint32_t)(0x3UL << MXC_F_FCR_XO32MKS_CLKSEL_POS)) /**< XO32MKS_CLKSEL Mask */ 240 #define MXC_V_FCR_XO32MKS_CLKSEL_NONE ((uint32_t)0x0UL) /**< XO32MKS_CLKSEL_NONE Value */ 241 #define MXC_S_FCR_XO32MKS_CLKSEL_NONE (MXC_V_FCR_XO32MKS_CLKSEL_NONE << MXC_F_FCR_XO32MKS_CLKSEL_POS) /**< XO32MKS_CLKSEL_NONE Setting */ 242 #define MXC_V_FCR_XO32MKS_CLKSEL_TEST ((uint32_t)0x1UL) /**< XO32MKS_CLKSEL_TEST Value */ 243 #define MXC_S_FCR_XO32MKS_CLKSEL_TEST (MXC_V_FCR_XO32MKS_CLKSEL_TEST << MXC_F_FCR_XO32MKS_CLKSEL_POS) /**< XO32MKS_CLKSEL_TEST Setting */ 244 #define MXC_V_FCR_XO32MKS_CLKSEL_ISO ((uint32_t)0x2UL) /**< XO32MKS_CLKSEL_ISO Value */ 245 #define MXC_S_FCR_XO32MKS_CLKSEL_ISO (MXC_V_FCR_XO32MKS_CLKSEL_ISO << MXC_F_FCR_XO32MKS_CLKSEL_POS) /**< XO32MKS_CLKSEL_ISO Setting */ 246 #define MXC_V_FCR_XO32MKS_CLKSEL_IPO ((uint32_t)0x3UL) /**< XO32MKS_CLKSEL_IPO Value */ 247 #define MXC_S_FCR_XO32MKS_CLKSEL_IPO (MXC_V_FCR_XO32MKS_CLKSEL_IPO << MXC_F_FCR_XO32MKS_CLKSEL_POS) /**< XO32MKS_CLKSEL_IPO Setting */ 248 249 /**@} end of group FCR_XO32MKS_Register */ 250 251 /** 252 * @ingroup fcr_registers 253 * @defgroup FCR_SARBUFCN FCR_SARBUFCN 254 * @brief TBD 255 * @{ 256 */ 257 #define MXC_F_FCR_SARBUFCN_THRU_PAD_SW_EN_POS 0 /**< SARBUFCN_THRU_PAD_SW_EN Position */ 258 #define MXC_F_FCR_SARBUFCN_THRU_PAD_SW_EN ((uint32_t)(0xFFUL << MXC_F_FCR_SARBUFCN_THRU_PAD_SW_EN_POS)) /**< SARBUFCN_THRU_PAD_SW_EN Mask */ 259 260 #define MXC_F_FCR_SARBUFCN_THRU_EN_POS 8 /**< SARBUFCN_THRU_EN Position */ 261 #define MXC_F_FCR_SARBUFCN_THRU_EN ((uint32_t)(0x1UL << MXC_F_FCR_SARBUFCN_THRU_EN_POS)) /**< SARBUFCN_THRU_EN Mask */ 262 263 #define MXC_F_FCR_SARBUFCN_RAMP_EN_POS 9 /**< SARBUFCN_RAMP_EN Position */ 264 #define MXC_F_FCR_SARBUFCN_RAMP_EN ((uint32_t)(0x1UL << MXC_F_FCR_SARBUFCN_RAMP_EN_POS)) /**< SARBUFCN_RAMP_EN Mask */ 265 266 #define MXC_F_FCR_SARBUFCN_THRU_RRI_EN_POS 10 /**< SARBUFCN_THRU_RRI_EN Position */ 267 #define MXC_F_FCR_SARBUFCN_THRU_RRI_EN ((uint32_t)(0x1UL << MXC_F_FCR_SARBUFCN_THRU_RRI_EN_POS)) /**< SARBUFCN_THRU_RRI_EN Mask */ 268 269 #define MXC_F_FCR_SARBUFCN_DIVSEL_POS 11 /**< SARBUFCN_DIVSEL Position */ 270 #define MXC_F_FCR_SARBUFCN_DIVSEL ((uint32_t)(0x1UL << MXC_F_FCR_SARBUFCN_DIVSEL_POS)) /**< SARBUFCN_DIVSEL Mask */ 271 272 /**@} end of group FCR_SARBUFCN_Register */ 273 274 /** 275 * @ingroup fcr_registers 276 * @defgroup FCR_TS0 FCR_TS0 277 * @brief Temp Sensor trim0 278 * @{ 279 */ 280 #define MXC_F_FCR_TS0_GAIN_POS 0 /**< TS0_GAIN Position */ 281 #define MXC_F_FCR_TS0_GAIN ((uint32_t)(0xFFFUL << MXC_F_FCR_TS0_GAIN_POS)) /**< TS0_GAIN Mask */ 282 283 /**@} end of group FCR_TS0_Register */ 284 285 /** 286 * @ingroup fcr_registers 287 * @defgroup FCR_TS1 FCR_TS1 288 * @brief Temp Sensor trim1 289 * @{ 290 */ 291 #define MXC_F_FCR_TS1_OFFSET_POS 0 /**< TS1_OFFSET Position */ 292 #define MXC_F_FCR_TS1_OFFSET ((uint32_t)(0x3FFFUL << MXC_F_FCR_TS1_OFFSET_POS)) /**< TS1_OFFSET Mask */ 293 294 #define MXC_F_FCR_TS1_TS_OFFSET_SIGN_POS 14 /**< TS1_TS_OFFSET_SIGN Position */ 295 #define MXC_F_FCR_TS1_TS_OFFSET_SIGN ((uint32_t)(0x3FFFFUL << MXC_F_FCR_TS1_TS_OFFSET_SIGN_POS)) /**< TS1_TS_OFFSET_SIGN Mask */ 296 297 /**@} end of group FCR_TS1_Register */ 298 299 /** 300 * @ingroup fcr_registers 301 * @defgroup FCR_ADCREFTRIM0 FCR_ADCREFTRIM0 302 * @brief Temp Sensor trim1 303 * @{ 304 */ 305 #define MXC_F_FCR_ADCREFTRIM0_VREFP_POS 0 /**< ADCREFTRIM0_VREFP Position */ 306 #define MXC_F_FCR_ADCREFTRIM0_VREFP ((uint32_t)(0x7FUL << MXC_F_FCR_ADCREFTRIM0_VREFP_POS)) /**< ADCREFTRIM0_VREFP Mask */ 307 308 #define MXC_F_FCR_ADCREFTRIM0_VREFM_POS 8 /**< ADCREFTRIM0_VREFM Position */ 309 #define MXC_F_FCR_ADCREFTRIM0_VREFM ((uint32_t)(0x7FUL << MXC_F_FCR_ADCREFTRIM0_VREFM_POS)) /**< ADCREFTRIM0_VREFM Mask */ 310 311 #define MXC_F_FCR_ADCREFTRIM0_VCM_POS 16 /**< ADCREFTRIM0_VCM Position */ 312 #define MXC_F_FCR_ADCREFTRIM0_VCM ((uint32_t)(0x3UL << MXC_F_FCR_ADCREFTRIM0_VCM_POS)) /**< ADCREFTRIM0_VCM Mask */ 313 314 #define MXC_F_FCR_ADCREFTRIM0_VX2_TUNE_POS 24 /**< ADCREFTRIM0_VX2_TUNE Position */ 315 #define MXC_F_FCR_ADCREFTRIM0_VX2_TUNE ((uint32_t)(0x3FUL << MXC_F_FCR_ADCREFTRIM0_VX2_TUNE_POS)) /**< ADCREFTRIM0_VX2_TUNE Mask */ 316 317 /**@} end of group FCR_ADCREFTRIM0_Register */ 318 319 /** 320 * @ingroup fcr_registers 321 * @defgroup FCR_ADCREFTRIM1 FCR_ADCREFTRIM1 322 * @brief Temp Sensor trim1 323 * @{ 324 */ 325 #define MXC_F_FCR_ADCREFTRIM1_VREFP_POS 0 /**< ADCREFTRIM1_VREFP Position */ 326 #define MXC_F_FCR_ADCREFTRIM1_VREFP ((uint32_t)(0x7FUL << MXC_F_FCR_ADCREFTRIM1_VREFP_POS)) /**< ADCREFTRIM1_VREFP Mask */ 327 328 #define MXC_F_FCR_ADCREFTRIM1_VREFM_POS 8 /**< ADCREFTRIM1_VREFM Position */ 329 #define MXC_F_FCR_ADCREFTRIM1_VREFM ((uint32_t)(0x7FUL << MXC_F_FCR_ADCREFTRIM1_VREFM_POS)) /**< ADCREFTRIM1_VREFM Mask */ 330 331 #define MXC_F_FCR_ADCREFTRIM1_VCM_POS 16 /**< ADCREFTRIM1_VCM Position */ 332 #define MXC_F_FCR_ADCREFTRIM1_VCM ((uint32_t)(0x3UL << MXC_F_FCR_ADCREFTRIM1_VCM_POS)) /**< ADCREFTRIM1_VCM Mask */ 333 334 #define MXC_F_FCR_ADCREFTRIM1_VX2_TUNE_POS 24 /**< ADCREFTRIM1_VX2_TUNE Position */ 335 #define MXC_F_FCR_ADCREFTRIM1_VX2_TUNE ((uint32_t)(0x3FUL << MXC_F_FCR_ADCREFTRIM1_VX2_TUNE_POS)) /**< ADCREFTRIM1_VX2_TUNE Mask */ 336 337 /**@} end of group FCR_ADCREFTRIM1_Register */ 338 339 /** 340 * @ingroup fcr_registers 341 * @defgroup FCR_ADCREFTRIM2 FCR_ADCREFTRIM2 342 * @brief Temp Sensor trim1 343 * @{ 344 */ 345 #define MXC_F_FCR_ADCREFTRIM2_IDRV_1P25_POS 0 /**< ADCREFTRIM2_IDRV_1P25 Position */ 346 #define MXC_F_FCR_ADCREFTRIM2_IDRV_1P25 ((uint32_t)(0xFUL << MXC_F_FCR_ADCREFTRIM2_IDRV_1P25_POS)) /**< ADCREFTRIM2_IDRV_1P25 Mask */ 347 348 #define MXC_F_FCR_ADCREFTRIM2_IBOOST_1P25_POS 4 /**< ADCREFTRIM2_IBOOST_1P25 Position */ 349 #define MXC_F_FCR_ADCREFTRIM2_IBOOST_1P25 ((uint32_t)(0x1UL << MXC_F_FCR_ADCREFTRIM2_IBOOST_1P25_POS)) /**< ADCREFTRIM2_IBOOST_1P25 Mask */ 350 351 #define MXC_F_FCR_ADCREFTRIM2_IDRV_2P048_POS 8 /**< ADCREFTRIM2_IDRV_2P048 Position */ 352 #define MXC_F_FCR_ADCREFTRIM2_IDRV_2P048 ((uint32_t)(0xFUL << MXC_F_FCR_ADCREFTRIM2_IDRV_2P048_POS)) /**< ADCREFTRIM2_IDRV_2P048 Mask */ 353 354 #define MXC_F_FCR_ADCREFTRIM2_IBOOST_2P048_POS 12 /**< ADCREFTRIM2_IBOOST_2P048 Position */ 355 #define MXC_F_FCR_ADCREFTRIM2_IBOOST_2P048 ((uint32_t)(0x1UL << MXC_F_FCR_ADCREFTRIM2_IBOOST_2P048_POS)) /**< ADCREFTRIM2_IBOOST_2P048 Mask */ 356 357 #define MXC_F_FCR_ADCREFTRIM2_VCM_POS 16 /**< ADCREFTRIM2_VCM Position */ 358 #define MXC_F_FCR_ADCREFTRIM2_VCM ((uint32_t)(0x3UL << MXC_F_FCR_ADCREFTRIM2_VCM_POS)) /**< ADCREFTRIM2_VCM Mask */ 359 360 #define MXC_F_FCR_ADCREFTRIM2_VX2_TUNE_POS 24 /**< ADCREFTRIM2_VX2_TUNE Position */ 361 #define MXC_F_FCR_ADCREFTRIM2_VX2_TUNE ((uint32_t)(0x3FUL << MXC_F_FCR_ADCREFTRIM2_VX2_TUNE_POS)) /**< ADCREFTRIM2_VX2_TUNE Mask */ 362 363 /**@} end of group FCR_ADCREFTRIM2_Register */ 364 365 #ifdef __cplusplus 366 } 367 #endif 368 369 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32690_INCLUDE_FCR_REGS_H_ 370
