1 /** 2 * @file i2c_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup i2c_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32680_INCLUDE_I2C_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32680_INCLUDE_I2C_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup i2c 67 * @defgroup i2c_registers I2C_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module. 69 * @details Inter-Integrated Circuit. 70 */ 71 72 /** 73 * @ingroup i2c_registers 74 * Structure type to access the I2C Registers. 75 */ 76 typedef struct { 77 __IO uint32_t ctrl; /**< <tt>\b 0x00:</tt> I2C CTRL Register */ 78 __IO uint32_t status; /**< <tt>\b 0x04:</tt> I2C STATUS Register */ 79 __IO uint32_t intfl0; /**< <tt>\b 0x08:</tt> I2C INTFL0 Register */ 80 __IO uint32_t inten0; /**< <tt>\b 0x0C:</tt> I2C INTEN0 Register */ 81 __IO uint32_t intfl1; /**< <tt>\b 0x10:</tt> I2C INTFL1 Register */ 82 __IO uint32_t inten1; /**< <tt>\b 0x14:</tt> I2C INTEN1 Register */ 83 __IO uint32_t fifolen; /**< <tt>\b 0x18:</tt> I2C FIFOLEN Register */ 84 __IO uint32_t rxctrl0; /**< <tt>\b 0x1C:</tt> I2C RXCTRL0 Register */ 85 __IO uint32_t rxctrl1; /**< <tt>\b 0x20:</tt> I2C RXCTRL1 Register */ 86 __IO uint32_t txctrl0; /**< <tt>\b 0x24:</tt> I2C TXCTRL0 Register */ 87 __IO uint32_t txctrl1; /**< <tt>\b 0x28:</tt> I2C TXCTRL1 Register */ 88 __IO uint32_t fifo; /**< <tt>\b 0x2C:</tt> I2C FIFO Register */ 89 __IO uint32_t mstctrl; /**< <tt>\b 0x30:</tt> I2C MSTCTRL Register */ 90 __IO uint32_t clklo; /**< <tt>\b 0x34:</tt> I2C CLKLO Register */ 91 __IO uint32_t clkhi; /**< <tt>\b 0x38:</tt> I2C CLKHI Register */ 92 __IO uint32_t hsclk; /**< <tt>\b 0x3C:</tt> I2C HSCLK Register */ 93 __IO uint32_t timeout; /**< <tt>\b 0x40:</tt> I2C TIMEOUT Register */ 94 __R uint32_t rsv_0x44; 95 __IO uint32_t dma; /**< <tt>\b 0x48:</tt> I2C DMA Register */ 96 union { 97 __IO uint32_t slave_multi[4]; /**< <tt>\b 0x4C:</tt> I2C SLAVE_MULTI Register */ 98 struct { 99 __IO uint32_t slave0; /**< <tt>\b 0x4C:</tt> I2C SLAVE0 Register */ 100 __IO uint32_t slave1; /**< <tt>\b 0x50:</tt> I2C SLAVE1 Register */ 101 __IO uint32_t slave2; /**< <tt>\b 0x54:</tt> I2C SLAVE2 Register */ 102 __IO uint32_t slave3; /**< <tt>\b 0x58:</tt> I2C SLAVE3 Register */ 103 }; 104 }; 105 } mxc_i2c_regs_t; 106 107 /* Register offsets for module I2C */ 108 /** 109 * @ingroup i2c_registers 110 * @defgroup I2C_Register_Offsets Register Offsets 111 * @brief I2C Peripheral Register Offsets from the I2C Base Peripheral Address. 112 * @{ 113 */ 114 #define MXC_R_I2C_CTRL ((uint32_t)0x00000000UL) /**< Offset from I2C Base Address: <tt> 0x0000</tt> */ 115 #define MXC_R_I2C_STATUS ((uint32_t)0x00000004UL) /**< Offset from I2C Base Address: <tt> 0x0004</tt> */ 116 #define MXC_R_I2C_INTFL0 ((uint32_t)0x00000008UL) /**< Offset from I2C Base Address: <tt> 0x0008</tt> */ 117 #define MXC_R_I2C_INTEN0 ((uint32_t)0x0000000CUL) /**< Offset from I2C Base Address: <tt> 0x000C</tt> */ 118 #define MXC_R_I2C_INTFL1 ((uint32_t)0x00000010UL) /**< Offset from I2C Base Address: <tt> 0x0010</tt> */ 119 #define MXC_R_I2C_INTEN1 ((uint32_t)0x00000014UL) /**< Offset from I2C Base Address: <tt> 0x0014</tt> */ 120 #define MXC_R_I2C_FIFOLEN ((uint32_t)0x00000018UL) /**< Offset from I2C Base Address: <tt> 0x0018</tt> */ 121 #define MXC_R_I2C_RXCTRL0 ((uint32_t)0x0000001CUL) /**< Offset from I2C Base Address: <tt> 0x001C</tt> */ 122 #define MXC_R_I2C_RXCTRL1 ((uint32_t)0x00000020UL) /**< Offset from I2C Base Address: <tt> 0x0020</tt> */ 123 #define MXC_R_I2C_TXCTRL0 ((uint32_t)0x00000024UL) /**< Offset from I2C Base Address: <tt> 0x0024</tt> */ 124 #define MXC_R_I2C_TXCTRL1 ((uint32_t)0x00000028UL) /**< Offset from I2C Base Address: <tt> 0x0028</tt> */ 125 #define MXC_R_I2C_FIFO ((uint32_t)0x0000002CUL) /**< Offset from I2C Base Address: <tt> 0x002C</tt> */ 126 #define MXC_R_I2C_MSTCTRL ((uint32_t)0x00000030UL) /**< Offset from I2C Base Address: <tt> 0x0030</tt> */ 127 #define MXC_R_I2C_CLKLO ((uint32_t)0x00000034UL) /**< Offset from I2C Base Address: <tt> 0x0034</tt> */ 128 #define MXC_R_I2C_CLKHI ((uint32_t)0x00000038UL) /**< Offset from I2C Base Address: <tt> 0x0038</tt> */ 129 #define MXC_R_I2C_HSCLK ((uint32_t)0x0000003CUL) /**< Offset from I2C Base Address: <tt> 0x003C</tt> */ 130 #define MXC_R_I2C_TIMEOUT ((uint32_t)0x00000040UL) /**< Offset from I2C Base Address: <tt> 0x0040</tt> */ 131 #define MXC_R_I2C_DMA ((uint32_t)0x00000048UL) /**< Offset from I2C Base Address: <tt> 0x0048</tt> */ 132 #define MXC_R_I2C_SLAVE_MULTI ((uint32_t)0x0000004CUL) /**< Offset from I2C Base Address: <tt> 0x004C</tt> */ 133 #define MXC_R_I2C_SLAVE0 ((uint32_t)0x0000004CUL) /**< Offset from I2C Base Address: <tt> 0x004C</tt> */ 134 #define MXC_R_I2C_SLAVE1 ((uint32_t)0x00000050UL) /**< Offset from I2C Base Address: <tt> 0x0050</tt> */ 135 #define MXC_R_I2C_SLAVE2 ((uint32_t)0x00000054UL) /**< Offset from I2C Base Address: <tt> 0x0054</tt> */ 136 #define MXC_R_I2C_SLAVE3 ((uint32_t)0x00000058UL) /**< Offset from I2C Base Address: <tt> 0x0058</tt> */ 137 /**@} end of group i2c_registers */ 138 139 /** 140 * @ingroup i2c_registers 141 * @defgroup I2C_CTRL I2C_CTRL 142 * @brief Control Register0. 143 * @{ 144 */ 145 #define MXC_F_I2C_CTRL_EN_POS 0 /**< CTRL_EN Position */ 146 #define MXC_F_I2C_CTRL_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_EN_POS)) /**< CTRL_EN Mask */ 147 148 #define MXC_F_I2C_CTRL_MST_MODE_POS 1 /**< CTRL_MST_MODE Position */ 149 #define MXC_F_I2C_CTRL_MST_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_MST_MODE_POS)) /**< CTRL_MST_MODE Mask */ 150 151 #define MXC_F_I2C_CTRL_GC_ADDR_EN_POS 2 /**< CTRL_GC_ADDR_EN Position */ 152 #define MXC_F_I2C_CTRL_GC_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_GC_ADDR_EN_POS)) /**< CTRL_GC_ADDR_EN Mask */ 153 154 #define MXC_F_I2C_CTRL_IRXM_EN_POS 3 /**< CTRL_IRXM_EN Position */ 155 #define MXC_F_I2C_CTRL_IRXM_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_IRXM_EN_POS)) /**< CTRL_IRXM_EN Mask */ 156 157 #define MXC_F_I2C_CTRL_IRXM_ACK_POS 4 /**< CTRL_IRXM_ACK Position */ 158 #define MXC_F_I2C_CTRL_IRXM_ACK ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_IRXM_ACK_POS)) /**< CTRL_IRXM_ACK Mask */ 159 160 #define MXC_F_I2C_CTRL_SCL_OUT_POS 6 /**< CTRL_SCL_OUT Position */ 161 #define MXC_F_I2C_CTRL_SCL_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_OUT_POS)) /**< CTRL_SCL_OUT Mask */ 162 163 #define MXC_F_I2C_CTRL_SDA_OUT_POS 7 /**< CTRL_SDA_OUT Position */ 164 #define MXC_F_I2C_CTRL_SDA_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_OUT_POS)) /**< CTRL_SDA_OUT Mask */ 165 166 #define MXC_F_I2C_CTRL_SCL_POS 8 /**< CTRL_SCL Position */ 167 #define MXC_F_I2C_CTRL_SCL ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_POS)) /**< CTRL_SCL Mask */ 168 169 #define MXC_F_I2C_CTRL_SDA_POS 9 /**< CTRL_SDA Position */ 170 #define MXC_F_I2C_CTRL_SDA ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_POS)) /**< CTRL_SDA Mask */ 171 172 #define MXC_F_I2C_CTRL_BB_MODE_POS 10 /**< CTRL_BB_MODE Position */ 173 #define MXC_F_I2C_CTRL_BB_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_BB_MODE_POS)) /**< CTRL_BB_MODE Mask */ 174 175 #define MXC_F_I2C_CTRL_READ_POS 11 /**< CTRL_READ Position */ 176 #define MXC_F_I2C_CTRL_READ ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_READ_POS)) /**< CTRL_READ Mask */ 177 178 #define MXC_F_I2C_CTRL_CLKSTR_DIS_POS 12 /**< CTRL_CLKSTR_DIS Position */ 179 #define MXC_F_I2C_CTRL_CLKSTR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_CLKSTR_DIS_POS)) /**< CTRL_CLKSTR_DIS Mask */ 180 181 #define MXC_F_I2C_CTRL_ONE_MST_MODE_POS 13 /**< CTRL_ONE_MST_MODE Position */ 182 #define MXC_F_I2C_CTRL_ONE_MST_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_ONE_MST_MODE_POS)) /**< CTRL_ONE_MST_MODE Mask */ 183 184 #define MXC_F_I2C_CTRL_HS_EN_POS 15 /**< CTRL_HS_EN Position */ 185 #define MXC_F_I2C_CTRL_HS_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_HS_EN_POS)) /**< CTRL_HS_EN Mask */ 186 187 /**@} end of group I2C_CTRL_Register */ 188 189 /** 190 * @ingroup i2c_registers 191 * @defgroup I2C_STATUS I2C_STATUS 192 * @brief Status Register. 193 * @{ 194 */ 195 #define MXC_F_I2C_STATUS_BUSY_POS 0 /**< STATUS_BUSY Position */ 196 #define MXC_F_I2C_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */ 197 198 #define MXC_F_I2C_STATUS_RX_EM_POS 1 /**< STATUS_RX_EM Position */ 199 #define MXC_F_I2C_STATUS_RX_EM ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_EM_POS)) /**< STATUS_RX_EM Mask */ 200 201 #define MXC_F_I2C_STATUS_RX_FULL_POS 2 /**< STATUS_RX_FULL Position */ 202 #define MXC_F_I2C_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */ 203 204 #define MXC_F_I2C_STATUS_TX_EM_POS 3 /**< STATUS_TX_EM Position */ 205 #define MXC_F_I2C_STATUS_TX_EM ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_EM_POS)) /**< STATUS_TX_EM Mask */ 206 207 #define MXC_F_I2C_STATUS_TX_FULL_POS 4 /**< STATUS_TX_FULL Position */ 208 #define MXC_F_I2C_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */ 209 210 #define MXC_F_I2C_STATUS_MST_BUSY_POS 5 /**< STATUS_MST_BUSY Position */ 211 #define MXC_F_I2C_STATUS_MST_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_MST_BUSY_POS)) /**< STATUS_MST_BUSY Mask */ 212 213 /**@} end of group I2C_STATUS_Register */ 214 215 /** 216 * @ingroup i2c_registers 217 * @defgroup I2C_INTFL0 I2C_INTFL0 218 * @brief Interrupt Status Register. 219 * @{ 220 */ 221 #define MXC_F_I2C_INTFL0_DONE_POS 0 /**< INTFL0_DONE Position */ 222 #define MXC_F_I2C_INTFL0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DONE_POS)) /**< INTFL0_DONE Mask */ 223 224 #define MXC_F_I2C_INTFL0_IRXM_POS 1 /**< INTFL0_IRXM Position */ 225 #define MXC_F_I2C_INTFL0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_IRXM_POS)) /**< INTFL0_IRXM Mask */ 226 227 #define MXC_F_I2C_INTFL0_GC_ADDR_MATCH_POS 2 /**< INTFL0_GC_ADDR_MATCH Position */ 228 #define MXC_F_I2C_INTFL0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_GC_ADDR_MATCH_POS)) /**< INTFL0_GC_ADDR_MATCH Mask */ 229 230 #define MXC_F_I2C_INTFL0_ADDR_MATCH_POS 3 /**< INTFL0_ADDR_MATCH Position */ 231 #define MXC_F_I2C_INTFL0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADDR_MATCH_POS)) /**< INTFL0_ADDR_MATCH Mask */ 232 233 #define MXC_F_I2C_INTFL0_RX_THD_POS 4 /**< INTFL0_RX_THD Position */ 234 #define MXC_F_I2C_INTFL0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_RX_THD_POS)) /**< INTFL0_RX_THD Mask */ 235 236 #define MXC_F_I2C_INTFL0_TX_THD_POS 5 /**< INTFL0_TX_THD Position */ 237 #define MXC_F_I2C_INTFL0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TX_THD_POS)) /**< INTFL0_TX_THD Mask */ 238 239 #define MXC_F_I2C_INTFL0_STOP_POS 6 /**< INTFL0_STOP Position */ 240 #define MXC_F_I2C_INTFL0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STOP_POS)) /**< INTFL0_STOP Mask */ 241 242 #define MXC_F_I2C_INTFL0_ADDR_ACK_POS 7 /**< INTFL0_ADDR_ACK Position */ 243 #define MXC_F_I2C_INTFL0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADDR_ACK_POS)) /**< INTFL0_ADDR_ACK Mask */ 244 245 #define MXC_F_I2C_INTFL0_ARB_ERR_POS 8 /**< INTFL0_ARB_ERR Position */ 246 #define MXC_F_I2C_INTFL0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ARB_ERR_POS)) /**< INTFL0_ARB_ERR Mask */ 247 248 #define MXC_F_I2C_INTFL0_TO_ERR_POS 9 /**< INTFL0_TO_ERR Position */ 249 #define MXC_F_I2C_INTFL0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TO_ERR_POS)) /**< INTFL0_TO_ERR Mask */ 250 251 #define MXC_F_I2C_INTFL0_ADDR_NACK_ERR_POS 10 /**< INTFL0_ADDR_NACK_ERR Position */ 252 #define MXC_F_I2C_INTFL0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADDR_NACK_ERR_POS)) /**< INTFL0_ADDR_NACK_ERR Mask */ 253 254 #define MXC_F_I2C_INTFL0_DATA_ERR_POS 11 /**< INTFL0_DATA_ERR Position */ 255 #define MXC_F_I2C_INTFL0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DATA_ERR_POS)) /**< INTFL0_DATA_ERR Mask */ 256 257 #define MXC_F_I2C_INTFL0_DNR_ERR_POS 12 /**< INTFL0_DNR_ERR Position */ 258 #define MXC_F_I2C_INTFL0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DNR_ERR_POS)) /**< INTFL0_DNR_ERR Mask */ 259 260 #define MXC_F_I2C_INTFL0_START_ERR_POS 13 /**< INTFL0_START_ERR Position */ 261 #define MXC_F_I2C_INTFL0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_START_ERR_POS)) /**< INTFL0_START_ERR Mask */ 262 263 #define MXC_F_I2C_INTFL0_STOP_ERR_POS 14 /**< INTFL0_STOP_ERR Position */ 264 #define MXC_F_I2C_INTFL0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STOP_ERR_POS)) /**< INTFL0_STOP_ERR Mask */ 265 266 #define MXC_F_I2C_INTFL0_TX_LOCKOUT_POS 15 /**< INTFL0_TX_LOCKOUT Position */ 267 #define MXC_F_I2C_INTFL0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TX_LOCKOUT_POS)) /**< INTFL0_TX_LOCKOUT Mask */ 268 269 #define MXC_F_I2C_INTFL0_MAMI_POS 16 /**< INTFL0_MAMI Position */ 270 #define MXC_F_I2C_INTFL0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_INTFL0_MAMI_POS)) /**< INTFL0_MAMI Mask */ 271 272 #define MXC_F_I2C_INTFL0_RD_ADDR_MATCH_POS 22 /**< INTFL0_RD_ADDR_MATCH Position */ 273 #define MXC_F_I2C_INTFL0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_RD_ADDR_MATCH_POS)) /**< INTFL0_RD_ADDR_MATCH Mask */ 274 275 #define MXC_F_I2C_INTFL0_WR_ADDR_MATCH_POS 23 /**< INTFL0_WR_ADDR_MATCH Position */ 276 #define MXC_F_I2C_INTFL0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_WR_ADDR_MATCH_POS)) /**< INTFL0_WR_ADDR_MATCH Mask */ 277 278 /**@} end of group I2C_INTFL0_Register */ 279 280 /** 281 * @ingroup i2c_registers 282 * @defgroup I2C_INTEN0 I2C_INTEN0 283 * @brief Interrupt Enable Register. 284 * @{ 285 */ 286 #define MXC_F_I2C_INTEN0_DONE_POS 0 /**< INTEN0_DONE Position */ 287 #define MXC_F_I2C_INTEN0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DONE_POS)) /**< INTEN0_DONE Mask */ 288 289 #define MXC_F_I2C_INTEN0_IRXM_POS 1 /**< INTEN0_IRXM Position */ 290 #define MXC_F_I2C_INTEN0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_IRXM_POS)) /**< INTEN0_IRXM Mask */ 291 292 #define MXC_F_I2C_INTEN0_GC_ADDR_MATCH_POS 2 /**< INTEN0_GC_ADDR_MATCH Position */ 293 #define MXC_F_I2C_INTEN0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_GC_ADDR_MATCH_POS)) /**< INTEN0_GC_ADDR_MATCH Mask */ 294 295 #define MXC_F_I2C_INTEN0_ADDR_MATCH_POS 3 /**< INTEN0_ADDR_MATCH Position */ 296 #define MXC_F_I2C_INTEN0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADDR_MATCH_POS)) /**< INTEN0_ADDR_MATCH Mask */ 297 298 #define MXC_F_I2C_INTEN0_RX_THD_POS 4 /**< INTEN0_RX_THD Position */ 299 #define MXC_F_I2C_INTEN0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_RX_THD_POS)) /**< INTEN0_RX_THD Mask */ 300 301 #define MXC_F_I2C_INTEN0_TX_THD_POS 5 /**< INTEN0_TX_THD Position */ 302 #define MXC_F_I2C_INTEN0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TX_THD_POS)) /**< INTEN0_TX_THD Mask */ 303 304 #define MXC_F_I2C_INTEN0_STOP_POS 6 /**< INTEN0_STOP Position */ 305 #define MXC_F_I2C_INTEN0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOP_POS)) /**< INTEN0_STOP Mask */ 306 307 #define MXC_F_I2C_INTEN0_ADDR_ACK_POS 7 /**< INTEN0_ADDR_ACK Position */ 308 #define MXC_F_I2C_INTEN0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADDR_ACK_POS)) /**< INTEN0_ADDR_ACK Mask */ 309 310 #define MXC_F_I2C_INTEN0_ARB_ERR_POS 8 /**< INTEN0_ARB_ERR Position */ 311 #define MXC_F_I2C_INTEN0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ARB_ERR_POS)) /**< INTEN0_ARB_ERR Mask */ 312 313 #define MXC_F_I2C_INTEN0_TO_ERR_POS 9 /**< INTEN0_TO_ERR Position */ 314 #define MXC_F_I2C_INTEN0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TO_ERR_POS)) /**< INTEN0_TO_ERR Mask */ 315 316 #define MXC_F_I2C_INTEN0_ADDR_NACK_ERR_POS 10 /**< INTEN0_ADDR_NACK_ERR Position */ 317 #define MXC_F_I2C_INTEN0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADDR_NACK_ERR_POS)) /**< INTEN0_ADDR_NACK_ERR Mask */ 318 319 #define MXC_F_I2C_INTEN0_DATA_ERR_POS 11 /**< INTEN0_DATA_ERR Position */ 320 #define MXC_F_I2C_INTEN0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DATA_ERR_POS)) /**< INTEN0_DATA_ERR Mask */ 321 322 #define MXC_F_I2C_INTEN0_DNR_ERR_POS 12 /**< INTEN0_DNR_ERR Position */ 323 #define MXC_F_I2C_INTEN0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DNR_ERR_POS)) /**< INTEN0_DNR_ERR Mask */ 324 325 #define MXC_F_I2C_INTEN0_START_ERR_POS 13 /**< INTEN0_START_ERR Position */ 326 #define MXC_F_I2C_INTEN0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_START_ERR_POS)) /**< INTEN0_START_ERR Mask */ 327 328 #define MXC_F_I2C_INTEN0_STOP_ERR_POS 14 /**< INTEN0_STOP_ERR Position */ 329 #define MXC_F_I2C_INTEN0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOP_ERR_POS)) /**< INTEN0_STOP_ERR Mask */ 330 331 #define MXC_F_I2C_INTEN0_TX_LOCKOUT_POS 15 /**< INTEN0_TX_LOCKOUT Position */ 332 #define MXC_F_I2C_INTEN0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TX_LOCKOUT_POS)) /**< INTEN0_TX_LOCKOUT Mask */ 333 334 #define MXC_F_I2C_INTEN0_MAMI_POS 16 /**< INTEN0_MAMI Position */ 335 #define MXC_F_I2C_INTEN0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_INTEN0_MAMI_POS)) /**< INTEN0_MAMI Mask */ 336 337 #define MXC_F_I2C_INTEN0_RD_ADDR_MATCH_POS 22 /**< INTEN0_RD_ADDR_MATCH Position */ 338 #define MXC_F_I2C_INTEN0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_RD_ADDR_MATCH_POS)) /**< INTEN0_RD_ADDR_MATCH Mask */ 339 340 #define MXC_F_I2C_INTEN0_WR_ADDR_MATCH_POS 23 /**< INTEN0_WR_ADDR_MATCH Position */ 341 #define MXC_F_I2C_INTEN0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_WR_ADDR_MATCH_POS)) /**< INTEN0_WR_ADDR_MATCH Mask */ 342 343 /**@} end of group I2C_INTEN0_Register */ 344 345 /** 346 * @ingroup i2c_registers 347 * @defgroup I2C_INTFL1 I2C_INTFL1 348 * @brief Interrupt Status Register 1. 349 * @{ 350 */ 351 #define MXC_F_I2C_INTFL1_RX_OV_POS 0 /**< INTFL1_RX_OV Position */ 352 #define MXC_F_I2C_INTFL1_RX_OV ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_RX_OV_POS)) /**< INTFL1_RX_OV Mask */ 353 354 #define MXC_F_I2C_INTFL1_TX_UN_POS 1 /**< INTFL1_TX_UN Position */ 355 #define MXC_F_I2C_INTFL1_TX_UN ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_TX_UN_POS)) /**< INTFL1_TX_UN Mask */ 356 357 #define MXC_F_I2C_INTFL1_START_POS 2 /**< INTFL1_START Position */ 358 #define MXC_F_I2C_INTFL1_START ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_START_POS)) /**< INTFL1_START Mask */ 359 360 /**@} end of group I2C_INTFL1_Register */ 361 362 /** 363 * @ingroup i2c_registers 364 * @defgroup I2C_INTEN1 I2C_INTEN1 365 * @brief Interrupt Staus Register 1. 366 * @{ 367 */ 368 #define MXC_F_I2C_INTEN1_RX_OV_POS 0 /**< INTEN1_RX_OV Position */ 369 #define MXC_F_I2C_INTEN1_RX_OV ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_RX_OV_POS)) /**< INTEN1_RX_OV Mask */ 370 371 #define MXC_F_I2C_INTEN1_TX_UN_POS 1 /**< INTEN1_TX_UN Position */ 372 #define MXC_F_I2C_INTEN1_TX_UN ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_TX_UN_POS)) /**< INTEN1_TX_UN Mask */ 373 374 #define MXC_F_I2C_INTEN1_START_POS 2 /**< INTEN1_START Position */ 375 #define MXC_F_I2C_INTEN1_START ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_START_POS)) /**< INTEN1_START Mask */ 376 377 /**@} end of group I2C_INTEN1_Register */ 378 379 /** 380 * @ingroup i2c_registers 381 * @defgroup I2C_FIFOLEN I2C_FIFOLEN 382 * @brief FIFO Configuration Register. 383 * @{ 384 */ 385 #define MXC_F_I2C_FIFOLEN_RX_DEPTH_POS 0 /**< FIFOLEN_RX_DEPTH Position */ 386 #define MXC_F_I2C_FIFOLEN_RX_DEPTH ((uint32_t)(0xFFUL << MXC_F_I2C_FIFOLEN_RX_DEPTH_POS)) /**< FIFOLEN_RX_DEPTH Mask */ 387 388 #define MXC_F_I2C_FIFOLEN_TX_DEPTH_POS 8 /**< FIFOLEN_TX_DEPTH Position */ 389 #define MXC_F_I2C_FIFOLEN_TX_DEPTH ((uint32_t)(0xFFUL << MXC_F_I2C_FIFOLEN_TX_DEPTH_POS)) /**< FIFOLEN_TX_DEPTH Mask */ 390 391 /**@} end of group I2C_FIFOLEN_Register */ 392 393 /** 394 * @ingroup i2c_registers 395 * @defgroup I2C_RXCTRL0 I2C_RXCTRL0 396 * @brief Receive Control Register 0. 397 * @{ 398 */ 399 #define MXC_F_I2C_RXCTRL0_DNR_POS 0 /**< RXCTRL0_DNR Position */ 400 #define MXC_F_I2C_RXCTRL0_DNR ((uint32_t)(0x1UL << MXC_F_I2C_RXCTRL0_DNR_POS)) /**< RXCTRL0_DNR Mask */ 401 402 #define MXC_F_I2C_RXCTRL0_FLUSH_POS 7 /**< RXCTRL0_FLUSH Position */ 403 #define MXC_F_I2C_RXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_RXCTRL0_FLUSH_POS)) /**< RXCTRL0_FLUSH Mask */ 404 405 #define MXC_F_I2C_RXCTRL0_THD_LVL_POS 8 /**< RXCTRL0_THD_LVL Position */ 406 #define MXC_F_I2C_RXCTRL0_THD_LVL ((uint32_t)(0xFUL << MXC_F_I2C_RXCTRL0_THD_LVL_POS)) /**< RXCTRL0_THD_LVL Mask */ 407 408 /**@} end of group I2C_RXCTRL0_Register */ 409 410 /** 411 * @ingroup i2c_registers 412 * @defgroup I2C_RXCTRL1 I2C_RXCTRL1 413 * @brief Receive Control Register 1. 414 * @{ 415 */ 416 #define MXC_F_I2C_RXCTRL1_CNT_POS 0 /**< RXCTRL1_CNT Position */ 417 #define MXC_F_I2C_RXCTRL1_CNT ((uint32_t)(0xFFUL << MXC_F_I2C_RXCTRL1_CNT_POS)) /**< RXCTRL1_CNT Mask */ 418 419 #define MXC_F_I2C_RXCTRL1_LVL_POS 8 /**< RXCTRL1_LVL Position */ 420 #define MXC_F_I2C_RXCTRL1_LVL ((uint32_t)(0xFUL << MXC_F_I2C_RXCTRL1_LVL_POS)) /**< RXCTRL1_LVL Mask */ 421 422 /**@} end of group I2C_RXCTRL1_Register */ 423 424 /** 425 * @ingroup i2c_registers 426 * @defgroup I2C_TXCTRL0 I2C_TXCTRL0 427 * @brief Transmit Control Register 0. 428 * @{ 429 */ 430 #define MXC_F_I2C_TXCTRL0_PRELOAD_MODE_POS 0 /**< TXCTRL0_PRELOAD_MODE Position */ 431 #define MXC_F_I2C_TXCTRL0_PRELOAD_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_PRELOAD_MODE_POS)) /**< TXCTRL0_PRELOAD_MODE Mask */ 432 433 #define MXC_F_I2C_TXCTRL0_TX_READY_MODE_POS 1 /**< TXCTRL0_TX_READY_MODE Position */ 434 #define MXC_F_I2C_TXCTRL0_TX_READY_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_TX_READY_MODE_POS)) /**< TXCTRL0_TX_READY_MODE Mask */ 435 436 #define MXC_F_I2C_TXCTRL0_GC_ADDR_FLUSH_DIS_POS 2 /**< TXCTRL0_GC_ADDR_FLUSH_DIS Position */ 437 #define MXC_F_I2C_TXCTRL0_GC_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_GC_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_GC_ADDR_FLUSH_DIS Mask */ 438 439 #define MXC_F_I2C_TXCTRL0_WR_ADDR_FLUSH_DIS_POS 3 /**< TXCTRL0_WR_ADDR_FLUSH_DIS Position */ 440 #define MXC_F_I2C_TXCTRL0_WR_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_WR_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_WR_ADDR_FLUSH_DIS Mask */ 441 442 #define MXC_F_I2C_TXCTRL0_RD_ADDR_FLUSH_DIS_POS 4 /**< TXCTRL0_RD_ADDR_FLUSH_DIS Position */ 443 #define MXC_F_I2C_TXCTRL0_RD_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_RD_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_RD_ADDR_FLUSH_DIS Mask */ 444 445 #define MXC_F_I2C_TXCTRL0_NACK_FLUSH_DIS_POS 5 /**< TXCTRL0_NACK_FLUSH_DIS Position */ 446 #define MXC_F_I2C_TXCTRL0_NACK_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_NACK_FLUSH_DIS_POS)) /**< TXCTRL0_NACK_FLUSH_DIS Mask */ 447 448 #define MXC_F_I2C_TXCTRL0_FLUSH_POS 7 /**< TXCTRL0_FLUSH Position */ 449 #define MXC_F_I2C_TXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_FLUSH_POS)) /**< TXCTRL0_FLUSH Mask */ 450 451 #define MXC_F_I2C_TXCTRL0_THD_VAL_POS 8 /**< TXCTRL0_THD_VAL Position */ 452 #define MXC_F_I2C_TXCTRL0_THD_VAL ((uint32_t)(0xFUL << MXC_F_I2C_TXCTRL0_THD_VAL_POS)) /**< TXCTRL0_THD_VAL Mask */ 453 454 /**@} end of group I2C_TXCTRL0_Register */ 455 456 /** 457 * @ingroup i2c_registers 458 * @defgroup I2C_TXCTRL1 I2C_TXCTRL1 459 * @brief Transmit Control Register 1. 460 * @{ 461 */ 462 #define MXC_F_I2C_TXCTRL1_PRELOAD_RDY_POS 0 /**< TXCTRL1_PRELOAD_RDY Position */ 463 #define MXC_F_I2C_TXCTRL1_PRELOAD_RDY ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_PRELOAD_RDY_POS)) /**< TXCTRL1_PRELOAD_RDY Mask */ 464 465 #define MXC_F_I2C_TXCTRL1_LVL_POS 8 /**< TXCTRL1_LVL Position */ 466 #define MXC_F_I2C_TXCTRL1_LVL ((uint32_t)(0xFUL << MXC_F_I2C_TXCTRL1_LVL_POS)) /**< TXCTRL1_LVL Mask */ 467 468 /**@} end of group I2C_TXCTRL1_Register */ 469 470 /** 471 * @ingroup i2c_registers 472 * @defgroup I2C_FIFO I2C_FIFO 473 * @brief Data Register. 474 * @{ 475 */ 476 #define MXC_F_I2C_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ 477 #define MXC_F_I2C_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ 478 479 /**@} end of group I2C_FIFO_Register */ 480 481 /** 482 * @ingroup i2c_registers 483 * @defgroup I2C_MSTCTRL I2C_MSTCTRL 484 * @brief Master Control Register. 485 * @{ 486 */ 487 #define MXC_F_I2C_MSTCTRL_START_POS 0 /**< MSTCTRL_START Position */ 488 #define MXC_F_I2C_MSTCTRL_START ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_START_POS)) /**< MSTCTRL_START Mask */ 489 490 #define MXC_F_I2C_MSTCTRL_RESTART_POS 1 /**< MSTCTRL_RESTART Position */ 491 #define MXC_F_I2C_MSTCTRL_RESTART ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_RESTART_POS)) /**< MSTCTRL_RESTART Mask */ 492 493 #define MXC_F_I2C_MSTCTRL_STOP_POS 2 /**< MSTCTRL_STOP Position */ 494 #define MXC_F_I2C_MSTCTRL_STOP ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_STOP_POS)) /**< MSTCTRL_STOP Mask */ 495 496 #define MXC_F_I2C_MSTCTRL_EX_ADDR_EN_POS 7 /**< MSTCTRL_EX_ADDR_EN Position */ 497 #define MXC_F_I2C_MSTCTRL_EX_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_EX_ADDR_EN_POS)) /**< MSTCTRL_EX_ADDR_EN Mask */ 498 499 /**@} end of group I2C_MSTCTRL_Register */ 500 501 /** 502 * @ingroup i2c_registers 503 * @defgroup I2C_CLKLO I2C_CLKLO 504 * @brief Clock Low Register. 505 * @{ 506 */ 507 #define MXC_F_I2C_CLKLO_LO_POS 0 /**< CLKLO_LO Position */ 508 #define MXC_F_I2C_CLKLO_LO ((uint32_t)(0x1FFUL << MXC_F_I2C_CLKLO_LO_POS)) /**< CLKLO_LO Mask */ 509 510 /**@} end of group I2C_CLKLO_Register */ 511 512 /** 513 * @ingroup i2c_registers 514 * @defgroup I2C_CLKHI I2C_CLKHI 515 * @brief Clock high Register. 516 * @{ 517 */ 518 #define MXC_F_I2C_CLKHI_HI_POS 0 /**< CLKHI_HI Position */ 519 #define MXC_F_I2C_CLKHI_HI ((uint32_t)(0x1FFUL << MXC_F_I2C_CLKHI_HI_POS)) /**< CLKHI_HI Mask */ 520 521 /**@} end of group I2C_CLKHI_Register */ 522 523 /** 524 * @ingroup i2c_registers 525 * @defgroup I2C_HSCLK I2C_HSCLK 526 * @brief Clock high Register. 527 * @{ 528 */ 529 #define MXC_F_I2C_HSCLK_LO_POS 0 /**< HSCLK_LO Position */ 530 #define MXC_F_I2C_HSCLK_LO ((uint32_t)(0xFFUL << MXC_F_I2C_HSCLK_LO_POS)) /**< HSCLK_LO Mask */ 531 532 #define MXC_F_I2C_HSCLK_HI_POS 8 /**< HSCLK_HI Position */ 533 #define MXC_F_I2C_HSCLK_HI ((uint32_t)(0xFFUL << MXC_F_I2C_HSCLK_HI_POS)) /**< HSCLK_HI Mask */ 534 535 /**@} end of group I2C_HSCLK_Register */ 536 537 /** 538 * @ingroup i2c_registers 539 * @defgroup I2C_TIMEOUT I2C_TIMEOUT 540 * @brief Timeout Register 541 * @{ 542 */ 543 #define MXC_F_I2C_TIMEOUT_SCL_TO_VAL_POS 0 /**< TIMEOUT_SCL_TO_VAL Position */ 544 #define MXC_F_I2C_TIMEOUT_SCL_TO_VAL ((uint32_t)(0xFFFFUL << MXC_F_I2C_TIMEOUT_SCL_TO_VAL_POS)) /**< TIMEOUT_SCL_TO_VAL Mask */ 545 546 /**@} end of group I2C_TIMEOUT_Register */ 547 548 /** 549 * @ingroup i2c_registers 550 * @defgroup I2C_DMA I2C_DMA 551 * @brief DMA Register. 552 * @{ 553 */ 554 #define MXC_F_I2C_DMA_TX_EN_POS 0 /**< DMA_TX_EN Position */ 555 #define MXC_F_I2C_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */ 556 557 #define MXC_F_I2C_DMA_RX_EN_POS 1 /**< DMA_RX_EN Position */ 558 #define MXC_F_I2C_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */ 559 560 /**@} end of group I2C_DMA_Register */ 561 562 /** 563 * @ingroup i2c_registers 564 * @defgroup I2C_SLAVE_MULTI I2C_SLAVE_MULTI 565 * @brief Slave Address Register. 566 * @{ 567 */ 568 #define MXC_F_I2C_SLAVE_MULTI_ADDR_POS 0 /**< SLAVE_MULTI_ADDR Position */ 569 #define MXC_F_I2C_SLAVE_MULTI_ADDR ((uint32_t)(0x3FFUL << MXC_F_I2C_SLAVE_MULTI_ADDR_POS)) /**< SLAVE_MULTI_ADDR Mask */ 570 571 #define MXC_F_I2C_SLAVE_MULTI_DIS_POS 10 /**< SLAVE_MULTI_DIS Position */ 572 #define MXC_F_I2C_SLAVE_MULTI_DIS ((uint32_t)(0x1UL << MXC_F_I2C_SLAVE_MULTI_DIS_POS)) /**< SLAVE_MULTI_DIS Mask */ 573 574 #define MXC_F_I2C_SLAVE_MULTI_EXT_ADDR_EN_POS 15 /**< SLAVE_MULTI_EXT_ADDR_EN Position */ 575 #define MXC_F_I2C_SLAVE_MULTI_EXT_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_SLAVE_MULTI_EXT_ADDR_EN_POS)) /**< SLAVE_MULTI_EXT_ADDR_EN Mask */ 576 577 /**@} end of group I2C_SLAVE_MULTI_Register */ 578 579 #ifdef __cplusplus 580 } 581 #endif 582 583 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32680_INCLUDE_I2C_REGS_H_ 584
