1 /** 2 * @file fcr_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the FCR Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup fcr_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32680_INCLUDE_FCR_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32680_INCLUDE_FCR_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup fcr 67 * @defgroup fcr_registers FCR_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the FCR Peripheral Module. 69 * @details Function Control Register. 70 */ 71 72 /** 73 * @ingroup fcr_registers 74 * Structure type to access the FCR Registers. 75 */ 76 typedef struct { 77 __IO uint32_t fctrl0; /**< <tt>\b 0x00:</tt> FCR FCTRL0 Register */ 78 __IO uint32_t autocal0; /**< <tt>\b 0x04:</tt> FCR AUTOCAL0 Register */ 79 __IO uint32_t autocal1; /**< <tt>\b 0x08:</tt> FCR AUTOCAL1 Register */ 80 __IO uint32_t autocal2; /**< <tt>\b 0x0C:</tt> FCR AUTOCAL2 Register */ 81 __IO uint32_t urvbootaddr; /**< <tt>\b 0x10:</tt> FCR URVBOOTADDR Register */ 82 __IO uint32_t urvctrl; /**< <tt>\b 0x14:</tt> FCR URVCTRL Register */ 83 __IO uint32_t erfoks; /**< <tt>\b 0x18:</tt> FCR ERFOKS Register */ 84 } mxc_fcr_regs_t; 85 86 /* Register offsets for module FCR */ 87 /** 88 * @ingroup fcr_registers 89 * @defgroup FCR_Register_Offsets Register Offsets 90 * @brief FCR Peripheral Register Offsets from the FCR Base Peripheral Address. 91 * @{ 92 */ 93 #define MXC_R_FCR_FCTRL0 ((uint32_t)0x00000000UL) /**< Offset from FCR Base Address: <tt> 0x0000</tt> */ 94 #define MXC_R_FCR_AUTOCAL0 ((uint32_t)0x00000004UL) /**< Offset from FCR Base Address: <tt> 0x0004</tt> */ 95 #define MXC_R_FCR_AUTOCAL1 ((uint32_t)0x00000008UL) /**< Offset from FCR Base Address: <tt> 0x0008</tt> */ 96 #define MXC_R_FCR_AUTOCAL2 ((uint32_t)0x0000000CUL) /**< Offset from FCR Base Address: <tt> 0x000C</tt> */ 97 #define MXC_R_FCR_URVBOOTADDR ((uint32_t)0x00000010UL) /**< Offset from FCR Base Address: <tt> 0x0010</tt> */ 98 #define MXC_R_FCR_URVCTRL ((uint32_t)0x00000014UL) /**< Offset from FCR Base Address: <tt> 0x0014</tt> */ 99 #define MXC_R_FCR_ERFOKS ((uint32_t)0x00000018UL) /**< Offset from FCR Base Address: <tt> 0x0018</tt> */ 100 /**@} end of group fcr_registers */ 101 102 /** 103 * @ingroup fcr_registers 104 * @defgroup FCR_FCTRL0 FCR_FCTRL0 105 * @brief Function Control 0. 106 * @{ 107 */ 108 #define MXC_F_FCR_FCTRL0_I2C0DGEN0_POS 20 /**< FCTRL0_I2C0DGEN0 Position */ 109 #define MXC_F_FCR_FCTRL0_I2C0DGEN0 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0DGEN0_POS)) /**< FCTRL0_I2C0DGEN0 Mask */ 110 111 #define MXC_F_FCR_FCTRL0_I2C0DGEN1_POS 21 /**< FCTRL0_I2C0DGEN1 Position */ 112 #define MXC_F_FCR_FCTRL0_I2C0DGEN1 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0DGEN1_POS)) /**< FCTRL0_I2C0DGEN1 Mask */ 113 114 #define MXC_F_FCR_FCTRL0_I2C1DGEN0_POS 22 /**< FCTRL0_I2C1DGEN0 Position */ 115 #define MXC_F_FCR_FCTRL0_I2C1DGEN0 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1DGEN0_POS)) /**< FCTRL0_I2C1DGEN0 Mask */ 116 117 #define MXC_F_FCR_FCTRL0_I2C1DGEN1_POS 23 /**< FCTRL0_I2C1DGEN1 Position */ 118 #define MXC_F_FCR_FCTRL0_I2C1DGEN1 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1DGEN1_POS)) /**< FCTRL0_I2C1DGEN1 Mask */ 119 120 #define MXC_F_FCR_FCTRL0_I2C2DGEN0_POS 24 /**< FCTRL0_I2C2DGEN0 Position */ 121 #define MXC_F_FCR_FCTRL0_I2C2DGEN0 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2DGEN0_POS)) /**< FCTRL0_I2C2DGEN0 Mask */ 122 123 #define MXC_F_FCR_FCTRL0_I2C2DGEN1_POS 25 /**< FCTRL0_I2C2DGEN1 Position */ 124 #define MXC_F_FCR_FCTRL0_I2C2DGEN1 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2DGEN1_POS)) /**< FCTRL0_I2C2DGEN1 Mask */ 125 126 /**@} end of group FCR_FCTRL0_Register */ 127 128 /** 129 * @ingroup fcr_registers 130 * @defgroup FCR_AUTOCAL0 FCR_AUTOCAL0 131 * @brief Automatic Calibration 0. 132 * @{ 133 */ 134 #define MXC_F_FCR_AUTOCAL0_ACEN_POS 0 /**< AUTOCAL0_ACEN Position */ 135 #define MXC_F_FCR_AUTOCAL0_ACEN ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_ACEN_POS)) /**< AUTOCAL0_ACEN Mask */ 136 137 #define MXC_F_FCR_AUTOCAL0_ACRUN_POS 1 /**< AUTOCAL0_ACRUN Position */ 138 #define MXC_F_FCR_AUTOCAL0_ACRUN ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_ACRUN_POS)) /**< AUTOCAL0_ACRUN Mask */ 139 140 #define MXC_F_FCR_AUTOCAL0_LDTRM_POS 2 /**< AUTOCAL0_LDTRM Position */ 141 #define MXC_F_FCR_AUTOCAL0_LDTRM ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_LDTRM_POS)) /**< AUTOCAL0_LDTRM Mask */ 142 143 #define MXC_F_FCR_AUTOCAL0_GAININV_POS 3 /**< AUTOCAL0_GAININV Position */ 144 #define MXC_F_FCR_AUTOCAL0_GAININV ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_GAININV_POS)) /**< AUTOCAL0_GAININV Mask */ 145 146 #define MXC_F_FCR_AUTOCAL0_ATOMIC_POS 4 /**< AUTOCAL0_ATOMIC Position */ 147 #define MXC_F_FCR_AUTOCAL0_ATOMIC ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_ATOMIC_POS)) /**< AUTOCAL0_ATOMIC Mask */ 148 149 #define MXC_F_FCR_AUTOCAL0_MU_POS 8 /**< AUTOCAL0_MU Position */ 150 #define MXC_F_FCR_AUTOCAL0_MU ((uint32_t)(0xFFFUL << MXC_F_FCR_AUTOCAL0_MU_POS)) /**< AUTOCAL0_MU Mask */ 151 152 #define MXC_F_FCR_AUTOCAL0_HIRC96MACTMROUT_POS 23 /**< AUTOCAL0_HIRC96MACTMROUT Position */ 153 #define MXC_F_FCR_AUTOCAL0_HIRC96MACTMROUT ((uint32_t)(0x1FFUL << MXC_F_FCR_AUTOCAL0_HIRC96MACTMROUT_POS)) /**< AUTOCAL0_HIRC96MACTMROUT Mask */ 154 155 /**@} end of group FCR_AUTOCAL0_Register */ 156 157 /** 158 * @ingroup fcr_registers 159 * @defgroup FCR_AUTOCAL1 FCR_AUTOCAL1 160 * @brief Automatic Calibration 1. 161 * @{ 162 */ 163 #define MXC_F_FCR_AUTOCAL1_INITTRM_POS 0 /**< AUTOCAL1_INITTRM Position */ 164 #define MXC_F_FCR_AUTOCAL1_INITTRM ((uint32_t)(0x1FFUL << MXC_F_FCR_AUTOCAL1_INITTRM_POS)) /**< AUTOCAL1_INITTRM Mask */ 165 166 /**@} end of group FCR_AUTOCAL1_Register */ 167 168 /** 169 * @ingroup fcr_registers 170 * @defgroup FCR_AUTOCAL2 FCR_AUTOCAL2 171 * @brief Automatic Calibration 2 172 * @{ 173 */ 174 #define MXC_F_FCR_AUTOCAL2_DONECNT_POS 0 /**< AUTOCAL2_DONECNT Position */ 175 #define MXC_F_FCR_AUTOCAL2_DONECNT ((uint32_t)(0xFFUL << MXC_F_FCR_AUTOCAL2_DONECNT_POS)) /**< AUTOCAL2_DONECNT Mask */ 176 177 #define MXC_F_FCR_AUTOCAL2_ACDIV_POS 8 /**< AUTOCAL2_ACDIV Position */ 178 #define MXC_F_FCR_AUTOCAL2_ACDIV ((uint32_t)(0x1FFFUL << MXC_F_FCR_AUTOCAL2_ACDIV_POS)) /**< AUTOCAL2_ACDIV Mask */ 179 180 /**@} end of group FCR_AUTOCAL2_Register */ 181 182 /** 183 * @ingroup fcr_registers 184 * @defgroup FCR_URVCTRL FCR_URVCTRL 185 * @brief RISC-V Control Register. 186 * @{ 187 */ 188 #define MXC_F_FCR_URVCTRL_MEMSEL_POS 0 /**< URVCTRL_MEMSEL Position */ 189 #define MXC_F_FCR_URVCTRL_MEMSEL ((uint32_t)(0x1UL << MXC_F_FCR_URVCTRL_MEMSEL_POS)) /**< URVCTRL_MEMSEL Mask */ 190 191 #define MXC_F_FCR_URVCTRL_IFLUSHEN_POS 1 /**< URVCTRL_IFLUSHEN Position */ 192 #define MXC_F_FCR_URVCTRL_IFLUSHEN ((uint32_t)(0x1UL << MXC_F_FCR_URVCTRL_IFLUSHEN_POS)) /**< URVCTRL_IFLUSHEN Mask */ 193 194 /**@} end of group FCR_URVCTRL_Register */ 195 196 /** 197 * @ingroup fcr_registers 198 * @defgroup FCR_ERFOKS FCR_ERFOKS 199 * @brief ERFO Kick Start Register. 200 * @{ 201 */ 202 #define MXC_F_FCR_ERFOKS_KSERFO_CNT_POS 0 /**< ERFOKS_KSERFO_CNT Position */ 203 #define MXC_F_FCR_ERFOKS_KSERFO_CNT ((uint32_t)(0x7FUL << MXC_F_FCR_ERFOKS_KSERFO_CNT_POS)) /**< ERFOKS_KSERFO_CNT Mask */ 204 205 #define MXC_F_FCR_ERFOKS_KSERFO_EN_POS 7 /**< ERFOKS_KSERFO_EN Position */ 206 #define MXC_F_FCR_ERFOKS_KSERFO_EN ((uint32_t)(0x1UL << MXC_F_FCR_ERFOKS_KSERFO_EN_POS)) /**< ERFOKS_KSERFO_EN Mask */ 207 208 #define MXC_F_FCR_ERFOKS_KSERFODRIVER_POS 8 /**< ERFOKS_KSERFODRIVER Position */ 209 #define MXC_F_FCR_ERFOKS_KSERFODRIVER ((uint32_t)(0x7UL << MXC_F_FCR_ERFOKS_KSERFODRIVER_POS)) /**< ERFOKS_KSERFODRIVER Mask */ 210 211 #define MXC_F_FCR_ERFOKS_KSERFO2X_POS 11 /**< ERFOKS_KSERFO2X Position */ 212 #define MXC_F_FCR_ERFOKS_KSERFO2X ((uint32_t)(0x1UL << MXC_F_FCR_ERFOKS_KSERFO2X_POS)) /**< ERFOKS_KSERFO2X Mask */ 213 214 #define MXC_F_FCR_ERFOKS_KSCLKSEL_POS 12 /**< ERFOKS_KSCLKSEL Position */ 215 #define MXC_F_FCR_ERFOKS_KSCLKSEL ((uint32_t)(0x3UL << MXC_F_FCR_ERFOKS_KSCLKSEL_POS)) /**< ERFOKS_KSCLKSEL Mask */ 216 #define MXC_V_FCR_ERFOKS_KSCLKSEL_ISO ((uint32_t)0x2UL) /**< ERFOKS_KSCLKSEL_ISO Value */ 217 #define MXC_S_FCR_ERFOKS_KSCLKSEL_ISO (MXC_V_FCR_ERFOKS_KSCLKSEL_ISO << MXC_F_FCR_ERFOKS_KSCLKSEL_POS) /**< ERFOKS_KSCLKSEL_ISO Setting */ 218 #define MXC_V_FCR_ERFOKS_KSCLKSEL_IPO ((uint32_t)0x3UL) /**< ERFOKS_KSCLKSEL_IPO Value */ 219 #define MXC_S_FCR_ERFOKS_KSCLKSEL_IPO (MXC_V_FCR_ERFOKS_KSCLKSEL_IPO << MXC_F_FCR_ERFOKS_KSCLKSEL_POS) /**< ERFOKS_KSCLKSEL_IPO Setting */ 220 221 /**@} end of group FCR_ERFOKS_Register */ 222 223 #ifdef __cplusplus 224 } 225 #endif 226 227 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32680_INCLUDE_FCR_REGS_H_ 228
