1 /** 2 * @file afe_hart_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the AFE_HART Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup afe_hart_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32680_INCLUDE_AFE_HART_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32680_INCLUDE_AFE_HART_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup afe_hart 67 * @defgroup afe_hart_registers AFE_HART_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the AFE_HART Peripheral Module. 69 * @details Analog Front End HART Registers on Stacked Die via SPI 70 */ 71 72 /* Register offsets for module AFE_HART */ 73 /** 74 * @ingroup afe_hart_registers 75 * @defgroup AFE_HART_Register_Offsets Register Offsets 76 * @brief AFE_HART Peripheral Register Offsets from the AFE_HART Base Peripheral Address. 77 * @{ 78 */ 79 #define MXC_R_AFE_HART_CTRL ((uint32_t)0x01800003UL) /**< Offset from AFE_HART Base Address: <tt> 0x1800003</tt> */ 80 #define MXC_R_AFE_HART_RX_TX_CTL ((uint32_t)0x01810003UL) /**< Offset from AFE_HART Base Address: <tt> 0x1810003</tt> */ 81 #define MXC_R_AFE_HART_RX_CTL_EXT1 ((uint32_t)0x01820003UL) /**< Offset from AFE_HART Base Address: <tt> 0x1820003</tt> */ 82 #define MXC_R_AFE_HART_RX_CTL_EXT2 ((uint32_t)0x01830003UL) /**< Offset from AFE_HART Base Address: <tt> 0x1830003</tt> */ 83 #define MXC_R_AFE_HART_RX_DB_THRSHLD ((uint32_t)0x01840003UL) /**< Offset from AFE_HART Base Address: <tt> 0x1840003</tt> */ 84 #define MXC_R_AFE_HART_RX_CRD_UP_THRSHLD ((uint32_t)0x01850003UL) /**< Offset from AFE_HART Base Address: <tt> 0x1850003</tt> */ 85 #define MXC_R_AFE_HART_RX_CRD_DN_THRSHLD ((uint32_t)0x01860003UL) /**< Offset from AFE_HART Base Address: <tt> 0x1860003</tt> */ 86 #define MXC_R_AFE_HART_RX_CRD_DOUT_THRSHLD ((uint32_t)0x01870003UL) /**< Offset from AFE_HART Base Address: <tt> 0x1870003</tt> */ 87 #define MXC_R_AFE_HART_TX_MARKSPACE_CNT ((uint32_t)0x01880003UL) /**< Offset from AFE_HART Base Address: <tt> 0x1880003</tt> */ 88 #define MXC_R_AFE_HART_STAT ((uint32_t)0x01890003UL) /**< Offset from AFE_HART Base Address: <tt> 0x1890003</tt> */ 89 #define MXC_R_AFE_HART_TRIM ((uint32_t)0x018A0003UL) /**< Offset from AFE_HART Base Address: <tt> 0x18A0003</tt> */ 90 #define MXC_R_AFE_HART_TM ((uint32_t)0x018B0003UL) /**< Offset from AFE_HART Base Address: <tt> 0x18B0003</tt> */ 91 /**@} end of group afe_hart_registers */ 92 93 /** 94 * @ingroup afe_hart_registers 95 * @defgroup AFE_HART_CTRL AFE_HART_CTRL 96 * @brief HART Control 97 * @{ 98 */ 99 #define MXC_F_AFE_HART_CTRL_ADM_TM_EN_POS 0 /**< CTRL_ADM_TM_EN Position */ 100 #define MXC_F_AFE_HART_CTRL_ADM_TM_EN ((uint32_t)(0x1UL << MXC_F_AFE_HART_CTRL_ADM_TM_EN_POS)) /**< CTRL_ADM_TM_EN Mask */ 101 102 /**@} end of group AFE_HART_CTRL_Register */ 103 104 /** 105 * @ingroup afe_hart_registers 106 * @defgroup AFE_HART_RX_TX_CTL AFE_HART_RX_TX_CTL 107 * @brief Control HART Transmit and Receive Functions 108 * @{ 109 */ 110 #define MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_REF_EN_POS 0 /**< RX_TX_CTL_RX_ADC_REF_EN Position */ 111 #define MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_REF_EN ((uint32_t)(0x1UL << MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_REF_EN_POS)) /**< RX_TX_CTL_RX_ADC_REF_EN Mask */ 112 113 #define MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_REFBUF_EN_POS 1 /**< RX_TX_CTL_RX_ADC_REFBUF_EN Position */ 114 #define MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_REFBUF_EN ((uint32_t)(0x1UL << MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_REFBUF_EN_POS)) /**< RX_TX_CTL_RX_ADC_REFBUF_EN Mask */ 115 116 #define MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_OFFSET_SEL_POS 2 /**< RX_TX_CTL_RX_ADC_OFFSET_SEL Position */ 117 #define MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_OFFSET_SEL ((uint32_t)(0x1UL << MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_OFFSET_SEL_POS)) /**< RX_TX_CTL_RX_ADC_OFFSET_SEL Mask */ 118 119 #define MXC_F_AFE_HART_RX_TX_CTL_RX_DOUT_UART_EN_POS 3 /**< RX_TX_CTL_RX_DOUT_UART_EN Position */ 120 #define MXC_F_AFE_HART_RX_TX_CTL_RX_DOUT_UART_EN ((uint32_t)(0x1UL << MXC_F_AFE_HART_RX_TX_CTL_RX_DOUT_UART_EN_POS)) /**< RX_TX_CTL_RX_DOUT_UART_EN Mask */ 121 122 #define MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_PWR_UP_SMP_IGNR_POS 4 /**< RX_TX_CTL_RX_ADC_PWR_UP_SMP_IGNR Position */ 123 #define MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_PWR_UP_SMP_IGNR ((uint32_t)(0xFUL << MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_PWR_UP_SMP_IGNR_POS)) /**< RX_TX_CTL_RX_ADC_PWR_UP_SMP_IGNR Mask */ 124 125 #define MXC_F_AFE_HART_RX_TX_CTL_RX_BP_SETTLE_CNT_POS 8 /**< RX_TX_CTL_RX_BP_SETTLE_CNT Position */ 126 #define MXC_F_AFE_HART_RX_TX_CTL_RX_BP_SETTLE_CNT ((uint32_t)(0xFFUL << MXC_F_AFE_HART_RX_TX_CTL_RX_BP_SETTLE_CNT_POS)) /**< RX_TX_CTL_RX_BP_SETTLE_CNT Mask */ 127 128 #define MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_PWR_DLY_CNT_POS 16 /**< RX_TX_CTL_RX_ADC_PWR_DLY_CNT Position */ 129 #define MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_PWR_DLY_CNT ((uint32_t)(0xFUL << MXC_F_AFE_HART_RX_TX_CTL_RX_ADC_PWR_DLY_CNT_POS)) /**< RX_TX_CTL_RX_ADC_PWR_DLY_CNT Mask */ 130 131 #define MXC_F_AFE_HART_RX_TX_CTL_TX_BUF_EN_POS 20 /**< RX_TX_CTL_TX_BUF_EN Position */ 132 #define MXC_F_AFE_HART_RX_TX_CTL_TX_BUF_EN ((uint32_t)(0x1UL << MXC_F_AFE_HART_RX_TX_CTL_TX_BUF_EN_POS)) /**< RX_TX_CTL_TX_BUF_EN Mask */ 133 134 #define MXC_F_AFE_HART_RX_TX_CTL_TX_BUS_DCL_EN_POS 21 /**< RX_TX_CTL_TX_BUS_DCL_EN Position */ 135 #define MXC_F_AFE_HART_RX_TX_CTL_TX_BUS_DCL_EN ((uint32_t)(0x1UL << MXC_F_AFE_HART_RX_TX_CTL_TX_BUS_DCL_EN_POS)) /**< RX_TX_CTL_TX_BUS_DCL_EN Mask */ 136 137 #define MXC_F_AFE_HART_RX_TX_CTL_TX_WS_DIS_RS_POS 22 /**< RX_TX_CTL_TX_WS_DIS_RS Position */ 138 #define MXC_F_AFE_HART_RX_TX_CTL_TX_WS_DIS_RS ((uint32_t)(0x1UL << MXC_F_AFE_HART_RX_TX_CTL_TX_WS_DIS_RS_POS)) /**< RX_TX_CTL_TX_WS_DIS_RS Mask */ 139 140 #define MXC_F_AFE_HART_RX_TX_CTL_TX_4MHZ_CLK_EN_POS 23 /**< RX_TX_CTL_TX_4MHZ_CLK_EN Position */ 141 #define MXC_F_AFE_HART_RX_TX_CTL_TX_4MHZ_CLK_EN ((uint32_t)(0x1UL << MXC_F_AFE_HART_RX_TX_CTL_TX_4MHZ_CLK_EN_POS)) /**< RX_TX_CTL_TX_4MHZ_CLK_EN Mask */ 142 143 /**@} end of group AFE_HART_RX_TX_CTL_Register */ 144 145 /** 146 * @ingroup afe_hart_registers 147 * @defgroup AFE_HART_RX_CTL_EXT1 AFE_HART_RX_CTL_EXT1 148 * @brief Receive Control Extension Register 1 149 * @{ 150 */ 151 #define MXC_F_AFE_HART_RX_CTL_EXT1_RX_AN_INIT_VAL_POS 0 /**< RX_CTL_EXT1_RX_AN_INIT_VAL Position */ 152 #define MXC_F_AFE_HART_RX_CTL_EXT1_RX_AN_INIT_VAL ((uint32_t)(0x7FFFFUL << MXC_F_AFE_HART_RX_CTL_EXT1_RX_AN_INIT_VAL_POS)) /**< RX_CTL_EXT1_RX_AN_INIT_VAL Mask */ 153 154 /**@} end of group AFE_HART_RX_CTL_EXT1_Register */ 155 156 /** 157 * @ingroup afe_hart_registers 158 * @defgroup AFE_HART_RX_CTL_EXT2 AFE_HART_RX_CTL_EXT2 159 * @brief Receive Control Extension Register 2 160 * @{ 161 */ 162 #define MXC_F_AFE_HART_RX_CTL_EXT2_RX_ARN_INIT_VAL_POS 0 /**< RX_CTL_EXT2_RX_ARN_INIT_VAL Position */ 163 #define MXC_F_AFE_HART_RX_CTL_EXT2_RX_ARN_INIT_VAL ((uint32_t)(0x7FFFUL << MXC_F_AFE_HART_RX_CTL_EXT2_RX_ARN_INIT_VAL_POS)) /**< RX_CTL_EXT2_RX_ARN_INIT_VAL Mask */ 164 165 #define MXC_F_AFE_HART_RX_CTL_EXT2_RX_ZC_IGN_VAL_POS 16 /**< RX_CTL_EXT2_RX_ZC_IGN_VAL Position */ 166 #define MXC_F_AFE_HART_RX_CTL_EXT2_RX_ZC_IGN_VAL ((uint32_t)(0x3UL << MXC_F_AFE_HART_RX_CTL_EXT2_RX_ZC_IGN_VAL_POS)) /**< RX_CTL_EXT2_RX_ZC_IGN_VAL Mask */ 167 168 #define MXC_F_AFE_HART_RX_CTL_EXT2_RX_UART_TIMER_SYN_ALWS_EN_POS 20 /**< RX_CTL_EXT2_RX_UART_TIMER_SYN_ALWS_EN Position */ 169 #define MXC_F_AFE_HART_RX_CTL_EXT2_RX_UART_TIMER_SYN_ALWS_EN ((uint32_t)(0x1UL << MXC_F_AFE_HART_RX_CTL_EXT2_RX_UART_TIMER_SYN_ALWS_EN_POS)) /**< RX_CTL_EXT2_RX_UART_TIMER_SYN_ALWS_EN Mask */ 170 171 #define MXC_F_AFE_HART_RX_CTL_EXT2_RX_UART_TIMER_FAST_CNT_EN_POS 21 /**< RX_CTL_EXT2_RX_UART_TIMER_FAST_CNT_EN Position */ 172 #define MXC_F_AFE_HART_RX_CTL_EXT2_RX_UART_TIMER_FAST_CNT_EN ((uint32_t)(0x1UL << MXC_F_AFE_HART_RX_CTL_EXT2_RX_UART_TIMER_FAST_CNT_EN_POS)) /**< RX_CTL_EXT2_RX_UART_TIMER_FAST_CNT_EN Mask */ 173 174 /**@} end of group AFE_HART_RX_CTL_EXT2_Register */ 175 176 /** 177 * @ingroup afe_hart_registers 178 * @defgroup AFE_HART_RX_DB_THRSHLD AFE_HART_RX_DB_THRSHLD 179 * @brief Receive Bit-Detect/Demodulation Threshold 180 * @{ 181 */ 182 #define MXC_F_AFE_HART_RX_DB_THRSHLD_RX_BITDTCT_DN_THRSHLD_POS 0 /**< RX_DB_THRSHLD_RX_BITDTCT_DN_THRSHLD Position */ 183 #define MXC_F_AFE_HART_RX_DB_THRSHLD_RX_BITDTCT_DN_THRSHLD ((uint32_t)(0x1FFUL << MXC_F_AFE_HART_RX_DB_THRSHLD_RX_BITDTCT_DN_THRSHLD_POS)) /**< RX_DB_THRSHLD_RX_BITDTCT_DN_THRSHLD Mask */ 184 185 #define MXC_F_AFE_HART_RX_DB_THRSHLD_RX_BITDTCT_UP_THRSHLD_POS 12 /**< RX_DB_THRSHLD_RX_BITDTCT_UP_THRSHLD Position */ 186 #define MXC_F_AFE_HART_RX_DB_THRSHLD_RX_BITDTCT_UP_THRSHLD ((uint32_t)(0x1FFUL << MXC_F_AFE_HART_RX_DB_THRSHLD_RX_BITDTCT_UP_THRSHLD_POS)) /**< RX_DB_THRSHLD_RX_BITDTCT_UP_THRSHLD Mask */ 187 188 /**@} end of group AFE_HART_RX_DB_THRSHLD_Register */ 189 190 /** 191 * @ingroup afe_hart_registers 192 * @defgroup AFE_HART_RX_CRD_UP_THRSHLD AFE_HART_RX_CRD_UP_THRSHLD 193 * @brief Receive Carrier Detect Up Threshold Register 194 * @{ 195 */ 196 #define MXC_F_AFE_HART_RX_CRD_UP_THRSHLD_RX_CRD_UP_THRSHLD_POS 0 /**< RX_CRD_UP_THRSHLD_RX_CRD_UP_THRSHLD Position */ 197 #define MXC_F_AFE_HART_RX_CRD_UP_THRSHLD_RX_CRD_UP_THRSHLD ((uint32_t)(0x7FFFFUL << MXC_F_AFE_HART_RX_CRD_UP_THRSHLD_RX_CRD_UP_THRSHLD_POS)) /**< RX_CRD_UP_THRSHLD_RX_CRD_UP_THRSHLD Mask */ 198 199 /**@} end of group AFE_HART_RX_CRD_UP_THRSHLD_Register */ 200 201 /** 202 * @ingroup afe_hart_registers 203 * @defgroup AFE_HART_RX_CRD_DN_THRSHLD AFE_HART_RX_CRD_DN_THRSHLD 204 * @brief Receive Carrier Detect Down Threshold Register 205 * @{ 206 */ 207 #define MXC_F_AFE_HART_RX_CRD_DN_THRSHLD_RX_CRD_DN_THRSHLD_POS 0 /**< RX_CRD_DN_THRSHLD_RX_CRD_DN_THRSHLD Position */ 208 #define MXC_F_AFE_HART_RX_CRD_DN_THRSHLD_RX_CRD_DN_THRSHLD ((uint32_t)(0x7FFFFUL << MXC_F_AFE_HART_RX_CRD_DN_THRSHLD_RX_CRD_DN_THRSHLD_POS)) /**< RX_CRD_DN_THRSHLD_RX_CRD_DN_THRSHLD Mask */ 209 210 /**@} end of group AFE_HART_RX_CRD_DN_THRSHLD_Register */ 211 212 /** 213 * @ingroup afe_hart_registers 214 * @defgroup AFE_HART_RX_CRD_DOUT_THRSHLD AFE_HART_RX_CRD_DOUT_THRSHLD 215 * @brief Receive Carrier Detect DOUT Threshold 216 * @{ 217 */ 218 #define MXC_F_AFE_HART_RX_CRD_DOUT_THRSHLD_RX_CRD_DOUT_THRSHLD_POS 0 /**< RX_CRD_DOUT_THRSHLD_RX_CRD_DOUT_THRSHLD Position */ 219 #define MXC_F_AFE_HART_RX_CRD_DOUT_THRSHLD_RX_CRD_DOUT_THRSHLD ((uint32_t)(0x7FFFFUL << MXC_F_AFE_HART_RX_CRD_DOUT_THRSHLD_RX_CRD_DOUT_THRSHLD_POS)) /**< RX_CRD_DOUT_THRSHLD_RX_CRD_DOUT_THRSHLD Mask */ 220 221 /**@} end of group AFE_HART_RX_CRD_DOUT_THRSHLD_Register */ 222 223 /** 224 * @ingroup afe_hart_registers 225 * @defgroup AFE_HART_TX_MARKSPACE_CNT AFE_HART_TX_MARKSPACE_CNT 226 * @brief Transmit Mark-Space Count Values 227 * @{ 228 */ 229 #define MXC_F_AFE_HART_TX_MARKSPACE_CNT_TX_SPACE_CNT_POS 0 /**< TX_MARKSPACE_CNT_TX_SPACE_CNT Position */ 230 #define MXC_F_AFE_HART_TX_MARKSPACE_CNT_TX_SPACE_CNT ((uint32_t)(0x3FFUL << MXC_F_AFE_HART_TX_MARKSPACE_CNT_TX_SPACE_CNT_POS)) /**< TX_MARKSPACE_CNT_TX_SPACE_CNT Mask */ 231 232 #define MXC_F_AFE_HART_TX_MARKSPACE_CNT_TX_MARK_CNT_POS 12 /**< TX_MARKSPACE_CNT_TX_MARK_CNT Position */ 233 #define MXC_F_AFE_HART_TX_MARKSPACE_CNT_TX_MARK_CNT ((uint32_t)(0x3FFUL << MXC_F_AFE_HART_TX_MARKSPACE_CNT_TX_MARK_CNT_POS)) /**< TX_MARKSPACE_CNT_TX_MARK_CNT Mask */ 234 235 /**@} end of group AFE_HART_TX_MARKSPACE_CNT_Register */ 236 237 /** 238 * @ingroup afe_hart_registers 239 * @defgroup AFE_HART_TRIM AFE_HART_TRIM 240 * @brief HART Trim Register 241 * @{ 242 */ 243 #define MXC_F_AFE_HART_TRIM_TRIM_BIAS_POS 0 /**< TRIM_TRIM_BIAS Position */ 244 #define MXC_F_AFE_HART_TRIM_TRIM_BIAS ((uint32_t)(0x1FUL << MXC_F_AFE_HART_TRIM_TRIM_BIAS_POS)) /**< TRIM_TRIM_BIAS Mask */ 245 246 #define MXC_F_AFE_HART_TRIM_TRIM_BG_POS 8 /**< TRIM_TRIM_BG Position */ 247 #define MXC_F_AFE_HART_TRIM_TRIM_BG ((uint32_t)(0x3FUL << MXC_F_AFE_HART_TRIM_TRIM_BG_POS)) /**< TRIM_TRIM_BG Mask */ 248 249 #define MXC_F_AFE_HART_TRIM_TRIM_TX_SR_POS 16 /**< TRIM_TRIM_TX_SR Position */ 250 #define MXC_F_AFE_HART_TRIM_TRIM_TX_SR ((uint32_t)(0xFUL << MXC_F_AFE_HART_TRIM_TRIM_TX_SR_POS)) /**< TRIM_TRIM_TX_SR Mask */ 251 252 /**@} end of group AFE_HART_TRIM_Register */ 253 254 /** 255 * @ingroup afe_hart_registers 256 * @defgroup AFE_HART_TM AFE_HART_TM 257 * @brief Testmode 258 * @{ 259 */ 260 #define MXC_F_AFE_HART_TM_TM_EN_POS 0 /**< TM_TM_EN Position */ 261 #define MXC_F_AFE_HART_TM_TM_EN ((uint32_t)(0x1UL << MXC_F_AFE_HART_TM_TM_EN_POS)) /**< TM_TM_EN Mask */ 262 263 #define MXC_F_AFE_HART_TM_TM_BIAS_EN_POS 1 /**< TM_TM_BIAS_EN Position */ 264 #define MXC_F_AFE_HART_TM_TM_BIAS_EN ((uint32_t)(0x1UL << MXC_F_AFE_HART_TM_TM_BIAS_EN_POS)) /**< TM_TM_BIAS_EN Mask */ 265 266 #define MXC_F_AFE_HART_TM_TM_BG_EN_POS 3 /**< TM_TM_BG_EN Position */ 267 #define MXC_F_AFE_HART_TM_TM_BG_EN ((uint32_t)(0x1UL << MXC_F_AFE_HART_TM_TM_BG_EN_POS)) /**< TM_TM_BG_EN Mask */ 268 269 #define MXC_F_AFE_HART_TM_TM_VREF_EN_POS 3 /**< TM_TM_VREF_EN Position */ 270 #define MXC_F_AFE_HART_TM_TM_VREF_EN ((uint32_t)(0x1UL << MXC_F_AFE_HART_TM_TM_VREF_EN_POS)) /**< TM_TM_VREF_EN Mask */ 271 272 /**@} end of group AFE_HART_TM_Register */ 273 274 #ifdef __cplusplus 275 } 276 #endif 277 278 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32680_INCLUDE_AFE_HART_REGS_H_ 279
