1 /** 2 * @file afe_dac_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the AFE_DAC Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup afe_dac_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32680_INCLUDE_AFE_DAC_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32680_INCLUDE_AFE_DAC_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup afe_dac 67 * @defgroup afe_dac_registers AFE_DAC_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the AFE_DAC Peripheral Module. 69 * @details Analog Front End DAC on Stacked Die via SPI 70 */ 71 72 /* Register offsets for module AFE_DAC */ 73 /** 74 * @ingroup afe_dac_registers 75 * @defgroup AFE_DAC_Register_Offsets Register Offsets 76 * @brief AFE_DAC Peripheral Register Offsets from the AFE_DAC Base Peripheral Address. 77 * @{ 78 */ 79 #define MXC_R_AFE_DAC_CTRL ((uint32_t)0x01000004UL) /**< Offset from AFE_DAC Base Address: <tt> 0x1000004</tt> */ 80 #define MXC_R_AFE_DAC_RATE ((uint32_t)0x01010004UL) /**< Offset from AFE_DAC Base Address: <tt> 0x1010004</tt> */ 81 #define MXC_R_AFE_DAC_INT ((uint32_t)0x01020004UL) /**< Offset from AFE_DAC Base Address: <tt> 0x1020004</tt> */ 82 #define MXC_R_AFE_DAC_REG ((uint32_t)0x01030004UL) /**< Offset from AFE_DAC Base Address: <tt> 0x1030004</tt> */ 83 #define MXC_R_AFE_DAC_TRIM ((uint32_t)0x01040004UL) /**< Offset from AFE_DAC Base Address: <tt> 0x1040004</tt> */ 84 #define MXC_R_AFE_DAC_VREF_CTRL ((uint32_t)0x01050002UL) /**< Offset from AFE_DAC Base Address: <tt> 0x1050002</tt> */ 85 #define MXC_R_AFE_DAC_FIFO ((uint32_t)0x01060002UL) /**< Offset from AFE_DAC Base Address: <tt> 0x1060002</tt> */ 86 #define MXC_R_AFE_DAC_VREF_TRIM ((uint32_t)0x01070002UL) /**< Offset from AFE_DAC Base Address: <tt> 0x1070002</tt> */ 87 /**@} end of group afe_dac_registers */ 88 89 /** 90 * @ingroup afe_dac_registers 91 * @defgroup AFE_DAC_CTRL AFE_DAC_CTRL 92 * @brief Control Register 93 * @{ 94 */ 95 #define MXC_F_AFE_DAC_CTRL_FIFO_AE_CNT_POS 0 /**< CTRL_FIFO_AE_CNT Position */ 96 #define MXC_F_AFE_DAC_CTRL_FIFO_AE_CNT ((uint32_t)(0xFUL << MXC_F_AFE_DAC_CTRL_FIFO_AE_CNT_POS)) /**< CTRL_FIFO_AE_CNT Mask */ 97 98 #define MXC_F_AFE_DAC_CTRL_FIFO_ALMOST_FULL_POS 5 /**< CTRL_FIFO_ALMOST_FULL Position */ 99 #define MXC_F_AFE_DAC_CTRL_FIFO_ALMOST_FULL ((uint32_t)(0x1UL << MXC_F_AFE_DAC_CTRL_FIFO_ALMOST_FULL_POS)) /**< CTRL_FIFO_ALMOST_FULL Mask */ 100 101 #define MXC_F_AFE_DAC_CTRL_FIFO_EMPTY_POS 6 /**< CTRL_FIFO_EMPTY Position */ 102 #define MXC_F_AFE_DAC_CTRL_FIFO_EMPTY ((uint32_t)(0x1UL << MXC_F_AFE_DAC_CTRL_FIFO_EMPTY_POS)) /**< CTRL_FIFO_EMPTY Mask */ 103 104 #define MXC_F_AFE_DAC_CTRL_FIFO_ALMOST_EMPTY_POS 7 /**< CTRL_FIFO_ALMOST_EMPTY Position */ 105 #define MXC_F_AFE_DAC_CTRL_FIFO_ALMOST_EMPTY ((uint32_t)(0x1UL << MXC_F_AFE_DAC_CTRL_FIFO_ALMOST_EMPTY_POS)) /**< CTRL_FIFO_ALMOST_EMPTY Mask */ 106 107 #define MXC_F_AFE_DAC_CTRL_INTERP_MODE_POS 8 /**< CTRL_INTERP_MODE Position */ 108 #define MXC_F_AFE_DAC_CTRL_INTERP_MODE ((uint32_t)(0x7UL << MXC_F_AFE_DAC_CTRL_INTERP_MODE_POS)) /**< CTRL_INTERP_MODE Mask */ 109 #define MXC_V_AFE_DAC_CTRL_INTERP_MODE_DISABLED ((uint32_t)0x0UL) /**< CTRL_INTERP_MODE_DISABLED Value */ 110 #define MXC_S_AFE_DAC_CTRL_INTERP_MODE_DISABLED (MXC_V_AFE_DAC_CTRL_INTERP_MODE_DISABLED << MXC_F_AFE_DAC_CTRL_INTERP_MODE_POS) /**< CTRL_INTERP_MODE_DISABLED Setting */ 111 #define MXC_V_AFE_DAC_CTRL_INTERP_MODE_2_TO_1_INTERPOLATION ((uint32_t)0x1UL) /**< CTRL_INTERP_MODE_2_TO_1_INTERPOLATION Value */ 112 #define MXC_S_AFE_DAC_CTRL_INTERP_MODE_2_TO_1_INTERPOLATION (MXC_V_AFE_DAC_CTRL_INTERP_MODE_2_TO_1_INTERPOLATION << MXC_F_AFE_DAC_CTRL_INTERP_MODE_POS) /**< CTRL_INTERP_MODE_2_TO_1_INTERPOLATION Setting */ 113 #define MXC_V_AFE_DAC_CTRL_INTERP_MODE_4_TO_1_INTERPOLATION ((uint32_t)0x2UL) /**< CTRL_INTERP_MODE_4_TO_1_INTERPOLATION Value */ 114 #define MXC_S_AFE_DAC_CTRL_INTERP_MODE_4_TO_1_INTERPOLATION (MXC_V_AFE_DAC_CTRL_INTERP_MODE_4_TO_1_INTERPOLATION << MXC_F_AFE_DAC_CTRL_INTERP_MODE_POS) /**< CTRL_INTERP_MODE_4_TO_1_INTERPOLATION Setting */ 115 #define MXC_V_AFE_DAC_CTRL_INTERP_MODE_8_TO_1_INTERPOLATION ((uint32_t)0x3UL) /**< CTRL_INTERP_MODE_8_TO_1_INTERPOLATION Value */ 116 #define MXC_S_AFE_DAC_CTRL_INTERP_MODE_8_TO_1_INTERPOLATION (MXC_V_AFE_DAC_CTRL_INTERP_MODE_8_TO_1_INTERPOLATION << MXC_F_AFE_DAC_CTRL_INTERP_MODE_POS) /**< CTRL_INTERP_MODE_8_TO_1_INTERPOLATION Setting */ 117 118 #define MXC_F_AFE_DAC_CTRL_FIFO_AF_CNT_POS 12 /**< CTRL_FIFO_AF_CNT Position */ 119 #define MXC_F_AFE_DAC_CTRL_FIFO_AF_CNT ((uint32_t)(0xFUL << MXC_F_AFE_DAC_CTRL_FIFO_AF_CNT_POS)) /**< CTRL_FIFO_AF_CNT Mask */ 120 121 #define MXC_F_AFE_DAC_CTRL_START_MODE_POS 16 /**< CTRL_START_MODE Position */ 122 #define MXC_F_AFE_DAC_CTRL_START_MODE ((uint32_t)(0x3UL << MXC_F_AFE_DAC_CTRL_START_MODE_POS)) /**< CTRL_START_MODE Mask */ 123 #define MXC_V_AFE_DAC_CTRL_START_MODE_START_WHEN_FIFO_NOT_EMPTY ((uint32_t)0x0UL) /**< CTRL_START_MODE_START_WHEN_FIFO_NOT_EMPTY Value */ 124 #define MXC_S_AFE_DAC_CTRL_START_MODE_START_WHEN_FIFO_NOT_EMPTY (MXC_V_AFE_DAC_CTRL_START_MODE_START_WHEN_FIFO_NOT_EMPTY << MXC_F_AFE_DAC_CTRL_START_MODE_POS) /**< CTRL_START_MODE_START_WHEN_FIFO_NOT_EMPTY Setting */ 125 #define MXC_V_AFE_DAC_CTRL_START_MODE_START_ON_ADC_START_STROBE ((uint32_t)0x1UL) /**< CTRL_START_MODE_START_ON_ADC_START_STROBE Value */ 126 #define MXC_S_AFE_DAC_CTRL_START_MODE_START_ON_ADC_START_STROBE (MXC_V_AFE_DAC_CTRL_START_MODE_START_ON_ADC_START_STROBE << MXC_F_AFE_DAC_CTRL_START_MODE_POS) /**< CTRL_START_MODE_START_ON_ADC_START_STROBE Setting */ 127 #define MXC_V_AFE_DAC_CTRL_START_MODE_START_WHEN_CPU_START_WRITTEN ((uint32_t)0x2UL) /**< CTRL_START_MODE_START_WHEN_CPU_START_WRITTEN Value */ 128 #define MXC_S_AFE_DAC_CTRL_START_MODE_START_WHEN_CPU_START_WRITTEN (MXC_V_AFE_DAC_CTRL_START_MODE_START_WHEN_CPU_START_WRITTEN << MXC_F_AFE_DAC_CTRL_START_MODE_POS) /**< CTRL_START_MODE_START_WHEN_CPU_START_WRITTEN Setting */ 129 #define MXC_V_AFE_DAC_CTRL_START_MODE_RESERVED ((uint32_t)0x3UL) /**< CTRL_START_MODE_RESERVED Value */ 130 #define MXC_S_AFE_DAC_CTRL_START_MODE_RESERVED (MXC_V_AFE_DAC_CTRL_START_MODE_RESERVED << MXC_F_AFE_DAC_CTRL_START_MODE_POS) /**< CTRL_START_MODE_RESERVED Setting */ 131 132 #define MXC_F_AFE_DAC_CTRL_ACTIVE_POS 18 /**< CTRL_ACTIVE Position */ 133 #define MXC_F_AFE_DAC_CTRL_ACTIVE ((uint32_t)(0x1UL << MXC_F_AFE_DAC_CTRL_ACTIVE_POS)) /**< CTRL_ACTIVE Mask */ 134 135 #define MXC_F_AFE_DAC_CTRL_BIN2GRAY_BYPASS_POS 19 /**< CTRL_BIN2GRAY_BYPASS Position */ 136 #define MXC_F_AFE_DAC_CTRL_BIN2GRAY_BYPASS ((uint32_t)(0x1UL << MXC_F_AFE_DAC_CTRL_BIN2GRAY_BYPASS_POS)) /**< CTRL_BIN2GRAY_BYPASS Mask */ 137 138 #define MXC_F_AFE_DAC_CTRL_CPU_START_POS 20 /**< CTRL_CPU_START Position */ 139 #define MXC_F_AFE_DAC_CTRL_CPU_START ((uint32_t)(0x1UL << MXC_F_AFE_DAC_CTRL_CPU_START_POS)) /**< CTRL_CPU_START Mask */ 140 141 #define MXC_F_AFE_DAC_CTRL_OP_MODE_POS 24 /**< CTRL_OP_MODE Position */ 142 #define MXC_F_AFE_DAC_CTRL_OP_MODE ((uint32_t)(0x3UL << MXC_F_AFE_DAC_CTRL_OP_MODE_POS)) /**< CTRL_OP_MODE Mask */ 143 #define MXC_V_AFE_DAC_CTRL_OP_MODE_OUTPUT_WHEN_FIFO_AVAIL ((uint32_t)0x0UL) /**< CTRL_OP_MODE_OUTPUT_WHEN_FIFO_AVAIL Value */ 144 #define MXC_S_AFE_DAC_CTRL_OP_MODE_OUTPUT_WHEN_FIFO_AVAIL (MXC_V_AFE_DAC_CTRL_OP_MODE_OUTPUT_WHEN_FIFO_AVAIL << MXC_F_AFE_DAC_CTRL_OP_MODE_POS) /**< CTRL_OP_MODE_OUTPUT_WHEN_FIFO_AVAIL Setting */ 145 #define MXC_V_AFE_DAC_CTRL_OP_MODE_OUTPUT_ONCE_AT_RATE_CNT ((uint32_t)0x1UL) /**< CTRL_OP_MODE_OUTPUT_ONCE_AT_RATE_CNT Value */ 146 #define MXC_S_AFE_DAC_CTRL_OP_MODE_OUTPUT_ONCE_AT_RATE_CNT (MXC_V_AFE_DAC_CTRL_OP_MODE_OUTPUT_ONCE_AT_RATE_CNT << MXC_F_AFE_DAC_CTRL_OP_MODE_POS) /**< CTRL_OP_MODE_OUTPUT_ONCE_AT_RATE_CNT Setting */ 147 #define MXC_V_AFE_DAC_CTRL_OP_MODE_RESERVED ((uint32_t)0x2UL) /**< CTRL_OP_MODE_RESERVED Value */ 148 #define MXC_S_AFE_DAC_CTRL_OP_MODE_RESERVED (MXC_V_AFE_DAC_CTRL_OP_MODE_RESERVED << MXC_F_AFE_DAC_CTRL_OP_MODE_POS) /**< CTRL_OP_MODE_RESERVED Setting */ 149 #define MXC_V_AFE_DAC_CTRL_OP_MODE_OUTPUT_SAMPLE_CNT_AT_RATE_CNT ((uint32_t)0x3UL) /**< CTRL_OP_MODE_OUTPUT_SAMPLE_CNT_AT_RATE_CNT Value */ 150 #define MXC_S_AFE_DAC_CTRL_OP_MODE_OUTPUT_SAMPLE_CNT_AT_RATE_CNT (MXC_V_AFE_DAC_CTRL_OP_MODE_OUTPUT_SAMPLE_CNT_AT_RATE_CNT << MXC_F_AFE_DAC_CTRL_OP_MODE_POS) /**< CTRL_OP_MODE_OUTPUT_SAMPLE_CNT_AT_RATE_CNT Setting */ 151 152 #define MXC_F_AFE_DAC_CTRL_POWER_MODE_1_0_POS 26 /**< CTRL_POWER_MODE_1_0 Position */ 153 #define MXC_F_AFE_DAC_CTRL_POWER_MODE_1_0 ((uint32_t)(0x3UL << MXC_F_AFE_DAC_CTRL_POWER_MODE_1_0_POS)) /**< CTRL_POWER_MODE_1_0 Mask */ 154 #define MXC_V_AFE_DAC_CTRL_POWER_MODE_1_0_POWLVL0 ((uint32_t)0x1UL) /**< CTRL_POWER_MODE_1_0_POWLVL0 Value */ 155 #define MXC_S_AFE_DAC_CTRL_POWER_MODE_1_0_POWLVL0 (MXC_V_AFE_DAC_CTRL_POWER_MODE_1_0_POWLVL0 << MXC_F_AFE_DAC_CTRL_POWER_MODE_1_0_POS) /**< CTRL_POWER_MODE_1_0_POWLVL0 Setting */ 156 #define MXC_V_AFE_DAC_CTRL_POWER_MODE_1_0_POWLVL1 ((uint32_t)0x3UL) /**< CTRL_POWER_MODE_1_0_POWLVL1 Value */ 157 #define MXC_S_AFE_DAC_CTRL_POWER_MODE_1_0_POWLVL1 (MXC_V_AFE_DAC_CTRL_POWER_MODE_1_0_POWLVL1 << MXC_F_AFE_DAC_CTRL_POWER_MODE_1_0_POS) /**< CTRL_POWER_MODE_1_0_POWLVL1 Setting */ 158 #define MXC_V_AFE_DAC_CTRL_POWER_MODE_1_0_POWLVL2 ((uint32_t)0x1UL) /**< CTRL_POWER_MODE_1_0_POWLVL2 Value */ 159 #define MXC_S_AFE_DAC_CTRL_POWER_MODE_1_0_POWLVL2 (MXC_V_AFE_DAC_CTRL_POWER_MODE_1_0_POWLVL2 << MXC_F_AFE_DAC_CTRL_POWER_MODE_1_0_POS) /**< CTRL_POWER_MODE_1_0_POWLVL2 Setting */ 160 #define MXC_V_AFE_DAC_CTRL_POWER_MODE_1_0_POWLVL3 ((uint32_t)0x3UL) /**< CTRL_POWER_MODE_1_0_POWLVL3 Value */ 161 #define MXC_S_AFE_DAC_CTRL_POWER_MODE_1_0_POWLVL3 (MXC_V_AFE_DAC_CTRL_POWER_MODE_1_0_POWLVL3 << MXC_F_AFE_DAC_CTRL_POWER_MODE_1_0_POS) /**< CTRL_POWER_MODE_1_0_POWLVL3 Setting */ 162 163 #define MXC_F_AFE_DAC_CTRL_POWER_ON_POS 28 /**< CTRL_POWER_ON Position */ 164 #define MXC_F_AFE_DAC_CTRL_POWER_ON ((uint32_t)(0x1UL << MXC_F_AFE_DAC_CTRL_POWER_ON_POS)) /**< CTRL_POWER_ON Mask */ 165 166 #define MXC_F_AFE_DAC_CTRL_CLOCK_GATE_EN_POS 29 /**< CTRL_CLOCK_GATE_EN Position */ 167 #define MXC_F_AFE_DAC_CTRL_CLOCK_GATE_EN ((uint32_t)(0x1UL << MXC_F_AFE_DAC_CTRL_CLOCK_GATE_EN_POS)) /**< CTRL_CLOCK_GATE_EN Mask */ 168 169 #define MXC_F_AFE_DAC_CTRL_POWER_MODE_2_POS 30 /**< CTRL_POWER_MODE_2 Position */ 170 #define MXC_F_AFE_DAC_CTRL_POWER_MODE_2 ((uint32_t)(0x1UL << MXC_F_AFE_DAC_CTRL_POWER_MODE_2_POS)) /**< CTRL_POWER_MODE_2 Mask */ 171 172 #define MXC_F_AFE_DAC_CTRL_RESET_POS 31 /**< CTRL_RESET Position */ 173 #define MXC_F_AFE_DAC_CTRL_RESET ((uint32_t)(0x1UL << MXC_F_AFE_DAC_CTRL_RESET_POS)) /**< CTRL_RESET Mask */ 174 175 /**@} end of group AFE_DAC_CTRL_Register */ 176 177 /** 178 * @ingroup afe_dac_registers 179 * @defgroup AFE_DAC_RATE AFE_DAC_RATE 180 * @brief Rate/Sample Control 181 * @{ 182 */ 183 #define MXC_F_AFE_DAC_RATE_RATE_CNT_POS 0 /**< RATE_RATE_CNT Position */ 184 #define MXC_F_AFE_DAC_RATE_RATE_CNT ((uint32_t)(0xFFFFUL << MXC_F_AFE_DAC_RATE_RATE_CNT_POS)) /**< RATE_RATE_CNT Mask */ 185 186 #define MXC_F_AFE_DAC_RATE_SAMPLE_CNT_POS 16 /**< RATE_SAMPLE_CNT Position */ 187 #define MXC_F_AFE_DAC_RATE_SAMPLE_CNT ((uint32_t)(0xFFFFUL << MXC_F_AFE_DAC_RATE_SAMPLE_CNT_POS)) /**< RATE_SAMPLE_CNT Mask */ 188 189 /**@} end of group AFE_DAC_RATE_Register */ 190 191 /** 192 * @ingroup afe_dac_registers 193 * @defgroup AFE_DAC_INT AFE_DAC_INT 194 * @brief Interrupt Flags and Enable/Disable 195 * @{ 196 */ 197 #define MXC_F_AFE_DAC_INT_OUT_DONE_IF_POS 0 /**< INT_OUT_DONE_IF Position */ 198 #define MXC_F_AFE_DAC_INT_OUT_DONE_IF ((uint32_t)(0x1UL << MXC_F_AFE_DAC_INT_OUT_DONE_IF_POS)) /**< INT_OUT_DONE_IF Mask */ 199 200 #define MXC_F_AFE_DAC_INT_UNDERFLOW_IF_POS 1 /**< INT_UNDERFLOW_IF Position */ 201 #define MXC_F_AFE_DAC_INT_UNDERFLOW_IF ((uint32_t)(0x1UL << MXC_F_AFE_DAC_INT_UNDERFLOW_IF_POS)) /**< INT_UNDERFLOW_IF Mask */ 202 203 #define MXC_F_AFE_DAC_INT_ALMOST_EMPTY_IF_POS 2 /**< INT_ALMOST_EMPTY_IF Position */ 204 #define MXC_F_AFE_DAC_INT_ALMOST_EMPTY_IF ((uint32_t)(0x1UL << MXC_F_AFE_DAC_INT_ALMOST_EMPTY_IF_POS)) /**< INT_ALMOST_EMPTY_IF Mask */ 205 206 #define MXC_F_AFE_DAC_INT_UNDERLFOW_POS 3 /**< INT_UNDERLFOW Position */ 207 #define MXC_F_AFE_DAC_INT_UNDERLFOW ((uint32_t)(0x1UL << MXC_F_AFE_DAC_INT_UNDERLFOW_POS)) /**< INT_UNDERLFOW Mask */ 208 209 #define MXC_F_AFE_DAC_INT_OUT_DONE_IE_POS 16 /**< INT_OUT_DONE_IE Position */ 210 #define MXC_F_AFE_DAC_INT_OUT_DONE_IE ((uint32_t)(0x1UL << MXC_F_AFE_DAC_INT_OUT_DONE_IE_POS)) /**< INT_OUT_DONE_IE Mask */ 211 212 #define MXC_F_AFE_DAC_INT_UNDERFLOW_IE_POS 17 /**< INT_UNDERFLOW_IE Position */ 213 #define MXC_F_AFE_DAC_INT_UNDERFLOW_IE ((uint32_t)(0x1UL << MXC_F_AFE_DAC_INT_UNDERFLOW_IE_POS)) /**< INT_UNDERFLOW_IE Mask */ 214 215 #define MXC_F_AFE_DAC_INT_AHB_CG_DISABLE_POS 28 /**< INT_AHB_CG_DISABLE Position */ 216 #define MXC_F_AFE_DAC_INT_AHB_CG_DISABLE ((uint32_t)(0x1UL << MXC_F_AFE_DAC_INT_AHB_CG_DISABLE_POS)) /**< INT_AHB_CG_DISABLE Mask */ 217 218 #define MXC_F_AFE_DAC_INT_APB_CG_DISABLE_POS 29 /**< INT_APB_CG_DISABLE Position */ 219 #define MXC_F_AFE_DAC_INT_APB_CG_DISABLE ((uint32_t)(0x1UL << MXC_F_AFE_DAC_INT_APB_CG_DISABLE_POS)) /**< INT_APB_CG_DISABLE Mask */ 220 221 /**@} end of group AFE_DAC_INT_Register */ 222 223 /** 224 * @ingroup afe_dac_registers 225 * @defgroup AFE_DAC_VREF_CTRL AFE_DAC_VREF_CTRL 226 * @brief DAC VREF Control 227 * @{ 228 */ 229 #define MXC_F_AFE_DAC_VREF_CTRL_REF_DAC_FAST_PD_POS 0 /**< VREF_CTRL_REF_DAC_FAST_PD Position */ 230 #define MXC_F_AFE_DAC_VREF_CTRL_REF_DAC_FAST_PD ((uint16_t)(0x1UL << MXC_F_AFE_DAC_VREF_CTRL_REF_DAC_FAST_PD_POS)) /**< VREF_CTRL_REF_DAC_FAST_PD Mask */ 231 232 #define MXC_F_AFE_DAC_VREF_CTRL_DACREFSEL_POS 1 /**< VREF_CTRL_DACREFSEL Position */ 233 #define MXC_F_AFE_DAC_VREF_CTRL_DACREFSEL ((uint16_t)(0x3UL << MXC_F_AFE_DAC_VREF_CTRL_DACREFSEL_POS)) /**< VREF_CTRL_DACREFSEL Mask */ 234 #define MXC_V_AFE_DAC_VREF_CTRL_DACREFSEL_VOLTS_1_024 ((uint16_t)0x0UL) /**< VREF_CTRL_DACREFSEL_VOLTS_1_024 Value */ 235 #define MXC_S_AFE_DAC_VREF_CTRL_DACREFSEL_VOLTS_1_024 (MXC_V_AFE_DAC_VREF_CTRL_DACREFSEL_VOLTS_1_024 << MXC_F_AFE_DAC_VREF_CTRL_DACREFSEL_POS) /**< VREF_CTRL_DACREFSEL_VOLTS_1_024 Setting */ 236 #define MXC_V_AFE_DAC_VREF_CTRL_DACREFSEL_VOLTS_1_500 ((uint16_t)0x1UL) /**< VREF_CTRL_DACREFSEL_VOLTS_1_500 Value */ 237 #define MXC_S_AFE_DAC_VREF_CTRL_DACREFSEL_VOLTS_1_500 (MXC_V_AFE_DAC_VREF_CTRL_DACREFSEL_VOLTS_1_500 << MXC_F_AFE_DAC_VREF_CTRL_DACREFSEL_POS) /**< VREF_CTRL_DACREFSEL_VOLTS_1_500 Setting */ 238 #define MXC_V_AFE_DAC_VREF_CTRL_DACREFSEL_VOLTS_2_048 ((uint16_t)0x2UL) /**< VREF_CTRL_DACREFSEL_VOLTS_2_048 Value */ 239 #define MXC_S_AFE_DAC_VREF_CTRL_DACREFSEL_VOLTS_2_048 (MXC_V_AFE_DAC_VREF_CTRL_DACREFSEL_VOLTS_2_048 << MXC_F_AFE_DAC_VREF_CTRL_DACREFSEL_POS) /**< VREF_CTRL_DACREFSEL_VOLTS_2_048 Setting */ 240 #define MXC_V_AFE_DAC_VREF_CTRL_DACREFSEL_VOLTS_2_500 ((uint16_t)0x3UL) /**< VREF_CTRL_DACREFSEL_VOLTS_2_500 Value */ 241 #define MXC_S_AFE_DAC_VREF_CTRL_DACREFSEL_VOLTS_2_500 (MXC_V_AFE_DAC_VREF_CTRL_DACREFSEL_VOLTS_2_500 << MXC_F_AFE_DAC_VREF_CTRL_DACREFSEL_POS) /**< VREF_CTRL_DACREFSEL_VOLTS_2_500 Setting */ 242 243 #define MXC_F_AFE_DAC_VREF_CTRL_REFDAC_OUTEN_POS 3 /**< VREF_CTRL_REFDAC_OUTEN Position */ 244 #define MXC_F_AFE_DAC_VREF_CTRL_REFDAC_OUTEN ((uint16_t)(0x1UL << MXC_F_AFE_DAC_VREF_CTRL_REFDAC_OUTEN_POS)) /**< VREF_CTRL_REFDAC_OUTEN Mask */ 245 246 #define MXC_F_AFE_DAC_VREF_CTRL_REF_PU_POS 4 /**< VREF_CTRL_REF_PU Position */ 247 #define MXC_F_AFE_DAC_VREF_CTRL_REF_PU ((uint16_t)(0x1UL << MXC_F_AFE_DAC_VREF_CTRL_REF_PU_POS)) /**< VREF_CTRL_REF_PU Mask */ 248 249 #define MXC_F_AFE_DAC_VREF_CTRL_REFDAC_CP_POS 5 /**< VREF_CTRL_REFDAC_CP Position */ 250 #define MXC_F_AFE_DAC_VREF_CTRL_REFDAC_CP ((uint16_t)(0x1UL << MXC_F_AFE_DAC_VREF_CTRL_REFDAC_CP_POS)) /**< VREF_CTRL_REFDAC_CP Mask */ 251 252 #define MXC_F_AFE_DAC_VREF_CTRL_REFDAC_GAIN_POS 6 /**< VREF_CTRL_REFDAC_GAIN Position */ 253 #define MXC_F_AFE_DAC_VREF_CTRL_REFDAC_GAIN ((uint16_t)(0x3UL << MXC_F_AFE_DAC_VREF_CTRL_REFDAC_GAIN_POS)) /**< VREF_CTRL_REFDAC_GAIN Mask */ 254 #define MXC_V_AFE_DAC_VREF_CTRL_REFDAC_GAIN_DEFAULT_GAIN ((uint16_t)0x0UL) /**< VREF_CTRL_REFDAC_GAIN_DEFAULT_GAIN Value */ 255 #define MXC_S_AFE_DAC_VREF_CTRL_REFDAC_GAIN_DEFAULT_GAIN (MXC_V_AFE_DAC_VREF_CTRL_REFDAC_GAIN_DEFAULT_GAIN << MXC_F_AFE_DAC_VREF_CTRL_REFDAC_GAIN_POS) /**< VREF_CTRL_REFDAC_GAIN_DEFAULT_GAIN Setting */ 256 #define MXC_V_AFE_DAC_VREF_CTRL_REFDAC_GAIN_HIGHEST_GAIN ((uint16_t)0x1UL) /**< VREF_CTRL_REFDAC_GAIN_HIGHEST_GAIN Value */ 257 #define MXC_S_AFE_DAC_VREF_CTRL_REFDAC_GAIN_HIGHEST_GAIN (MXC_V_AFE_DAC_VREF_CTRL_REFDAC_GAIN_HIGHEST_GAIN << MXC_F_AFE_DAC_VREF_CTRL_REFDAC_GAIN_POS) /**< VREF_CTRL_REFDAC_GAIN_HIGHEST_GAIN Setting */ 258 259 #define MXC_F_AFE_DAC_VREF_CTRL_REF_ABUS_POS 8 /**< VREF_CTRL_REF_ABUS Position */ 260 #define MXC_F_AFE_DAC_VREF_CTRL_REF_ABUS ((uint16_t)(0xFUL << MXC_F_AFE_DAC_VREF_CTRL_REF_ABUS_POS)) /**< VREF_CTRL_REF_ABUS Mask */ 261 262 /**@} end of group AFE_DAC_VREF_CTRL_Register */ 263 264 /** 265 * @ingroup afe_dac_registers 266 * @defgroup AFE_DAC_FIFO AFE_DAC_FIFO 267 * @brief DAC FIFO 268 * @{ 269 */ 270 #define MXC_F_AFE_DAC_FIFO_FIFO_DATA_POS 0 /**< FIFO_FIFO_DATA Position */ 271 #define MXC_F_AFE_DAC_FIFO_FIFO_DATA ((uint16_t)(0xFFFFUL << MXC_F_AFE_DAC_FIFO_FIFO_DATA_POS)) /**< FIFO_FIFO_DATA Mask */ 272 273 /**@} end of group AFE_DAC_FIFO_Register */ 274 275 /** 276 * @ingroup afe_dac_registers 277 * @defgroup AFE_DAC_VREF_TRIM AFE_DAC_VREF_TRIM 278 * @brief Control behavior of GPIO1 279 * @{ 280 */ 281 #define MXC_F_AFE_DAC_VREF_TRIM_V1_TRIM_POS 0 /**< VREF_TRIM_V1_TRIM Position */ 282 #define MXC_F_AFE_DAC_VREF_TRIM_V1_TRIM ((uint16_t)(0x1FUL << MXC_F_AFE_DAC_VREF_TRIM_V1_TRIM_POS)) /**< VREF_TRIM_V1_TRIM Mask */ 283 284 #define MXC_F_AFE_DAC_VREF_TRIM_REF_BG_TRIM_POS 5 /**< VREF_TRIM_REF_BG_TRIM Position */ 285 #define MXC_F_AFE_DAC_VREF_TRIM_REF_BG_TRIM ((uint16_t)(0x3FUL << MXC_F_AFE_DAC_VREF_TRIM_REF_BG_TRIM_POS)) /**< VREF_TRIM_REF_BG_TRIM Mask */ 286 287 /**@} end of group AFE_DAC_VREF_TRIM_Register */ 288 289 #ifdef __cplusplus 290 } 291 #endif 292 293 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32680_INCLUDE_AFE_DAC_REGS_H_ 294
