1 /** 2 * @file adc_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the ADC Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup adc_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32680_INCLUDE_ADC_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32680_INCLUDE_ADC_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup adc 67 * @defgroup adc_registers ADC_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the ADC Peripheral Module. 69 * @details 10-bit Analog to Digital Converter 70 */ 71 72 /** 73 * @ingroup adc_registers 74 * Structure type to access the ADC Registers. 75 */ 76 typedef struct { 77 __IO uint32_t ctrl; /**< <tt>\b 0x0000:</tt> ADC CTRL Register */ 78 __IO uint32_t status; /**< <tt>\b 0x0004:</tt> ADC STATUS Register */ 79 __IO uint32_t data; /**< <tt>\b 0x0008:</tt> ADC DATA Register */ 80 __IO uint32_t intr; /**< <tt>\b 0x000C:</tt> ADC INTR Register */ 81 __IO uint32_t limit[4]; /**< <tt>\b 0x0010:</tt> ADC LIMIT Register */ 82 } mxc_adc_regs_t; 83 84 /* Register offsets for module ADC */ 85 /** 86 * @ingroup adc_registers 87 * @defgroup ADC_Register_Offsets Register Offsets 88 * @brief ADC Peripheral Register Offsets from the ADC Base Peripheral Address. 89 * @{ 90 */ 91 #define MXC_R_ADC_CTRL ((uint32_t)0x00000000UL) /**< Offset from ADC Base Address: <tt> 0x0000</tt> */ 92 #define MXC_R_ADC_STATUS ((uint32_t)0x00000004UL) /**< Offset from ADC Base Address: <tt> 0x0004</tt> */ 93 #define MXC_R_ADC_DATA ((uint32_t)0x00000008UL) /**< Offset from ADC Base Address: <tt> 0x0008</tt> */ 94 #define MXC_R_ADC_INTR ((uint32_t)0x0000000CUL) /**< Offset from ADC Base Address: <tt> 0x000C</tt> */ 95 #define MXC_R_ADC_LIMIT ((uint32_t)0x00000010UL) /**< Offset from ADC Base Address: <tt> 0x0010</tt> */ 96 /**@} end of group adc_registers */ 97 98 /** 99 * @ingroup adc_registers 100 * @defgroup ADC_CTRL ADC_CTRL 101 * @brief ADC Control 102 * @{ 103 */ 104 #define MXC_F_ADC_CTRL_START_POS 0 /**< CTRL_START Position */ 105 #define MXC_F_ADC_CTRL_START ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_START_POS)) /**< CTRL_START Mask */ 106 107 #define MXC_F_ADC_CTRL_PWR_POS 1 /**< CTRL_PWR Position */ 108 #define MXC_F_ADC_CTRL_PWR ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_PWR_POS)) /**< CTRL_PWR Mask */ 109 110 #define MXC_F_ADC_CTRL_REFBUF_PWR_POS 3 /**< CTRL_REFBUF_PWR Position */ 111 #define MXC_F_ADC_CTRL_REFBUF_PWR ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_REFBUF_PWR_POS)) /**< CTRL_REFBUF_PWR Mask */ 112 113 #define MXC_F_ADC_CTRL_REF_SEL_POS 4 /**< CTRL_REF_SEL Position */ 114 #define MXC_F_ADC_CTRL_REF_SEL ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_REF_SEL_POS)) /**< CTRL_REF_SEL Mask */ 115 116 #define MXC_F_ADC_CTRL_REF_SCALE_POS 8 /**< CTRL_REF_SCALE Position */ 117 #define MXC_F_ADC_CTRL_REF_SCALE ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_REF_SCALE_POS)) /**< CTRL_REF_SCALE Mask */ 118 119 #define MXC_F_ADC_CTRL_SCALE_POS 9 /**< CTRL_SCALE Position */ 120 #define MXC_F_ADC_CTRL_SCALE ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_SCALE_POS)) /**< CTRL_SCALE Mask */ 121 122 #define MXC_F_ADC_CTRL_CLK_EN_POS 11 /**< CTRL_CLK_EN Position */ 123 #define MXC_F_ADC_CTRL_CLK_EN ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_CLK_EN_POS)) /**< CTRL_CLK_EN Mask */ 124 125 #define MXC_F_ADC_CTRL_CH_SEL_POS 12 /**< CTRL_CH_SEL Position */ 126 #define MXC_F_ADC_CTRL_CH_SEL ((uint32_t)(0x1FUL << MXC_F_ADC_CTRL_CH_SEL_POS)) /**< CTRL_CH_SEL Mask */ 127 #define MXC_V_ADC_CTRL_CH_SEL_AIN0 ((uint32_t)0x0UL) /**< CTRL_CH_SEL_AIN0 Value */ 128 #define MXC_S_ADC_CTRL_CH_SEL_AIN0 (MXC_V_ADC_CTRL_CH_SEL_AIN0 << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN0 Setting */ 129 #define MXC_V_ADC_CTRL_CH_SEL_AIN1 ((uint32_t)0x1UL) /**< CTRL_CH_SEL_AIN1 Value */ 130 #define MXC_S_ADC_CTRL_CH_SEL_AIN1 (MXC_V_ADC_CTRL_CH_SEL_AIN1 << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN1 Setting */ 131 #define MXC_V_ADC_CTRL_CH_SEL_AIN2 ((uint32_t)0x2UL) /**< CTRL_CH_SEL_AIN2 Value */ 132 #define MXC_S_ADC_CTRL_CH_SEL_AIN2 (MXC_V_ADC_CTRL_CH_SEL_AIN2 << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN2 Setting */ 133 #define MXC_V_ADC_CTRL_CH_SEL_AIN3 ((uint32_t)0x3UL) /**< CTRL_CH_SEL_AIN3 Value */ 134 #define MXC_S_ADC_CTRL_CH_SEL_AIN3 (MXC_V_ADC_CTRL_CH_SEL_AIN3 << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN3 Setting */ 135 #define MXC_V_ADC_CTRL_CH_SEL_AIN4 ((uint32_t)0x4UL) /**< CTRL_CH_SEL_AIN4 Value */ 136 #define MXC_S_ADC_CTRL_CH_SEL_AIN4 (MXC_V_ADC_CTRL_CH_SEL_AIN4 << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN4 Setting */ 137 #define MXC_V_ADC_CTRL_CH_SEL_AIN5 ((uint32_t)0x5UL) /**< CTRL_CH_SEL_AIN5 Value */ 138 #define MXC_S_ADC_CTRL_CH_SEL_AIN5 (MXC_V_ADC_CTRL_CH_SEL_AIN5 << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN5 Setting */ 139 #define MXC_V_ADC_CTRL_CH_SEL_AIN6 ((uint32_t)0x6UL) /**< CTRL_CH_SEL_AIN6 Value */ 140 #define MXC_S_ADC_CTRL_CH_SEL_AIN6 (MXC_V_ADC_CTRL_CH_SEL_AIN6 << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN6 Setting */ 141 #define MXC_V_ADC_CTRL_CH_SEL_AIN7 ((uint32_t)0x7UL) /**< CTRL_CH_SEL_AIN7 Value */ 142 #define MXC_S_ADC_CTRL_CH_SEL_AIN7 (MXC_V_ADC_CTRL_CH_SEL_AIN7 << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN7 Setting */ 143 #define MXC_V_ADC_CTRL_CH_SEL_VCOREA ((uint32_t)0x8UL) /**< CTRL_CH_SEL_VCOREA Value */ 144 #define MXC_S_ADC_CTRL_CH_SEL_VCOREA (MXC_V_ADC_CTRL_CH_SEL_VCOREA << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VCOREA Setting */ 145 #define MXC_V_ADC_CTRL_CH_SEL_VCOREB ((uint32_t)0x9UL) /**< CTRL_CH_SEL_VCOREB Value */ 146 #define MXC_S_ADC_CTRL_CH_SEL_VCOREB (MXC_V_ADC_CTRL_CH_SEL_VCOREB << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VCOREB Setting */ 147 #define MXC_V_ADC_CTRL_CH_SEL_VRXOUT ((uint32_t)0xAUL) /**< CTRL_CH_SEL_VRXOUT Value */ 148 #define MXC_S_ADC_CTRL_CH_SEL_VRXOUT (MXC_V_ADC_CTRL_CH_SEL_VRXOUT << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VRXOUT Setting */ 149 #define MXC_V_ADC_CTRL_CH_SEL_VTXOUT ((uint32_t)0xBUL) /**< CTRL_CH_SEL_VTXOUT Value */ 150 #define MXC_S_ADC_CTRL_CH_SEL_VTXOUT (MXC_V_ADC_CTRL_CH_SEL_VTXOUT << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VTXOUT Setting */ 151 #define MXC_V_ADC_CTRL_CH_SEL_VDDA ((uint32_t)0xCUL) /**< CTRL_CH_SEL_VDDA Value */ 152 #define MXC_S_ADC_CTRL_CH_SEL_VDDA (MXC_V_ADC_CTRL_CH_SEL_VDDA << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VDDA Setting */ 153 #define MXC_V_ADC_CTRL_CH_SEL_VDDB ((uint32_t)0xDUL) /**< CTRL_CH_SEL_VDDB Value */ 154 #define MXC_S_ADC_CTRL_CH_SEL_VDDB (MXC_V_ADC_CTRL_CH_SEL_VDDB << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VDDB Setting */ 155 #define MXC_V_ADC_CTRL_CH_SEL_VDDIO ((uint32_t)0xEUL) /**< CTRL_CH_SEL_VDDIO Value */ 156 #define MXC_S_ADC_CTRL_CH_SEL_VDDIO (MXC_V_ADC_CTRL_CH_SEL_VDDIO << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VDDIO Setting */ 157 #define MXC_V_ADC_CTRL_CH_SEL_VDDIOH ((uint32_t)0xFUL) /**< CTRL_CH_SEL_VDDIOH Value */ 158 #define MXC_S_ADC_CTRL_CH_SEL_VDDIOH (MXC_V_ADC_CTRL_CH_SEL_VDDIOH << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VDDIOH Setting */ 159 #define MXC_V_ADC_CTRL_CH_SEL_VREGI ((uint32_t)0x10UL) /**< CTRL_CH_SEL_VREGI Value */ 160 #define MXC_S_ADC_CTRL_CH_SEL_VREGI (MXC_V_ADC_CTRL_CH_SEL_VREGI << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VREGI Setting */ 161 162 #define MXC_F_ADC_CTRL_ADC_DIVSEL_POS 17 /**< CTRL_ADC_DIVSEL Position */ 163 #define MXC_F_ADC_CTRL_ADC_DIVSEL ((uint32_t)(0x3UL << MXC_F_ADC_CTRL_ADC_DIVSEL_POS)) /**< CTRL_ADC_DIVSEL Mask */ 164 #define MXC_V_ADC_CTRL_ADC_DIVSEL_DIV1 ((uint32_t)0x0UL) /**< CTRL_ADC_DIVSEL_DIV1 Value */ 165 #define MXC_S_ADC_CTRL_ADC_DIVSEL_DIV1 (MXC_V_ADC_CTRL_ADC_DIVSEL_DIV1 << MXC_F_ADC_CTRL_ADC_DIVSEL_POS) /**< CTRL_ADC_DIVSEL_DIV1 Setting */ 166 #define MXC_V_ADC_CTRL_ADC_DIVSEL_DIV2 ((uint32_t)0x1UL) /**< CTRL_ADC_DIVSEL_DIV2 Value */ 167 #define MXC_S_ADC_CTRL_ADC_DIVSEL_DIV2 (MXC_V_ADC_CTRL_ADC_DIVSEL_DIV2 << MXC_F_ADC_CTRL_ADC_DIVSEL_POS) /**< CTRL_ADC_DIVSEL_DIV2 Setting */ 168 #define MXC_V_ADC_CTRL_ADC_DIVSEL_DIV3 ((uint32_t)0x2UL) /**< CTRL_ADC_DIVSEL_DIV3 Value */ 169 #define MXC_S_ADC_CTRL_ADC_DIVSEL_DIV3 (MXC_V_ADC_CTRL_ADC_DIVSEL_DIV3 << MXC_F_ADC_CTRL_ADC_DIVSEL_POS) /**< CTRL_ADC_DIVSEL_DIV3 Setting */ 170 #define MXC_V_ADC_CTRL_ADC_DIVSEL_DIV4 ((uint32_t)0x3UL) /**< CTRL_ADC_DIVSEL_DIV4 Value */ 171 #define MXC_S_ADC_CTRL_ADC_DIVSEL_DIV4 (MXC_V_ADC_CTRL_ADC_DIVSEL_DIV4 << MXC_F_ADC_CTRL_ADC_DIVSEL_POS) /**< CTRL_ADC_DIVSEL_DIV4 Setting */ 172 173 #define MXC_F_ADC_CTRL_DATA_ALIGN_POS 20 /**< CTRL_DATA_ALIGN Position */ 174 #define MXC_F_ADC_CTRL_DATA_ALIGN ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_DATA_ALIGN_POS)) /**< CTRL_DATA_ALIGN Mask */ 175 176 /**@} end of group ADC_CTRL_Register */ 177 178 /** 179 * @ingroup adc_registers 180 * @defgroup ADC_STATUS ADC_STATUS 181 * @brief ADC Status 182 * @{ 183 */ 184 #define MXC_F_ADC_STATUS_ACTIVE_POS 0 /**< STATUS_ACTIVE Position */ 185 #define MXC_F_ADC_STATUS_ACTIVE ((uint32_t)(0x1UL << MXC_F_ADC_STATUS_ACTIVE_POS)) /**< STATUS_ACTIVE Mask */ 186 187 #define MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE_POS 2 /**< STATUS_AFE_PWR_UP_ACTIVE Position */ 188 #define MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE ((uint32_t)(0x1UL << MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE_POS)) /**< STATUS_AFE_PWR_UP_ACTIVE Mask */ 189 190 #define MXC_F_ADC_STATUS_OVERFLOW_POS 3 /**< STATUS_OVERFLOW Position */ 191 #define MXC_F_ADC_STATUS_OVERFLOW ((uint32_t)(0x1UL << MXC_F_ADC_STATUS_OVERFLOW_POS)) /**< STATUS_OVERFLOW Mask */ 192 193 /**@} end of group ADC_STATUS_Register */ 194 195 /** 196 * @ingroup adc_registers 197 * @defgroup ADC_DATA ADC_DATA 198 * @brief ADC Output Data 199 * @{ 200 */ 201 #define MXC_F_ADC_DATA_ADC_DATA_POS 0 /**< DATA_ADC_DATA Position */ 202 #define MXC_F_ADC_DATA_ADC_DATA ((uint32_t)(0xFFFFUL << MXC_F_ADC_DATA_ADC_DATA_POS)) /**< DATA_ADC_DATA Mask */ 203 204 /**@} end of group ADC_DATA_Register */ 205 206 /** 207 * @ingroup adc_registers 208 * @defgroup ADC_INTR ADC_INTR 209 * @brief ADC Interrupt Control Register 210 * @{ 211 */ 212 #define MXC_F_ADC_INTR_DONE_IE_POS 0 /**< INTR_DONE_IE Position */ 213 #define MXC_F_ADC_INTR_DONE_IE ((uint32_t)(0x1UL << MXC_F_ADC_INTR_DONE_IE_POS)) /**< INTR_DONE_IE Mask */ 214 215 #define MXC_F_ADC_INTR_REF_READY_IE_POS 1 /**< INTR_REF_READY_IE Position */ 216 #define MXC_F_ADC_INTR_REF_READY_IE ((uint32_t)(0x1UL << MXC_F_ADC_INTR_REF_READY_IE_POS)) /**< INTR_REF_READY_IE Mask */ 217 218 #define MXC_F_ADC_INTR_HI_LIMIT_IE_POS 2 /**< INTR_HI_LIMIT_IE Position */ 219 #define MXC_F_ADC_INTR_HI_LIMIT_IE ((uint32_t)(0x1UL << MXC_F_ADC_INTR_HI_LIMIT_IE_POS)) /**< INTR_HI_LIMIT_IE Mask */ 220 221 #define MXC_F_ADC_INTR_LO_LIMIT_IE_POS 3 /**< INTR_LO_LIMIT_IE Position */ 222 #define MXC_F_ADC_INTR_LO_LIMIT_IE ((uint32_t)(0x1UL << MXC_F_ADC_INTR_LO_LIMIT_IE_POS)) /**< INTR_LO_LIMIT_IE Mask */ 223 224 #define MXC_F_ADC_INTR_OVERFLOW_IE_POS 4 /**< INTR_OVERFLOW_IE Position */ 225 #define MXC_F_ADC_INTR_OVERFLOW_IE ((uint32_t)(0x1UL << MXC_F_ADC_INTR_OVERFLOW_IE_POS)) /**< INTR_OVERFLOW_IE Mask */ 226 227 #define MXC_F_ADC_INTR_DONE_IF_POS 16 /**< INTR_DONE_IF Position */ 228 #define MXC_F_ADC_INTR_DONE_IF ((uint32_t)(0x1UL << MXC_F_ADC_INTR_DONE_IF_POS)) /**< INTR_DONE_IF Mask */ 229 230 #define MXC_F_ADC_INTR_REF_READY_IF_POS 17 /**< INTR_REF_READY_IF Position */ 231 #define MXC_F_ADC_INTR_REF_READY_IF ((uint32_t)(0x1UL << MXC_F_ADC_INTR_REF_READY_IF_POS)) /**< INTR_REF_READY_IF Mask */ 232 233 #define MXC_F_ADC_INTR_HI_LIMIT_IF_POS 18 /**< INTR_HI_LIMIT_IF Position */ 234 #define MXC_F_ADC_INTR_HI_LIMIT_IF ((uint32_t)(0x1UL << MXC_F_ADC_INTR_HI_LIMIT_IF_POS)) /**< INTR_HI_LIMIT_IF Mask */ 235 236 #define MXC_F_ADC_INTR_LO_LIMIT_IF_POS 19 /**< INTR_LO_LIMIT_IF Position */ 237 #define MXC_F_ADC_INTR_LO_LIMIT_IF ((uint32_t)(0x1UL << MXC_F_ADC_INTR_LO_LIMIT_IF_POS)) /**< INTR_LO_LIMIT_IF Mask */ 238 239 #define MXC_F_ADC_INTR_OVERFLOW_IF_POS 20 /**< INTR_OVERFLOW_IF Position */ 240 #define MXC_F_ADC_INTR_OVERFLOW_IF ((uint32_t)(0x1UL << MXC_F_ADC_INTR_OVERFLOW_IF_POS)) /**< INTR_OVERFLOW_IF Mask */ 241 242 #define MXC_F_ADC_INTR_PENDING_POS 22 /**< INTR_PENDING Position */ 243 #define MXC_F_ADC_INTR_PENDING ((uint32_t)(0x1UL << MXC_F_ADC_INTR_PENDING_POS)) /**< INTR_PENDING Mask */ 244 245 /**@} end of group ADC_INTR_Register */ 246 247 /** 248 * @ingroup adc_registers 249 * @defgroup ADC_LIMIT ADC_LIMIT 250 * @brief ADC Limit 251 * @{ 252 */ 253 #define MXC_F_ADC_LIMIT_CH_LO_LIMIT_POS 0 /**< LIMIT_CH_LO_LIMIT Position */ 254 #define MXC_F_ADC_LIMIT_CH_LO_LIMIT ((uint32_t)(0x3FFUL << MXC_F_ADC_LIMIT_CH_LO_LIMIT_POS)) /**< LIMIT_CH_LO_LIMIT Mask */ 255 256 #define MXC_F_ADC_LIMIT_CH_HI_LIMIT_POS 12 /**< LIMIT_CH_HI_LIMIT Position */ 257 #define MXC_F_ADC_LIMIT_CH_HI_LIMIT ((uint32_t)(0x3FFUL << MXC_F_ADC_LIMIT_CH_HI_LIMIT_POS)) /**< LIMIT_CH_HI_LIMIT Mask */ 258 259 #define MXC_F_ADC_LIMIT_CH_SEL_POS 24 /**< LIMIT_CH_SEL Position */ 260 #define MXC_F_ADC_LIMIT_CH_SEL ((uint32_t)(0x1FUL << MXC_F_ADC_LIMIT_CH_SEL_POS)) /**< LIMIT_CH_SEL Mask */ 261 262 #define MXC_F_ADC_LIMIT_CH_LO_LIMIT_EN_POS 29 /**< LIMIT_CH_LO_LIMIT_EN Position */ 263 #define MXC_F_ADC_LIMIT_CH_LO_LIMIT_EN ((uint32_t)(0x1UL << MXC_F_ADC_LIMIT_CH_LO_LIMIT_EN_POS)) /**< LIMIT_CH_LO_LIMIT_EN Mask */ 264 265 #define MXC_F_ADC_LIMIT_CH_HI_LIMIT_EN_POS 30 /**< LIMIT_CH_HI_LIMIT_EN Position */ 266 #define MXC_F_ADC_LIMIT_CH_HI_LIMIT_EN ((uint32_t)(0x1UL << MXC_F_ADC_LIMIT_CH_HI_LIMIT_EN_POS)) /**< LIMIT_CH_HI_LIMIT_EN Mask */ 267 268 /**@} end of group ADC_LIMIT_Register */ 269 270 #ifdef __cplusplus 271 } 272 #endif 273 274 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32680_INCLUDE_ADC_REGS_H_ 275
