1 /** 2 * @file pwrseq_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup pwrseq_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32675_INCLUDE_PWRSEQ_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32675_INCLUDE_PWRSEQ_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup pwrseq 67 * @defgroup pwrseq_registers PWRSEQ_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module. 69 * @details Power Sequencer / Low Power Control Register. 70 */ 71 72 /** 73 * @ingroup pwrseq_registers 74 * Structure type to access the PWRSEQ Registers. 75 */ 76 typedef struct { 77 __IO uint32_t lpcn; /**< <tt>\b 0x00:</tt> PWRSEQ LPCN Register */ 78 __IO uint32_t lpwkst0; /**< <tt>\b 0x04:</tt> PWRSEQ LPWKST0 Register */ 79 __IO uint32_t lpwken0; /**< <tt>\b 0x08:</tt> PWRSEQ LPWKEN0 Register */ 80 __IO uint32_t lpwkst1; /**< <tt>\b 0x0C:</tt> PWRSEQ LPWKST1 Register */ 81 __IO uint32_t lpwken1; /**< <tt>\b 0x10:</tt> PWRSEQ LPWKEN1 Register */ 82 __R uint32_t rsv_0x14_0x2f[7]; 83 __IO uint32_t lppwkst; /**< <tt>\b 0x30:</tt> PWRSEQ LPPWKST Register */ 84 __IO uint32_t lppwken; /**< <tt>\b 0x34:</tt> PWRSEQ LPPWKEN Register */ 85 __R uint32_t rsv_0x38_0x3f[2]; 86 __IO uint32_t lpmemsd; /**< <tt>\b 0x40:</tt> PWRSEQ LPMEMSD Register */ 87 __R uint32_t rsv_0x44; 88 __IO uint32_t gp0; /**< <tt>\b 0x48:</tt> PWRSEQ GP0 Register */ 89 __IO uint32_t gp1; /**< <tt>\b 0x4C:</tt> PWRSEQ GP1 Register */ 90 } mxc_pwrseq_regs_t; 91 92 /* Register offsets for module PWRSEQ */ 93 /** 94 * @ingroup pwrseq_registers 95 * @defgroup PWRSEQ_Register_Offsets Register Offsets 96 * @brief PWRSEQ Peripheral Register Offsets from the PWRSEQ Base Peripheral Address. 97 * @{ 98 */ 99 #define MXC_R_PWRSEQ_LPCN ((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0000</tt> */ 100 #define MXC_R_PWRSEQ_LPWKST0 ((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0004</tt> */ 101 #define MXC_R_PWRSEQ_LPWKEN0 ((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0008</tt> */ 102 #define MXC_R_PWRSEQ_LPWKST1 ((uint32_t)0x0000000CUL) /**< Offset from PWRSEQ Base Address: <tt> 0x000C</tt> */ 103 #define MXC_R_PWRSEQ_LPWKEN1 ((uint32_t)0x00000010UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0010</tt> */ 104 #define MXC_R_PWRSEQ_LPPWKST ((uint32_t)0x00000030UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0030</tt> */ 105 #define MXC_R_PWRSEQ_LPPWKEN ((uint32_t)0x00000034UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0034</tt> */ 106 #define MXC_R_PWRSEQ_LPMEMSD ((uint32_t)0x00000040UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0040</tt> */ 107 #define MXC_R_PWRSEQ_GP0 ((uint32_t)0x00000048UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0048</tt> */ 108 #define MXC_R_PWRSEQ_GP1 ((uint32_t)0x0000004CUL) /**< Offset from PWRSEQ Base Address: <tt> 0x004C</tt> */ 109 /**@} end of group pwrseq_registers */ 110 111 /** 112 * @ingroup pwrseq_registers 113 * @defgroup PWRSEQ_LPCN PWRSEQ_LPCN 114 * @brief Low Power Control Register. 115 * @{ 116 */ 117 #define MXC_F_PWRSEQ_LPCN_RAM0RET_EN_POS 0 /**< LPCN_RAM0RET_EN Position */ 118 #define MXC_F_PWRSEQ_LPCN_RAM0RET_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAM0RET_EN_POS)) /**< LPCN_RAM0RET_EN Mask */ 119 120 #define MXC_F_PWRSEQ_LPCN_RAM1RET_EN_POS 1 /**< LPCN_RAM1RET_EN Position */ 121 #define MXC_F_PWRSEQ_LPCN_RAM1RET_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAM1RET_EN_POS)) /**< LPCN_RAM1RET_EN Mask */ 122 123 #define MXC_F_PWRSEQ_LPCN_RAM2RET_EN_POS 2 /**< LPCN_RAM2RET_EN Position */ 124 #define MXC_F_PWRSEQ_LPCN_RAM2RET_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAM2RET_EN_POS)) /**< LPCN_RAM2RET_EN Mask */ 125 126 #define MXC_F_PWRSEQ_LPCN_RAM3RET_EN_POS 3 /**< LPCN_RAM3RET_EN Position */ 127 #define MXC_F_PWRSEQ_LPCN_RAM3RET_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RAM3RET_EN_POS)) /**< LPCN_RAM3RET_EN Mask */ 128 129 #define MXC_F_PWRSEQ_LPCN_OVR_POS 4 /**< LPCN_OVR Position */ 130 #define MXC_F_PWRSEQ_LPCN_OVR ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPCN_OVR_POS)) /**< LPCN_OVR Mask */ 131 #define MXC_V_PWRSEQ_LPCN_OVR_0_9V ((uint32_t)0x0UL) /**< LPCN_OVR_0_9V Value */ 132 #define MXC_S_PWRSEQ_LPCN_OVR_0_9V (MXC_V_PWRSEQ_LPCN_OVR_0_9V << MXC_F_PWRSEQ_LPCN_OVR_POS) /**< LPCN_OVR_0_9V Setting */ 133 #define MXC_V_PWRSEQ_LPCN_OVR_1_0V ((uint32_t)0x1UL) /**< LPCN_OVR_1_0V Value */ 134 #define MXC_S_PWRSEQ_LPCN_OVR_1_0V (MXC_V_PWRSEQ_LPCN_OVR_1_0V << MXC_F_PWRSEQ_LPCN_OVR_POS) /**< LPCN_OVR_1_0V Setting */ 135 #define MXC_V_PWRSEQ_LPCN_OVR_1_1V ((uint32_t)0x2UL) /**< LPCN_OVR_1_1V Value */ 136 #define MXC_S_PWRSEQ_LPCN_OVR_1_1V (MXC_V_PWRSEQ_LPCN_OVR_1_1V << MXC_F_PWRSEQ_LPCN_OVR_POS) /**< LPCN_OVR_1_1V Setting */ 137 138 #define MXC_F_PWRSEQ_LPCN_VCORE_DET_BYPASS_POS 6 /**< LPCN_VCORE_DET_BYPASS Position */ 139 #define MXC_F_PWRSEQ_LPCN_VCORE_DET_BYPASS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCORE_DET_BYPASS_POS)) /**< LPCN_VCORE_DET_BYPASS Mask */ 140 141 #define MXC_F_PWRSEQ_LPCN_RETREG_EN_POS 8 /**< LPCN_RETREG_EN Position */ 142 #define MXC_F_PWRSEQ_LPCN_RETREG_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RETREG_EN_POS)) /**< LPCN_RETREG_EN Mask */ 143 144 #define MXC_F_PWRSEQ_LPCN_STORAGE_EN_POS 9 /**< LPCN_STORAGE_EN Position */ 145 #define MXC_F_PWRSEQ_LPCN_STORAGE_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_STORAGE_EN_POS)) /**< LPCN_STORAGE_EN Mask */ 146 147 #define MXC_F_PWRSEQ_LPCN_FASTWK_EN_POS 10 /**< LPCN_FASTWK_EN Position */ 148 #define MXC_F_PWRSEQ_LPCN_FASTWK_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_FASTWK_EN_POS)) /**< LPCN_FASTWK_EN Mask */ 149 150 #define MXC_F_PWRSEQ_LPCN_BG_DIS_POS 11 /**< LPCN_BG_DIS Position */ 151 #define MXC_F_PWRSEQ_LPCN_BG_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_BG_DIS_POS)) /**< LPCN_BG_DIS Mask */ 152 153 #define MXC_F_PWRSEQ_LPCN_VCOREPOR_DIS_POS 12 /**< LPCN_VCOREPOR_DIS Position */ 154 #define MXC_F_PWRSEQ_LPCN_VCOREPOR_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCOREPOR_DIS_POS)) /**< LPCN_VCOREPOR_DIS Mask */ 155 156 #define MXC_F_PWRSEQ_LPCN_LDO_DIS_POS 16 /**< LPCN_LDO_DIS Position */ 157 #define MXC_F_PWRSEQ_LPCN_LDO_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_LDO_DIS_POS)) /**< LPCN_LDO_DIS Mask */ 158 159 #define MXC_F_PWRSEQ_LPCN_VCORE_EXT_POS 17 /**< LPCN_VCORE_EXT Position */ 160 #define MXC_F_PWRSEQ_LPCN_VCORE_EXT ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCORE_EXT_POS)) /**< LPCN_VCORE_EXT Mask */ 161 162 #define MXC_F_PWRSEQ_LPCN_VCOREMON_DIS_POS 20 /**< LPCN_VCOREMON_DIS Position */ 163 #define MXC_F_PWRSEQ_LPCN_VCOREMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCOREMON_DIS_POS)) /**< LPCN_VCOREMON_DIS Mask */ 164 165 #define MXC_F_PWRSEQ_LPCN_VDDAMON_DIS_POS 22 /**< LPCN_VDDAMON_DIS Position */ 166 #define MXC_F_PWRSEQ_LPCN_VDDAMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDAMON_DIS_POS)) /**< LPCN_VDDAMON_DIS Mask */ 167 168 #define MXC_F_PWRSEQ_LPCN_PORVDDMON_DIS_POS 25 /**< LPCN_PORVDDMON_DIS Position */ 169 #define MXC_F_PWRSEQ_LPCN_PORVDDMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_PORVDDMON_DIS_POS)) /**< LPCN_PORVDDMON_DIS Mask */ 170 171 #define MXC_F_PWRSEQ_LPCN_INRO_EN_POS 28 /**< LPCN_INRO_EN Position */ 172 #define MXC_F_PWRSEQ_LPCN_INRO_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_INRO_EN_POS)) /**< LPCN_INRO_EN Mask */ 173 174 #define MXC_F_PWRSEQ_LPCN_ERTCO_EN_POS 29 /**< LPCN_ERTCO_EN Position */ 175 #define MXC_F_PWRSEQ_LPCN_ERTCO_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_ERTCO_EN_POS)) /**< LPCN_ERTCO_EN Mask */ 176 177 #define MXC_F_PWRSEQ_LPCN_ERTCO_PD_POS 31 /**< LPCN_ERTCO_PD Position */ 178 #define MXC_F_PWRSEQ_LPCN_ERTCO_PD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_ERTCO_PD_POS)) /**< LPCN_ERTCO_PD Mask */ 179 180 /**@} end of group PWRSEQ_LPCN_Register */ 181 182 /** 183 * @ingroup pwrseq_registers 184 * @defgroup PWRSEQ_LPWKST0 PWRSEQ_LPWKST0 185 * @brief Low Power I/O Wakeup Status Register 0. This register indicates the low power 186 * wakeup status for GPIO0. 187 * @{ 188 */ 189 #define MXC_F_PWRSEQ_LPWKST0_ST_POS 0 /**< LPWKST0_ST Position */ 190 #define MXC_F_PWRSEQ_LPWKST0_ST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPWKST0_ST_POS)) /**< LPWKST0_ST Mask */ 191 192 /**@} end of group PWRSEQ_LPWKST0_Register */ 193 194 /** 195 * @ingroup pwrseq_registers 196 * @defgroup PWRSEQ_LPWKEN0 PWRSEQ_LPWKEN0 197 * @brief Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup 198 * functionality for GPIO0. 199 * @{ 200 */ 201 #define MXC_F_PWRSEQ_LPWKEN0_EN_POS 0 /**< LPWKEN0_EN Position */ 202 #define MXC_F_PWRSEQ_LPWKEN0_EN ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRSEQ_LPWKEN0_EN_POS)) /**< LPWKEN0_EN Mask */ 203 204 /**@} end of group PWRSEQ_LPWKEN0_Register */ 205 206 /** 207 * @ingroup pwrseq_registers 208 * @defgroup PWRSEQ_LPPWKST PWRSEQ_LPPWKST 209 * @brief Low Power Peripheral Wakeup Status Register. 210 * @{ 211 */ 212 #define MXC_F_PWRSEQ_LPPWKST_LPTMR0_POS 0 /**< LPPWKST_LPTMR0 Position */ 213 #define MXC_F_PWRSEQ_LPPWKST_LPTMR0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKST_LPTMR0_POS)) /**< LPPWKST_LPTMR0 Mask */ 214 215 #define MXC_F_PWRSEQ_LPPWKST_LPTMR1_POS 1 /**< LPPWKST_LPTMR1 Position */ 216 #define MXC_F_PWRSEQ_LPPWKST_LPTMR1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKST_LPTMR1_POS)) /**< LPPWKST_LPTMR1 Mask */ 217 218 #define MXC_F_PWRSEQ_LPPWKST_LPUART0_POS 2 /**< LPPWKST_LPUART0 Position */ 219 #define MXC_F_PWRSEQ_LPPWKST_LPUART0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKST_LPUART0_POS)) /**< LPPWKST_LPUART0 Mask */ 220 221 /**@} end of group PWRSEQ_LPPWKST_Register */ 222 223 /** 224 * @ingroup pwrseq_registers 225 * @defgroup PWRSEQ_LPPWKEN PWRSEQ_LPPWKEN 226 * @brief Low Power Peripheral Wakeup Enable Register. 227 * @{ 228 */ 229 #define MXC_F_PWRSEQ_LPPWKEN_LPTMR0_POS 0 /**< LPPWKEN_LPTMR0 Position */ 230 #define MXC_F_PWRSEQ_LPPWKEN_LPTMR0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_LPTMR0_POS)) /**< LPPWKEN_LPTMR0 Mask */ 231 232 #define MXC_F_PWRSEQ_LPPWKEN_LPTMR1_POS 1 /**< LPPWKEN_LPTMR1 Position */ 233 #define MXC_F_PWRSEQ_LPPWKEN_LPTMR1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_LPTMR1_POS)) /**< LPPWKEN_LPTMR1 Mask */ 234 235 #define MXC_F_PWRSEQ_LPPWKEN_LPUART0_POS 2 /**< LPPWKEN_LPUART0 Position */ 236 #define MXC_F_PWRSEQ_LPPWKEN_LPUART0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_LPUART0_POS)) /**< LPPWKEN_LPUART0 Mask */ 237 238 /**@} end of group PWRSEQ_LPPWKEN_Register */ 239 240 /** 241 * @ingroup pwrseq_registers 242 * @defgroup PWRSEQ_LPMEMSD PWRSEQ_LPMEMSD 243 * @brief Low Power Memory Shutdown Control. 244 * @{ 245 */ 246 #define MXC_F_PWRSEQ_LPMEMSD_RAM0_POS 0 /**< LPMEMSD_RAM0 Position */ 247 #define MXC_F_PWRSEQ_LPMEMSD_RAM0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM0_POS)) /**< LPMEMSD_RAM0 Mask */ 248 249 #define MXC_F_PWRSEQ_LPMEMSD_RAM1_POS 1 /**< LPMEMSD_RAM1 Position */ 250 #define MXC_F_PWRSEQ_LPMEMSD_RAM1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM1_POS)) /**< LPMEMSD_RAM1 Mask */ 251 252 #define MXC_F_PWRSEQ_LPMEMSD_RAM2_POS 2 /**< LPMEMSD_RAM2 Position */ 253 #define MXC_F_PWRSEQ_LPMEMSD_RAM2 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM2_POS)) /**< LPMEMSD_RAM2 Mask */ 254 255 #define MXC_F_PWRSEQ_LPMEMSD_RAM3_POS 3 /**< LPMEMSD_RAM3 Position */ 256 #define MXC_F_PWRSEQ_LPMEMSD_RAM3 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM3_POS)) /**< LPMEMSD_RAM3 Mask */ 257 258 /**@} end of group PWRSEQ_LPMEMSD_Register */ 259 260 #ifdef __cplusplus 261 } 262 #endif 263 264 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32675_INCLUDE_PWRSEQ_REGS_H_ 265
