1<?xml version='1.0' encoding='utf-8'?> 2<device xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.1" xsi:noNamespaceSchemaLocation="svd_schema.xsd"> 3 <vendor>Maxim-Integrated</vendor> 4 <vendorID>Maxim</vendorID> 5 <name>max32675</name> 6 <series>ARMCM4</series> 7 <version>1.0</version> 8 <description>MAX32675 32-bit ARM Cortex-M4 microcontroller, 1024KB of flash, 760KB of system RAM, 128KB of Boot ROM.</description> 9 <cpu> 10 <name>CM4</name> 11 <revision>r2p1</revision> 12 <endian>little</endian> 13 <mpuPresent>true</mpuPresent> 14 <fpuPresent>true</fpuPresent> 15 <nvicPrioBits>3</nvicPrioBits> 16 <vendorSystickConfig>false</vendorSystickConfig> 17 </cpu> 18 <addressUnitBits>8</addressUnitBits> 19 <width>32</width> 20 <size>0x20</size> 21 <access>read-write</access> 22 <resetValue>0x00000000</resetValue> 23 <resetMask>0xFFFFFFFF</resetMask> 24 <peripherals> 25 <peripheral> 26 <name>AESKEYS</name> 27 <description>AES Key Registers.</description> 28 <baseAddress>0x40007800</baseAddress> 29 <addressBlock> 30 <offset>0x00</offset> 31 <size>0x400</size> 32 <usage>registers</usage> 33 </addressBlock> 34 <registers> 35 <register> 36 <name>KEY0</name> 37 <description>AES Key 0.</description> 38 <addressOffset>0x00</addressOffset> 39 <size>32</size> 40 </register> 41 <register> 42 <name>KEY1</name> 43 <description>AES Key 1.</description> 44 <addressOffset>0x04</addressOffset> 45 <size>32</size> 46 </register> 47 <register> 48 <name>KEY2</name> 49 <description>AES Key 2.</description> 50 <addressOffset>0x08</addressOffset> 51 <size>32</size> 52 </register> 53 <register> 54 <name>KEY3</name> 55 <description>AES Key 3.</description> 56 <addressOffset>0x0C</addressOffset> 57 <size>32</size> 58 </register> 59 <register> 60 <name>KEY4</name> 61 <description>AES Key 4.</description> 62 <addressOffset>0x10</addressOffset> 63 <size>32</size> 64 </register> 65 <register> 66 <name>KEY5</name> 67 <description>AES Key 5.</description> 68 <addressOffset>0x14</addressOffset> 69 <size>32</size> 70 </register> 71 <register> 72 <name>KEY6</name> 73 <description>AES Key 6.</description> 74 <addressOffset>0x18</addressOffset> 75 <size>32</size> 76 </register> 77 <register> 78 <name>KEY7</name> 79 <description>AES Key 7.</description> 80 <addressOffset>0x1C</addressOffset> 81 <size>32</size> 82 </register> 83 </registers> 84 </peripheral> 85<!--AESKEYS AES Key Registers.--> 86 <peripheral> 87 <name>AES</name> 88 <description>AES Keys.</description> 89 <baseAddress>0x40007400</baseAddress> 90 <addressBlock> 91 <offset>0x00</offset> 92 <size>0x400</size> 93 <usage>registers</usage> 94 </addressBlock> 95 <registers> 96 <register> 97 <name>CTRL</name> 98 <description>AES Control Register</description> 99 <addressOffset>0x0000</addressOffset> 100 <size>32</size> 101 <fields> 102 <field> 103 <name>EN</name> 104 <description>AES Enable</description> 105 <bitRange>[0:0]</bitRange> 106 <access>read-write</access> 107 </field> 108 <field> 109 <name>DMA_RX_EN</name> 110 <description>DMA Request To Read Data Output FIFO</description> 111 <bitRange>[1:1]</bitRange> 112 <access>read-write</access> 113 </field> 114 <field> 115 <name>DMA_TX_EN</name> 116 <description>DMA Request To Write Data Input FIFO</description> 117 <bitRange>[2:2]</bitRange> 118 <access>read-write</access> 119 </field> 120 <field> 121 <name>START</name> 122 <description>Start AES Calculation</description> 123 <bitRange>[3:3]</bitRange> 124 <access>read-write</access> 125 </field> 126 <field> 127 <name>INPUT_FLUSH</name> 128 <description>Flush the data input FIFO</description> 129 <bitRange>[4:4]</bitRange> 130 <access>read-write</access> 131 </field> 132 <field> 133 <name>OUTPUT_FLUSH</name> 134 <description>Flush the data output FIFO</description> 135 <bitRange>[5:5]</bitRange> 136 <access>read-write</access> 137 </field> 138 <field> 139 <name>KEY_SIZE</name> 140 <description>Encryption Key Size</description> 141 <bitRange>[7:6]</bitRange> 142 <access>read-write</access> 143 <enumeratedValues> 144 <enumeratedValue> 145 <name>AES128</name> 146 <description>128 Bits.</description> 147 <value>0</value> 148 </enumeratedValue> 149 <enumeratedValue> 150 <name>AES192</name> 151 <description>192 Bits.</description> 152 <value>1</value> 153 </enumeratedValue> 154 <enumeratedValue> 155 <name>AES256</name> 156 <description>256 Bits.</description> 157 <value>2</value> 158 </enumeratedValue> 159 </enumeratedValues> 160 </field> 161 <field> 162 <name>TYPE</name> 163 <description>Encryption Type Selection</description> 164 <bitRange>[9:8]</bitRange> 165 <access>read-write</access> 166 </field> 167 </fields> 168 </register> 169 <register> 170 <name>STATUS</name> 171 <description>AES Status Register</description> 172 <addressOffset>0x0004</addressOffset> 173 <fields> 174 <field> 175 <name>BUSY</name> 176 <description>AES Busy Status</description> 177 <bitRange>[0:0]</bitRange> 178 <access>read-write</access> 179 </field> 180 <field> 181 <name>INPUT_EM</name> 182 <description>Data input FIFO empty status</description> 183 <bitRange>[1:1]</bitRange> 184 <access>read-write</access> 185 </field> 186 <field> 187 <name>INPUT_FULL</name> 188 <description>Data input FIFO full status</description> 189 <bitRange>[2:2]</bitRange> 190 <access>read-write</access> 191 </field> 192 <field> 193 <name>OUTPUT_EM</name> 194 <description>Data output FIFO empty status</description> 195 <bitRange>[3:3]</bitRange> 196 <access>read-write</access> 197 </field> 198 <field> 199 <name>OUTPUT_FULL</name> 200 <description>Data output FIFO full status</description> 201 <bitRange>[4:4]</bitRange> 202 <access>read-write</access> 203 </field> 204 </fields> 205 </register> 206 <register> 207 <name>INTFL</name> 208 <description>AES Interrupt Flag Register</description> 209 <addressOffset>0x0008</addressOffset> 210 <fields> 211 <field> 212 <name>DONE</name> 213 <description>AES Done Interrupt</description> 214 <bitRange>[0:0]</bitRange> 215 <access>read-write</access> 216 </field> 217 <field> 218 <name>KEY_CHANGE</name> 219 <description>External AES Key Changed Interrupt</description> 220 <bitRange>[1:1]</bitRange> 221 <access>read-write</access> 222 </field> 223 <field> 224 <name>KEY_ZERO</name> 225 <description>External AES Key Zero Interrupt</description> 226 <bitRange>[2:2]</bitRange> 227 <access>read-write</access> 228 </field> 229 <field> 230 <name>OV</name> 231 <description>Data Output FIFO Overrun Interrupt</description> 232 <bitRange>[3:3]</bitRange> 233 <access>read-write</access> 234 </field> 235 <field> 236 <name>KEY_ONE</name> 237 <description>KEY_ONE</description> 238 <bitRange>[4:4]</bitRange> 239 <access>read-write</access> 240 </field> 241 </fields> 242 </register> 243 <register> 244 <name>INTEN</name> 245 <description>AES Interrupt Enable Register</description> 246 <addressOffset>0x000C</addressOffset> 247 <fields> 248 <field> 249 <name>DONE</name> 250 <description>AES Done Interrupt Enable</description> 251 <bitRange>[0:0]</bitRange> 252 <access>read-write</access> 253 </field> 254 <field> 255 <name>KEY_CHANGE</name> 256 <description>External AES Key Changed Interrupt Enable</description> 257 <bitRange>[1:1]</bitRange> 258 <access>read-write</access> 259 </field> 260 <field> 261 <name>KEY_ZERO</name> 262 <description>External AES Key Zero Interrupt Enable</description> 263 <bitRange>[2:2]</bitRange> 264 <access>read-write</access> 265 </field> 266 <field> 267 <name>OV</name> 268 <description>Data Output FIFO Overrun Interrupt Enable</description> 269 <bitRange>[3:3]</bitRange> 270 <access>read-write</access> 271 </field> 272 <field> 273 <name>KEY_ONE</name> 274 <description>KEY_ONE</description> 275 <bitRange>[4:4]</bitRange> 276 <access>read-write</access> 277 </field> 278 </fields> 279 </register> 280 <register> 281 <name>FIFO</name> 282 <description>AES Data Register</description> 283 <addressOffset>0x0010</addressOffset> 284 <fields> 285 <field> 286 <name>DATA</name> 287 <description>AES FIFO</description> 288 <bitRange>[0:0]</bitRange> 289 <access>read-write</access> 290 </field> 291 </fields> 292 </register> 293 </registers> 294 </peripheral> 295<!--AES AES Keys.--> 296 <peripheral> 297 <name>CRC</name> 298 <description>CRC Registers.</description> 299 <baseAddress>0x4000F000</baseAddress> 300 <addressBlock> 301 <offset>0x00</offset> 302 <size>0x1000</size> 303 <usage>registers</usage> 304 </addressBlock> 305 <registers> 306 <register> 307 <name>CTRL</name> 308 <description>CRC Control</description> 309 <addressOffset>0x0000</addressOffset> 310 <size>32</size> 311 <fields> 312 <field> 313 <name>EN</name> 314 <description>CRC Enable</description> 315 <bitRange>[0:0]</bitRange> 316 <access>read-write</access> 317 </field> 318 <field> 319 <name>DMA_EN</name> 320 <description>DMA Request Enable</description> 321 <bitRange>[1:1]</bitRange> 322 <access>read-write</access> 323 </field> 324 <field> 325 <name>MSB</name> 326 <description>MSB Select</description> 327 <bitRange>[2:2]</bitRange> 328 <access>read-write</access> 329 </field> 330 <field> 331 <name>BYTE_SWAP_IN</name> 332 <description>Byte Swap CRC Data Input</description> 333 <bitRange>[3:3]</bitRange> 334 <access>read-write</access> 335 </field> 336 <field> 337 <name>BYTE_SWAP_OUT</name> 338 <description>Byte Swap CRC Value Output</description> 339 <bitRange>[4:4]</bitRange> 340 <access>read-write</access> 341 </field> 342 <field> 343 <name>BUSY</name> 344 <description>CRC Busy</description> 345 <bitRange>[16:16]</bitRange> 346 <access>read-write</access> 347 </field> 348 </fields> 349 </register> 350 <register> 351 <name>DATAIN32</name> 352 <description>CRC Data Input</description> 353 <addressOffset>0x0004</addressOffset> 354 <fields> 355 <field> 356 <name>DATA</name> 357 <description>CRC Data</description> 358 <bitRange>[31:0]</bitRange> 359 <access>read-write</access> 360 </field> 361 </fields> 362 </register> 363 <register> 364 <dim>2</dim> 365 <dimIncrement>2</dimIncrement> 366 <name>DATAIN16[%s]</name> 367 <description>CRC Data Input</description> 368 <addressOffset>0x0004</addressOffset> 369 <size>16</size> 370 <access>read-write</access> 371 <fields> 372 <field> 373 <name>DATA</name> 374 <description>CRC Data</description> 375 <bitOffset>0</bitOffset> 376 <bitWidth>16</bitWidth> 377 <access>read-write</access> 378 </field> 379 </fields> 380 </register> 381 <register> 382 <dim>4</dim> 383 <dimIncrement>1</dimIncrement> 384 <name>DATAIN8[%s]</name> 385 <description>CRC Data Input</description> 386 <addressOffset>0x0004</addressOffset> 387 <size>8</size> 388 <access>read-write</access> 389 <fields> 390 <field> 391 <name>DATA</name> 392 <description>CRC Data</description> 393 <bitOffset>0</bitOffset> 394 <bitWidth>8</bitWidth> 395 <access>read-write</access> 396 </field> 397 </fields> 398 </register> 399 <register> 400 <name>POLY</name> 401 <description>CRC Polynomial</description> 402 <addressOffset>0x0008</addressOffset> 403 <fields> 404 <field> 405 <name>POLY</name> 406 <description>CRC Polynomial</description> 407 <bitRange>[31:0]</bitRange> 408 <access>read-write</access> 409 </field> 410 </fields> 411 </register> 412 <register> 413 <name>VAL</name> 414 <description>Current CRC Value</description> 415 <addressOffset>0x000C</addressOffset> 416 <fields> 417 <field> 418 <name>VALUE</name> 419 <description>Current CRC Value</description> 420 <bitRange>[31:0]</bitRange> 421 <access>read-write</access> 422 </field> 423 </fields> 424 </register> 425 </registers> 426 </peripheral> 427<!--CRC CRC Registers.--> 428 <peripheral> 429 <name>DMA</name> 430 <description>DMA Controller Fully programmable, chaining capable DMA channels.</description> 431 <baseAddress>0x40028000</baseAddress> 432 <size>32</size> 433 <addressBlock> 434 <offset>0x00</offset> 435 <size>0x1000</size> 436 <usage>registers</usage> 437 </addressBlock> 438 <interrupt> 439 <name>DMA0</name> 440 <value>28</value> 441 </interrupt> 442 <interrupt> 443 <name>DMA1</name> 444 <value>29</value> 445 </interrupt> 446 <interrupt> 447 <name>DMA2</name> 448 <value>30</value> 449 </interrupt> 450 <interrupt> 451 <name>DMA3</name> 452 <value>31</value> 453 </interrupt> 454 <interrupt> 455 <name>DMA4</name> 456 <value>68</value> 457 </interrupt> 458 <interrupt> 459 <name>DMA5</name> 460 <value>69</value> 461 </interrupt> 462 <interrupt> 463 <name>DMA6</name> 464 <value>70</value> 465 </interrupt> 466 <interrupt> 467 <name>DMA7</name> 468 <value>71</value> 469 </interrupt> 470 <interrupt> 471 <name>DMA8</name> 472 <value>72</value> 473 </interrupt> 474 <interrupt> 475 <name>DMA9</name> 476 <value>73</value> 477 </interrupt> 478 <interrupt> 479 <name>DMA10</name> 480 <value>74</value> 481 </interrupt> 482 <interrupt> 483 <name>DMA11</name> 484 <value>75</value> 485 </interrupt> 486 <interrupt> 487 <name>DMA12</name> 488 <value>76</value> 489 </interrupt> 490 <interrupt> 491 <name>DMA13</name> 492 <value>77</value> 493 </interrupt> 494 <interrupt> 495 <name>DMA14</name> 496 <value>78</value> 497 </interrupt> 498 <interrupt> 499 <name>DMA15</name> 500 <value>79</value> 501 </interrupt> 502 <registers> 503 <register> 504 <name>INTEN</name> 505 <description>DMA Control Register.</description> 506 <addressOffset>0x000</addressOffset> 507 <fields> 508 <field> 509 <name>CH0</name> 510 <description>Channel 0 Interrupt Enable.</description> 511 <bitOffset>0</bitOffset> 512 <bitWidth>1</bitWidth> 513 <enumeratedValues> 514 <enumeratedValue> 515 <name>dis</name> 516 <description>Disable.</description> 517 <value>0</value> 518 </enumeratedValue> 519 <enumeratedValue> 520 <name>en</name> 521 <description>Enable.</description> 522 <value>1</value> 523 </enumeratedValue> 524 </enumeratedValues> 525 </field> 526 <field derivedFrom="CH0"> 527 <name>CH1</name> 528 <description>Channel 1 Interrupt Enable.</description> 529 <bitOffset>1</bitOffset> 530 <bitWidth>1</bitWidth> 531 </field> 532 <field derivedFrom="CH0"> 533 <name>CH2</name> 534 <description>Channel 2 Interrupt Enable.</description> 535 <bitOffset>2</bitOffset> 536 <bitWidth>1</bitWidth> 537 </field> 538 <field derivedFrom="CH0"> 539 <name>CH3</name> 540 <description>Channel 3 Interrupt Enable.</description> 541 <bitOffset>3</bitOffset> 542 <bitWidth>1</bitWidth> 543 </field> 544 <field derivedFrom="CH0"> 545 <name>CH4</name> 546 <description>Channel 4 Interrupt Enable.</description> 547 <bitOffset>4</bitOffset> 548 <bitWidth>1</bitWidth> 549 </field> 550 <field derivedFrom="CH0"> 551 <name>CH5</name> 552 <description>Channel 5 Interrupt Enable.</description> 553 <bitOffset>5</bitOffset> 554 <bitWidth>1</bitWidth> 555 </field> 556 <field derivedFrom="CH0"> 557 <name>CH6</name> 558 <description>Channel 6 Interrupt Enable.</description> 559 <bitOffset>6</bitOffset> 560 <bitWidth>1</bitWidth> 561 </field> 562 <field derivedFrom="CH0"> 563 <name>CH7</name> 564 <description>Channel 7 Interrupt Enable.</description> 565 <bitOffset>7</bitOffset> 566 <bitWidth>1</bitWidth> 567 </field> 568 </fields> 569 </register> 570 <register> 571 <name>INTFL</name> 572 <description>DMA Interrupt Register.</description> 573 <addressOffset>0x004</addressOffset> 574 <access>read-only</access> 575 <fields> 576 <field> 577 <name>CH0</name> 578 <description>Channel Interrupt. To clear an interrupt, all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN.</description> 579 <bitOffset>0</bitOffset> 580 <bitWidth>1</bitWidth> 581 <enumeratedValues> 582 <enumeratedValue> 583 <name>inactive</name> 584 <description>No interrupt is pending.</description> 585 <value>0</value> 586 </enumeratedValue> 587 <enumeratedValue> 588 <name>pending</name> 589 <description>An interrupt is pending.</description> 590 <value>1</value> 591 </enumeratedValue> 592 </enumeratedValues> 593 </field> 594 <field derivedFrom="CH0"> 595 <name>CH1</name> 596 <bitOffset>1</bitOffset> 597 <bitWidth>1</bitWidth> 598 </field> 599 <field derivedFrom="CH0"> 600 <name>CH2</name> 601 <bitOffset>2</bitOffset> 602 <bitWidth>1</bitWidth> 603 </field> 604 <field derivedFrom="CH0"> 605 <name>CH3</name> 606 <bitOffset>3</bitOffset> 607 <bitWidth>1</bitWidth> 608 </field> 609 <field derivedFrom="CH0"> 610 <name>CH4</name> 611 <bitOffset>4</bitOffset> 612 <bitWidth>1</bitWidth> 613 </field> 614 <field derivedFrom="CH0"> 615 <name>CH5</name> 616 <bitOffset>5</bitOffset> 617 <bitWidth>1</bitWidth> 618 </field> 619 <field derivedFrom="CH0"> 620 <name>CH6</name> 621 <bitOffset>6</bitOffset> 622 <bitWidth>1</bitWidth> 623 </field> 624 <field derivedFrom="CH0"> 625 <name>CH7</name> 626 <bitOffset>7</bitOffset> 627 <bitWidth>1</bitWidth> 628 </field> 629 </fields> 630 </register> 631 <cluster> 632 <dim>8</dim> 633 <dimIncrement>0x20</dimIncrement> 634 <name>CH[%s]</name> 635 <description>DMA Channel registers.</description> 636 <headerStructName>dma_ch</headerStructName> 637 <addressOffset>0x100</addressOffset> 638 <access>read-write</access> 639 <register> 640 <name>CTRL</name> 641 <description>DMA Channel Control Register.</description> 642 <addressOffset>0x000</addressOffset> 643 <fields> 644 <field> 645 <name>EN</name> 646 <description>Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0.</description> 647 <bitOffset>0</bitOffset> 648 <bitWidth>1</bitWidth> 649 <enumeratedValues> 650 <enumeratedValue> 651 <name>dis</name> 652 <description>Disable.</description> 653 <value>0</value> 654 </enumeratedValue> 655 <enumeratedValue> 656 <name>en</name> 657 <description>Enable.</description> 658 <value>1</value> 659 </enumeratedValue> 660 </enumeratedValues> 661 </field> 662 <field> 663 <name>RLDEN</name> 664 <description>Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed.</description> 665 <bitOffset>1</bitOffset> 666 <bitWidth>1</bitWidth> 667 <enumeratedValues> 668 <enumeratedValue> 669 <name>dis</name> 670 <description>Disable.</description> 671 <value>0</value> 672 </enumeratedValue> 673 <enumeratedValue> 674 <name>en</name> 675 <description>Enable.</description> 676 <value>1</value> 677 </enumeratedValue> 678 </enumeratedValues> 679 </field> 680 <field> 681 <name>PRI</name> 682 <description>DMA Priority.</description> 683 <bitOffset>2</bitOffset> 684 <bitWidth>2</bitWidth> 685 <enumeratedValues> 686 <enumeratedValue> 687 <name>high</name> 688 <description>Highest Priority.</description> 689 <value>0</value> 690 </enumeratedValue> 691 <enumeratedValue> 692 <name>medHigh</name> 693 <description>Medium High Priority.</description> 694 <value>1</value> 695 </enumeratedValue> 696 <enumeratedValue> 697 <name>medLow</name> 698 <description>Medium Low Priority.</description> 699 <value>2</value> 700 </enumeratedValue> 701 <enumeratedValue> 702 <name>low</name> 703 <description>Lowest Priority.</description> 704 <value>3</value> 705 </enumeratedValue> 706 </enumeratedValues> 707 </field> 708 <field> 709 <name>REQUEST</name> 710 <description>Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active.</description> 711 <bitOffset>4</bitOffset> 712 <bitWidth>6</bitWidth> 713 <enumeratedValues> 714 <enumeratedValue> 715 <name>MEMTOMEM</name> 716 <description>Memory To Memory</description> 717 <value>0x00</value> 718 </enumeratedValue> 719 <enumeratedValue> 720 <name>SPI0RX</name> 721 <description>SPI0 RX</description> 722 <value>0x01</value> 723 </enumeratedValue> 724 <enumeratedValue> 725 <name>SPI1RX</name> 726 <description>SPI1 RX</description> 727 <value>0x02</value> 728 </enumeratedValue> 729 <enumeratedValue> 730 <name>SPI2RX</name> 731 <description>SPI2 RX</description> 732 <value>0x03</value> 733 </enumeratedValue> 734 <enumeratedValue> 735 <name>UART0RX</name> 736 <description>UART0 RX</description> 737 <value>0x04</value> 738 </enumeratedValue> 739 <enumeratedValue> 740 <name>UART1RX</name> 741 <description>UART1 RX</description> 742 <value>0x05</value> 743 </enumeratedValue> 744 <enumeratedValue> 745 <name>I2C0RX</name> 746 <description>I2C0 RX</description> 747 <value>0x07</value> 748 </enumeratedValue> 749 <enumeratedValue> 750 <name>I2C1RX</name> 751 <description>I2C1 RX</description> 752 <value>0x08</value> 753 </enumeratedValue> 754 <enumeratedValue> 755 <name>I2C2RX</name> 756 <description>I2C2 RX</description> 757 <value>0x0A</value> 758 </enumeratedValue> 759 <enumeratedValue> 760 <name>UART2RX</name> 761 <description>UART2 RX</description> 762 <value>0x0E</value> 763 </enumeratedValue> 764 <enumeratedValue> 765 <name>SPI3RX</name> 766 <description>SPI3 RX</description> 767 <value>0x0F</value> 768 </enumeratedValue> 769 <enumeratedValue> 770 <name>AESRX</name> 771 <description>AES RX</description> 772 <value>0x10</value> 773 </enumeratedValue> 774 <enumeratedValue> 775 <name>UART3RX</name> 776 <description>UART3 RX</description> 777 <value>0x1C</value> 778 </enumeratedValue> 779 <enumeratedValue> 780 <name>I2SRX</name> 781 <description>I2S RX</description> 782 <value>0x1E</value> 783 </enumeratedValue> 784 <enumeratedValue> 785 <name>SPI0TX</name> 786 <description>SPI0 TX</description> 787 <value>0x21</value> 788 </enumeratedValue> 789 <enumeratedValue> 790 <name>SPI1TX</name> 791 <description>SPI1 TX</description> 792 <value>0x22</value> 793 </enumeratedValue> 794 <enumeratedValue> 795 <name>SPI2TX</name> 796 <description>SPI2 TX</description> 797 <value>0x23</value> 798 </enumeratedValue> 799 <enumeratedValue> 800 <name>UART0TX</name> 801 <description>UART0 TX</description> 802 <value>0x24</value> 803 </enumeratedValue> 804 <enumeratedValue> 805 <name>UART1TX</name> 806 <description>UART1 TX</description> 807 <value>0x25</value> 808 </enumeratedValue> 809 <enumeratedValue> 810 <name>I2C0TX</name> 811 <description>I2C0 TX</description> 812 <value>0x27</value> 813 </enumeratedValue> 814 <enumeratedValue> 815 <name>I2C1TX</name> 816 <description>I2C1 TX</description> 817 <value>0x28</value> 818 </enumeratedValue> 819 <enumeratedValue> 820 <name>I2C2TX</name> 821 <description>I2C2 TX</description> 822 <value>0x2A</value> 823 </enumeratedValue> 824 <enumeratedValue> 825 <name>CRCTX</name> 826 <description>CRC TX</description> 827 <value>0x2C</value> 828 </enumeratedValue> 829 <enumeratedValue> 830 <name>UART2TX</name> 831 <description>UART2 TX</description> 832 <value>0x2E</value> 833 </enumeratedValue> 834 <enumeratedValue> 835 <name>SPI3TX</name> 836 <description>SPI3 TX</description> 837 <value>0x2F</value> 838 </enumeratedValue> 839 <enumeratedValue> 840 <name>AESTX</name> 841 <description>AES TX</description> 842 <value>0x30</value> 843 </enumeratedValue> 844 <enumeratedValue> 845 <name>UART3TX</name> 846 <description>UART3 TX</description> 847 <value>0x3C</value> 848 </enumeratedValue> 849 <enumeratedValue> 850 <name>I2STX</name> 851 <description>I2S TX</description> 852 <value>0x3E</value> 853 </enumeratedValue> 854 </enumeratedValues> 855 </field> 856 <field> 857 <name>TO_WAIT</name> 858 <description>Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive.</description> 859 <bitOffset>10</bitOffset> 860 <bitWidth>1</bitWidth> 861 <enumeratedValues> 862 <enumeratedValue> 863 <name>dis</name> 864 <description>Disable.</description> 865 <value>0</value> 866 </enumeratedValue> 867 <enumeratedValue> 868 <name>en</name> 869 <description>Enable.</description> 870 <value>1</value> 871 </enumeratedValue> 872 </enumeratedValues> 873 </field> 874 <field> 875 <name>TO_PER</name> 876 <description>Timeout Period Select.</description> 877 <bitOffset>11</bitOffset> 878 <bitWidth>3</bitWidth> 879 <enumeratedValues> 880 <enumeratedValue> 881 <name>to4</name> 882 <description>Timeout of 3 to 4 prescale clocks.</description> 883 <value>0</value> 884 </enumeratedValue> 885 <enumeratedValue> 886 <name>to8</name> 887 <description>Timeout of 7 to 8 prescale clocks.</description> 888 <value>1</value> 889 </enumeratedValue> 890 <enumeratedValue> 891 <name>to16</name> 892 <description>Timeout of 15 to 16 prescale clocks.</description> 893 <value>2</value> 894 </enumeratedValue> 895 <enumeratedValue> 896 <name>to32</name> 897 <description>Timeout of 31 to 32 prescale clocks.</description> 898 <value>3</value> 899 </enumeratedValue> 900 <enumeratedValue> 901 <name>to64</name> 902 <description>Timeout of 63 to 64 prescale clocks.</description> 903 <value>4</value> 904 </enumeratedValue> 905 <enumeratedValue> 906 <name>to128</name> 907 <description>Timeout of 127 to 128 prescale clocks.</description> 908 <value>5</value> 909 </enumeratedValue> 910 <enumeratedValue> 911 <name>to256</name> 912 <description>Timeout of 255 to 256 prescale clocks.</description> 913 <value>6</value> 914 </enumeratedValue> 915 <enumeratedValue> 916 <name>to512</name> 917 <description>Timeout of 511 to 512 prescale clocks.</description> 918 <value>7</value> 919 </enumeratedValue> 920 </enumeratedValues> 921 </field> 922 <field> 923 <name>TO_CLKDIV</name> 924 <description>Pre-Scale Select. Selects the Pre-Scale divider for timer clock input.</description> 925 <bitOffset>14</bitOffset> 926 <bitWidth>2</bitWidth> 927 <enumeratedValues> 928 <enumeratedValue> 929 <name>dis</name> 930 <description>Disable timer.</description> 931 <value>0</value> 932 </enumeratedValue> 933 <enumeratedValue> 934 <name>div256</name> 935 <description>hclk / 256.</description> 936 <value>1</value> 937 </enumeratedValue> 938 <enumeratedValue> 939 <name>div64k</name> 940 <description>hclk / 64k.</description> 941 <value>2</value> 942 </enumeratedValue> 943 <enumeratedValue> 944 <name>div16M</name> 945 <description>hclk / 16M.</description> 946 <value>3</value> 947 </enumeratedValue> 948 </enumeratedValues> 949 </field> 950 <field> 951 <name>SRCWD</name> 952 <description>Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value.</description> 953 <bitOffset>16</bitOffset> 954 <bitWidth>2</bitWidth> 955 <enumeratedValues> 956 <enumeratedValue> 957 <name>byte</name> 958 <description>Byte.</description> 959 <value>0</value> 960 </enumeratedValue> 961 <enumeratedValue> 962 <name>halfWord</name> 963 <description>Halfword.</description> 964 <value>1</value> 965 </enumeratedValue> 966 <enumeratedValue> 967 <name>word</name> 968 <description>Word.</description> 969 <value>2</value> 970 </enumeratedValue> 971 </enumeratedValues> 972 </field> 973 <field> 974 <name>SRCINC</name> 975 <description>Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals.</description> 976 <bitOffset>18</bitOffset> 977 <bitWidth>1</bitWidth> 978 <enumeratedValues> 979 <enumeratedValue> 980 <name>dis</name> 981 <description>Disable.</description> 982 <value>0</value> 983 </enumeratedValue> 984 <enumeratedValue> 985 <name>en</name> 986 <description>Enable.</description> 987 <value>1</value> 988 </enumeratedValue> 989 </enumeratedValues> 990 </field> 991 <field> 992 <name>DSTWD</name> 993 <description>Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width).</description> 994 <bitOffset>20</bitOffset> 995 <bitWidth>2</bitWidth> 996 <enumeratedValues> 997 <enumeratedValue> 998 <name>byte</name> 999 <description>Byte.</description> 1000 <value>0</value> 1001 </enumeratedValue> 1002 <enumeratedValue> 1003 <name>halfWord</name> 1004 <description>Halfword.</description> 1005 <value>1</value> 1006 </enumeratedValue> 1007 <enumeratedValue> 1008 <name>word</name> 1009 <description>Word.</description> 1010 <value>2</value> 1011 </enumeratedValue> 1012 </enumeratedValues> 1013 </field> 1014 <field> 1015 <name>DSTINC</name> 1016 <description>Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals.</description> 1017 <bitOffset>22</bitOffset> 1018 <bitWidth>1</bitWidth> 1019 <enumeratedValues> 1020 <enumeratedValue> 1021 <name>dis</name> 1022 <description>Disable.</description> 1023 <value>0</value> 1024 </enumeratedValue> 1025 <enumeratedValue> 1026 <name>en</name> 1027 <description>Enable.</description> 1028 <value>1</value> 1029 </enumeratedValue> 1030 </enumeratedValues> 1031 </field> 1032 <field> 1033 <name>BURST_SIZE</name> 1034 <description>Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field.</description> 1035 <bitOffset>24</bitOffset> 1036 <bitWidth>5</bitWidth> 1037 </field> 1038 <field> 1039 <name>DIS_IE</name> 1040 <description>Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0.</description> 1041 <bitOffset>30</bitOffset> 1042 <bitWidth>1</bitWidth> 1043 <enumeratedValues> 1044 <enumeratedValue> 1045 <name>dis</name> 1046 <description>Disable.</description> 1047 <value>0</value> 1048 </enumeratedValue> 1049 <enumeratedValue> 1050 <name>en</name> 1051 <description>Enable.</description> 1052 <value>1</value> 1053 </enumeratedValue> 1054 </enumeratedValues> 1055 </field> 1056 <field> 1057 <name>CTZ_IE</name> 1058 <description>Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs.</description> 1059 <bitOffset>31</bitOffset> 1060 <bitWidth>1</bitWidth> 1061 <enumeratedValues> 1062 <enumeratedValue> 1063 <name>dis</name> 1064 <description>Disable.</description> 1065 <value>0</value> 1066 </enumeratedValue> 1067 <enumeratedValue> 1068 <name>en</name> 1069 <description>Enable.</description> 1070 <value>1</value> 1071 </enumeratedValue> 1072 </enumeratedValues> 1073 </field> 1074 </fields> 1075 </register> 1076 <register> 1077 <name>STATUS</name> 1078 <description>DMA Channel Status Register.</description> 1079 <addressOffset>0x004</addressOffset> 1080 <fields> 1081 <field> 1082 <name>STATUS</name> 1083 <description>Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already).</description> 1084 <bitOffset>0</bitOffset> 1085 <bitWidth>1</bitWidth> 1086 <access>read-only</access> 1087 <enumeratedValues> 1088 <enumeratedValue> 1089 <name>dis</name> 1090 <description>Disable.</description> 1091 <value>0</value> 1092 </enumeratedValue> 1093 <enumeratedValue> 1094 <name>en</name> 1095 <description>Enable.</description> 1096 <value>1</value> 1097 </enumeratedValue> 1098 </enumeratedValues> 1099 </field> 1100 <field> 1101 <name>IPEND</name> 1102 <description>Channel Interrupt.</description> 1103 <bitOffset>1</bitOffset> 1104 <bitWidth>1</bitWidth> 1105 <access>read-only</access> 1106 <enumeratedValues> 1107 <enumeratedValue> 1108 <name>inactive</name> 1109 <description>No interrupt is pending.</description> 1110 <value>0</value> 1111 </enumeratedValue> 1112 <enumeratedValue> 1113 <name>pending</name> 1114 <description>An interrupt is pending.</description> 1115 <value>1</value> 1116 </enumeratedValue> 1117 </enumeratedValues> 1118 </field> 1119 <field> 1120 <name>CTZ_IF</name> 1121 <description>Count-to-Zero (CTZ) Interrupt Flag</description> 1122 <bitOffset>2</bitOffset> 1123 <bitWidth>1</bitWidth> 1124 <modifiedWriteValues>oneToClear</modifiedWriteValues> 1125 </field> 1126 <field> 1127 <name>RLD_IF</name> 1128 <description>Reload Event Interrupt Flag.</description> 1129 <bitOffset>3</bitOffset> 1130 <bitWidth>1</bitWidth> 1131 <modifiedWriteValues>oneToClear</modifiedWriteValues> 1132 </field> 1133 <field> 1134 <name>BUS_ERR</name> 1135 <description>Bus Error. Indicates that an AHB abort was received and the channel has been disabled.</description> 1136 <bitOffset>4</bitOffset> 1137 <bitWidth>1</bitWidth> 1138 <modifiedWriteValues>oneToClear</modifiedWriteValues> 1139 </field> 1140 <field> 1141 <name>TO_IF</name> 1142 <description>Time-Out Event Interrupt Flag.</description> 1143 <bitOffset>6</bitOffset> 1144 <bitWidth>1</bitWidth> 1145 <modifiedWriteValues>oneToClear</modifiedWriteValues> 1146 </field> 1147 </fields> 1148 </register> 1149 <register> 1150 <name>SRC</name> 1151 <description>Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.</description> 1152 <addressOffset>0x008</addressOffset> 1153 <fields> 1154 <field> 1155 <name>ADDR</name> 1156 <bitOffset>0</bitOffset> 1157 <bitWidth>32</bitWidth> 1158 </field> 1159 </fields> 1160 </register> 1161 <register> 1162 <name>DST</name> 1163 <description>Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD.</description> 1164 <addressOffset>0x00C</addressOffset> 1165 <fields> 1166 <field> 1167 <name>ADDR</name> 1168 <bitOffset>0</bitOffset> 1169 <bitWidth>32</bitWidth> 1170 </field> 1171 </fields> 1172 </register> 1173 <register> 1174 <name>CNT</name> 1175 <description>DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered.</description> 1176 <addressOffset>0x010</addressOffset> 1177 <fields> 1178 <field> 1179 <name>CNT</name> 1180 <description>DMA Counter.</description> 1181 <bitOffset>0</bitOffset> 1182 <bitWidth>24</bitWidth> 1183 </field> 1184 </fields> 1185 </register> 1186 <register> 1187 <name>SRCRLD</name> 1188 <description>Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition.</description> 1189 <addressOffset>0x014</addressOffset> 1190 <fields> 1191 <field> 1192 <name>ADDR</name> 1193 <description>Source Address Reload Value.</description> 1194 <bitOffset>0</bitOffset> 1195 <bitWidth>31</bitWidth> 1196 </field> 1197 </fields> 1198 </register> 1199 <register> 1200 <name>DSTRLD</name> 1201 <description>Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition.</description> 1202 <addressOffset>0x018</addressOffset> 1203 <fields> 1204 <field> 1205 <name>ADDR</name> 1206 <description>Destination Address Reload Value.</description> 1207 <bitOffset>0</bitOffset> 1208 <bitWidth>31</bitWidth> 1209 </field> 1210 </fields> 1211 </register> 1212 <register> 1213 <name>CNTRLD</name> 1214 <description>DMA Channel Count Reload Register.</description> 1215 <addressOffset>0x01C</addressOffset> 1216 <fields> 1217 <field> 1218 <name>CNT</name> 1219 <description>Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition.</description> 1220 <bitOffset>0</bitOffset> 1221 <bitWidth>24</bitWidth> 1222 </field> 1223 <field> 1224 <name>EN</name> 1225 <description>Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs.</description> 1226 <bitOffset>31</bitOffset> 1227 <bitWidth>1</bitWidth> 1228 <enumeratedValues> 1229 <enumeratedValue> 1230 <name>dis</name> 1231 <description>Disable.</description> 1232 <value>0</value> 1233 </enumeratedValue> 1234 <enumeratedValue> 1235 <name>en</name> 1236 <description>Enable.</description> 1237 <value>1</value> 1238 </enumeratedValue> 1239 </enumeratedValues> 1240 </field> 1241 </fields> 1242 </register> 1243 </cluster> 1244 </registers> 1245 </peripheral> 1246<!--DMA DMA Controller Fully programmable, chaining capable DMA channels.--> 1247 <peripheral> 1248 <name>FCR</name> 1249 <description>Function Control Register.</description> 1250 <baseAddress>0x40000800</baseAddress> 1251 <addressBlock> 1252 <offset>0x00</offset> 1253 <size>0x400</size> 1254 <usage>registers</usage> 1255 </addressBlock> 1256 <registers> 1257 <register> 1258 <name>FCTRL0</name> 1259 <description>Register 0.</description> 1260 <addressOffset>0x00</addressOffset> 1261 <access>read-write</access> 1262 <fields> 1263 <field> 1264 <name>ERFO_RANGE_SEL</name> 1265 <description>14MHz-32MHz ERFO Frequency Range Select.</description> 1266 <bitOffset>0</bitOffset> 1267 <bitWidth>3</bitWidth> 1268 </field> 1269 <field> 1270 <name>I2C0_SDA_FILTER_EN</name> 1271 <description>I2C0 SDA Glitch Filter Enable.</description> 1272 <bitOffset>20</bitOffset> 1273 <bitWidth>1</bitWidth> 1274 <enumeratedValues> 1275 <enumeratedValue> 1276 <name>dis</name> 1277 <description>Filter disabled.</description> 1278 <value>0</value> 1279 </enumeratedValue> 1280 <enumeratedValue> 1281 <name>en</name> 1282 <description>Filter enabled.</description> 1283 <value>1</value> 1284 </enumeratedValue> 1285 </enumeratedValues> 1286 </field> 1287 <field> 1288 <name>I2C0_SCL_FILTER_EN</name> 1289 <description>I2C0 SCL Glitch Filter Enable.</description> 1290 <bitOffset>21</bitOffset> 1291 <bitWidth>1</bitWidth> 1292 <enumeratedValues> 1293 <enumeratedValue> 1294 <name>dis</name> 1295 <description>Filter disabled.</description> 1296 <value>0</value> 1297 </enumeratedValue> 1298 <enumeratedValue> 1299 <name>en</name> 1300 <description>Filter enabled.</description> 1301 <value>1</value> 1302 </enumeratedValue> 1303 </enumeratedValues> 1304 </field> 1305 <field> 1306 <name>I2C1_SDA_FILTER_EN</name> 1307 <description>I2C1 SDA Glitch Filter Enable.</description> 1308 <bitOffset>22</bitOffset> 1309 <bitWidth>1</bitWidth> 1310 <enumeratedValues> 1311 <enumeratedValue> 1312 <name>dis</name> 1313 <description>Filter disabled.</description> 1314 <value>0</value> 1315 </enumeratedValue> 1316 <enumeratedValue> 1317 <name>en</name> 1318 <description>Filter enabled.</description> 1319 <value>1</value> 1320 </enumeratedValue> 1321 </enumeratedValues> 1322 </field> 1323 <field> 1324 <name>I2C1_SCL_FILTER_EN</name> 1325 <description>I2C1 SCL Glitch Filter Enable.</description> 1326 <bitOffset>23</bitOffset> 1327 <bitWidth>1</bitWidth> 1328 <enumeratedValues> 1329 <enumeratedValue> 1330 <name>dis</name> 1331 <description>Filter disabled.</description> 1332 <value>0</value> 1333 </enumeratedValue> 1334 <enumeratedValue> 1335 <name>en</name> 1336 <description>Filter enabled.</description> 1337 <value>1</value> 1338 </enumeratedValue> 1339 </enumeratedValues> 1340 </field> 1341 <field> 1342 <name>I2C2_SDA_FILTER_EN</name> 1343 <description>I2C2 SDA Glitch Filter Enable.</description> 1344 <bitOffset>24</bitOffset> 1345 <bitWidth>1</bitWidth> 1346 <enumeratedValues> 1347 <enumeratedValue> 1348 <name>dis</name> 1349 <description>Filter disabled.</description> 1350 <value>0</value> 1351 </enumeratedValue> 1352 <enumeratedValue> 1353 <name>en</name> 1354 <description>Filter enabled.</description> 1355 <value>1</value> 1356 </enumeratedValue> 1357 </enumeratedValues> 1358 </field> 1359 <field> 1360 <name>I2C2_SCL_FILTER_EN</name> 1361 <description>I2C2 SCL Glitch Filter Enable.</description> 1362 <bitOffset>25</bitOffset> 1363 <bitWidth>1</bitWidth> 1364 <enumeratedValues> 1365 <enumeratedValue> 1366 <name>dis</name> 1367 <description>Filter disabled.</description> 1368 <value>0</value> 1369 </enumeratedValue> 1370 <enumeratedValue> 1371 <name>en</name> 1372 <description>Filter enabled.</description> 1373 <value>1</value> 1374 </enumeratedValue> 1375 </enumeratedValues> 1376 </field> 1377 </fields> 1378 </register> 1379 <register> 1380 <name>AUTOCAL0</name> 1381 <description>Register 1.</description> 1382 <addressOffset>0x04</addressOffset> 1383 <access>read-write</access> 1384 <fields> 1385 <field> 1386 <name>SEL</name> 1387 <description>Auto-calibration Enable.</description> 1388 <bitOffset>0</bitOffset> 1389 <bitWidth>1</bitWidth> 1390 <enumeratedValues> 1391 <enumeratedValue> 1392 <name>dis</name> 1393 <description>Disabled.</description> 1394 <value>0</value> 1395 </enumeratedValue> 1396 <enumeratedValue> 1397 <name>en</name> 1398 <description>Enabled.</description> 1399 <value>1</value> 1400 </enumeratedValue> 1401 </enumeratedValues> 1402 </field> 1403 <field> 1404 <name>EN</name> 1405 <description>Autocalibration Run.</description> 1406 <bitOffset>1</bitOffset> 1407 <bitWidth>1</bitWidth> 1408 <enumeratedValues> 1409 <enumeratedValue> 1410 <name>not</name> 1411 <description>Not Running.</description> 1412 <value>0</value> 1413 </enumeratedValue> 1414 <enumeratedValue> 1415 <name>run</name> 1416 <description>Running.</description> 1417 <value>1</value> 1418 </enumeratedValue> 1419 </enumeratedValues> 1420 </field> 1421 <field> 1422 <name>LOAD</name> 1423 <description>Load Trim.</description> 1424 <bitOffset>2</bitOffset> 1425 <bitWidth>1</bitWidth> 1426 </field> 1427 <field> 1428 <name>INVERT</name> 1429 <description>Invert Gain.</description> 1430 <bitOffset>3</bitOffset> 1431 <bitWidth>1</bitWidth> 1432 <enumeratedValues> 1433 <enumeratedValue> 1434 <name>not</name> 1435 <description>Not Running.</description> 1436 <value>0</value> 1437 </enumeratedValue> 1438 <enumeratedValue> 1439 <name>run</name> 1440 <description>Running.</description> 1441 <value>1</value> 1442 </enumeratedValue> 1443 </enumeratedValues> 1444 </field> 1445 <field> 1446 <name>ATOMIC</name> 1447 <description>Atomic mode.</description> 1448 <bitOffset>4</bitOffset> 1449 <bitWidth>1</bitWidth> 1450 <enumeratedValues> 1451 <enumeratedValue> 1452 <name>not</name> 1453 <description>Not Running.</description> 1454 <value>0</value> 1455 </enumeratedValue> 1456 <enumeratedValue> 1457 <name>run</name> 1458 <description>Running.</description> 1459 <value>1</value> 1460 </enumeratedValue> 1461 </enumeratedValues> 1462 </field> 1463 <field> 1464 <name>GAIN</name> 1465 <description>MU value.</description> 1466 <bitOffset>8</bitOffset> 1467 <bitWidth>12</bitWidth> 1468 </field> 1469 <field> 1470 <name>TRIM</name> 1471 <description>150MHz HFIO Auto Calibration Trim</description> 1472 <bitOffset>23</bitOffset> 1473 <bitWidth>9</bitWidth> 1474 </field> 1475 </fields> 1476 </register> 1477 <register> 1478 <name>AUTOCAL1</name> 1479 <description>Register 2.</description> 1480 <addressOffset>0x08</addressOffset> 1481 <access>read-write</access> 1482 <fields> 1483 <field> 1484 <name>INITIAL</name> 1485 <description>100MHz IPO Trim Automatic Calibration Initial Trim.</description> 1486 <bitOffset>0</bitOffset> 1487 <bitWidth>9</bitWidth> 1488 </field> 1489 </fields> 1490 </register> 1491 <register> 1492 <name>AUTOCAL2</name> 1493 <description>Register 3.</description> 1494 <addressOffset>0x0C</addressOffset> 1495 <access>read-write</access> 1496 <fields> 1497 <field> 1498 <name>RUNTIME</name> 1499 <description>100MHz IPO Trim Automatic Calibration Run Time.</description> 1500 <bitOffset>0</bitOffset> 1501 <bitWidth>8</bitWidth> 1502 </field> 1503 <field> 1504 <name>DIV</name> 1505 <description>100MHz IPO Trim Automatic Calibration Divide Factor.</description> 1506 <bitOffset>8</bitOffset> 1507 <bitWidth>13</bitWidth> 1508 </field> 1509 </fields> 1510 </register> 1511 </registers> 1512 </peripheral> 1513<!--FCR Function Control Register.--> 1514 <peripheral> 1515 <name>FLC</name> 1516 <description>Flash Memory Control.</description> 1517 <prependToName>FLSH_</prependToName> 1518 <baseAddress>0x40029000</baseAddress> 1519 <addressBlock> 1520 <offset>0x00</offset> 1521 <size>0x1000</size> 1522 <usage>registers</usage> 1523 </addressBlock> 1524 <interrupt> 1525 <name>Flash_Controller</name> 1526 <description>Flash Controller interrupt.</description> 1527 <value>23</value> 1528 </interrupt> 1529 <registers> 1530 <register> 1531 <name>ADDR</name> 1532 <description>Flash Write Address.</description> 1533 <addressOffset>0x00</addressOffset> 1534 <fields> 1535 <field> 1536 <name>ADDR</name> 1537 <description>Address for next operation.</description> 1538 <bitOffset>0</bitOffset> 1539 <bitWidth>32</bitWidth> 1540 </field> 1541 </fields> 1542 </register> 1543 <register> 1544 <name>CLKDIV</name> 1545 <description>Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller.</description> 1546 <addressOffset>0x04</addressOffset> 1547 <resetValue>0x00000064</resetValue> 1548 <fields> 1549 <field> 1550 <name>CLKDIV</name> 1551 <description>Flash Clock Divide. The clock is divided by this value to generate a 1MHz clock for flash controller.</description> 1552 <bitOffset>0</bitOffset> 1553 <bitWidth>8</bitWidth> 1554 </field> 1555 </fields> 1556 </register> 1557 <register> 1558 <name>CTRL</name> 1559 <description>Flash Control Register.</description> 1560 <addressOffset>0x08</addressOffset> 1561 <fields> 1562 <field> 1563 <name>WR</name> 1564 <description>Write. This bit is automatically cleared after the operation.</description> 1565 <bitOffset>0</bitOffset> 1566 <bitWidth>1</bitWidth> 1567 <enumeratedValues> 1568 <enumeratedValue> 1569 <name>complete</name> 1570 <description>No operation/complete.</description> 1571 <value>0</value> 1572 </enumeratedValue> 1573 <enumeratedValue> 1574 <name>start</name> 1575 <description>Start operation.</description> 1576 <value>1</value> 1577 </enumeratedValue> 1578 </enumeratedValues> 1579 </field> 1580 <field derivedFrom="WR"> 1581 <name>ME</name> 1582 <description>Mass Erase. This bit is automatically cleared after the operation.</description> 1583 <bitOffset>1</bitOffset> 1584 <bitWidth>1</bitWidth> 1585 </field> 1586 <field derivedFrom="WR"> 1587 <name>PGE</name> 1588 <description>Page Erase. This bit is automatically cleared after the operation.</description> 1589 <bitOffset>2</bitOffset> 1590 <bitWidth>1</bitWidth> 1591 </field> 1592 <field> 1593 <name>ERASE_CODE</name> 1594 <description>Erase Code. The ERASE_CODE must be set up property before erase operation can be initiated. These bits are automatically cleared after the operation is complete.</description> 1595 <bitOffset>8</bitOffset> 1596 <bitWidth>8</bitWidth> 1597 <enumeratedValues> 1598 <enumeratedValue> 1599 <name>nop</name> 1600 <description>No operation.</description> 1601 <value>0</value> 1602 </enumeratedValue> 1603 <enumeratedValue> 1604 <name>erasePage</name> 1605 <description>Enable Page Erase.</description> 1606 <value>0x55</value> 1607 </enumeratedValue> 1608 <enumeratedValue> 1609 <name>eraseAll</name> 1610 <description>Enable Mass Erase. The debug port must be enabled.</description> 1611 <value>0xAA</value> 1612 </enumeratedValue> 1613 </enumeratedValues> 1614 </field> 1615 <field> 1616 <name>PEND</name> 1617 <description>Flash Pending. When Flash operation is in progress (busy), Flash reads and writes will fail. When PEND is set, write to all Flash registers, with exception of the Flash interrupt register, are ignored.</description> 1618 <bitOffset>24</bitOffset> 1619 <bitWidth>1</bitWidth> 1620 <access>read-only</access> 1621 <enumeratedValues> 1622 <enumeratedValue> 1623 <name>idle</name> 1624 <description>Idle.</description> 1625 <value>0</value> 1626 </enumeratedValue> 1627 <enumeratedValue> 1628 <name>busy</name> 1629 <description>Busy.</description> 1630 <value>1</value> 1631 </enumeratedValue> 1632 </enumeratedValues> 1633 </field> 1634 <field> 1635 <name>LVE</name> 1636 <description>Low Voltage enable.</description> 1637 <bitOffset>25</bitOffset> 1638 <bitWidth>1</bitWidth> 1639 </field> 1640 <field> 1641 <name>UNLOCK</name> 1642 <description>Flash Unlock. The correct unlock code must be written to these four bits before any Flash write or erase operation is allowed.</description> 1643 <bitOffset>28</bitOffset> 1644 <bitWidth>4</bitWidth> 1645 <enumeratedValues> 1646 <enumeratedValue> 1647 <name>unlocked</name> 1648 <description>Flash Unlocked.</description> 1649 <value>2</value> 1650 </enumeratedValue> 1651 <enumeratedValue> 1652 <name>locked</name> 1653 <description>Flash Locked.</description> 1654 <value>3</value> 1655 </enumeratedValue> 1656 </enumeratedValues> 1657 </field> 1658 </fields> 1659 </register> 1660 <register> 1661 <name>INTR</name> 1662 <description>Flash Interrupt Register.</description> 1663 <addressOffset>0x024</addressOffset> 1664 <fields> 1665 <field> 1666 <name>DONE</name> 1667 <description>Flash Done Interrupt. This bit is set to 1 upon Flash write or erase completion.</description> 1668 <bitOffset>0</bitOffset> 1669 <bitWidth>1</bitWidth> 1670 <enumeratedValues> 1671 <enumeratedValue> 1672 <name>inactive</name> 1673 <description>No interrupt is pending.</description> 1674 <value>0</value> 1675 </enumeratedValue> 1676 <enumeratedValue> 1677 <name>pending</name> 1678 <description>An interrupt is pending.</description> 1679 <value>1</value> 1680 </enumeratedValue> 1681 </enumeratedValues> 1682 </field> 1683 <field> 1684 <name>AF</name> 1685 <description>Flash Access Fail. This bit is set when an attempt is made to write the flash while the flash is busy or the flash is locked. This bit can only be set to 1 by hardware.</description> 1686 <bitOffset>1</bitOffset> 1687 <bitWidth>1</bitWidth> 1688 <enumeratedValues> 1689 <enumeratedValue> 1690 <name>noError</name> 1691 <description>No Failure.</description> 1692 <value>0</value> 1693 </enumeratedValue> 1694 <enumeratedValue> 1695 <name>error</name> 1696 <description>Failure occurs.</description> 1697 <value>1</value> 1698 </enumeratedValue> 1699 </enumeratedValues> 1700 </field> 1701 <field> 1702 <name>DONEIE</name> 1703 <description>Flash Done Interrupt Enable.</description> 1704 <bitOffset>8</bitOffset> 1705 <bitWidth>1</bitWidth> 1706 <enumeratedValues> 1707 <enumeratedValue> 1708 <name>disable</name> 1709 <description>Disable.</description> 1710 <value>0</value> 1711 </enumeratedValue> 1712 <enumeratedValue> 1713 <name>enable</name> 1714 <description>Enable.</description> 1715 <value>1</value> 1716 </enumeratedValue> 1717 </enumeratedValues> 1718 </field> 1719 <field derivedFrom="DONEIE"> 1720 <name>AFIE</name> 1721 <bitOffset>9</bitOffset> 1722 <bitWidth>1</bitWidth> 1723 </field> 1724 </fields> 1725 </register> 1726 <register> 1727 <name>ECCDATA</name> 1728 <description>ECC Data Register.</description> 1729 <addressOffset>0x028</addressOffset> 1730 <fields> 1731 <field> 1732 <name>EVEN</name> 1733 <description>Error Correction Code Odd Data.</description> 1734 <bitOffset>0</bitOffset> 1735 <bitWidth>9</bitWidth> 1736 </field> 1737 <field> 1738 <name>ODD</name> 1739 <description>Error Correction Code Even Data.</description> 1740 <bitOffset>16</bitOffset> 1741 <bitWidth>9</bitWidth> 1742 </field> 1743 </fields> 1744 </register> 1745 <register> 1746 <dim>4</dim> 1747 <dimIncrement>4</dimIncrement> 1748 <name>DATA[%s]</name> 1749 <description>Flash Write Data.</description> 1750 <addressOffset>0x30</addressOffset> 1751 <fields> 1752 <field> 1753 <name>DATA</name> 1754 <description>Data next operation.</description> 1755 <bitOffset>0</bitOffset> 1756 <bitWidth>32</bitWidth> 1757 </field> 1758 </fields> 1759 </register> 1760 <register> 1761 <name>ACTRL</name> 1762 <description>Access Control Register. Writing the ACTRL register with the following values in the order shown, allows read and write access to the system and user Information block: 1763 pflc-actrl = 0x3a7f5ca3; 1764 pflc-actrl = 0xa1e34f20; 1765 pflc-actrl = 0x9608b2c1. When unlocked, a write of any word will disable access to system and user information block. Readback of this register is always zero.</description> 1766 <addressOffset>0x40</addressOffset> 1767 <access>write-only</access> 1768 <fields> 1769 <field> 1770 <name>ACTRL</name> 1771 <description>Access control.</description> 1772 <bitOffset>0</bitOffset> 1773 <bitWidth>32</bitWidth> 1774 </field> 1775 </fields> 1776 </register> 1777 <register> 1778 <name>WELR0</name> 1779 <description>WELR0</description> 1780 <addressOffset>0x80</addressOffset> 1781 <fields> 1782 <field> 1783 <name>WELR0</name> 1784 <description>Access control.</description> 1785 <bitOffset>0</bitOffset> 1786 <bitWidth>32</bitWidth> 1787 </field> 1788 </fields> 1789 </register> 1790 <register> 1791 <name>WELR1</name> 1792 <description>WELR1</description> 1793 <addressOffset>0x88</addressOffset> 1794 <fields> 1795 <field> 1796 <name>WELR1</name> 1797 <description>Access control.</description> 1798 <bitOffset>0</bitOffset> 1799 <bitWidth>32</bitWidth> 1800 </field> 1801 </fields> 1802 </register> 1803 <register> 1804 <name>RLR0</name> 1805 <description>RLR0</description> 1806 <addressOffset>0x90</addressOffset> 1807 <fields> 1808 <field> 1809 <name>RLR0</name> 1810 <description>Access control.</description> 1811 <bitOffset>0</bitOffset> 1812 <bitWidth>32</bitWidth> 1813 </field> 1814 </fields> 1815 </register> 1816 <register> 1817 <name>RLR1</name> 1818 <description>RLR1</description> 1819 <addressOffset>0x98</addressOffset> 1820 <fields> 1821 <field> 1822 <name>RLR1</name> 1823 <description>Access control.</description> 1824 <bitOffset>0</bitOffset> 1825 <bitWidth>32</bitWidth> 1826 </field> 1827 </fields> 1828 </register> 1829 </registers> 1830 </peripheral> 1831<!--FLC Flash Memory Control.--> 1832 <peripheral> 1833 <name>GCR</name> 1834 <description>Global Control Registers.</description> 1835 <baseAddress>0x40000000</baseAddress> 1836 <addressBlock> 1837 <offset>0</offset> 1838 <size>0x400</size> 1839 <usage>registers</usage> 1840 </addressBlock> 1841 <registers> 1842 <register> 1843 <name>SYSCTRL</name> 1844 <description>System Control.</description> 1845 <addressOffset>0x00</addressOffset> 1846 <resetMask>0xFFFFFFFE</resetMask> 1847 <fields> 1848 <field> 1849 <name>SBUSARB</name> 1850 <description>System bus abritration scheme. These bits are used to select between Fixed-burst abritration and Round-Robin scheme. The Round-Robin scheme is selected by default. These bits are reset by the system reset.</description> 1851 <bitOffset>1</bitOffset> 1852 <bitWidth>2</bitWidth> 1853 <enumeratedValues> 1854 <enumeratedValue> 1855 <name>fix</name> 1856 <description>Fixed Burst abritration.</description> 1857 <value>0</value> 1858 </enumeratedValue> 1859 <enumeratedValue> 1860 <name>round</name> 1861 <description>Round-robin scheme.</description> 1862 <value>1</value> 1863 </enumeratedValue> 1864 </enumeratedValues> 1865 </field> 1866 <field> 1867 <name>FPU_DIS</name> 1868 <description>Cortex M4 Floating Point Disable This bit is used to disable the floating-point unit of the Cortex-M4</description> 1869 <bitOffset>5</bitOffset> 1870 <bitWidth>1</bitWidth> 1871 </field> 1872 <field> 1873 <name>ICC0_FLUSH</name> 1874 <description>Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. </description> 1875 <bitOffset>6</bitOffset> 1876 <bitWidth>1</bitWidth> 1877 <enumeratedValues> 1878 <enumeratedValue> 1879 <name>normal</name> 1880 <description>Normal Code Cache Operation</description> 1881 <value>0</value> 1882 </enumeratedValue> 1883 <enumeratedValue> 1884 <name>flush</name> 1885 <description>Code Caches and CPU instruction buffer are flushed </description> 1886 <value>1</value> 1887 </enumeratedValue> 1888 </enumeratedValues> 1889 </field> 1890 <field> 1891 <name>ROMDONE</name> 1892 <description>ROM_DONE status. Used to disable SWD interface during system initialization procedure</description> 1893 <bitOffset>12</bitOffset> 1894 <bitWidth>1</bitWidth> 1895 </field> 1896 <field> 1897 <name>CCHK</name> 1898 <description>Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed.</description> 1899 <bitOffset>13</bitOffset> 1900 <bitWidth>1</bitWidth> 1901 <enumeratedValues> 1902 <enumeratedValue> 1903 <name>complete</name> 1904 <description>No operation/complete.</description> 1905 <value>0</value> 1906 </enumeratedValue> 1907 <enumeratedValue> 1908 <name>start</name> 1909 <description>Start operation.</description> 1910 <value>1</value> 1911 </enumeratedValue> 1912 </enumeratedValues> 1913 </field> 1914 <field> 1915 <name>SWD_DIS</name> 1916 <description> Serial Wire Debug Disable. This bit is used to disable the serial wire debug interface This bit is only writeable if (FMV lock word is not programmed) or if (ICE lock word is not programmed and the ROM_DONE bit is not set) 1917 </description> 1918 <bitOffset>14</bitOffset> 1919 <bitWidth>1</bitWidth> 1920 </field> 1921 <field> 1922 <name>CHKRES</name> 1923 <description>ROM Checksum Result. This bit is only valid when CHKRD=1.</description> 1924 <bitOffset>15</bitOffset> 1925 <bitWidth>1</bitWidth> 1926 <enumeratedValues> 1927 <enumeratedValue> 1928 <name>pass</name> 1929 <description>ROM Checksum Correct.</description> 1930 <value>0</value> 1931 </enumeratedValue> 1932 <enumeratedValue> 1933 <name>fail</name> 1934 <description>ROM Checksum Fail.</description> 1935 <value>1</value> 1936 </enumeratedValue> 1937 </enumeratedValues> 1938 </field> 1939 </fields> 1940 </register> 1941 <register> 1942 <name>RST0</name> 1943 <description>Reset.</description> 1944 <addressOffset>0x04</addressOffset> 1945 <fields> 1946 <field> 1947 <name>DMA</name> 1948 <description>DMA Reset.</description> 1949 <bitOffset>0</bitOffset> 1950 <bitWidth>1</bitWidth> 1951 <enumeratedValues> 1952 <name>reset</name> 1953 <usage>read-write</usage> 1954 <enumeratedValue> 1955 <name>reset_done</name> 1956 <description>Reset complete.</description> 1957 <value>0</value> 1958 </enumeratedValue> 1959 <enumeratedValue> 1960 <name>busy</name> 1961 <description>Starts Reset or indicates reset in progress.</description> 1962 <value>1</value> 1963 </enumeratedValue> 1964 </enumeratedValues> 1965 </field> 1966 <field derivedFrom="DMA"> 1967 <name>WDT0</name> 1968 <description>Watchdog Timer Reset.</description> 1969 <bitOffset>1</bitOffset> 1970 <bitWidth>1</bitWidth> 1971 </field> 1972 <field derivedFrom="DMA"> 1973 <name>GPIO0</name> 1974 <description>GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states.</description> 1975 <bitOffset>2</bitOffset> 1976 <bitWidth>1</bitWidth> 1977 </field> 1978 <field derivedFrom="DMA"> 1979 <name>GPIO1</name> 1980 <description>GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states.</description> 1981 <bitOffset>3</bitOffset> 1982 <bitWidth>1</bitWidth> 1983 </field> 1984 <field derivedFrom="DMA"> 1985 <name>TMR0</name> 1986 <description>Timer0 Reset. Setting this bit to 1 resets Timer 0 blocks.</description> 1987 <bitOffset>5</bitOffset> 1988 <bitWidth>1</bitWidth> 1989 </field> 1990 <field derivedFrom="DMA"> 1991 <name>TMR1</name> 1992 <description>Timer1 Reset. Setting this bit to 1 resets Timer 1 blocks.</description> 1993 <bitOffset>6</bitOffset> 1994 <bitWidth>1</bitWidth> 1995 </field> 1996 <field derivedFrom="DMA"> 1997 <name>TMR2</name> 1998 <description>Timer2 Reset. Setting this bit to 1 resets Timer 2 blocks.</description> 1999 <bitOffset>7</bitOffset> 2000 <bitWidth>1</bitWidth> 2001 </field> 2002 <field derivedFrom="DMA"> 2003 <name>TMR3</name> 2004 <description>Timer3 Reset. Setting this bit to 1 resets Timer 3 blocks.</description> 2005 <bitOffset>8</bitOffset> 2006 <bitWidth>1</bitWidth> 2007 </field> 2008 <field derivedFrom="DMA"> 2009 <name>UART0</name> 2010 <description>UART0 Reset. Setting this bit to 1 resets all UART 0 blocks.</description> 2011 <bitOffset>11</bitOffset> 2012 <bitWidth>1</bitWidth> 2013 </field> 2014 <field derivedFrom="DMA"> 2015 <name>UART1</name> 2016 <description>UART1 Reset. Setting this bit to 1 resets all UART 1 blocks.</description> 2017 <bitOffset>12</bitOffset> 2018 <bitWidth>1</bitWidth> 2019 </field> 2020 <field derivedFrom="DMA"> 2021 <name>SPI0</name> 2022 <description>SPI0 Reset. Setting this bit to 1 resets all SPI 0 blocks.</description> 2023 <bitOffset>13</bitOffset> 2024 <bitWidth>1</bitWidth> 2025 </field> 2026 <field derivedFrom="DMA"> 2027 <name>SPI1</name> 2028 <description>SPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks.</description> 2029 <bitOffset>14</bitOffset> 2030 <bitWidth>1</bitWidth> 2031 </field> 2032 <field derivedFrom="DMA"> 2033 <name>SPI2</name> 2034 <description>SPI2 Reset. Setting this bit to 1 resets all SPI 2 blocks.</description> 2035 <bitOffset>15</bitOffset> 2036 <bitWidth>1</bitWidth> 2037 </field> 2038 <field derivedFrom="DMA"> 2039 <name>I2C0</name> 2040 <description>I2C0 Reset.</description> 2041 <bitOffset>16</bitOffset> 2042 <bitWidth>1</bitWidth> 2043 </field> 2044 <field derivedFrom="DMA"> 2045 <name>RTC</name> 2046 <description>Real Time Clock Reset.</description> 2047 <bitOffset>17</bitOffset> 2048 <bitWidth>1</bitWidth> 2049 </field> 2050 <field derivedFrom="DMA"> 2051 <name>TRNG</name> 2052 <description>TRNG Reset.</description> 2053 <bitOffset>24</bitOffset> 2054 <bitWidth>1</bitWidth> 2055 </field> 2056 <field derivedFrom="DMA"> 2057 <name>UART2</name> 2058 <description>UART2 Reset. Setting this bit to 1 resets all UART 2 blocks.</description> 2059 <bitOffset>28</bitOffset> 2060 <bitWidth>1</bitWidth> 2061 </field> 2062 <field derivedFrom="DMA"> 2063 <name>SOFT</name> 2064 <description>Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer.</description> 2065 <bitOffset>29</bitOffset> 2066 <bitWidth>1</bitWidth> 2067 </field> 2068 <field derivedFrom="DMA"> 2069 <name>PERIPH</name> 2070 <description>Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset.</description> 2071 <bitOffset>30</bitOffset> 2072 <bitWidth>1</bitWidth> 2073 </field> 2074 <field derivedFrom="DMA"> 2075 <name>SYS</name> 2076 <description>System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer.</description> 2077 <bitOffset>31</bitOffset> 2078 <bitWidth>1</bitWidth> 2079 </field> 2080 </fields> 2081 </register> 2082 <register> 2083 <name>CLKCTRL</name> 2084 <description>Clock Control.</description> 2085 <addressOffset>0x08</addressOffset> 2086 <resetValue>0x00000008</resetValue> 2087 <fields> 2088 <field> 2089 <name>SYSCLK_DIV</name> 2090 <description>Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0.</description> 2091 <bitOffset>6</bitOffset> 2092 <bitWidth>3</bitWidth> 2093 <enumeratedValues> 2094 <enumeratedValue> 2095 <name>div1</name> 2096 <description>Divide by 1.</description> 2097 <value>0</value> 2098 </enumeratedValue> 2099 <enumeratedValue> 2100 <name>div2</name> 2101 <description>Divide by 2.</description> 2102 <value>1</value> 2103 </enumeratedValue> 2104 <enumeratedValue> 2105 <name>div4</name> 2106 <description>Divide by 4.</description> 2107 <value>2</value> 2108 </enumeratedValue> 2109 <enumeratedValue> 2110 <name>div8</name> 2111 <description>Divide by 8.</description> 2112 <value>3</value> 2113 </enumeratedValue> 2114 <enumeratedValue> 2115 <name>div16</name> 2116 <description>Divide by 16.</description> 2117 <value>4</value> 2118 </enumeratedValue> 2119 <enumeratedValue> 2120 <name>div32</name> 2121 <description>Divide by 32.</description> 2122 <value>5</value> 2123 </enumeratedValue> 2124 <enumeratedValue> 2125 <name>div64</name> 2126 <description>Divide by 64.</description> 2127 <value>6</value> 2128 </enumeratedValue> 2129 <enumeratedValue> 2130 <name>div128</name> 2131 <description>Divide by 128.</description> 2132 <value>7</value> 2133 </enumeratedValue> 2134 </enumeratedValues> 2135 </field> 2136 <field> 2137 <name>SYSCLK_SEL</name> 2138 <description>Clock Source Select. This 3 bit field selects the source for the system clock.</description> 2139 <bitOffset>9</bitOffset> 2140 <bitWidth>3</bitWidth> 2141 <enumeratedValues> 2142 <enumeratedValue> 2143 <name>ERFO</name> 2144 <description>32MHz Crystal is used for the system clock.</description> 2145 <value>2</value> 2146 </enumeratedValue> 2147 <enumeratedValue> 2148 <name>INRO</name> 2149 <description>80kHz LIRC is used for the system clock.</description> 2150 <value>3</value> 2151 </enumeratedValue> 2152 <enumeratedValue> 2153 <name>IPO</name> 2154 <description>The internal 96 MHz oscillator is used for the system clock.</description> 2155 <value>4</value> 2156 </enumeratedValue> 2157 <enumeratedValue> 2158 <name>IBRO</name> 2159 <description>The internal 8 MHz oscillator is used for the system clock.</description> 2160 <value>5</value> 2161 </enumeratedValue> 2162 <enumeratedValue> 2163 <name>ERTCO</name> 2164 <description> 32kHz is used for the system clock.</description> 2165 <value>6</value> 2166 </enumeratedValue> 2167 <enumeratedValue> 2168 <name>EXTCLK</name> 2169 <description> External clock on gpio0 11.</description> 2170 <value>7</value> 2171 </enumeratedValue> 2172 </enumeratedValues> 2173 </field> 2174 <field> 2175 <name>SYSCLK_RDY</name> 2176 <description>Clock Ready. This read only bit reflects whether the currently selected system clock source is running.</description> 2177 <bitOffset>13</bitOffset> 2178 <bitWidth>1</bitWidth> 2179 <access>read-only</access> 2180 <enumeratedValues> 2181 <enumeratedValue> 2182 <name>busy</name> 2183 <description>Switchover to the new clock source (as selected by CLKSEL) has not yet occurred.</description> 2184 <value>0</value> 2185 </enumeratedValue> 2186 <enumeratedValue> 2187 <name>ready</name> 2188 <description>System clock running from CLKSEL clock source.</description> 2189 <value>1</value> 2190 </enumeratedValue> 2191 </enumeratedValues> 2192 </field> 2193 <field> 2194 <name>IPO_DIV</name> 2195 <description>Divides the HIRC96M clock before the system clock prescaler, will affect HIRC96M Autocalibration.</description> 2196 <bitOffset>14</bitOffset> 2197 <bitWidth>2</bitWidth> 2198 <enumeratedValues> 2199 <enumeratedValue> 2200 <name>div1</name> 2201 <description>divide clock by 1</description> 2202 <value>0</value> 2203 </enumeratedValue> 2204 <enumeratedValue> 2205 <name>div2</name> 2206 <description>divide clock by 2</description> 2207 <value>1</value> 2208 </enumeratedValue> 2209 <enumeratedValue> 2210 <name>div4</name> 2211 <description>divide clock by 4</description> 2212 <value>2</value> 2213 </enumeratedValue> 2214 <enumeratedValue> 2215 <name>div8</name> 2216 <description>divide clock by 8</description> 2217 <value>3</value> 2218 </enumeratedValue> 2219 </enumeratedValues> 2220 </field> 2221 <field> 2222 <name>ERFO_EN</name> 2223 <description>32MHz Crystal Oscillator Enable.</description> 2224 <bitOffset>16</bitOffset> 2225 <bitWidth>1</bitWidth> 2226 <enumeratedValues> 2227 <enumeratedValue> 2228 <name>dis</name> 2229 <description>Is Disabled.</description> 2230 <value>0</value> 2231 </enumeratedValue> 2232 <enumeratedValue> 2233 <name>en</name> 2234 <description>Is Enabled.</description> 2235 <value>1</value> 2236 </enumeratedValue> 2237 </enumeratedValues> 2238 </field> 2239 <field> 2240 <name>ERTCO_EN</name> 2241 <description>32kHz Crystal Oscillator Enable.</description> 2242 <bitOffset>17</bitOffset> 2243 <bitWidth>1</bitWidth> 2244 <enumeratedValues> 2245 <enumeratedValue> 2246 <name>dis</name> 2247 <description>Is Disabled.</description> 2248 <value>0</value> 2249 </enumeratedValue> 2250 <enumeratedValue> 2251 <name>en</name> 2252 <description>Is Enabled.</description> 2253 <value>1</value> 2254 </enumeratedValue> 2255 </enumeratedValues> 2256 </field> 2257 <field derivedFrom="ERTCO_EN"> 2258 <name>IPO_EN</name> 2259 <description>96MHz High Frequency Internal Reference Clock Enable.</description> 2260 <bitOffset>19</bitOffset> 2261 <bitWidth>1</bitWidth> 2262 </field> 2263 <field derivedFrom="ERTCO_EN"> 2264 <name>IBRO_EN</name> 2265 <description>8MHz High Frequency Internal Reference Clock Enable.</description> 2266 <bitOffset>20</bitOffset> 2267 <bitWidth>1</bitWidth> 2268 </field> 2269 <field> 2270 <name>IBRO_VS</name> 2271 <description>8MHz High Frequency Internal Reference Clock Voltage Select. This register bit is used to select the power supply to the HIRC8M.</description> 2272 <bitOffset>21</bitOffset> 2273 <bitWidth>1</bitWidth> 2274 <enumeratedValues> 2275 <enumeratedValue> 2276 <name>Vcor</name> 2277 <description>VCore Supply</description> 2278 <value>0</value> 2279 </enumeratedValue> 2280 <enumeratedValue> 2281 <name>1V</name> 2282 <description>Dedicated 1v regulated supply.</description> 2283 <value>1</value> 2284 </enumeratedValue> 2285 </enumeratedValues> 2286 </field> 2287 <field> 2288 <name>ERFO_RDY</name> 2289 <description>32MHz Crystal Oscillator Ready</description> 2290 <bitOffset>24</bitOffset> 2291 <bitWidth>1</bitWidth> 2292 <access>read-only</access> 2293 <enumeratedValues> 2294 <enumeratedValue> 2295 <name>not</name> 2296 <description>Is not Ready.</description> 2297 <value>0</value> 2298 </enumeratedValue> 2299 <enumeratedValue> 2300 <name>ready</name> 2301 <description>Is Ready.</description> 2302 <value>1</value> 2303 </enumeratedValue> 2304 </enumeratedValues> 2305 </field> 2306 <field> 2307 <name>ERTCO_RDY</name> 2308 <description>32kHz Crystal Oscillator Ready</description> 2309 <bitOffset>25</bitOffset> 2310 <bitWidth>1</bitWidth> 2311 <access>read-only</access> 2312 <enumeratedValues> 2313 <enumeratedValue> 2314 <name>not</name> 2315 <description>Is not Ready.</description> 2316 <value>0</value> 2317 </enumeratedValue> 2318 <enumeratedValue> 2319 <name>ready</name> 2320 <description>Is Ready.</description> 2321 <value>1</value> 2322 </enumeratedValue> 2323 </enumeratedValues> 2324 </field> 2325 <field derivedFrom="ERTCO_RDY"> 2326 <name>IPO_RDY</name> 2327 <description>96MHz HIRC Ready.</description> 2328 <bitOffset>27</bitOffset> 2329 <bitWidth>1</bitWidth> 2330 </field> 2331 <field derivedFrom="ERTCO_RDY"> 2332 <name>IBRO_RDY</name> 2333 <description>8MHz HIRC Ready.</description> 2334 <bitOffset>28</bitOffset> 2335 <bitWidth>1</bitWidth> 2336 </field> 2337 <field derivedFrom="ERTCO_RDY"> 2338 <name>INRO_RDY</name> 2339 <description>8kHz Low Frequency Reference Clock Ready.</description> 2340 <bitOffset>29</bitOffset> 2341 <bitWidth>1</bitWidth> 2342 </field> 2343 <field derivedFrom="ERTCO_RDY"> 2344 <name>EXTCLK_RDY</name> 2345 <description>External Clock (GPIO0[11] AF2) </description> 2346 <bitOffset>31</bitOffset> 2347 <bitWidth>1</bitWidth> 2348 </field> 2349 </fields> 2350 </register> 2351 <register> 2352 <name>PM</name> 2353 <description>Power Management.</description> 2354 <addressOffset>0x0C</addressOffset> 2355 <fields> 2356 <field> 2357 <name>MODE</name> 2358 <description>Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode.</description> 2359 <bitOffset>0</bitOffset> 2360 <bitWidth>3</bitWidth> 2361 <enumeratedValues> 2362 <enumeratedValue> 2363 <name>active</name> 2364 <description>Active Mode.</description> 2365 <value>0</value> 2366 </enumeratedValue> 2367 <enumeratedValue> 2368 <name>shutdown</name> 2369 <description>Shutdown Mode.</description> 2370 <value>3</value> 2371 </enumeratedValue> 2372 <enumeratedValue> 2373 <name>backup</name> 2374 <description>Backup Mode.</description> 2375 <value>4</value> 2376 </enumeratedValue> 2377 </enumeratedValues> 2378 </field> 2379 <field> 2380 <name>GPIO_WE</name> 2381 <description>GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set.</description> 2382 <bitOffset>4</bitOffset> 2383 <bitWidth>1</bitWidth> 2384 <enumeratedValues> 2385 <enumeratedValue> 2386 <name>dis</name> 2387 <description>Wake Up Disable.</description> 2388 <value>0</value> 2389 </enumeratedValue> 2390 <enumeratedValue> 2391 <name>en</name> 2392 <description>Wake Up Enable.</description> 2393 <value>1</value> 2394 </enumeratedValue> 2395 </enumeratedValues> 2396 </field> 2397 <field derivedFrom="GPIO_WE"> 2398 <name>RTC_WE</name> 2399 <description>RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers.</description> 2400 <bitOffset>5</bitOffset> 2401 <bitWidth>1</bitWidth> 2402 </field> 2403 <field derivedFrom="GPIO_WE"> 2404 <name>LPTMR0_WE</name> 2405 <description>TIMER4 Wake Up Enable. This bit enables TIMER4 as wakeup source. </description> 2406 <bitOffset>6</bitOffset> 2407 <bitWidth>1</bitWidth> 2408 </field> 2409 <field derivedFrom="GPIO_WE"> 2410 <name>LPTMR1_WE</name> 2411 <description>TIMER5 Wake Up Enable. This bit enables TIMER5 as wakeup source. </description> 2412 <bitOffset>7</bitOffset> 2413 <bitWidth>1</bitWidth> 2414 </field> 2415 <field derivedFrom="GPIO_WE"> 2416 <name>LPUART0_WE</name> 2417 <description>LPUART3 Wake Up Enable. This bit enables LPUART3 as wakeup source. </description> 2418 <bitOffset>8</bitOffset> 2419 <bitWidth>1</bitWidth> 2420 </field> 2421 <field> 2422 <name>ERFO_PD</name> 2423 <description>32MHz power down. This bit selects 32MHz Crystal power state in DEEPSLEEP mode.</description> 2424 <bitOffset>12</bitOffset> 2425 <bitWidth>1</bitWidth> 2426 <enumeratedValues> 2427 <enumeratedValue> 2428 <name>active</name> 2429 <description>Mode is Active.</description> 2430 <value>0</value> 2431 </enumeratedValue> 2432 <enumeratedValue> 2433 <name>deepsleep</name> 2434 <description>Powered down in DEEPSLEEP.</description> 2435 <value>1</value> 2436 </enumeratedValue> 2437 </enumeratedValues> 2438 </field> 2439 <field derivedFrom="ERFO_PD"> 2440 <name>IPO_PD</name> 2441 <description>96MHz power down. This bit selects 96MHz HIRC power state in DEEPSLEEP mode. </description> 2442 <bitOffset>16</bitOffset> 2443 <bitWidth>1</bitWidth> 2444 </field> 2445 <field derivedFrom="ERFO_PD"> 2446 <name>IBRO_PD</name> 2447 <description>8MHz power down. This bit selects 8MHz HIRC power state in DEEPSLEEP mode. </description> 2448 <bitOffset>17</bitOffset> 2449 <bitWidth>1</bitWidth> 2450 </field> 2451 <field> 2452 <name>ERFO_BP</name> 2453 <description>32MHz Oscillator Bypass</description> 2454 <bitOffset>20</bitOffset> 2455 <bitWidth>1</bitWidth> 2456 </field> 2457 </fields> 2458 </register> 2459 <register> 2460 <name>PCLKDIV</name> 2461 <description>Peripheral Clock Divider.</description> 2462 <addressOffset>0x18</addressOffset> 2463 <resetValue>0x00000001</resetValue> 2464 <fields> 2465 <field> 2466 <name>AON_CLKDIV</name> 2467 <description>Always-ON (AON) domain Clock Divider. These bits define the AON domain clock divider</description> 2468 <bitOffset>0</bitOffset> 2469 <bitWidth>2</bitWidth> 2470 <enumeratedValues> 2471 <enumeratedValue> 2472 <name>div4</name> 2473 <value>0</value> 2474 </enumeratedValue> 2475 <enumeratedValue> 2476 <name>div8</name> 2477 <value>1</value> 2478 </enumeratedValue> 2479 <enumeratedValue> 2480 <name>div16</name> 2481 <value>2</value> 2482 </enumeratedValue> 2483 <enumeratedValue> 2484 <name>div32</name> 2485 <value>3</value> 2486 </enumeratedValue> 2487 </enumeratedValues> 2488 </field> 2489 <field> 2490 <name>DIV_CLK_OUT_CTRL</name> 2491 <description>DIV_CLK_OUT Control</description> 2492 <bitOffset>14</bitOffset> 2493 <bitWidth>2</bitWidth> 2494 </field> 2495 <field> 2496 <name>DIV_CLK_OUT_EN</name> 2497 <description>DIV_CLK_OUT Enable</description> 2498 <bitOffset>16</bitOffset> 2499 <bitWidth>1</bitWidth> 2500 </field> 2501 </fields> 2502 </register> 2503 <register> 2504 <name>PCLKDIS0</name> 2505 <description>Peripheral Clock Disable.</description> 2506 <addressOffset>0x24</addressOffset> 2507 <fields> 2508 <field> 2509 <name>GPIO0</name> 2510 <description>GPIO0 Disable.</description> 2511 <bitOffset>0</bitOffset> 2512 <bitWidth>1</bitWidth> 2513 <enumeratedValues> 2514 <enumeratedValue> 2515 <name>en</name> 2516 <description>enable it.</description> 2517 <value>0</value> 2518 </enumeratedValue> 2519 <enumeratedValue> 2520 <name>dis</name> 2521 <description>disable it.</description> 2522 <value>1</value> 2523 </enumeratedValue> 2524 </enumeratedValues> 2525 </field> 2526 <field derivedFrom="GPIO0"> 2527 <name>GPIO1</name> 2528 <description>GPIO1 Disable.</description> 2529 <bitOffset>1</bitOffset> 2530 <bitWidth>1</bitWidth> 2531 </field> 2532 <field derivedFrom="GPIO0"> 2533 <name>DMA</name> 2534 <description>DMA Disable.</description> 2535 <bitOffset>5</bitOffset> 2536 <bitWidth>1</bitWidth> 2537 </field> 2538 <field derivedFrom="GPIO0"> 2539 <name>SPI0</name> 2540 <description>SPI 0 Disable.</description> 2541 <bitOffset>6</bitOffset> 2542 <bitWidth>1</bitWidth> 2543 </field> 2544 <field derivedFrom="GPIO0"> 2545 <name>SPI1</name> 2546 <description>SPI 1 Disable.</description> 2547 <bitOffset>7</bitOffset> 2548 <bitWidth>1</bitWidth> 2549 </field> 2550 <field derivedFrom="GPIO0"> 2551 <name>SPI2</name> 2552 <description>SPI 2 Disable.</description> 2553 <bitOffset>8</bitOffset> 2554 <bitWidth>1</bitWidth> 2555 </field> 2556 <field derivedFrom="GPIO0"> 2557 <name>UART0</name> 2558 <description>UART 0 Disable.</description> 2559 <bitOffset>9</bitOffset> 2560 <bitWidth>1</bitWidth> 2561 </field> 2562 <field derivedFrom="GPIO0"> 2563 <name>UART1</name> 2564 <description>UART 1 Disable.</description> 2565 <bitOffset>10</bitOffset> 2566 <bitWidth>1</bitWidth> 2567 </field> 2568 <field derivedFrom="GPIO0"> 2569 <name>I2C0</name> 2570 <description>I2C 0 Disable.</description> 2571 <bitOffset>13</bitOffset> 2572 <bitWidth>1</bitWidth> 2573 </field> 2574 <field derivedFrom="GPIO0"> 2575 <name>TMR0</name> 2576 <description>Timer 0 Disable.</description> 2577 <bitOffset>15</bitOffset> 2578 <bitWidth>1</bitWidth> 2579 </field> 2580 <field derivedFrom="GPIO0"> 2581 <name>TMR1</name> 2582 <description>Timer 1 Disable.</description> 2583 <bitOffset>16</bitOffset> 2584 <bitWidth>1</bitWidth> 2585 </field> 2586 <field derivedFrom="GPIO0"> 2587 <name>TMR2</name> 2588 <description>Timer 2 Disable.</description> 2589 <bitOffset>17</bitOffset> 2590 <bitWidth>1</bitWidth> 2591 </field> 2592 <field derivedFrom="GPIO0"> 2593 <name>TMR3</name> 2594 <description>Timer 3 Disable.</description> 2595 <bitOffset>18</bitOffset> 2596 <bitWidth>1</bitWidth> 2597 </field> 2598 <field derivedFrom="GPIO0"> 2599 <name>I2C1</name> 2600 <description>I2C 1 Disable.</description> 2601 <bitOffset>28</bitOffset> 2602 <bitWidth>1</bitWidth> 2603 </field> 2604 </fields> 2605 </register> 2606 <register> 2607 <name>MEMCTRL</name> 2608 <description>Memory Clock Control Register.</description> 2609 <addressOffset>0x28</addressOffset> 2610 <fields> 2611 <field> 2612 <name>FWS</name> 2613 <description>Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2.</description> 2614 <bitOffset>0</bitOffset> 2615 <bitWidth>3</bitWidth> 2616 </field> 2617 <field> 2618 <name>RAMWS_EN</name> 2619 <description>System RAM Wait State enable</description> 2620 <bitOffset>4</bitOffset> 2621 <bitWidth>1</bitWidth> 2622 </field> 2623 <field> 2624 <name>RAM0LS_EN</name> 2625 <description>System RAM 0 Light Sleep Mode.</description> 2626 <bitOffset>8</bitOffset> 2627 <bitWidth>1</bitWidth> 2628 <enumeratedValues> 2629 <enumeratedValue> 2630 <name>active</name> 2631 <description>RAM is active.</description> 2632 <value>0</value> 2633 </enumeratedValue> 2634 <enumeratedValue> 2635 <name>light_sleep</name> 2636 <description>RAM is in Light Sleep mode.</description> 2637 <value>1</value> 2638 </enumeratedValue> 2639 </enumeratedValues> 2640 </field> 2641 <field derivedFrom="RAM0LS_EN"> 2642 <name>RAM1LS_EN</name> 2643 <description>System RAM 1 Light Sleep Mode.</description> 2644 <bitOffset>9</bitOffset> 2645 <bitWidth>1</bitWidth> 2646 </field> 2647 <field derivedFrom="RAM0LS_EN"> 2648 <name>RAM2LS_EN</name> 2649 <description>System RAM 2 Light Sleep Mode.</description> 2650 <bitOffset>10</bitOffset> 2651 <bitWidth>1</bitWidth> 2652 </field> 2653 <field derivedFrom="RAM0LS_EN"> 2654 <name>RAM3LS_EN</name> 2655 <description>System RAM 3 Light Sleep Mode.</description> 2656 <bitOffset>11</bitOffset> 2657 <bitWidth>1</bitWidth> 2658 </field> 2659 <field derivedFrom="RAM0LS_EN"> 2660 <name>ICC0LS_EN</name> 2661 <description>ICache RAM Light Sleep Mode.</description> 2662 <bitOffset>12</bitOffset> 2663 <bitWidth>1</bitWidth> 2664 </field> 2665 <field derivedFrom="RAM0LS_EN"> 2666 <name>ROMLS_EN</name> 2667 <description>ROM Light Sleep Mode.</description> 2668 <bitOffset>13</bitOffset> 2669 <bitWidth>1</bitWidth> 2670 </field> 2671 </fields> 2672 </register> 2673 <register> 2674 <name>MEMZ</name> 2675 <description>Memory Zeroize Control.</description> 2676 <addressOffset>0x2C</addressOffset> 2677 <fields> 2678 <field> 2679 <name>RAM</name> 2680 <description>System RAM Block.</description> 2681 <bitOffset>0</bitOffset> 2682 <bitWidth>1</bitWidth> 2683 <enumeratedValues> 2684 <enumeratedValue> 2685 <name>nop</name> 2686 <description>No operation/complete.</description> 2687 <value>0</value> 2688 </enumeratedValue> 2689 <enumeratedValue> 2690 <name>start</name> 2691 <description>Start operation.</description> 2692 <value>1</value> 2693 </enumeratedValue> 2694 </enumeratedValues> 2695 </field> 2696 <field derivedFrom="RAM"> 2697 <name>RAMCB</name> 2698 <description>System RAM check bit zeroization.</description> 2699 <bitOffset>1</bitOffset> 2700 <bitWidth>1</bitWidth> 2701 </field> 2702 <field derivedFrom="RAM"> 2703 <name>ICC0</name> 2704 <description>Instruction Cache.</description> 2705 <bitOffset>2</bitOffset> 2706 <bitWidth>1</bitWidth> 2707 </field> 2708 </fields> 2709 </register> 2710 <register> 2711 <name>SYSST</name> 2712 <description>System Status Register.</description> 2713 <addressOffset>0x40</addressOffset> 2714 <fields> 2715 <field> 2716 <name>ICELOCK</name> 2717 <description>ARM ICE Lock Status.</description> 2718 <bitOffset>0</bitOffset> 2719 <bitWidth>1</bitWidth> 2720 <enumeratedValues> 2721 <enumeratedValue> 2722 <name>unlocked</name> 2723 <description>ICE is unlocked.</description> 2724 <value>0</value> 2725 </enumeratedValue> 2726 <enumeratedValue> 2727 <name>locked</name> 2728 <description>ICE is locked.</description> 2729 <value>1</value> 2730 </enumeratedValue> 2731 </enumeratedValues> 2732 </field> 2733 </fields> 2734 </register> 2735 <register> 2736 <name>RST1</name> 2737 <description>Reset 1.</description> 2738 <addressOffset>0x44</addressOffset> 2739 <fields> 2740 <field> 2741 <name>I2C1</name> 2742 <description>I2C1 Reset.</description> 2743 <bitOffset>0</bitOffset> 2744 <bitWidth>1</bitWidth> 2745 <enumeratedValues> 2746 <name>reset_read</name> 2747 <usage>read</usage> 2748 <enumeratedValue> 2749 <name>reset_done</name> 2750 <description>Reset complete.</description> 2751 <value>0</value> 2752 </enumeratedValue> 2753 <enumeratedValue> 2754 <name>busy</name> 2755 <description>Starts reset or indicates reset in progress.</description> 2756 <value>1</value> 2757 </enumeratedValue> 2758 </enumeratedValues> 2759 </field> 2760 <field derivedFrom="I2C1"> 2761 <name>WDT1</name> 2762 <description>WDT1 Reset.</description> 2763 <bitOffset>8</bitOffset> 2764 <bitWidth>1</bitWidth> 2765 </field> 2766 <field derivedFrom="I2C1"> 2767 <name>CRC</name> 2768 <description>CRC Reset.</description> 2769 <bitOffset>9</bitOffset> 2770 <bitWidth>1</bitWidth> 2771 </field> 2772 <field derivedFrom="I2C1"> 2773 <name>AES</name> 2774 <description>AES Reset.</description> 2775 <bitOffset>10</bitOffset> 2776 <bitWidth>1</bitWidth> 2777 </field> 2778 <field derivedFrom="I2C1"> 2779 <name>AC</name> 2780 <description>AC Reset.</description> 2781 <bitOffset>14</bitOffset> 2782 <bitWidth>1</bitWidth> 2783 </field> 2784 <field derivedFrom="I2C1"> 2785 <name>I2C2</name> 2786 <description>I2C2 Reset.</description> 2787 <bitOffset>17</bitOffset> 2788 <bitWidth>1</bitWidth> 2789 </field> 2790 <field derivedFrom="I2C1"> 2791 <name>I2S</name> 2792 <description>I2S Reset.</description> 2793 <bitOffset>23</bitOffset> 2794 <bitWidth>1</bitWidth> 2795 </field> 2796 <field derivedFrom="I2C1"> 2797 <name>AFE</name> 2798 <description>AFE Reset.</description> 2799 <bitOffset>25</bitOffset> 2800 <bitWidth>1</bitWidth> 2801 </field> 2802 </fields> 2803 </register> 2804 <register> 2805 <name>PCLKDIS1</name> 2806 <description>Peripheral Clock Disable.</description> 2807 <addressOffset>0x48</addressOffset> 2808 <fields> 2809 <field> 2810 <name>UART2</name> 2811 <description>UART2 Disable.</description> 2812 <bitOffset>1</bitOffset> 2813 <bitWidth>1</bitWidth> 2814 <enumeratedValues> 2815 <enumeratedValue> 2816 <name>en</name> 2817 <description>Enable.</description> 2818 <value>0</value> 2819 </enumeratedValue> 2820 <enumeratedValue> 2821 <name>dis</name> 2822 <description>Disable.</description> 2823 <value>1</value> 2824 </enumeratedValue> 2825 </enumeratedValues> 2826 </field> 2827 <field derivedFrom="UART2"> 2828 <name>TRNG</name> 2829 <description>TRNG Disable.</description> 2830 <bitOffset>2</bitOffset> 2831 <bitWidth>1</bitWidth> 2832 </field> 2833 <field derivedFrom="UART2"> 2834 <name>WWDT0</name> 2835 <description>WDT0 Disable.</description> 2836 <bitOffset>4</bitOffset> 2837 <bitWidth>1</bitWidth> 2838 </field> 2839 <field derivedFrom="UART2"> 2840 <name>WWDT1</name> 2841 <description>WDT1 Disable.</description> 2842 <bitOffset>5</bitOffset> 2843 <bitWidth>1</bitWidth> 2844 </field> 2845 <field derivedFrom="UART2"> 2846 <name>ICC0</name> 2847 <description>ICACHE Disable.</description> 2848 <bitOffset>11</bitOffset> 2849 <bitWidth>1</bitWidth> 2850 </field> 2851 <field derivedFrom="UART2"> 2852 <name>CRC</name> 2853 <description>CRC Disable.</description> 2854 <bitOffset>14</bitOffset> 2855 <bitWidth>1</bitWidth> 2856 </field> 2857 <field derivedFrom="UART2"> 2858 <name>AES</name> 2859 <description>AES Disable.</description> 2860 <bitOffset>15</bitOffset> 2861 <bitWidth>1</bitWidth> 2862 </field> 2863 <field derivedFrom="UART2"> 2864 <name>I2C2</name> 2865 <description>I2C2 Disable.</description> 2866 <bitOffset>21</bitOffset> 2867 <bitWidth>1</bitWidth> 2868 </field> 2869 <field derivedFrom="UART2"> 2870 <name>I2S</name> 2871 <description>I2S Clock Disable.</description> 2872 <bitOffset>23</bitOffset> 2873 <bitWidth>1</bitWidth> 2874 </field> 2875 </fields> 2876 </register> 2877 <register> 2878 <name>EVENTEN</name> 2879 <description>Event Enable Register.</description> 2880 <addressOffset>0x4C</addressOffset> 2881 <fields> 2882 <field> 2883 <name>DMA</name> 2884 <description>Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode.</description> 2885 <bitOffset>0</bitOffset> 2886 <bitWidth>1</bitWidth> 2887 </field> 2888 <field> 2889 <name>RX</name> 2890 <description>Enable RXEV pin event. When this bit is set, a logic high of GPIO0[20] will cause an RXEV event to wake the CPU from WFE sleep mode. </description> 2891 <bitOffset>1</bitOffset> 2892 <bitWidth>1</bitWidth> 2893 </field> 2894 <field> 2895 <name>TX</name> 2896 <description>Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO[21].</description> 2897 <bitOffset>2</bitOffset> 2898 <bitWidth>1</bitWidth> 2899 </field> 2900 </fields> 2901 </register> 2902 <register> 2903 <name>REVISION</name> 2904 <description>Revision Register.</description> 2905 <addressOffset>0x50</addressOffset> 2906 <access>read-only</access> 2907 <fields> 2908 <field> 2909 <name>REVISION</name> 2910 <description>Manufacturer Chip Revision. </description> 2911 <bitOffset>0</bitOffset> 2912 <bitWidth>16</bitWidth> 2913 </field> 2914 </fields> 2915 </register> 2916 <register> 2917 <name>SYSIE</name> 2918 <description>System Status Interrupt Enable Register.</description> 2919 <addressOffset>0x54</addressOffset> 2920 <fields> 2921 <field> 2922 <name>ICEUNLOCK</name> 2923 <description>ARM ICE Unlock Interrupt Enable.</description> 2924 <bitOffset>0</bitOffset> 2925 <bitWidth>1</bitWidth> 2926 <enumeratedValues> 2927 <enumeratedValue> 2928 <name>dis</name> 2929 <description>disabled.</description> 2930 <value>0</value> 2931 </enumeratedValue> 2932 <enumeratedValue> 2933 <name>en</name> 2934 <description>enabled.</description> 2935 <value>1</value> 2936 </enumeratedValue> 2937 </enumeratedValues> 2938 </field> 2939 </fields> 2940 </register> 2941 <register> 2942 <name>ECCERR</name> 2943 <description>ECC Error Register</description> 2944 <addressOffset>0x64</addressOffset> 2945 <fields> 2946 <field> 2947 <name>RAM</name> 2948 <description>ECC System RAM0 Error Flag. Write 1 to clear.</description> 2949 <bitOffset>0</bitOffset> 2950 <bitWidth>1</bitWidth> 2951 </field> 2952 <field> 2953 <name>ICC0</name> 2954 <description>ECC Icache Error Flag. Write 1 to clear.</description> 2955 <bitOffset>1</bitOffset> 2956 <bitWidth>1</bitWidth> 2957 </field> 2958 <field> 2959 <name>FLASH</name> 2960 <description>ECC Flash Error Flag. Write 1 to clear.</description> 2961 <bitOffset>2</bitOffset> 2962 <bitWidth>1</bitWidth> 2963 </field> 2964 </fields> 2965 </register> 2966 <register> 2967 <name>ECCCED</name> 2968 <description>ECC Not Double Error Detect Register</description> 2969 <addressOffset>0x68</addressOffset> 2970 <fields> 2971 <field> 2972 <name>RAM</name> 2973 <description>ECC System RAM0 Error Flag. Write 1 to clear.</description> 2974 <bitOffset>0</bitOffset> 2975 <bitWidth>1</bitWidth> 2976 </field> 2977 <field> 2978 <name>ICC0</name> 2979 <description>ECC Icache Not Double Error Detect. Write 1 to clear.</description> 2980 <bitOffset>1</bitOffset> 2981 <bitWidth>1</bitWidth> 2982 </field> 2983 <field> 2984 <name>FLASH</name> 2985 <description>ECC Flash0 Not Double Error Detect. Write 1 to clear.</description> 2986 <bitOffset>2</bitOffset> 2987 <bitWidth>1</bitWidth> 2988 </field> 2989 </fields> 2990 </register> 2991 <register> 2992 <name>ECCIE</name> 2993 <description>ECC IRQ Enable Register</description> 2994 <addressOffset>0x6C</addressOffset> 2995 <fields> 2996 <field> 2997 <name>RAM</name> 2998 <description>ECC System RAM0 Error Interrup Enable</description> 2999 <bitOffset>0</bitOffset> 3000 <bitWidth>1</bitWidth> 3001 </field> 3002 <field> 3003 <name>ICC0</name> 3004 <description>ECC Icache0 Error Interrup Enable</description> 3005 <bitOffset>1</bitOffset> 3006 <bitWidth>1</bitWidth> 3007 </field> 3008 <field> 3009 <name>FLASH</name> 3010 <description>ECC Flash0 NError Interrup Enable</description> 3011 <bitOffset>2</bitOffset> 3012 <bitWidth>1</bitWidth> 3013 </field> 3014 </fields> 3015 </register> 3016 <register> 3017 <name>ECCADDR</name> 3018 <description>ECC Error Address Register</description> 3019 <addressOffset>0x70</addressOffset> 3020 <fields> 3021 <field> 3022 <name>DATARAMADDR</name> 3023 <description>ECC Error Address/TAG RAM Error Address.</description> 3024 <bitOffset>0</bitOffset> 3025 <bitWidth>14</bitWidth> 3026 </field> 3027 <field> 3028 <name>DATARAMBANK</name> 3029 <description>ECC Error Address/DATA RAM Error Bank.</description> 3030 <bitOffset>14</bitOffset> 3031 <bitWidth>1</bitWidth> 3032 </field> 3033 <field> 3034 <name>DATARAMERR</name> 3035 <description>ECC Error Address/DATA RAM Error Address.</description> 3036 <bitOffset>15</bitOffset> 3037 <bitWidth>1</bitWidth> 3038 </field> 3039 <field> 3040 <name>TAGRAMADDR</name> 3041 <description>ECC Error Address/TAG RAM Error Address.</description> 3042 <bitOffset>16</bitOffset> 3043 <bitWidth>14</bitWidth> 3044 </field> 3045 <field> 3046 <name>TAGRAMBANK</name> 3047 <description>ECC Error Address/TAG RAM Error Bank.</description> 3048 <bitOffset>30</bitOffset> 3049 <bitWidth>1</bitWidth> 3050 </field> 3051 <field> 3052 <name>TAGRAMERR</name> 3053 <description>ECC Error Address/TAG RAM Error.</description> 3054 <bitOffset>31</bitOffset> 3055 <bitWidth>1</bitWidth> 3056 </field> 3057 </fields> 3058 </register> 3059 </registers> 3060 </peripheral> 3061<!--GCR Global Control Registers.--> 3062 <peripheral> 3063 <name>GPIO0</name> 3064 <description>Individual I/O for each GPIO</description> 3065 <groupName>GPIO</groupName> 3066 <baseAddress>0x40008000</baseAddress> 3067 <addressBlock> 3068 <offset>0x00</offset> 3069 <size>0x1000</size> 3070 <usage>registers</usage> 3071 </addressBlock> 3072 <interrupt> 3073 <name>GPIO0</name> 3074 <description>GPIO0 interrupt.</description> 3075 <value>24</value> 3076 </interrupt> 3077 <registers> 3078 <register> 3079 <name>EN0</name> 3080 <description>GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port.</description> 3081 <addressOffset>0x00</addressOffset> 3082 <fields> 3083 <field> 3084 <name>GPIO_EN</name> 3085 <description>Mask of all of the pins on the port.</description> 3086 <bitOffset>0</bitOffset> 3087 <bitWidth>32</bitWidth> 3088 <enumeratedValues> 3089 <enumeratedValue> 3090 <name>ALTERNATE</name> 3091 <description>Alternate function enabled.</description> 3092 <value>0</value> 3093 </enumeratedValue> 3094 <enumeratedValue> 3095 <name>GPIO</name> 3096 <description>GPIO function is enabled.</description> 3097 <value>1</value> 3098 </enumeratedValue> 3099 </enumeratedValues> 3100 </field> 3101 </fields> 3102 </register> 3103 <register> 3104 <name>EN0_SET</name> 3105 <description>GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1, without affecting other bits in that register.</description> 3106 <addressOffset>0x04</addressOffset> 3107 <fields> 3108 <field> 3109 <name>ALL</name> 3110 <description>Mask of all of the pins on the port.</description> 3111 <bitOffset>0</bitOffset> 3112 <bitWidth>32</bitWidth> 3113 </field> 3114 </fields> 3115 </register> 3116 <register> 3117 <name>EN0_CLR</name> 3118 <description>GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register.</description> 3119 <addressOffset>0x08</addressOffset> 3120 <fields> 3121 <field> 3122 <name>ALL</name> 3123 <description>Mask of all of the pins on the port.</description> 3124 <bitOffset>0</bitOffset> 3125 <bitWidth>32</bitWidth> 3126 </field> 3127 </fields> 3128 </register> 3129 <register> 3130 <name>OUTEN</name> 3131 <description>GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port.</description> 3132 <addressOffset>0x0C</addressOffset> 3133 <fields> 3134 <field> 3135 <name>EN</name> 3136 <description>Mask of all of the pins on the port.</description> 3137 <bitOffset>0</bitOffset> 3138 <bitWidth>32</bitWidth> 3139 <enumeratedValues> 3140 <enumeratedValue> 3141 <name>dis</name> 3142 <description>GPIO Output Disable</description> 3143 <value>0</value> 3144 </enumeratedValue> 3145 <enumeratedValue> 3146 <name>en</name> 3147 <description>GPIO Output Enable</description> 3148 <value>1</value> 3149 </enumeratedValue> 3150 </enumeratedValues> 3151 </field> 3152 </fields> 3153 </register> 3154 <register> 3155 <name>OUTEN_SET</name> 3156 <description>GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1, without affecting other bits in that register.</description> 3157 <addressOffset>0x10</addressOffset> 3158 <fields> 3159 <field> 3160 <name>ALL</name> 3161 <description>Mask of all of the pins on the port.</description> 3162 <bitOffset>0</bitOffset> 3163 <bitWidth>32</bitWidth> 3164 </field> 3165 </fields> 3166 </register> 3167 <register> 3168 <name>OUTEN_CLR</name> 3169 <description>GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, without affecting other bits in that register.</description> 3170 <addressOffset>0x14</addressOffset> 3171 <fields> 3172 <field> 3173 <name>ALL</name> 3174 <description>Mask of all of the pins on the port.</description> 3175 <bitOffset>0</bitOffset> 3176 <bitWidth>32</bitWidth> 3177 </field> 3178 </fields> 3179 </register> 3180 <register> 3181 <name>OUT</name> 3182 <description>GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers.</description> 3183 <addressOffset>0x18</addressOffset> 3184 <fields> 3185 <field> 3186 <name>GPIO_OUT</name> 3187 <description>Mask of all of the pins on the port.</description> 3188 <bitOffset>0</bitOffset> 3189 <bitWidth>32</bitWidth> 3190 <enumeratedValues> 3191 <enumeratedValue> 3192 <name>low</name> 3193 <description>Drive Logic 0 (low) on GPIO output.</description> 3194 <value>0</value> 3195 </enumeratedValue> 3196 <enumeratedValue> 3197 <name>high</name> 3198 <description>Drive logic 1 (high) on GPIO output.</description> 3199 <value>1</value> 3200 </enumeratedValue> 3201 </enumeratedValues> 3202 </field> 3203 </fields> 3204 </register> 3205 <register> 3206 <name>OUT_SET</name> 3207 <description>GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1, without affecting other bits in that register.</description> 3208 <addressOffset>0x1C</addressOffset> 3209 <access>write-only</access> 3210 <fields> 3211 <field> 3212 <name>GPIO_OUT_SET</name> 3213 <description>Mask of all of the pins on the port.</description> 3214 <bitOffset>0</bitOffset> 3215 <bitWidth>32</bitWidth> 3216 <enumeratedValues> 3217 <enumeratedValue> 3218 <name>no</name> 3219 <description>No Effect.</description> 3220 <value>0</value> 3221 </enumeratedValue> 3222 <enumeratedValue> 3223 <name>set</name> 3224 <description>Set GPIO_OUT bit in this position to '1'</description> 3225 <value>1</value> 3226 </enumeratedValue> 3227 </enumeratedValues> 3228 </field> 3229 </fields> 3230 </register> 3231 <register> 3232 <name>OUT_CLR</name> 3233 <description>GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0, without affecting other bits in that register.</description> 3234 <addressOffset>0x20</addressOffset> 3235 <access>write-only</access> 3236 <fields> 3237 <field> 3238 <name>GPIO_OUT_CLR</name> 3239 <description>Mask of all of the pins on the port.</description> 3240 <bitOffset>0</bitOffset> 3241 <bitWidth>32</bitWidth> 3242 </field> 3243 </fields> 3244 </register> 3245 <register> 3246 <name>IN</name> 3247 <description>GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port.</description> 3248 <addressOffset>0x24</addressOffset> 3249 <access>read-only</access> 3250 <fields> 3251 <field> 3252 <name>GPIO_IN</name> 3253 <description>Mask of all of the pins on the port.</description> 3254 <bitOffset>0</bitOffset> 3255 <bitWidth>32</bitWidth> 3256 </field> 3257 </fields> 3258 </register> 3259 <register> 3260 <name>INTMODE</name> 3261 <description>GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port.</description> 3262 <addressOffset>0x28</addressOffset> 3263 <fields> 3264 <field> 3265 <name>GPIO_INTMODE</name> 3266 <description>Mask of all of the pins on the port.</description> 3267 <bitOffset>0</bitOffset> 3268 <bitWidth>32</bitWidth> 3269 <enumeratedValues> 3270 <enumeratedValue> 3271 <name>level</name> 3272 <description>Interrupts for this pin are level triggered.</description> 3273 <value>0</value> 3274 </enumeratedValue> 3275 <enumeratedValue> 3276 <name>edge</name> 3277 <description>Interrupts for this pin are edge triggered.</description> 3278 <value>1</value> 3279 </enumeratedValue> 3280 </enumeratedValues> 3281 </field> 3282 </fields> 3283 </register> 3284 <register> 3285 <name>INTPOL</name> 3286 <description>GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port.</description> 3287 <addressOffset>0x2C</addressOffset> 3288 <fields> 3289 <field> 3290 <name>GPIO_INTPOL</name> 3291 <description>Mask of all of the pins on the port.</description> 3292 <bitOffset>0</bitOffset> 3293 <bitWidth>32</bitWidth> 3294 <enumeratedValues> 3295 <enumeratedValue> 3296 <name>falling</name> 3297 <description>Interrupts are latched on a falling edge or low level condition for this pin.</description> 3298 <value>0</value> 3299 </enumeratedValue> 3300 <enumeratedValue> 3301 <name>rising</name> 3302 <description>Interrupts are latched on a rising edge or high condition for this pin.</description> 3303 <value>1</value> 3304 </enumeratedValue> 3305 </enumeratedValues> 3306 </field> 3307 </fields> 3308 </register> 3309 <register> 3310 <name>INEN</name> 3311 <description>GPIO Input Enable</description> 3312 <addressOffset>0x30</addressOffset> 3313 </register> 3314 <register> 3315 <name>INTEN</name> 3316 <description>GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port.</description> 3317 <addressOffset>0x34</addressOffset> 3318 <fields> 3319 <field> 3320 <name>GPIO_INTEN</name> 3321 <description>Mask of all of the pins on the port.</description> 3322 <bitOffset>0</bitOffset> 3323 <bitWidth>32</bitWidth> 3324 <enumeratedValues> 3325 <enumeratedValue> 3326 <name>dis</name> 3327 <description>Interrupts are disabled for this GPIO pin.</description> 3328 <value>0</value> 3329 </enumeratedValue> 3330 <enumeratedValue> 3331 <name>en</name> 3332 <description>Interrupts are enabled for this GPIO pin.</description> 3333 <value>1</value> 3334 </enumeratedValue> 3335 </enumeratedValues> 3336 </field> 3337 </fields> 3338 </register> 3339 <register> 3340 <name>INTEN_SET</name> 3341 <description>GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits in that register.</description> 3342 <addressOffset>0x38</addressOffset> 3343 <fields> 3344 <field> 3345 <name>GPIO_INTEN_SET</name> 3346 <description>Mask of all of the pins on the port.</description> 3347 <bitOffset>0</bitOffset> 3348 <bitWidth>32</bitWidth> 3349 <enumeratedValues> 3350 <enumeratedValue> 3351 <name>no</name> 3352 <description>No effect.</description> 3353 <value>0</value> 3354 </enumeratedValue> 3355 <enumeratedValue> 3356 <name>set</name> 3357 <description>Set GPIO_INT_EN bit in this position to '1'</description> 3358 <value>1</value> 3359 </enumeratedValue> 3360 </enumeratedValues> 3361 </field> 3362 </fields> 3363 </register> 3364 <register> 3365 <name>INTEN_CLR</name> 3366 <description>GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0, without affecting other bits in that register.</description> 3367 <addressOffset>0x3C</addressOffset> 3368 <fields> 3369 <field> 3370 <name>GPIO_INTEN_CLR</name> 3371 <description>Mask of all of the pins on the port.</description> 3372 <bitOffset>0</bitOffset> 3373 <bitWidth>32</bitWidth> 3374 <enumeratedValues> 3375 <enumeratedValue> 3376 <name>no</name> 3377 <description>No Effect.</description> 3378 <value>0</value> 3379 </enumeratedValue> 3380 <enumeratedValue> 3381 <name>clear</name> 3382 <description>Clear GPIO_INT_EN bit in this position to '0'</description> 3383 <value>1</value> 3384 </enumeratedValue> 3385 </enumeratedValues> 3386 </field> 3387 </fields> 3388 </register> 3389 <register> 3390 <name>INTFL</name> 3391 <description>GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port.</description> 3392 <addressOffset>0x40</addressOffset> 3393 <access>read-only</access> 3394 <fields> 3395 <field> 3396 <name>GPIO_INTFL</name> 3397 <description>Mask of all of the pins on the port.</description> 3398 <bitOffset>0</bitOffset> 3399 <bitWidth>32</bitWidth> 3400 <enumeratedValues> 3401 <enumeratedValue> 3402 <name>no</name> 3403 <description>No Interrupt is pending on this GPIO pin.</description> 3404 <value>0</value> 3405 </enumeratedValue> 3406 <enumeratedValue> 3407 <name>pending</name> 3408 <description>An Interrupt is pending on this GPIO pin.</description> 3409 <value>1</value> 3410 </enumeratedValue> 3411 </enumeratedValues> 3412 </field> 3413 </fields> 3414 </register> 3415 <register> 3416 <name>INTFL_CLR</name> 3417 <description>GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits in that register.</description> 3418 <addressOffset>0x48</addressOffset> 3419 <fields> 3420 <field> 3421 <name>ALL</name> 3422 <description>Mask of all of the pins on the port.</description> 3423 <bitOffset>0</bitOffset> 3424 <bitWidth>32</bitWidth> 3425 </field> 3426 </fields> 3427 </register> 3428 <register> 3429 <name>WKEN</name> 3430 <description>GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port.</description> 3431 <addressOffset>0x4C</addressOffset> 3432 <fields> 3433 <field> 3434 <name>GPIO_WKEN</name> 3435 <description>Mask of all of the pins on the port.</description> 3436 <bitOffset>0</bitOffset> 3437 <bitWidth>32</bitWidth> 3438 <enumeratedValues> 3439 <enumeratedValue> 3440 <name>dis</name> 3441 <description>PMU wakeup for this GPIO is disabled.</description> 3442 <value>0</value> 3443 </enumeratedValue> 3444 <enumeratedValue> 3445 <name>en</name> 3446 <description>PMU wakeup for this GPIO is enabled.</description> 3447 <value>1</value> 3448 </enumeratedValue> 3449 </enumeratedValues> 3450 </field> 3451 </fields> 3452 </register> 3453 <register> 3454 <name>WKEN_SET</name> 3455 <description>GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in that register.</description> 3456 <addressOffset>0x50</addressOffset> 3457 <fields> 3458 <field> 3459 <name>ALL</name> 3460 <description>Mask of all of the pins on the port.</description> 3461 <bitOffset>0</bitOffset> 3462 <bitWidth>32</bitWidth> 3463 </field> 3464 </fields> 3465 </register> 3466 <register> 3467 <name>WKEN_CLR</name> 3468 <description>GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other bits in that register.</description> 3469 <addressOffset>0x54</addressOffset> 3470 <fields> 3471 <field> 3472 <name>ALL</name> 3473 <description>Mask of all of the pins on the port.</description> 3474 <bitOffset>0</bitOffset> 3475 <bitWidth>32</bitWidth> 3476 </field> 3477 </fields> 3478 </register> 3479 <register> 3480 <name>DUALEDGE</name> 3481 <description>GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port.</description> 3482 <addressOffset>0x5C</addressOffset> 3483 <fields> 3484 <field> 3485 <name>GPIO_DUALEDGE</name> 3486 <description>Mask of all of the pins on the port.</description> 3487 <bitOffset>0</bitOffset> 3488 <bitWidth>32</bitWidth> 3489 <enumeratedValues> 3490 <enumeratedValue> 3491 <name>no</name> 3492 <description>No Effect.</description> 3493 <value>0</value> 3494 </enumeratedValue> 3495 <enumeratedValue> 3496 <name>en</name> 3497 <description>Dual Edge mode is enabled. If edge-triggered interrupts are enabled on this GPIO pin, then both rising and falling edges will trigger interrupts regardless of the GPIO_INT_POL setting.</description> 3498 <value>1</value> 3499 </enumeratedValue> 3500 </enumeratedValues> 3501 </field> 3502 </fields> 3503 </register> 3504 <register> 3505 <name>PADCTRL0</name> 3506 <description>GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port.</description> 3507 <addressOffset>0x60</addressOffset> 3508 <fields> 3509 <field> 3510 <name>GPIO_PADCTRL0</name> 3511 <description>The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode.</description> 3512 <bitOffset>0</bitOffset> 3513 <bitWidth>32</bitWidth> 3514 <enumeratedValues> 3515 <enumeratedValue> 3516 <name>impedance</name> 3517 <description>High Impedance.</description> 3518 <value>0</value> 3519 </enumeratedValue> 3520 <enumeratedValue> 3521 <name>pu</name> 3522 <description>Weak pull-up mode.</description> 3523 <value>1</value> 3524 </enumeratedValue> 3525 <enumeratedValue> 3526 <name>pd</name> 3527 <description>weak pull-down mode.</description> 3528 <value>2</value> 3529 </enumeratedValue> 3530 </enumeratedValues> 3531 </field> 3532 </fields> 3533 </register> 3534 <register> 3535 <name>PADCTRL1</name> 3536 <description>GPIO Input Mode Config 2. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port.</description> 3537 <addressOffset>0x64</addressOffset> 3538 <fields> 3539 <field> 3540 <name>GPIO_PADCTRL1</name> 3541 <description>The two bits in GPIO_PAD_CFG1 and GPIO_PAD_CFG2 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode.</description> 3542 <bitOffset>0</bitOffset> 3543 <bitWidth>32</bitWidth> 3544 <enumeratedValues> 3545 <enumeratedValue> 3546 <name>impedance</name> 3547 <description>High Impedance.</description> 3548 <value>0</value> 3549 </enumeratedValue> 3550 <enumeratedValue> 3551 <name>pu</name> 3552 <description>Weak pull-up mode.</description> 3553 <value>1</value> 3554 </enumeratedValue> 3555 <enumeratedValue> 3556 <name>pd</name> 3557 <description>weak pull-down mode.</description> 3558 <value>2</value> 3559 </enumeratedValue> 3560 </enumeratedValues> 3561 </field> 3562 </fields> 3563 </register> 3564 <register> 3565 <name>EN1</name> 3566 <description>GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port.</description> 3567 <addressOffset>0x68</addressOffset> 3568 <fields> 3569 <field> 3570 <name>GPIO_EN1</name> 3571 <description>Mask of all of the pins on the port.</description> 3572 <bitOffset>0</bitOffset> 3573 <bitWidth>32</bitWidth> 3574 <enumeratedValues> 3575 <enumeratedValue> 3576 <name>primary</name> 3577 <description>Primary function selected.</description> 3578 <value>0</value> 3579 </enumeratedValue> 3580 <enumeratedValue> 3581 <name>secondary</name> 3582 <description>Secondary function selected.</description> 3583 <value>1</value> 3584 </enumeratedValue> 3585 </enumeratedValues> 3586 </field> 3587 </fields> 3588 </register> 3589 <register> 3590 <name>EN1_SET</name> 3591 <description>GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1, without affecting other bits in that register.</description> 3592 <addressOffset>0x6C</addressOffset> 3593 <fields> 3594 <field> 3595 <name>ALL</name> 3596 <description>Mask of all of the pins on the port.</description> 3597 <bitOffset>0</bitOffset> 3598 <bitWidth>32</bitWidth> 3599 </field> 3600 </fields> 3601 </register> 3602 <register> 3603 <name>EN1_CLR</name> 3604 <description>GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0, without affecting other bits in that register.</description> 3605 <addressOffset>0x70</addressOffset> 3606 <fields> 3607 <field> 3608 <name>ALL</name> 3609 <description>Mask of all of the pins on the port.</description> 3610 <bitOffset>0</bitOffset> 3611 <bitWidth>32</bitWidth> 3612 </field> 3613 </fields> 3614 </register> 3615 <register> 3616 <name>EN2</name> 3617 <description>GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port.</description> 3618 <addressOffset>0x74</addressOffset> 3619 <fields> 3620 <field> 3621 <name>GPIO_EN2</name> 3622 <description>Mask of all of the pins on the port.</description> 3623 <bitOffset>0</bitOffset> 3624 <bitWidth>32</bitWidth> 3625 <enumeratedValues> 3626 <enumeratedValue> 3627 <name>primary</name> 3628 <description>Primary function selected.</description> 3629 <value>0</value> 3630 </enumeratedValue> 3631 <enumeratedValue> 3632 <name>secondary</name> 3633 <description>Secondary function selected.</description> 3634 <value>1</value> 3635 </enumeratedValue> 3636 </enumeratedValues> 3637 </field> 3638 </fields> 3639 </register> 3640 <register> 3641 <name>EN2_SET</name> 3642 <description>GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1, without affecting other bits in that register.</description> 3643 <addressOffset>0x78</addressOffset> 3644 <fields> 3645 <field> 3646 <name>ALL</name> 3647 <description>Mask of all of the pins on the port.</description> 3648 <bitOffset>0</bitOffset> 3649 <bitWidth>32</bitWidth> 3650 </field> 3651 </fields> 3652 </register> 3653 <register> 3654 <name>EN2_CLR</name> 3655 <description>GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0, without affecting other bits in that register.</description> 3656 <addressOffset>0x7C</addressOffset> 3657 <fields> 3658 <field> 3659 <name>ALL</name> 3660 <description>Mask of all of the pins on the port.</description> 3661 <bitOffset>0</bitOffset> 3662 <bitWidth>32</bitWidth> 3663 </field> 3664 </fields> 3665 </register> 3666 <register> 3667 <name>HYSEN</name> 3668 <description>GPIO Input Hysteresis Enable.</description> 3669 <addressOffset>0xA8</addressOffset> 3670 <fields> 3671 <field> 3672 <name>GPIO_HYSEN</name> 3673 <description>Mask of all of the pins on the port.</description> 3674 <bitOffset>0</bitOffset> 3675 <bitWidth>32</bitWidth> 3676 </field> 3677 </fields> 3678 </register> 3679 <register> 3680 <name>SRSEL</name> 3681 <description>GPIO Slew Rate Enable Register.</description> 3682 <addressOffset>0xAC</addressOffset> 3683 <fields> 3684 <field> 3685 <name>GPIO_SRSEL</name> 3686 <description>Mask of all of the pins on the port.</description> 3687 <bitOffset>0</bitOffset> 3688 <bitWidth>32</bitWidth> 3689 <enumeratedValues> 3690 <enumeratedValue> 3691 <name>FAST</name> 3692 <description>Fast Slew Rate selected.</description> 3693 <value>0</value> 3694 </enumeratedValue> 3695 <enumeratedValue> 3696 <name>SLOW</name> 3697 <description>Slow Slew Rate selected.</description> 3698 <value>1</value> 3699 </enumeratedValue> 3700 </enumeratedValues> 3701 </field> 3702 </fields> 3703 </register> 3704 <register> 3705 <name>DS0</name> 3706 <description>GPIO Drive Strength Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode.</description> 3707 <addressOffset>0xB0</addressOffset> 3708 <fields> 3709 <field> 3710 <name>GPIO_DS0</name> 3711 <description>Mask of all of the pins on the port.</description> 3712 <bitOffset>0</bitOffset> 3713 <bitWidth>32</bitWidth> 3714 <enumeratedValues> 3715 <enumeratedValue> 3716 <name>ld</name> 3717 <description>GPIO port pin is in low-drive mode.</description> 3718 <value>0</value> 3719 </enumeratedValue> 3720 <enumeratedValue> 3721 <name>hd</name> 3722 <description>GPIO port pin is in high-drive mode.</description> 3723 <value>1</value> 3724 </enumeratedValue> 3725 </enumeratedValues> 3726 </field> 3727 </fields> 3728 </register> 3729 <register> 3730 <name>DS1</name> 3731 <description>GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode.</description> 3732 <addressOffset>0xB4</addressOffset> 3733 <fields> 3734 <field> 3735 <name>GPIO_DS1</name> 3736 <description>Mask of all of the pins on the port.</description> 3737 <bitOffset>0</bitOffset> 3738 <bitWidth>32</bitWidth> 3739 </field> 3740 </fields> 3741 </register> 3742 <register> 3743 <name>PS</name> 3744 <description>GPIO Pull Select Mode.</description> 3745 <addressOffset>0xB8</addressOffset> 3746 <fields> 3747 <field> 3748 <name>ALL</name> 3749 <description>Mask of all of the pins on the port.</description> 3750 <bitOffset>0</bitOffset> 3751 <bitWidth>32</bitWidth> 3752 </field> 3753 </fields> 3754 </register> 3755 </registers> 3756 </peripheral> 3757<!--GPIO0 Individual I/O for each GPIO--> 3758 <peripheral derivedFrom="GPIO0"> 3759 <name>GPIO1</name> 3760 <description>Individual I/O for each GPIO 1</description> 3761 <baseAddress>0x40009000</baseAddress> 3762 <interrupt> 3763 <name>GPIO1</name> 3764 <description>GPIO1 IRQ</description> 3765 <value>25</value> 3766 </interrupt> 3767 </peripheral> 3768<!--GPIO1 Individual I/O for each GPIO 1--> 3769 <peripheral> 3770 <name>I2C0</name> 3771 <description>Inter-Integrated Circuit.</description> 3772 <groupName>I2C</groupName> 3773 <baseAddress>0x4001D000</baseAddress> 3774 <size>32</size> 3775 <addressBlock> 3776 <offset>0x00</offset> 3777 <size>0x1000</size> 3778 <usage>registers</usage> 3779 </addressBlock> 3780 <interrupt> 3781 <name>I2C0</name> 3782 <description>I2C0 IRQ</description> 3783 <value>13</value> 3784 </interrupt> 3785 <registers> 3786 <register> 3787 <name>CTRL</name> 3788 <description>Control Register0.</description> 3789 <addressOffset>0x00</addressOffset> 3790 <fields> 3791 <field> 3792 <name>EN</name> 3793 <description>I2C Enable.</description> 3794 <bitRange>[0:0]</bitRange> 3795 <access>read-write</access> 3796 <enumeratedValues> 3797 <enumeratedValue> 3798 <name>dis</name> 3799 <description>Disable I2C.</description> 3800 <value>0</value> 3801 </enumeratedValue> 3802 <enumeratedValue> 3803 <name>en</name> 3804 <description>enable I2C.</description> 3805 <value>1</value> 3806 </enumeratedValue> 3807 </enumeratedValues> 3808 </field> 3809 <field> 3810 <name>MST_MODE</name> 3811 <description>Master Mode Enable.</description> 3812 <bitRange>[1:1]</bitRange> 3813 <access>read-write</access> 3814 <enumeratedValues> 3815 <enumeratedValue> 3816 <name>slave_mode</name> 3817 <description>Slave Mode.</description> 3818 <value>0</value> 3819 </enumeratedValue> 3820 <enumeratedValue> 3821 <name>master_mode</name> 3822 <description>Master Mode.</description> 3823 <value>1</value> 3824 </enumeratedValue> 3825 </enumeratedValues> 3826 </field> 3827 <field> 3828 <name>GC_ADDR_EN</name> 3829 <description>General Call Address Enable.</description> 3830 <bitRange>[2:2]</bitRange> 3831 <access>read-write</access> 3832 <enumeratedValues> 3833 <enumeratedValue> 3834 <name>dis</name> 3835 <description>Ignore Gneral Call Address.</description> 3836 <value>0</value> 3837 </enumeratedValue> 3838 <enumeratedValue> 3839 <name>en</name> 3840 <description>Acknowledge general call address.</description> 3841 <value>1</value> 3842 </enumeratedValue> 3843 </enumeratedValues> 3844 </field> 3845 <field> 3846 <name>IRXM_EN</name> 3847 <description>Interactive Receive Mode.</description> 3848 <bitRange>[3:3]</bitRange> 3849 <access>read-write</access> 3850 <enumeratedValues> 3851 <enumeratedValue> 3852 <name>dis</name> 3853 <description>Disable Interactive Receive Mode.</description> 3854 <value>0</value> 3855 </enumeratedValue> 3856 <enumeratedValue> 3857 <name>en</name> 3858 <description>Enable Interactive Receive Mode.</description> 3859 <value>1</value> 3860 </enumeratedValue> 3861 </enumeratedValues> 3862 </field> 3863 <field> 3864 <name>IRXM_ACK</name> 3865 <description>Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0.</description> 3866 <bitRange>[4:4]</bitRange> 3867 <access>read-write</access> 3868 <enumeratedValues> 3869 <enumeratedValue> 3870 <name>ack</name> 3871 <description>return ACK (pulling SDA LOW).</description> 3872 <value>0</value> 3873 </enumeratedValue> 3874 <enumeratedValue> 3875 <name>nack</name> 3876 <description>return NACK (leaving SDA HIGH).</description> 3877 <value>1</value> 3878 </enumeratedValue> 3879 </enumeratedValues> 3880 </field> 3881 <field> 3882 <name>SCL_OUT</name> 3883 <description>SCL Output. This bits control SCL output when SWOE =1.</description> 3884 <bitRange>[6:6]</bitRange> 3885 <access>read-write</access> 3886 <enumeratedValues> 3887 <enumeratedValue> 3888 <name>drive_scl_low</name> 3889 <description>Drive SCL low. </description> 3890 <value>0</value> 3891 </enumeratedValue> 3892 <enumeratedValue> 3893 <name>release_scl</name> 3894 <description>Release SCL.</description> 3895 <value>1</value> 3896 </enumeratedValue> 3897 </enumeratedValues> 3898 </field> 3899 <field> 3900 <name>SDA_OUT</name> 3901 <description>SDA Output. This bits control SDA output when SWOE = 1. </description> 3902 <bitRange>[7:7]</bitRange> 3903 <access>read-write</access> 3904 <enumeratedValues> 3905 <enumeratedValue> 3906 <name>drive_sda_low</name> 3907 <description>Drive SDA low. </description> 3908 <value>0</value> 3909 </enumeratedValue> 3910 <enumeratedValue> 3911 <name>release_sda</name> 3912 <description>Release SDA.</description> 3913 <value>1</value> 3914 </enumeratedValue> 3915 </enumeratedValues> 3916 </field> 3917 <field> 3918 <name>SCL</name> 3919 <description>SCL status. This bit reflects the logic gate of SCL signal. </description> 3920 <bitRange>[8:8]</bitRange> 3921 <access>read-only</access> 3922 </field> 3923 <field> 3924 <name>SDA</name> 3925 <description>SDA status. THis bit reflects the logic gate of SDA signal.</description> 3926 <bitRange>[9:9]</bitRange> 3927 <access>read-only</access> 3928 </field> 3929 <field> 3930 <name>BB_MODE</name> 3931 <description>Software Output Enable.</description> 3932 <bitRange>[10:10]</bitRange> 3933 <access>read-write</access> 3934 <enumeratedValues> 3935 <enumeratedValue> 3936 <name>outputs_disable</name> 3937 <description>I2C Outputs SCLO and SDAO disabled. </description> 3938 <value>0</value> 3939 </enumeratedValue> 3940 <enumeratedValue> 3941 <name>outputs_enable</name> 3942 <description>I2C Outputs SCLO and SDAO enabled.</description> 3943 <value>1</value> 3944 </enumeratedValue> 3945 </enumeratedValues> 3946 </field> 3947 <field> 3948 <name>READ</name> 3949 <description>Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match (GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set.</description> 3950 <bitRange>[11:11]</bitRange> 3951 <access>read-only</access> 3952 <enumeratedValues> 3953 <enumeratedValue> 3954 <name>write</name> 3955 <description>Write.</description> 3956 <value>0</value> 3957 </enumeratedValue> 3958 <enumeratedValue> 3959 <name>read</name> 3960 <description>Read.</description> 3961 <value>1</value> 3962 </enumeratedValue> 3963 </enumeratedValues> 3964 </field> 3965 <field> 3966 <name>CLKSTR_DIS</name> 3967 <description>This bit will disable slave clock stretching when set.</description> 3968 <bitRange>[12:12]</bitRange> 3969 <access>read-write</access> 3970 <enumeratedValues> 3971 <enumeratedValue> 3972 <name>en</name> 3973 <description>Slave clock stretching enabled.</description> 3974 <value>0</value> 3975 </enumeratedValue> 3976 <enumeratedValue> 3977 <name>dis</name> 3978 <description>Slave clock stretching disabled.</description> 3979 <value>1</value> 3980 </enumeratedValue> 3981 </enumeratedValues> 3982 </field> 3983 <field> 3984 <name>ONE_MST_MODE</name> 3985 <description>SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode, or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating as a master and communicating with slaves that are guaranteed to never drive SCL low. </description> 3986 <bitRange>[13:13]</bitRange> 3987 <access>read-write</access> 3988 <enumeratedValues> 3989 <enumeratedValue> 3990 <name>dis</name> 3991 <description>Standard open-drain operation: 3992 drive low for 0, Hi-Z for 1</description> 3993 <value>0</value> 3994 </enumeratedValue> 3995 <enumeratedValue> 3996 <name>en</name> 3997 <description>Non-standard push-pull operation: 3998 drive low for 0, drive high for 1</description> 3999 <value>1</value> 4000 </enumeratedValue> 4001 </enumeratedValues> 4002 </field> 4003 <field> 4004 <name>HS_EN</name> 4005 <description>High speed mode enable</description> 4006 <bitRange>[15:15]</bitRange> 4007 <access>read-write</access> 4008 </field>IRXM 4009 </fields> 4010 </register> 4011 <register> 4012 <name>STATUS</name> 4013 <description>Status Register.</description> 4014 <addressOffset>0x04</addressOffset> 4015 <fields> 4016 <field> 4017 <name>BUSY</name> 4018 <description>Bus Status.</description> 4019 <bitRange>[0:0]</bitRange> 4020 <access>read-only</access> 4021 <enumeratedValues> 4022 <enumeratedValue> 4023 <name>idle</name> 4024 <description>I2C Bus Idle.</description> 4025 <value>0</value> 4026 </enumeratedValue> 4027 <enumeratedValue> 4028 <name>busy</name> 4029 <description>I2C Bus Busy.</description> 4030 <value>1</value> 4031 </enumeratedValue> 4032 </enumeratedValues> 4033 </field> 4034 <field> 4035 <name>RX_EM</name> 4036 <description>RX empty.</description> 4037 <bitRange>[1:1]</bitRange> 4038 <access>read-only</access> 4039 <enumeratedValues> 4040 <enumeratedValue> 4041 <name>not_empty</name> 4042 <description>Not Empty.</description> 4043 <value>0</value> 4044 </enumeratedValue> 4045 <enumeratedValue> 4046 <name>empty</name> 4047 <description>Empty.</description> 4048 <value>1</value> 4049 </enumeratedValue> 4050 </enumeratedValues> 4051 </field> 4052 <field> 4053 <name>RX_FULL</name> 4054 <description>RX Full.</description> 4055 <bitRange>[2:2]</bitRange> 4056 <access>read-only</access> 4057 <enumeratedValues> 4058 <enumeratedValue> 4059 <name>not_full</name> 4060 <description>Not Full.</description> 4061 <value>0</value> 4062 </enumeratedValue> 4063 <enumeratedValue> 4064 <name>full</name> 4065 <description>Full.</description> 4066 <value>1</value> 4067 </enumeratedValue> 4068 </enumeratedValues> 4069 </field> 4070 <field> 4071 <name>TX_EM</name> 4072 <description>TX Empty.</description> 4073 <bitRange>[3:3]</bitRange> 4074 <enumeratedValues> 4075 <enumeratedValue> 4076 <name>not_empty</name> 4077 <description>Not Empty.</description> 4078 <value>0</value> 4079 </enumeratedValue> 4080 <enumeratedValue> 4081 <name>empty</name> 4082 <description>Empty.</description> 4083 <value>1</value> 4084 </enumeratedValue> 4085 </enumeratedValues> 4086 </field> 4087 <field> 4088 <name>TX_FULL</name> 4089 <description>TX Full.</description> 4090 <bitRange>[4:4]</bitRange> 4091 <enumeratedValues> 4092 <enumeratedValue> 4093 <name>not_empty</name> 4094 <description>Not Empty.</description> 4095 <value>0</value> 4096 </enumeratedValue> 4097 <enumeratedValue> 4098 <name>empty</name> 4099 <description>Empty.</description> 4100 <value>1</value> 4101 </enumeratedValue> 4102 </enumeratedValues> 4103 </field> 4104 <field> 4105 <name>MST_BUSY</name> 4106 <description>Clock Mode.</description> 4107 <bitRange>[5:5]</bitRange> 4108 <access>read-only</access> 4109 <enumeratedValues> 4110 <enumeratedValue> 4111 <name>not_actively_driving_scl_clock</name> 4112 <description>Device not actively driving SCL clock cycles.</description> 4113 <value>0</value> 4114 </enumeratedValue> 4115 <enumeratedValue> 4116 <name>actively_driving_scl_clock</name> 4117 <description>Device operating as master and actively driving SCL clock cycles.</description> 4118 <value>1</value> 4119 </enumeratedValue> 4120 </enumeratedValues> 4121 </field> 4122 </fields> 4123 </register> 4124 <register> 4125 <name>INTFL0</name> 4126 <description>Interrupt Status Register.</description> 4127 <addressOffset>0x08</addressOffset> 4128 <fields> 4129 <field> 4130 <name>DONE</name> 4131 <description>Transfer Done Interrupt.</description> 4132 <bitRange>[0:0]</bitRange> 4133 <enumeratedValues> 4134 <name>INT_FL0_Done</name> 4135 <enumeratedValue> 4136 <name>inactive</name> 4137 <description>No Interrupt is Pending.</description> 4138 <value>0</value> 4139 </enumeratedValue> 4140 <enumeratedValue> 4141 <name>pending</name> 4142 <description>An interrupt is pending.</description> 4143 <value>1</value> 4144 </enumeratedValue> 4145 </enumeratedValues> 4146 </field> 4147 <field> 4148 <name>IRXM</name> 4149 <description>Interactive Receive Interrupt.</description> 4150 <bitRange>[1:1]</bitRange> 4151 <enumeratedValues> 4152 <enumeratedValue> 4153 <name>inactive</name> 4154 <description>No Interrupt is Pending.</description> 4155 <value>0</value> 4156 </enumeratedValue> 4157 <enumeratedValue> 4158 <name>pending</name> 4159 <description>An interrupt is pending.</description> 4160 <value>1</value> 4161 </enumeratedValue> 4162 </enumeratedValues> 4163 </field> 4164 <field> 4165 <name>GC_ADDR_MATCH</name> 4166 <description>Slave General Call Address Match Interrupt.</description> 4167 <bitRange>[2:2]</bitRange> 4168 <enumeratedValues> 4169 <enumeratedValue> 4170 <name>inactive</name> 4171 <description>No Interrupt is Pending.</description> 4172 <value>0</value> 4173 </enumeratedValue> 4174 <enumeratedValue> 4175 <name>pending</name> 4176 <description>An interrupt is pending.</description> 4177 <value>1</value> 4178 </enumeratedValue> 4179 </enumeratedValues> 4180 </field> 4181 <field> 4182 <name>ADDR_MATCH</name> 4183 <description>Slave Address Match Interrupt.</description> 4184 <bitRange>[3:3]</bitRange> 4185 <enumeratedValues> 4186 <enumeratedValue> 4187 <name>inactive</name> 4188 <description>No Interrupt is Pending.</description> 4189 <value>0</value> 4190 </enumeratedValue> 4191 <enumeratedValue> 4192 <name>pending</name> 4193 <description>An interrupt is pending.</description> 4194 <value>1</value> 4195 </enumeratedValue> 4196 </enumeratedValues> 4197 </field> 4198 <field> 4199 <name>RX_THD</name> 4200 <description>Receive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level.</description> 4201 <bitRange>[4:4]</bitRange> 4202 <enumeratedValues> 4203 <enumeratedValue> 4204 <name>inactive</name> 4205 <description>No interrupt is pending.</description> 4206 <value>0</value> 4207 </enumeratedValue> 4208 <enumeratedValue> 4209 <name>pending</name> 4210 <description>An interrupt is pending. RX_FIFO equal or more bytes than the threshold.</description> 4211 <value>1</value> 4212 </enumeratedValue> 4213 </enumeratedValues> 4214 </field> 4215 <field> 4216 <name>TX_THD</name> 4217 <description>Transmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level.</description> 4218 <bitRange>[5:5]</bitRange> 4219 <enumeratedValues> 4220 <enumeratedValue> 4221 <name>inactive</name> 4222 <description>No interrupt is pending.</description> 4223 <value>0</value> 4224 </enumeratedValue> 4225 <enumeratedValue> 4226 <name>pending</name> 4227 <description>An interrupt is pending. TX_FIFO has equal or less bytes than the threshold.</description> 4228 <value>1</value> 4229 </enumeratedValue> 4230 </enumeratedValues> 4231 </field> 4232 <field> 4233 <name>STOP</name> 4234 <description>STOP Interrupt.</description> 4235 <bitRange>[6:6]</bitRange> 4236 <enumeratedValues> 4237 <enumeratedValue> 4238 <name>inactive</name> 4239 <description>No interrupt is pending.</description> 4240 <value>0</value> 4241 </enumeratedValue> 4242 <enumeratedValue> 4243 <name>pending</name> 4244 <description>An interrupt is pending. TX_FIFO has equal or less bytes than the threshold.</description> 4245 <value>1</value> 4246 </enumeratedValue> 4247 </enumeratedValues> 4248 </field> 4249 <field> 4250 <name>ADDR_ACK</name> 4251 <description>Address Acknowledge Interrupt.</description> 4252 <bitRange>[7:7]</bitRange> 4253 <enumeratedValues> 4254 <enumeratedValue> 4255 <name>inactive</name> 4256 <description>No Interrupt is Pending.</description> 4257 <value>0</value> 4258 </enumeratedValue> 4259 <enumeratedValue> 4260 <name>pending</name> 4261 <description>An interrupt is pending.</description> 4262 <value>1</value> 4263 </enumeratedValue> 4264 </enumeratedValues> 4265 </field> 4266 <field> 4267 <name>ARB_ERR</name> 4268 <description>Arbritation error Interrupt.</description> 4269 <bitRange>[8:8]</bitRange> 4270 <enumeratedValues> 4271 <enumeratedValue> 4272 <name>inactive</name> 4273 <description>No Interrupt is Pending.</description> 4274 <value>0</value> 4275 </enumeratedValue> 4276 <enumeratedValue> 4277 <name>pending</name> 4278 <description>An interrupt is pending.</description> 4279 <value>1</value> 4280 </enumeratedValue> 4281 </enumeratedValues> 4282 </field> 4283 <field> 4284 <name>TO_ERR</name> 4285 <description>timeout Error Interrupt.</description> 4286 <bitRange>[9:9]</bitRange> 4287 <enumeratedValues> 4288 <enumeratedValue> 4289 <name>inactive</name> 4290 <description>No Interrupt is Pending.</description> 4291 <value>0</value> 4292 </enumeratedValue> 4293 <enumeratedValue> 4294 <name>pending</name> 4295 <description>An interrupt is pending.</description> 4296 <value>1</value> 4297 </enumeratedValue> 4298 </enumeratedValues> 4299 </field> 4300 <field> 4301 <name>ADDR_NACK_ERR</name> 4302 <description>Address NACK Error Interrupt.</description> 4303 <bitRange>[10:10]</bitRange> 4304 <enumeratedValues> 4305 <enumeratedValue> 4306 <name>inactive</name> 4307 <description>No Interrupt is Pending.</description> 4308 <value>0</value> 4309 </enumeratedValue> 4310 <enumeratedValue> 4311 <name>pending</name> 4312 <description>An interrupt is pending.</description> 4313 <value>1</value> 4314 </enumeratedValue> 4315 </enumeratedValues> 4316 </field> 4317 <field> 4318 <name>DATA_ERR</name> 4319 <description>Data NACK Error Interrupt.</description> 4320 <bitRange>[11:11]</bitRange> 4321 <enumeratedValues> 4322 <enumeratedValue> 4323 <name>inactive</name> 4324 <description>No Interrupt is Pending.</description> 4325 <value>0</value> 4326 </enumeratedValue> 4327 <enumeratedValue> 4328 <name>pending</name> 4329 <description>An interrupt is pending.</description> 4330 <value>1</value> 4331 </enumeratedValue> 4332 </enumeratedValues> 4333 </field> 4334 <field> 4335 <name>DNR_ERR</name> 4336 <description>Do Not Respond Error Interrupt.</description> 4337 <bitRange>[12:12]</bitRange> 4338 <enumeratedValues> 4339 <enumeratedValue> 4340 <name>inactive</name> 4341 <description>No Interrupt is Pending.</description> 4342 <value>0</value> 4343 </enumeratedValue> 4344 <enumeratedValue> 4345 <name>pending</name> 4346 <description>An interrupt is pending.</description> 4347 <value>1</value> 4348 </enumeratedValue> 4349 </enumeratedValues> 4350 </field> 4351 <field> 4352 <name>START_ERR</name> 4353 <description>Start Error Interrupt.</description> 4354 <bitRange>[13:13]</bitRange> 4355 <enumeratedValues> 4356 <enumeratedValue> 4357 <name>inactive</name> 4358 <description>No Interrupt is Pending.</description> 4359 <value>0</value> 4360 </enumeratedValue> 4361 <enumeratedValue> 4362 <name>pending</name> 4363 <description>An interrupt is pending.</description> 4364 <value>1</value> 4365 </enumeratedValue> 4366 </enumeratedValues> 4367 </field> 4368 <field> 4369 <name>STOP_ERR</name> 4370 <description>Stop Error Interrupt.</description> 4371 <bitRange>[14:14]</bitRange> 4372 <enumeratedValues> 4373 <enumeratedValue> 4374 <name>inactive</name> 4375 <description>No Interrupt is Pending.</description> 4376 <value>0</value> 4377 </enumeratedValue> 4378 <enumeratedValue> 4379 <name>pending</name> 4380 <description>An interrupt is pending.</description> 4381 <value>1</value> 4382 </enumeratedValue> 4383 </enumeratedValues> 4384 </field> 4385 <field> 4386 <name>TX_LOCKOUT</name> 4387 <description>Transmit Lock Out Interrupt.</description> 4388 <bitRange>[15:15]</bitRange> 4389 </field> 4390 <field> 4391 <name>MAMI</name> 4392 <description>Multiple Address Match Interrupt</description> 4393 <bitRange>[21:16]</bitRange> 4394 </field> 4395 <field> 4396 <name>RD_ADDR_MATCH</name> 4397 <description>Slave Read Address Match Interrupt</description> 4398 <bitRange>[22:22]</bitRange> 4399 </field> 4400 <field> 4401 <name>WR_ADDR_MATCH</name> 4402 <description>Slave Write Address Match Interrupt</description> 4403 <bitRange>[23:23]</bitRange> 4404 </field> 4405 </fields> 4406 </register> 4407 <register> 4408 <name>INTEN0</name> 4409 <description>Interrupt Enable Register.</description> 4410 <addressOffset>0x0C</addressOffset> 4411 <access>read-write</access> 4412 <fields> 4413 <field> 4414 <name>DONE</name> 4415 <description>Transfer Done Interrupt Enable.</description> 4416 <bitRange>[0:0]</bitRange> 4417 <access>read-write</access> 4418 <enumeratedValues> 4419 <enumeratedValue> 4420 <name>dis</name> 4421 <description>Interrupt disabled.</description> 4422 <value>0</value> 4423 </enumeratedValue> 4424 <enumeratedValue> 4425 <name>en</name> 4426 <description>Interrupt enabled when DONE = 1.</description> 4427 <value>1</value> 4428 </enumeratedValue> 4429 </enumeratedValues> 4430 </field> 4431 <field> 4432 <name>IRXM</name> 4433 <description>Description not available.</description> 4434 <bitRange>[1:1]</bitRange> 4435 <access>read-write</access> 4436 <enumeratedValues> 4437 <enumeratedValue> 4438 <name>dis</name> 4439 <description>Interrupt disabled.</description> 4440 <value>0</value> 4441 </enumeratedValue> 4442 <enumeratedValue> 4443 <name>en</name> 4444 <description>Interrupt enabled when RX_MODE = 1.</description> 4445 <value>1</value> 4446 </enumeratedValue> 4447 </enumeratedValues> 4448 </field> 4449 <field> 4450 <name>GC_ADDR_MATCH</name> 4451 <description>Slave mode general call address match received input enable.</description> 4452 <bitRange>[2:2]</bitRange> 4453 <access>read-write</access> 4454 <enumeratedValues> 4455 <enumeratedValue> 4456 <name>dis</name> 4457 <description>Interrupt disabled.</description> 4458 <value>0</value> 4459 </enumeratedValue> 4460 <enumeratedValue> 4461 <name>en</name> 4462 <description>Interrupt enabled when GEN_CTRL_ADDR = 1.</description> 4463 <value>1</value> 4464 </enumeratedValue> 4465 </enumeratedValues> 4466 </field> 4467 <field> 4468 <name>ADDR_MATCH</name> 4469 <description>Slave mode incoming address match interrupt.</description> 4470 <bitRange>[3:3]</bitRange> 4471 <access>read-write</access> 4472 <enumeratedValues> 4473 <enumeratedValue> 4474 <name>dis</name> 4475 <description>Interrupt disabled.</description> 4476 <value>0</value> 4477 </enumeratedValue> 4478 <enumeratedValue> 4479 <name>en</name> 4480 <description>Interrupt enabled when ADDR_MATCH = 1.</description> 4481 <value>1</value> 4482 </enumeratedValue> 4483 </enumeratedValues> 4484 </field> 4485 <field> 4486 <name>RX_THD</name> 4487 <description>RX FIFO Above Treshold Level Interrupt Enable.</description> 4488 <bitRange>[4:4]</bitRange> 4489 <access>read-write</access> 4490 <enumeratedValues> 4491 <enumeratedValue> 4492 <name>dis</name> 4493 <description>Interrupt disabled.</description> 4494 <value>0</value> 4495 </enumeratedValue> 4496 <enumeratedValue> 4497 <name>en</name> 4498 <description>Interrupt enabled.</description> 4499 <value>1</value> 4500 </enumeratedValue> 4501 </enumeratedValues> 4502 </field> 4503 <field> 4504 <name>TX_THD</name> 4505 <description>TX FIFO Below Treshold Level Interrupt Enable.</description> 4506 <bitRange>[5:5]</bitRange> 4507 <enumeratedValues> 4508 <enumeratedValue> 4509 <name>dis</name> 4510 <description>Interrupt disabled.</description> 4511 <value>0</value> 4512 </enumeratedValue> 4513 <enumeratedValue> 4514 <name>en</name> 4515 <description>Interrupt enabled.</description> 4516 <value>1</value> 4517 </enumeratedValue> 4518 </enumeratedValues> 4519 </field> 4520 <field> 4521 <name>STOP</name> 4522 <description>Stop Interrupt Enable</description> 4523 <bitRange>[6:6]</bitRange> 4524 <access>read-write</access> 4525 <enumeratedValues> 4526 <enumeratedValue> 4527 <name>dis</name> 4528 <description>Interrupt disabled.</description> 4529 <value>0</value> 4530 </enumeratedValue> 4531 <enumeratedValue> 4532 <name>en</name> 4533 <description>Interrupt enabled when STOP = 1.</description> 4534 <value>1</value> 4535 </enumeratedValue> 4536 </enumeratedValues> 4537 </field> 4538 <field> 4539 <name>ADDR_ACK</name> 4540 <description>Received Address ACK from Slave Interrupt.</description> 4541 <bitRange>[7:7]</bitRange> 4542 <enumeratedValues> 4543 <enumeratedValue> 4544 <name>dis</name> 4545 <description>Interrupt disabled.</description> 4546 <value>0</value> 4547 </enumeratedValue> 4548 <enumeratedValue> 4549 <name>en</name> 4550 <description>Interrupt enabled.</description> 4551 <value>1</value> 4552 </enumeratedValue> 4553 </enumeratedValues> 4554 </field> 4555 <field> 4556 <name>ARB_ERR</name> 4557 <description>Master Mode Arbitration Lost Interrupt.</description> 4558 <bitRange>[8:8]</bitRange> 4559 <enumeratedValues> 4560 <enumeratedValue> 4561 <name>dis</name> 4562 <description>Interrupt disabled.</description> 4563 <value>0</value> 4564 </enumeratedValue> 4565 <enumeratedValue> 4566 <name>en</name> 4567 <description>Interrupt enabled.</description> 4568 <value>1</value> 4569 </enumeratedValue> 4570 </enumeratedValues> 4571 </field> 4572 <field> 4573 <name>TO_ERR</name> 4574 <description>Timeout Error Interrupt Enable.</description> 4575 <bitRange>[9:9]</bitRange> 4576 <enumeratedValues> 4577 <enumeratedValue> 4578 <name>dis</name> 4579 <description>Interrupt disabled.</description> 4580 <value>0</value> 4581 </enumeratedValue> 4582 <enumeratedValue> 4583 <name>en</name> 4584 <description>Interrupt enabled.</description> 4585 <value>1</value> 4586 </enumeratedValue> 4587 </enumeratedValues> 4588 </field> 4589 <field> 4590 <name>ADDR_NACK_ERR</name> 4591 <description>Master Mode Address NACK Received Interrupt.</description> 4592 <bitRange>[10:10]</bitRange> 4593 <enumeratedValues> 4594 <enumeratedValue> 4595 <name>dis</name> 4596 <description>Interrupt disabled.</description> 4597 <value>0</value> 4598 </enumeratedValue> 4599 <enumeratedValue> 4600 <name>en</name> 4601 <description>Interrupt enabled.</description> 4602 <value>1</value> 4603 </enumeratedValue> 4604 </enumeratedValues> 4605 </field> 4606 <field> 4607 <name>DATA_ERR</name> 4608 <description>Master Mode Data NACK Received Interrupt.</description> 4609 <bitRange>[11:11]</bitRange> 4610 <enumeratedValues> 4611 <enumeratedValue> 4612 <name>dis</name> 4613 <description>Interrupt disabled.</description> 4614 <value>0</value> 4615 </enumeratedValue> 4616 <enumeratedValue> 4617 <name>en</name> 4618 <description>Interrupt enabled.</description> 4619 <value>1</value> 4620 </enumeratedValue> 4621 </enumeratedValues> 4622 </field> 4623 <field> 4624 <name>DNR_ERR</name> 4625 <description>Slave Mode Do Not Respond Interrupt.</description> 4626 <bitRange>[12:12]</bitRange> 4627 <enumeratedValues> 4628 <enumeratedValue> 4629 <name>dis</name> 4630 <description>Interrupt disabled.</description> 4631 <value>0</value> 4632 </enumeratedValue> 4633 <enumeratedValue> 4634 <name>en</name> 4635 <description>Interrupt enabled.</description> 4636 <value>1</value> 4637 </enumeratedValue> 4638 </enumeratedValues> 4639 </field> 4640 <field> 4641 <name>START_ERR</name> 4642 <description>Out of Sequence START condition detected interrupt.</description> 4643 <bitRange>[13:13]</bitRange> 4644 <enumeratedValues> 4645 <enumeratedValue> 4646 <name>dis</name> 4647 <description>Interrupt disabled.</description> 4648 <value>0</value> 4649 </enumeratedValue> 4650 <enumeratedValue> 4651 <name>en</name> 4652 <description>Interrupt enabled.</description> 4653 <value>1</value> 4654 </enumeratedValue> 4655 </enumeratedValues> 4656 </field> 4657 <field> 4658 <name>STOP_ERR</name> 4659 <description>Out of Sequence STOP condition detected interrupt.</description> 4660 <bitRange>[14:14]</bitRange> 4661 <enumeratedValues> 4662 <enumeratedValue> 4663 <name>dis</name> 4664 <description>Interrupt disabled.</description> 4665 <value>0</value> 4666 </enumeratedValue> 4667 <enumeratedValue> 4668 <name>en</name> 4669 <description>Interrupt enabled.</description> 4670 <value>1</value> 4671 </enumeratedValue> 4672 </enumeratedValues> 4673 </field> 4674 <field> 4675 <name>TX_LOCKOUT</name> 4676 <description>TX FIFO Locked Out Interrupt.</description> 4677 <bitRange>[15:15]</bitRange> 4678 </field> 4679 <field> 4680 <name>MAMI</name> 4681 <description>Multiple Address Match Interrupt</description> 4682 <bitRange>[21:16]</bitRange> 4683 </field> 4684 <field> 4685 <name>RD_ADDR_MATCH</name> 4686 <description>Slave Read Address Match Interrupt</description> 4687 <bitRange>[22:22]</bitRange> 4688 </field> 4689 <field> 4690 <name>WR_ADDR_MATCH</name> 4691 <description>Slave Write Address Match Interrupt</description> 4692 <bitRange>[23:23]</bitRange> 4693 </field> 4694 </fields> 4695 </register> 4696 <register> 4697 <name>INTFL1</name> 4698 <description>Interrupt Status Register 1.</description> 4699 <addressOffset>0x10</addressOffset> 4700 <fields> 4701 <field> 4702 <name>RX_OV</name> 4703 <description>Receiver Overflow Interrupt. When operating as a slave receiver, this bit is set when you reach the first data bit and the RX FIFO and shift register are both full.</description> 4704 <bitRange>[0:0]</bitRange> 4705 <enumeratedValues> 4706 <enumeratedValue> 4707 <name>inactive</name> 4708 <description>No Interrupt is Pending.</description> 4709 <value>0</value> 4710 </enumeratedValue> 4711 <enumeratedValue> 4712 <name>pending</name> 4713 <description>An interrupt is pending.</description> 4714 <value>1</value> 4715 </enumeratedValue> 4716 </enumeratedValues> 4717 </field> 4718 <field> 4719 <name>TX_UN</name> 4720 <description>Transmit Underflow Interrupt. When operating as a slave transmitter, this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet).</description> 4721 <bitRange>[1:1]</bitRange> 4722 <enumeratedValues> 4723 <enumeratedValue> 4724 <name>inactive</name> 4725 <description>No Interrupt is Pending.</description> 4726 <value>0</value> 4727 </enumeratedValue> 4728 <enumeratedValue> 4729 <name>pending</name> 4730 <description>An interrupt is pending.</description> 4731 <value>1</value> 4732 </enumeratedValue> 4733 </enumeratedValues> 4734 </field> 4735 <field> 4736 <name>START</name> 4737 <description>START Condition Status Flag.</description> 4738 <bitRange>[2:2]</bitRange> 4739 </field> 4740 </fields> 4741 </register> 4742 <register> 4743 <name>INTEN1</name> 4744 <description>Interrupt Staus Register 1.</description> 4745 <addressOffset>0x14</addressOffset> 4746 <access>read-write</access> 4747 <fields> 4748 <field> 4749 <name>RX_OV</name> 4750 <description>Receiver Overflow Interrupt Enable.</description> 4751 <bitRange>[0:0]</bitRange> 4752 <enumeratedValues> 4753 <enumeratedValue> 4754 <name>dis</name> 4755 <description>No Interrupt is Pending.</description> 4756 <value>0</value> 4757 </enumeratedValue> 4758 <enumeratedValue> 4759 <name>en</name> 4760 <description>An interrupt is pending.</description> 4761 <value>1</value> 4762 </enumeratedValue> 4763 </enumeratedValues> 4764 </field> 4765 <field> 4766 <name>TX_UN</name> 4767 <description>Transmit Underflow Interrupt Enable.</description> 4768 <bitRange>[1:1]</bitRange> 4769 <enumeratedValues> 4770 <enumeratedValue> 4771 <name>dis</name> 4772 <description>No Interrupt is Pending.</description> 4773 <value>0</value> 4774 </enumeratedValue> 4775 <enumeratedValue> 4776 <name>en</name> 4777 <description>An interrupt is pending.</description> 4778 <value>1</value> 4779 </enumeratedValue> 4780 </enumeratedValues> 4781 </field> 4782 <field> 4783 <name>START</name> 4784 <description>START Condition Interrupt Enable.</description> 4785 <bitRange>[2:2]</bitRange> 4786 </field> 4787 </fields> 4788 </register> 4789 <register> 4790 <name>FIFOLEN</name> 4791 <description>FIFO Configuration Register.</description> 4792 <addressOffset>0x18</addressOffset> 4793 <fields> 4794 <field> 4795 <name>RX_DEPTH</name> 4796 <description>Receive FIFO Length.</description> 4797 <bitRange>[7:0]</bitRange> 4798 <access>read-only</access> 4799 </field> 4800 <field> 4801 <name>TX_DEPTH</name> 4802 <description>Transmit FIFO Length.</description> 4803 <bitRange>[15:8]</bitRange> 4804 <access>read-only</access> 4805 </field> 4806 </fields> 4807 </register> 4808 <register> 4809 <name>RXCTRL0</name> 4810 <description>Receive Control Register 0.</description> 4811 <addressOffset>0x1C</addressOffset> 4812 <fields> 4813 <field> 4814 <name>DNR</name> 4815 <description>Do Not Respond.</description> 4816 <bitRange>[0:0]</bitRange> 4817 <enumeratedValues> 4818 <enumeratedValue> 4819 <name>respond</name> 4820 <description>Always respond to address match.</description> 4821 <value>0</value> 4822 </enumeratedValue> 4823 <enumeratedValue> 4824 <name>not_respond_rx_fifo_empty</name> 4825 <description>Do not respond to address match when RX_FIFO is not empty.</description> 4826 <value>1</value> 4827 </enumeratedValue> 4828 </enumeratedValues> 4829 </field> 4830 <field> 4831 <name>FLUSH</name> 4832 <description>Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status.</description> 4833 <bitRange>[7:7]</bitRange> 4834 <enumeratedValues> 4835 <enumeratedValue> 4836 <name>not_flushed</name> 4837 <description>FIFO not flushed.</description> 4838 <value>0</value> 4839 </enumeratedValue> 4840 <enumeratedValue> 4841 <name>flush</name> 4842 <description>Flush RX_FIFO.</description> 4843 <value>1</value> 4844 </enumeratedValue> 4845 </enumeratedValues> 4846 </field> 4847 <field> 4848 <name>THD_LVL</name> 4849 <description>Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold.</description> 4850 <bitRange>[11:8]</bitRange> 4851 </field> 4852 </fields> 4853 </register> 4854 <register> 4855 <name>RXCTRL1</name> 4856 <description>Receive Control Register 1.</description> 4857 <addressOffset>0x20</addressOffset> 4858 <fields> 4859 <field> 4860 <name>CNT</name> 4861 <description>Receive Count Bits. These bits define the number of bytes to be received in a transaction, except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction.</description> 4862 <bitRange>[7:0]</bitRange> 4863 </field> 4864 <field> 4865 <name>LVL</name> 4866 <description>Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0.</description> 4867 <bitRange>[11:8]</bitRange> 4868 <access>read-only</access> 4869 </field> 4870 </fields> 4871 </register> 4872 <register> 4873 <name>TXCTRL0</name> 4874 <description>Transmit Control Register 0.</description> 4875 <addressOffset>0x24</addressOffset> 4876 <fields> 4877 <field> 4878 <name>PRELOAD_MODE</name> 4879 <description>Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match.</description> 4880 <bitRange>[0:0]</bitRange> 4881 </field> 4882 <field> 4883 <name>TX_READY_MODE</name> 4884 <description>Transmit FIFO Ready Manual Mode.</description> 4885 <bitRange>[1:1]</bitRange> 4886 <enumeratedValues> 4887 <enumeratedValue> 4888 <name>en</name> 4889 <description>HW control of I2CTXRDY enabled.</description> 4890 <value>0</value> 4891 </enumeratedValue> 4892 <enumeratedValue> 4893 <name>dis</name> 4894 <description>HW control of I2CTXRDY disabled.</description> 4895 <value>1</value> 4896 </enumeratedValue> 4897 </enumeratedValues> 4898 </field> 4899 <field> 4900 <name>GC_ADDR_FLUSH_DIS</name> 4901 <description>TX FIFO General Call Address Match Auto Flush Disable.</description> 4902 <bitRange>[2:2]</bitRange> 4903 <enumeratedValues> 4904 <enumeratedValue> 4905 <name>en</name> 4906 <description>Enabled.</description> 4907 <value>0</value> 4908 </enumeratedValue> 4909 <enumeratedValue> 4910 <name>dis</name> 4911 <description>Disabled.</description> 4912 <value>1</value> 4913 </enumeratedValue> 4914 </enumeratedValues> 4915 </field> 4916 <field> 4917 <name>WR_ADDR_FLUSH_DIS</name> 4918 <description>TX FIFO Slave Address Match Write Auto Flush Disable.</description> 4919 <bitRange>[3:3]</bitRange> 4920 <enumeratedValues> 4921 <enumeratedValue> 4922 <name>en</name> 4923 <description>Enabled.</description> 4924 <value>0</value> 4925 </enumeratedValue> 4926 <enumeratedValue> 4927 <name>dis</name> 4928 <description>Disabled.</description> 4929 <value>1</value> 4930 </enumeratedValue> 4931 </enumeratedValues> 4932 </field> 4933 <field> 4934 <name>RD_ADDR_FLUSH_DIS</name> 4935 <description>TX FIFO Slave Address Match Read Auto Flush Disable.</description> 4936 <bitRange>[4:4]</bitRange> 4937 <enumeratedValues> 4938 <enumeratedValue> 4939 <name>en</name> 4940 <description>Enabled.</description> 4941 <value>0</value> 4942 </enumeratedValue> 4943 <enumeratedValue> 4944 <name>dis</name> 4945 <description>Disabled.</description> 4946 <value>1</value> 4947 </enumeratedValue> 4948 </enumeratedValues> 4949 </field> 4950 <field> 4951 <name>NACK_FLUSH_DIS</name> 4952 <description>TX FIFO received NACK Auto Flush Disable.</description> 4953 <bitRange>[5:5]</bitRange> 4954 <enumeratedValues> 4955 <enumeratedValue> 4956 <name>en</name> 4957 <description>Enabled.</description> 4958 <value>0</value> 4959 </enumeratedValue> 4960 <enumeratedValue> 4961 <name>dis</name> 4962 <description>Disabled.</description> 4963 <value>1</value> 4964 </enumeratedValue> 4965 </enumeratedValues> 4966 </field> 4967 <field> 4968 <name>FLUSH</name> 4969 <description>Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation.</description> 4970 <bitRange>[7:7]</bitRange> 4971 <enumeratedValues> 4972 <enumeratedValue> 4973 <name>not_flushed</name> 4974 <description>FIFO not flushed.</description> 4975 <value>0</value> 4976 </enumeratedValue> 4977 <enumeratedValue> 4978 <name>flush</name> 4979 <description>Flush TX_FIFO.</description> 4980 <value>1</value> 4981 </enumeratedValue> 4982 </enumeratedValues> 4983 </field> 4984 <field> 4985 <name>THD_VAL</name> 4986 <description>Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold.</description> 4987 <bitRange>[11:8]</bitRange> 4988 </field> 4989 </fields> 4990 </register> 4991 <register> 4992 <name>TXCTRL1</name> 4993 <description>Transmit Control Register 1.</description> 4994 <addressOffset>0x28</addressOffset> 4995 <fields> 4996 <field> 4997 <name>PRELOAD_RDY</name> 4998 <description>Transmit FIFO Preload Ready.</description> 4999 <bitRange>[0:0]</bitRange> 5000 </field> 5001 <field> 5002 <name>LVL</name> 5003 <description>Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO.</description> 5004 <bitRange>[11:8]</bitRange> 5005 <access>read-only</access> 5006 </field> 5007 </fields> 5008 </register> 5009 <register> 5010 <name>FIFO</name> 5011 <description>Data Register.</description> 5012 <addressOffset>0x2C</addressOffset> 5013 <fields> 5014 <field> 5015 <name>DATA</name> 5016 <description>Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location.</description> 5017 <bitOffset>0</bitOffset> 5018 <bitWidth>8</bitWidth> 5019 </field> 5020 </fields> 5021 </register> 5022 <register> 5023 <name>MSTCTRL</name> 5024 <description>Master Control Register.</description> 5025 <addressOffset>0x30</addressOffset> 5026 <fields> 5027 <field> 5028 <name>START</name> 5029 <description>Setting this bit to 1 will start a master transfer.</description> 5030 <bitRange>[0:0]</bitRange> 5031 </field> 5032 <field> 5033 <name>RESTART</name> 5034 <description>Setting this bit to 1 will generate a repeated START.</description> 5035 <bitRange>[1:1]</bitRange> 5036 </field> 5037 <field> 5038 <name>STOP</name> 5039 <description>Setting this bit to 1 will generate a STOP condition.</description> 5040 <bitRange>[2:2]</bitRange> 5041 </field> 5042 <field> 5043 <name>EX_ADDR_EN</name> 5044 <description>Slave Extend Address Select.</description> 5045 <bitRange>[7:7]</bitRange> 5046 <enumeratedValues> 5047 <enumeratedValue> 5048 <name>7_bits_address</name> 5049 <description>7-bit address.</description> 5050 <value>0</value> 5051 </enumeratedValue> 5052 <enumeratedValue> 5053 <name>10_bits_address</name> 5054 <description>10-bit address.</description> 5055 <value>1</value> 5056 </enumeratedValue> 5057 </enumeratedValues> 5058 </field> 5059 </fields> 5060 </register> 5061 <register> 5062 <name>CLKLO</name> 5063 <description>Clock Low Register.</description> 5064 <addressOffset>0x34</addressOffset> 5065 <fields> 5066 <field> 5067 <name>LO</name> 5068 <description>Clock low. In master mode, these bits define the SCL low period. In slave mode, these bits define the time SCL will be held low after data is outputted.</description> 5069 <bitRange>[8:0]</bitRange> 5070 </field> 5071 </fields> 5072 </register> 5073 <register> 5074 <name>CLKHI</name> 5075 <description>Clock high Register.</description> 5076 <addressOffset>0x38</addressOffset> 5077 <fields> 5078 <field> 5079 <name>HI</name> 5080 <description>Clock High. In master mode, these bits define the SCL high period.</description> 5081 <bitRange>[8:0]</bitRange> 5082 </field> 5083 </fields> 5084 </register> 5085 <register> 5086 <name>HSCLK</name> 5087 <description>Clock high Register.</description> 5088 <addressOffset>0x3C</addressOffset> 5089 <fields> 5090 <field> 5091 <name>LO</name> 5092 <description>Clock Low. This field sets the Hs-Mode clock low count. In Slave mode, this is the time SCL is held low after data is output on SDA.</description> 5093 <bitRange>[7:0]</bitRange> 5094 </field> 5095 <field> 5096 <name>HI</name> 5097 <description>Clock High. This field sets the Hs-Mode clock high count. In Slave mode, this is the time SCL is held high after data is output on SDA</description> 5098 <bitRange>[15:8]</bitRange> 5099 </field> 5100 </fields> 5101 </register> 5102 <register> 5103 <name>TIMEOUT</name> 5104 <description>Timeout Register</description> 5105 <addressOffset>0x40</addressOffset> 5106 <fields> 5107 <field> 5108 <name>SCL_TO_VAL</name> 5109 <description>Timeout</description> 5110 <bitRange>[15:0]</bitRange> 5111 </field> 5112 </fields> 5113 </register> 5114 <register> 5115 <name>SLAVE</name> 5116 <description>Slave Address Register.</description> 5117 <addressOffset>0x44</addressOffset> 5118 <fields> 5119 <field> 5120 <name>ADDR</name> 5121 <description>Slave Address.</description> 5122 <bitRange>[9:0]</bitRange> 5123 </field> 5124 <field> 5125 <name>DIS</name> 5126 <description>Slave Address Disable.</description> 5127 <bitRange>[10:10]</bitRange> 5128 </field> 5129 <field> 5130 <name>IDX</name> 5131 <description>Slave Address Index.</description> 5132 <bitRange>[14:11]</bitRange> 5133 </field> 5134 <field> 5135 <name>EXT_ADDR_EN</name> 5136 <description>Extended Address Select.</description> 5137 <bitRange>[15:15]</bitRange> 5138 <enumeratedValues> 5139 <enumeratedValue> 5140 <name>7_bits_address</name> 5141 <description>7-bit address.</description> 5142 <value>0</value> 5143 </enumeratedValue> 5144 <enumeratedValue> 5145 <name>10_bits_address</name> 5146 <description>10-bit address.</description> 5147 <value>1</value> 5148 </enumeratedValue> 5149 </enumeratedValues> 5150 </field> 5151 </fields> 5152 </register> 5153 <register> 5154 <name>DMA</name> 5155 <description>DMA Register.</description> 5156 <addressOffset>0x48</addressOffset> 5157 <fields> 5158 <field> 5159 <name>TX_EN</name> 5160 <description>TX channel enable.</description> 5161 <bitRange>[0:0]</bitRange> 5162 <enumeratedValues> 5163 <enumeratedValue> 5164 <name>dis</name> 5165 <description>Disable.</description> 5166 <value>0</value> 5167 </enumeratedValue> 5168 <enumeratedValue> 5169 <name>en</name> 5170 <description>Enable.</description> 5171 <value>1</value> 5172 </enumeratedValue> 5173 </enumeratedValues> 5174 </field> 5175 <field> 5176 <name>RX_EN</name> 5177 <description>RX channel enable.</description> 5178 <bitRange>[1:1]</bitRange> 5179 <enumeratedValues> 5180 <enumeratedValue> 5181 <name>dis</name> 5182 <description>Disable.</description> 5183 <value>0</value> 5184 </enumeratedValue> 5185 <enumeratedValue> 5186 <name>en</name> 5187 <description>Enable.</description> 5188 <value>1</value> 5189 </enumeratedValue> 5190 </enumeratedValues> 5191 </field> 5192 </fields> 5193 </register> 5194 </registers> 5195 </peripheral> 5196<!--I2C0 Inter-Integrated Circuit.--> 5197 <peripheral derivedFrom="I2C0"> 5198 <name>I2C1</name> 5199 <description>Inter-Integrated Circuit. 1</description> 5200 <baseAddress>0x4001E000</baseAddress> 5201 <interrupt> 5202 <name>I2C1</name> 5203 <description>I2C1 IRQ</description> 5204 <value>36</value> 5205 </interrupt> 5206 </peripheral> 5207<!--I2C1 Inter-Integrated Circuit. 1--> 5208 <peripheral derivedFrom="I2C0"> 5209 <name>I2C2</name> 5210 <description>Inter-Integrated Circuit. 2</description> 5211 <baseAddress>0x4001F000</baseAddress> 5212 <interrupt> 5213 <name>I2C2</name> 5214 <description>I2C2 IRQ</description> 5215 <value>62</value> 5216 </interrupt> 5217 </peripheral> 5218<!--I2C2 Inter-Integrated Circuit. 2--> 5219 <peripheral> 5220 <name>I2S</name> 5221 <description>Inter-IC Sound Interface.</description> 5222 <groupName>I2S</groupName> 5223 <baseAddress>0x40060000</baseAddress> 5224 <size>32</size> 5225 <addressBlock> 5226 <offset>0x00</offset> 5227 <size>0x1000</size> 5228 <usage>registers</usage> 5229 </addressBlock> 5230 <interrupt> 5231 <name>I2S</name> 5232 <description>I2S IRQ</description> 5233 <value>99</value> 5234 </interrupt> 5235 <registers> 5236 <register> 5237 <name>CTRL0CH0</name> 5238 <description>Global mode channel.</description> 5239 <addressOffset>0x00</addressOffset> 5240 <fields> 5241 <field> 5242 <name>LSB_FIRST</name> 5243 <description>LSB Transmit Receive First.</description> 5244 <bitRange>[1:1]</bitRange> 5245 <access>read-write</access> 5246 </field> 5247 <field> 5248 <name>CH_MODE</name> 5249 <description>SCK Select.</description> 5250 <bitRange>[7:6]</bitRange> 5251 <access>read-write</access> 5252 </field> 5253 <field> 5254 <name>WS_POL</name> 5255 <description>WS polarity select. </description> 5256 <bitRange>[8:8]</bitRange> 5257 <access>read-write</access> 5258 </field> 5259 <field> 5260 <name>MSB_LOC</name> 5261 <description>MSB location. </description> 5262 <bitRange>[9:9]</bitRange> 5263 <access>read-only</access> 5264 </field> 5265 <field> 5266 <name>ALIGN</name> 5267 <description>Align to MSB or LSB.</description> 5268 <bitRange>[10:10]</bitRange> 5269 <access>read-only</access> 5270 </field> 5271 <field> 5272 <name>EXT_SEL</name> 5273 <description>External SCK/WS selection.</description> 5274 <bitRange>[11:11]</bitRange> 5275 <access>read-write</access> 5276 </field> 5277 <field> 5278 <name>STEREO</name> 5279 <description>Stereo mode of I2S.</description> 5280 <bitRange>[13:12]</bitRange> 5281 <access>read-only</access> 5282 </field> 5283 <field> 5284 <name>WSIZE</name> 5285 <description>Data size when write to FIFO.</description> 5286 <bitRange>[15:14]</bitRange> 5287 <access>read-write</access> 5288 </field> 5289 <field> 5290 <name>TX_EN</name> 5291 <description>TX channel enable. </description> 5292 <bitRange>[16:16]</bitRange> 5293 <access>read-write</access> 5294 </field> 5295 <field> 5296 <name>RX_EN</name> 5297 <description>RX channel enable. </description> 5298 <bitRange>[17:17]</bitRange> 5299 <access>read-write</access> 5300 </field> 5301 <field> 5302 <name>FLUSH</name> 5303 <description>Flushes the TX/RX FIFO buffer. </description> 5304 <bitRange>[18:18]</bitRange> 5305 <access>read-write</access> 5306 </field> 5307 <field> 5308 <name>RST</name> 5309 <description>Write 1 to reset channel. </description> 5310 <bitRange>[19:19]</bitRange> 5311 <access>read-write</access> 5312 </field> 5313 <field> 5314 <name>FIFO_LSB</name> 5315 <description>Bit Field Control. </description> 5316 <bitRange>[20:20]</bitRange> 5317 <access>read-write</access> 5318 </field> 5319 <field> 5320 <name>RX_THD_VAL</name> 5321 <description>depth of receive FIFO for threshold interrupt generation. </description> 5322 <bitRange>[31:24]</bitRange> 5323 <access>read-write</access> 5324 </field> 5325 </fields> 5326 </register> 5327 <register> 5328 <name>CTRL1CH0</name> 5329 <description>Local channel Setup.</description> 5330 <addressOffset>0x10</addressOffset> 5331 <fields> 5332 <field> 5333 <name>BITS_WORD</name> 5334 <description>I2S word length.</description> 5335 <bitRange>[4:0]</bitRange> 5336 <access>read-write</access> 5337 </field> 5338 <field> 5339 <name>EN</name> 5340 <description>I2S clock enable.</description> 5341 <bitRange>[8:8]</bitRange> 5342 <access>read-write</access> 5343 </field> 5344 <field> 5345 <name>SMP_SIZE</name> 5346 <description>I2S sample size length.</description> 5347 <bitRange>[13:9]</bitRange> 5348 <access>read-write</access> 5349 </field> 5350 <field> 5351 <name>ADJST</name> 5352 <description>LSB/MSB Justify.</description> 5353 <bitRange>[15:15]</bitRange> 5354 <access>read-write</access> 5355 </field> 5356 <field> 5357 <name>CLKDIV</name> 5358 <description>I2S clock frequency divisor.</description> 5359 <bitRange>[31:16]</bitRange> 5360 <access>read-write</access> 5361 </field> 5362 </fields> 5363 </register> 5364 <register> 5365 <name>DMACH0</name> 5366 <description>DMA Control.</description> 5367 <addressOffset>0x30</addressOffset> 5368 <fields> 5369 <field> 5370 <name>DMA_TX_THD_VAL</name> 5371 <description>TX FIFO Level DMA Trigger.</description> 5372 <bitRange>[6:0]</bitRange> 5373 <access>read-write</access> 5374 </field> 5375 <field> 5376 <name>DMA_TX_EN</name> 5377 <description>TX DMA channel enable.</description> 5378 <bitRange>[7:7]</bitRange> 5379 <access>read-write</access> 5380 </field> 5381 <field> 5382 <name>DMA_RX_THD_VAL</name> 5383 <description>RX FIFO Level DMA Trigger.</description> 5384 <bitRange>[14:8]</bitRange> 5385 <access>read-write</access> 5386 </field> 5387 <field> 5388 <name>DMA_RX_EN</name> 5389 <description>RX DMA channel enable.</description> 5390 <bitRange>[15:15]</bitRange> 5391 <access>read-write</access> 5392 </field> 5393 <field> 5394 <name>TX_LVL</name> 5395 <description>Number of data word in the TX FIFO.</description> 5396 <bitRange>[23:16]</bitRange> 5397 <access>read-write</access> 5398 </field> 5399 <field> 5400 <name>RX_LVL</name> 5401 <description>Number of data word in the RX FIFO.</description> 5402 <bitRange>[31:24]</bitRange> 5403 <access>read-write</access> 5404 </field> 5405 </fields> 5406 </register> 5407 <register> 5408 <name>FIFOCH0</name> 5409 <description>I2S Fifo.</description> 5410 <addressOffset>0x40</addressOffset> 5411 <fields> 5412 <field> 5413 <name>DATA</name> 5414 <description>Load/unload location for TX and RX FIFO buffers.</description> 5415 <bitRange>[31:0]</bitRange> 5416 <access>read-write</access> 5417 </field> 5418 </fields> 5419 </register> 5420 <register> 5421 <name>INTFL</name> 5422 <description>ISR Status.</description> 5423 <addressOffset>0x50</addressOffset> 5424 <fields> 5425 <field> 5426 <name>RX_OV_CH0</name> 5427 <description>Status for RX FIFO Overrun interrupt.</description> 5428 <bitRange>[0:0]</bitRange> 5429 <access>read-write</access> 5430 </field> 5431 <field> 5432 <name>RX_THD_CH0</name> 5433 <description>Status for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.</description> 5434 <bitRange>[1:1]</bitRange> 5435 <access>read-write</access> 5436 </field> 5437 <field> 5438 <name>TX_OB_CH0</name> 5439 <description>Status for interrupt when TX FIFO has only one byte remaining.</description> 5440 <bitRange>[2:2]</bitRange> 5441 <access>read-write</access> 5442 </field> 5443 <field> 5444 <name>TX_HE_CH0</name> 5445 <description>Status for interrupt when TX FIFO is half empty.</description> 5446 <bitRange>[3:3]</bitRange> 5447 <access>read-write</access> 5448 </field> 5449 </fields> 5450 </register> 5451 <register> 5452 <name>INTEN</name> 5453 <description>Interrupt Enable.</description> 5454 <addressOffset>0x54</addressOffset> 5455 <fields> 5456 <field> 5457 <name>RX_OV_CH0</name> 5458 <description>Enable for RX FIFO Overrun interrupt.</description> 5459 <bitRange>[0:0]</bitRange> 5460 <access>read-write</access> 5461 </field> 5462 <field> 5463 <name>RX_THD_CH0</name> 5464 <description>Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field.</description> 5465 <bitRange>[1:1]</bitRange> 5466 <access>read-write</access> 5467 </field> 5468 <field> 5469 <name>TX_OB_CH0</name> 5470 <description>Enable for interrupt when TX FIFO has only one byte remaining.</description> 5471 <bitRange>[2:2]</bitRange> 5472 <access>read-write</access> 5473 </field> 5474 <field> 5475 <name>TX_HE_CH0</name> 5476 <description>Enable for interrupt when TX FIFO is half empty.</description> 5477 <bitRange>[3:3]</bitRange> 5478 <access>read-write</access> 5479 </field> 5480 </fields> 5481 </register> 5482 <register> 5483 <name>EXTSETUP</name> 5484 <description>Ext Control.</description> 5485 <addressOffset>0x58</addressOffset> 5486 <fields> 5487 <field> 5488 <name>EXT_BITS_WORD</name> 5489 <description>Word Length for ch_mode.</description> 5490 <bitRange>[4:0]</bitRange> 5491 <access>read-write</access> 5492 </field> 5493 </fields> 5494 </register> 5495 </registers> 5496 </peripheral> 5497<!--I2S Inter-IC Sound Interface.--> 5498 <peripheral> 5499 <name>ICC0</name> 5500 <description>Instruction Cache Controller Registers</description> 5501 <baseAddress>0x4002A000</baseAddress> 5502 <addressBlock> 5503 <offset>0x00</offset> 5504 <size>0x800</size> 5505 <usage>registers</usage> 5506 </addressBlock> 5507 <registers> 5508 <register> 5509 <name>INFO</name> 5510 <description>Cache ID Register.</description> 5511 <addressOffset>0x0000</addressOffset> 5512 <access>read-only</access> 5513 <fields> 5514 <field> 5515 <name>RELNUM</name> 5516 <description>Release Number. Identifies the RTL release version.</description> 5517 <bitOffset>0</bitOffset> 5518 <bitWidth>6</bitWidth> 5519 </field> 5520 <field> 5521 <name>PARTNUM</name> 5522 <description>Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter.</description> 5523 <bitOffset>6</bitOffset> 5524 <bitWidth>4</bitWidth> 5525 </field> 5526 <field> 5527 <name>ID</name> 5528 <description>Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter.</description> 5529 <bitOffset>10</bitOffset> 5530 <bitWidth>6</bitWidth> 5531 </field> 5532 </fields> 5533 </register> 5534 <register> 5535 <name>SZ</name> 5536 <description>Memory Configuration Register.</description> 5537 <addressOffset>0x0004</addressOffset> 5538 <access>read-only</access> 5539 <resetValue>0x00080008</resetValue> 5540 <fields> 5541 <field> 5542 <name>CCH</name> 5543 <description>Cache Size. Indicates total size in Kbytes of cache.</description> 5544 <bitOffset>0</bitOffset> 5545 <bitWidth>16</bitWidth> 5546 </field> 5547 <field> 5548 <name>MEM</name> 5549 <description>Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller.</description> 5550 <bitOffset>16</bitOffset> 5551 <bitWidth>16</bitWidth> 5552 </field> 5553 </fields> 5554 </register> 5555 <register> 5556 <name>CTRL</name> 5557 <description>Cache Control and Status Register.</description> 5558 <addressOffset>0x0100</addressOffset> 5559 <fields> 5560 <field> 5561 <name>EN</name> 5562 <description>Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated.</description> 5563 <bitOffset>0</bitOffset> 5564 <bitWidth>1</bitWidth> 5565 <enumeratedValues> 5566 <enumeratedValue> 5567 <name>dis</name> 5568 <description>Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array.</description> 5569 <value>0</value> 5570 </enumeratedValue> 5571 <enumeratedValue> 5572 <name>en</name> 5573 <description>Cache Enabled.</description> 5574 <value>1</value> 5575 </enumeratedValue> 5576 </enumeratedValues> 5577 </field> 5578 <field> 5579 <name>RDY</name> 5580 <description>Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready.</description> 5581 <bitOffset>16</bitOffset> 5582 <bitWidth>1</bitWidth> 5583 <access>read-only</access> 5584 <enumeratedValues> 5585 <enumeratedValue> 5586 <name>notReady</name> 5587 <description>Not Ready.</description> 5588 <value>0</value> 5589 </enumeratedValue> 5590 <enumeratedValue> 5591 <name>ready</name> 5592 <description>Ready.</description> 5593 <value>1</value> 5594 </enumeratedValue> 5595 </enumeratedValues> 5596 </field> 5597 </fields> 5598 </register> 5599 <register> 5600 <name>INVALIDATE</name> 5601 <description>Invalidate All Registers.</description> 5602 <addressOffset>0x0700</addressOffset> 5603 <access>read-write</access> 5604 <fields> 5605 <field> 5606 <name>INVALID</name> 5607 <description>Invalidate.</description> 5608 <bitOffset>0</bitOffset> 5609 <bitWidth>32</bitWidth> 5610 </field> 5611 </fields> 5612 </register> 5613 </registers> 5614 </peripheral> 5615<!--ICC0 Instruction Cache Controller Registers--> 5616 <peripheral> 5617 <name>MCR</name> 5618 <description>Miscellaneous Control Registers.</description> 5619 <baseAddress>0x40106C00</baseAddress> 5620 <addressBlock> 5621 <offset>0</offset> 5622 <size>0x400</size> 5623 <usage>registers</usage> 5624 </addressBlock> 5625 <registers> 5626 <register> 5627 <name>RST</name> 5628 <description>Reset control register 0.</description> 5629 <addressOffset>0x04</addressOffset> 5630 <resetMask>0</resetMask> 5631 <fields> 5632 <field> 5633 <name>lptmr0</name> 5634 <description>Setting this bit will reset LPTMR0.</description> 5635 <bitOffset>0</bitOffset> 5636 <bitWidth>1</bitWidth> 5637 <enumeratedValues> 5638 <enumeratedValue> 5639 <name>rst</name> 5640 <description>Reset LPTMR0.</description> 5641 <value>1</value> 5642 </enumeratedValue> 5643 </enumeratedValues> 5644 </field> 5645 <field> 5646 <name>lptmr1</name> 5647 <description>Setting this bit will reset LPTMR1.</description> 5648 <bitOffset>1</bitOffset> 5649 <bitWidth>1</bitWidth> 5650 <enumeratedValues> 5651 <enumeratedValue> 5652 <name>rst</name> 5653 <description>Reset LPTMR1.</description> 5654 <value>1</value> 5655 </enumeratedValue> 5656 </enumeratedValues> 5657 </field> 5658 <field> 5659 <name>lpuart0</name> 5660 <description>Setting this bit will reset LPUART0.</description> 5661 <bitOffset>2</bitOffset> 5662 <bitWidth>1</bitWidth> 5663 <enumeratedValues> 5664 <enumeratedValue> 5665 <name>rst</name> 5666 <description>Reset LPUART0.</description> 5667 <value>1</value> 5668 </enumeratedValue> 5669 </enumeratedValues> 5670 </field> 5671 <field> 5672 <name>rtc</name> 5673 <description>Setting this bit will reset the Real-Time Clock.</description> 5674 <bitOffset>3</bitOffset> 5675 <bitWidth>1</bitWidth> 5676 <enumeratedValues> 5677 <enumeratedValue> 5678 <name>rst</name> 5679 <description>Reset Real-Time Clock.</description> 5680 <value>1</value> 5681 </enumeratedValue> 5682 </enumeratedValues> 5683 </field> 5684 </fields> 5685 </register> 5686 <register> 5687 <name>LPPIOCTRL</name> 5688 <description>Low-power peripheral IO control.</description> 5689 <addressOffset>0x10</addressOffset> 5690 <resetMask>0</resetMask> 5691 <fields> 5692 <field> 5693 <name>LPTMR0_I</name> 5694 <description>Setting this bit will enable the low-power timer 0 (timer 4) input pin while operating in low-power modes.</description> 5695 <bitOffset>0</bitOffset> 5696 <bitWidth>1</bitWidth> 5697 <enumeratedValues> 5698 <enumeratedValue> 5699 <name>dis</name> 5700 <description>Disable LPTMR0 input pin.</description> 5701 <value>0</value> 5702 </enumeratedValue> 5703 <enumeratedValue> 5704 <name>en</name> 5705 <description>Enable LPTMR0 input pin.</description> 5706 <value>1</value> 5707 </enumeratedValue> 5708 </enumeratedValues> 5709 </field> 5710 <field> 5711 <name>LPTMR0_O</name> 5712 <description>Setting this bit will enable the low-power timer 0 (timer 4) output pin while operating in low-power modes.</description> 5713 <bitOffset>1</bitOffset> 5714 <bitWidth>1</bitWidth> 5715 <enumeratedValues> 5716 <enumeratedValue> 5717 <name>dis</name> 5718 <description>Disable LPTMR0 output pin.</description> 5719 <value>0</value> 5720 </enumeratedValue> 5721 <enumeratedValue> 5722 <name>en</name> 5723 <description>Enable LPTMR0 output pin.</description> 5724 <value>1</value> 5725 </enumeratedValue> 5726 </enumeratedValues> 5727 </field> 5728 <field> 5729 <name>LPTMR1_I</name> 5730 <description>Setting this bit will enable the low-power timer 1 (timer 5) input pin while operating in low-power modes.</description> 5731 <bitOffset>2</bitOffset> 5732 <bitWidth>1</bitWidth> 5733 <enumeratedValues> 5734 <enumeratedValue> 5735 <name>dis</name> 5736 <description>Disable LPTMR1 input pin.</description> 5737 <value>0</value> 5738 </enumeratedValue> 5739 <enumeratedValue> 5740 <name>en</name> 5741 <description>Enable LPTMR1 input pin.</description> 5742 <value>1</value> 5743 </enumeratedValue> 5744 </enumeratedValues> 5745 </field> 5746 <field> 5747 <name>LPTMR1_O</name> 5748 <description>Setting this bit will enable the low-power timer 1 (timer 5) output pin while operating in low-power modes.</description> 5749 <bitOffset>3</bitOffset> 5750 <bitWidth>1</bitWidth> 5751 <enumeratedValues> 5752 <enumeratedValue> 5753 <name>dis</name> 5754 <description>Disable LPTMR1 output pin.</description> 5755 <value>0</value> 5756 </enumeratedValue> 5757 <enumeratedValue> 5758 <name>en</name> 5759 <description>Enable LPTMR1 output pin.</description> 5760 <value>1</value> 5761 </enumeratedValue> 5762 </enumeratedValues> 5763 </field> 5764 <field> 5765 <name>LPUART0_RX</name> 5766 <description>Setting this bit will enable the low-power UART 0 (UART3) RX pin while operating in low-power modes.</description> 5767 <bitOffset>4</bitOffset> 5768 <bitWidth>1</bitWidth> 5769 <enumeratedValues> 5770 <enumeratedValue> 5771 <name>dis</name> 5772 <description>Disable LPUART0 RX pin.</description> 5773 <value>0</value> 5774 </enumeratedValue> 5775 <enumeratedValue> 5776 <name>en</name> 5777 <description>Enable LPUART0 RX pin.</description> 5778 <value>1</value> 5779 </enumeratedValue> 5780 </enumeratedValues> 5781 </field> 5782 <field> 5783 <name>LPUART0_TX</name> 5784 <description>Setting this bit will enable the low-power UART 0 (UART3) TX pin while operating in low-power modes.</description> 5785 <bitOffset>5</bitOffset> 5786 <bitWidth>1</bitWidth> 5787 <enumeratedValues> 5788 <enumeratedValue> 5789 <name>dis</name> 5790 <description>Disable LPUART0 TX pin.</description> 5791 <value>0</value> 5792 </enumeratedValue> 5793 <enumeratedValue> 5794 <name>en</name> 5795 <description>Enable LPUART0 TX pin.</description> 5796 <value>1</value> 5797 </enumeratedValue> 5798 </enumeratedValues> 5799 </field> 5800 <field> 5801 <name>LPUART0_CTS</name> 5802 <description>Setting this bit will enable the low-power UART 0 (UART3) CTS pin while operating in low-power modes.</description> 5803 <bitOffset>6</bitOffset> 5804 <bitWidth>1</bitWidth> 5805 <enumeratedValues> 5806 <enumeratedValue> 5807 <name>dis</name> 5808 <description>Disable LPUART0 CTS pin.</description> 5809 <value>0</value> 5810 </enumeratedValue> 5811 <enumeratedValue> 5812 <name>en</name> 5813 <description>Enable LPUART0 CTS pin.</description> 5814 <value>1</value> 5815 </enumeratedValue> 5816 </enumeratedValues> 5817 </field> 5818 <field> 5819 <name>LPUART0_RTS</name> 5820 <description>Setting this bit will enable the low-power UART 0 (UART3) RTS pin while operating in low-power modes.</description> 5821 <bitOffset>7</bitOffset> 5822 <bitWidth>1</bitWidth> 5823 <enumeratedValues> 5824 <enumeratedValue> 5825 <name>dis</name> 5826 <description>Disable LPUART0 RTS pin.</description> 5827 <value>0</value> 5828 </enumeratedValue> 5829 <enumeratedValue> 5830 <name>en</name> 5831 <description>Enable LPUART0 RTS pin.</description> 5832 <value>1</value> 5833 </enumeratedValue> 5834 </enumeratedValues> 5835 </field> 5836 </fields> 5837 </register> 5838 <register> 5839 <name>CLKDIS</name> 5840 <description>Peripheral clock control register.</description> 5841 <addressOffset>0x24</addressOffset> 5842 <resetMask>0xFFFFFFFF</resetMask> 5843 <fields> 5844 <field> 5845 <name>lptmr0</name> 5846 <description>Clearing this bit will enable the low-power timer 0 (timer 4) peripheral clock.</description> 5847 <bitOffset>0</bitOffset> 5848 <bitWidth>1</bitWidth> 5849 <enumeratedValues> 5850 <enumeratedValue> 5851 <name>en</name> 5852 <description>Enable LPTMR0 clock.</description> 5853 <value>0</value> 5854 </enumeratedValue> 5855 <enumeratedValue> 5856 <name>dis</name> 5857 <description>Disable LPTMR0 clock.</description> 5858 <value>1</value> 5859 </enumeratedValue> 5860 </enumeratedValues> 5861 </field> 5862 <field> 5863 <name>lptmr1</name> 5864 <description>Clearing this bit will enable the low-power timer 1 (timer 5) peripheral clock.</description> 5865 <bitOffset>1</bitOffset> 5866 <bitWidth>1</bitWidth> 5867 <enumeratedValues> 5868 <enumeratedValue> 5869 <name>en</name> 5870 <description>Enable LPTMR1 clock.</description> 5871 <value>0</value> 5872 </enumeratedValue> 5873 <enumeratedValue> 5874 <name>dis</name> 5875 <description>Disable LPTMR1 clock.</description> 5876 <value>1</value> 5877 </enumeratedValue> 5878 </enumeratedValues> 5879 </field> 5880 <field> 5881 <name>lpuart0</name> 5882 <description>Clearing this bit will enable the low-power UART 0 (UART3) peripheral clock.</description> 5883 <bitOffset>2</bitOffset> 5884 <bitWidth>1</bitWidth> 5885 <enumeratedValues> 5886 <enumeratedValue> 5887 <name>en</name> 5888 <description>Enable LPUART0 clock.</description> 5889 <value>0</value> 5890 </enumeratedValue> 5891 <enumeratedValue> 5892 <name>dis</name> 5893 <description>Disable LPUART0 clock.</description> 5894 <value>1</value> 5895 </enumeratedValue> 5896 </enumeratedValues> 5897 </field> 5898 </fields> 5899 </register> 5900 </registers> 5901 </peripheral> 5902<!--MCR Miscellaneous Control Registers.--> 5903 <peripheral> 5904 <name>PWRSEQ</name> 5905 <description>Power Sequencer / Low Power Control Register.</description> 5906 <baseAddress>0x40106800</baseAddress> 5907 <addressBlock> 5908 <offset>0x00</offset> 5909 <size>0x400</size> 5910 <usage>registers</usage> 5911 </addressBlock> 5912 <registers> 5913 <register> 5914 <name>LPCN</name> 5915 <description>Low Power Control Register.</description> 5916 <addressOffset>0x00</addressOffset> 5917 <fields> 5918 <field> 5919 <name>RAM0RET_EN</name> 5920 <description>System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description> 5921 <bitOffset>0</bitOffset> 5922 <bitWidth>1</bitWidth> 5923 <enumeratedValues> 5924 <enumeratedValue> 5925 <name>dis</name> 5926 <description>Disable Ram Retention.</description> 5927 <value>0</value> 5928 </enumeratedValue> 5929 <enumeratedValue> 5930 <name>en</name> 5931 <description>Enable System RAM 0 retention.</description> 5932 <value>1</value> 5933 </enumeratedValue> 5934 </enumeratedValues> 5935 </field> 5936 <field> 5937 <name>RAM1RET_EN</name> 5938 <description>System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description> 5939 <bitOffset>1</bitOffset> 5940 <bitWidth>1</bitWidth> 5941 <enumeratedValues> 5942 <enumeratedValue> 5943 <name>dis</name> 5944 <description>Disable Ram Retention.</description> 5945 <value>0</value> 5946 </enumeratedValue> 5947 <enumeratedValue> 5948 <name>en</name> 5949 <description>Enable System RAM 1 retention.</description> 5950 <value>1</value> 5951 </enumeratedValue> 5952 </enumeratedValues> 5953 </field> 5954 <field> 5955 <name>RAM2RET_EN</name> 5956 <description>System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description> 5957 <bitOffset>2</bitOffset> 5958 <bitWidth>1</bitWidth> 5959 <enumeratedValues> 5960 <enumeratedValue> 5961 <name>dis</name> 5962 <description>Disable Ram Retention.</description> 5963 <value>0</value> 5964 </enumeratedValue> 5965 <enumeratedValue> 5966 <name>en</name> 5967 <description>Enable System RAM 2 retention.</description> 5968 <value>1</value> 5969 </enumeratedValue> 5970 </enumeratedValues> 5971 </field> 5972 <field> 5973 <name>RAM3RET_EN</name> 5974 <description>System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. </description> 5975 <bitOffset>3</bitOffset> 5976 <bitWidth>1</bitWidth> 5977 <enumeratedValues> 5978 <enumeratedValue> 5979 <name>dis</name> 5980 <description>Disable Ram Retention.</description> 5981 <value>0</value> 5982 </enumeratedValue> 5983 <enumeratedValue> 5984 <name>en</name> 5985 <description>Enable System RAM 3 retention.</description> 5986 <value>1</value> 5987 </enumeratedValue> 5988 </enumeratedValues> 5989 </field> 5990 <field> 5991 <name>OVR</name> 5992 <description>Operating Voltage Range</description> 5993 <bitOffset>4</bitOffset> 5994 <bitWidth>2</bitWidth> 5995 <enumeratedValues> 5996 <enumeratedValue> 5997 <name>0_9V</name> 5998 <description>0.9V 24MHz</description> 5999 <value>0</value> 6000 </enumeratedValue> 6001 <enumeratedValue> 6002 <name>1_0V</name> 6003 <description>1.0V 48MHz</description> 6004 <value>1</value> 6005 </enumeratedValue> 6006 <enumeratedValue> 6007 <name>1_1V</name> 6008 <description>1.1V 96MHz</description> 6009 <value>2</value> 6010 </enumeratedValue> 6011 </enumeratedValues> 6012 </field> 6013 <field> 6014 <name>VCORE_DET_BYPASS</name> 6015 <description>Block Auto-Detect</description> 6016 <bitOffset>6</bitOffset> 6017 <bitWidth>1</bitWidth> 6018 <enumeratedValues> 6019 <enumeratedValue> 6020 <name>enabled</name> 6021 <description>enable</description> 6022 <value>0</value> 6023 </enumeratedValue> 6024 <enumeratedValue> 6025 <name>Disable</name> 6026 <description>disable</description> 6027 <value>1</value> 6028 </enumeratedValue> 6029 </enumeratedValues> 6030 </field> 6031 <field> 6032 <name>RETREG_EN</name> 6033 <description>Retention Regulator Enable. This bit controls the retention regulator in BACKUP mode. </description> 6034 <bitOffset>8</bitOffset> 6035 <bitWidth>1</bitWidth> 6036 <enumeratedValues> 6037 <enumeratedValue> 6038 <name>dis</name> 6039 <description>Disabled.</description> 6040 <value>0</value> 6041 </enumeratedValue> 6042 <enumeratedValue> 6043 <name>en</name> 6044 <description>Enabled.</description> 6045 <value>1</value> 6046 </enumeratedValue> 6047 </enumeratedValues> 6048 </field> 6049 <field> 6050 <name>STORAGE_EN</name> 6051 <description>STORAGE Mode ENable. This bit allows low-power background mode operations, while the CPU is in DeepSleep.</description> 6052 <bitOffset>9</bitOffset> 6053 <bitWidth>1</bitWidth> 6054 <enumeratedValues> 6055 <enumeratedValue> 6056 <name>dis</name> 6057 <description>Disabled.</description> 6058 <value>0</value> 6059 </enumeratedValue> 6060 <enumeratedValue> 6061 <name>en</name> 6062 <description>Enabled.</description> 6063 <value>1</value> 6064 </enumeratedValue> 6065 </enumeratedValues> 6066 </field> 6067 <field> 6068 <name>FASTWK_EN</name> 6069 <description>Fast Wake-Up Mode. This bit enables fast wake-up from DeepSleep mode. (5uS typical). </description> 6070 <bitOffset>10</bitOffset> 6071 <bitWidth>1</bitWidth> 6072 <enumeratedValues> 6073 <enumeratedValue> 6074 <name>dis</name> 6075 <description>Disabled.</description> 6076 <value>0</value> 6077 </enumeratedValue> 6078 <enumeratedValue> 6079 <name>en</name> 6080 <description>Enabled.</description> 6081 <value>1</value> 6082 </enumeratedValue> 6083 </enumeratedValues> 6084 </field> 6085 <field> 6086 <name>BG_DIS</name> 6087 <description>Bandgap OFF. This controls the System Bandgap in DeepSleep mode.</description> 6088 <bitOffset>11</bitOffset> 6089 <bitWidth>1</bitWidth> 6090 <enumeratedValues> 6091 <enumeratedValue> 6092 <name>on</name> 6093 <description>Bandgap is always ON.</description> 6094 <value>0</value> 6095 </enumeratedValue> 6096 <enumeratedValue> 6097 <name>off</name> 6098 <description>Bandgap is OFF in DeepSleep mode (default).</description> 6099 <value>1</value> 6100 </enumeratedValue> 6101 </enumeratedValues> 6102 </field> 6103 <field> 6104 <name>VCOREPOR_DIS</name> 6105 <description>VDDC (Vcore) Power on reset Monitor Disable.This bit controls the Power-On Reset monitor on VDDC supply in 6106 DeepSleep and BACKUP mode.</description> 6107 <bitOffset>12</bitOffset> 6108 <bitWidth>1</bitWidth> 6109 <enumeratedValues> 6110 <enumeratedValue> 6111 <name>en</name> 6112 <description>Enable</description> 6113 <value>0</value> 6114 </enumeratedValue> 6115 <enumeratedValue> 6116 <name>dis</name> 6117 <description>Disabled.</description> 6118 <value>1</value> 6119 </enumeratedValue> 6120 </enumeratedValues> 6121 </field> 6122 <field> 6123 <name>LDO_DIS</name> 6124 <description>Disable Main LDO</description> 6125 <bitOffset>16</bitOffset> 6126 <bitWidth>1</bitWidth> 6127 <enumeratedValues> 6128 <enumeratedValue> 6129 <name>en</name> 6130 <description>Enable </description> 6131 <value>0</value> 6132 </enumeratedValue> 6133 <enumeratedValue> 6134 <name>dis</name> 6135 <description>Disabled.</description> 6136 <value>1</value> 6137 </enumeratedValue> 6138 </enumeratedValues> 6139 </field> 6140 <field> 6141 <name>VCORE_EXT</name> 6142 <description>Use external VCORE for 1V supply</description> 6143 <bitOffset>17</bitOffset> 6144 <bitWidth>1</bitWidth> 6145 <enumeratedValues> 6146 <enumeratedValue> 6147 <name>dis</name> 6148 <description>disable </description> 6149 <value>0</value> 6150 </enumeratedValue> 6151 <enumeratedValue> 6152 <name>en</name> 6153 <description>use Vcore for retention.</description> 6154 <value>1</value> 6155 </enumeratedValue> 6156 </enumeratedValues> 6157 </field> 6158 <field> 6159 <name>VCOREMON_DIS</name> 6160 <description>VDDC (Vcore) Monitor Disable. This bit controls the power monitor on the VCore supply in all operating modes.</description> 6161 <bitOffset>20</bitOffset> 6162 <bitWidth>1</bitWidth> 6163 <enumeratedValues> 6164 <enumeratedValue> 6165 <name>en</name> 6166 <description>Enable</description> 6167 <value>0</value> 6168 </enumeratedValue> 6169 <enumeratedValue> 6170 <name>dis</name> 6171 <description>Disabled.</description> 6172 <value>1</value> 6173 </enumeratedValue> 6174 </enumeratedValues> 6175 </field> 6176 <field> 6177 <name>VDDAMON_DIS</name> 6178 <description>VDDA Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes.</description> 6179 <bitOffset>22</bitOffset> 6180 <bitWidth>1</bitWidth> 6181 <enumeratedValues> 6182 <enumeratedValue> 6183 <name>en</name> 6184 <description>Enable if Bandgap is ON (default) </description> 6185 <value>0</value> 6186 </enumeratedValue> 6187 <enumeratedValue> 6188 <name>dis</name> 6189 <description>Disabled.</description> 6190 <value>1</value> 6191 </enumeratedValue> 6192 </enumeratedValues> 6193 </field> 6194 <field> 6195 <name>PORVDDMON_DIS</name> 6196 <description>VDDIO Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDIO supply in all operating mods.</description> 6197 <bitOffset>25</bitOffset> 6198 <bitWidth>1</bitWidth> 6199 <enumeratedValues> 6200 <enumeratedValue> 6201 <name>dis</name> 6202 <description>Disabled.</description> 6203 <value>0</value> 6204 </enumeratedValue> 6205 <enumeratedValue> 6206 <name>en</name> 6207 <description>Enabled.</description> 6208 <value>1</value> 6209 </enumeratedValue> 6210 </enumeratedValues> 6211 </field> 6212 <field> 6213 <name>INRO_EN</name> 6214 <description>INRO remains on in all power modes if this bit is set otherwise it is controled by the LP controller</description> 6215 <bitOffset>28</bitOffset> 6216 <bitWidth>1</bitWidth> 6217 </field> 6218 <field> 6219 <name>ERTCO_EN</name> 6220 <description>XRTCO remains on in all power modes if this bit is set otherwise it is controled by the LP controller</description> 6221 <bitOffset>29</bitOffset> 6222 <bitWidth>1</bitWidth> 6223 </field> 6224 <field> 6225 <name>ERTCO_PD</name> 6226 <description>ERTCO Powerdown.</description> 6227 <bitOffset>31</bitOffset> 6228 <bitWidth>1</bitWidth> 6229 </field> 6230 </fields> 6231 </register> 6232 <register> 6233 <name>LPWKST0</name> 6234 <description>Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO0.</description> 6235 <addressOffset>0x04</addressOffset> 6236 <fields> 6237 <field> 6238 <name>ST</name> 6239 <description>Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin (s) transition (s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode.</description> 6240 <bitOffset>0</bitOffset> 6241 <bitWidth>1</bitWidth> 6242 </field> 6243 </fields> 6244 </register> 6245 <register> 6246 <name>LPWKEN0</name> 6247 <description>Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0.</description> 6248 <addressOffset>0x08</addressOffset> 6249 <fields> 6250 <field> 6251 <name>EN</name> 6252 <description>Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register.</description> 6253 <bitOffset>0</bitOffset> 6254 <bitWidth>31</bitWidth> 6255 </field> 6256 </fields> 6257 </register> 6258 <register derivedFrom="LPWKST0"> 6259 <name>LPWKST1</name> 6260 <description>Low Power I/O Wakeup Status Register 1. This register indicates the low power wakeup status for GPIO1.</description> 6261 <addressOffset>0x0C</addressOffset> 6262 </register> 6263 <register derivedFrom="LPWKEN0"> 6264 <name>LPWKEN1</name> 6265 <description>Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup functionality for GPIO1.</description> 6266 <addressOffset>0x10</addressOffset> 6267 </register> 6268 <register> 6269 <name>LPPWKST</name> 6270 <description>Low Power Peripheral Wakeup Status Register.</description> 6271 <addressOffset>0x30</addressOffset> 6272 <fields> 6273 <field> 6274 <name>LPTMR0</name> 6275 <description>LPTM0 Wakeup Flag.</description> 6276 <bitOffset>0</bitOffset> 6277 <bitWidth>1</bitWidth> 6278 </field> 6279 <field> 6280 <name>LPTMR1</name> 6281 <description>LPTMR1 Wakeup Flag.</description> 6282 <bitOffset>1</bitOffset> 6283 <bitWidth>1</bitWidth> 6284 </field> 6285 <field> 6286 <name>LPUART0</name> 6287 <description>LPUART0 Wakeup Flag.</description> 6288 <bitOffset>2</bitOffset> 6289 <bitWidth>1</bitWidth> 6290 </field> 6291 </fields> 6292 </register> 6293 <register> 6294 <name>LPPWKEN</name> 6295 <description>Low Power Peripheral Wakeup Enable Register.</description> 6296 <addressOffset>0x34</addressOffset> 6297 <fields> 6298 <field> 6299 <name>LPTMR0</name> 6300 <description> TIMER4 Wakeup Enable. This bit allows wakeup from the TIMER4.</description> 6301 <bitOffset>0</bitOffset> 6302 <bitWidth>1</bitWidth> 6303 </field> 6304 <field> 6305 <name>LPTMR1</name> 6306 <description> TIMER5 Wakeup Enable. This bit allows wakeup from the TIMER5.</description> 6307 <bitOffset>1</bitOffset> 6308 <bitWidth>1</bitWidth> 6309 </field> 6310 <field> 6311 <name>LPUART0</name> 6312 <description> LPUART Wakeup Enable. This bit allows wakeup from the LPUART.</description> 6313 <bitOffset>2</bitOffset> 6314 <bitWidth>1</bitWidth> 6315 </field> 6316 </fields> 6317 </register> 6318 <register> 6319 <name>LPMEMSD</name> 6320 <description>Low Power Memory Shutdown Control.</description> 6321 <addressOffset>0x40</addressOffset> 6322 <fields> 6323 <field> 6324 <name>RAM0</name> 6325 <description>System RAM block 0 Shut Down.</description> 6326 <bitOffset>0</bitOffset> 6327 <bitWidth>1</bitWidth> 6328 <enumeratedValues> 6329 <enumeratedValue> 6330 <name>normal</name> 6331 <description>Normal Operating Mode.</description> 6332 <value>0</value> 6333 </enumeratedValue> 6334 <enumeratedValue> 6335 <name>shutdown</name> 6336 <description>Shutdown Mode.</description> 6337 <value>1</value> 6338 </enumeratedValue> 6339 </enumeratedValues> 6340 </field> 6341 <field> 6342 <name>RAM1</name> 6343 <description>System RAM block 1 Shut Down.</description> 6344 <bitOffset>1</bitOffset> 6345 <bitWidth>1</bitWidth> 6346 <enumeratedValues> 6347 <enumeratedValue> 6348 <name>normal</name> 6349 <description>Normal Operating Mode.</description> 6350 <value>0</value> 6351 </enumeratedValue> 6352 <enumeratedValue> 6353 <name>shutdown</name> 6354 <description>Shutdown Mode.</description> 6355 <value>1</value> 6356 </enumeratedValue> 6357 </enumeratedValues> 6358 </field> 6359 <field> 6360 <name>RAM2</name> 6361 <description>System RAM block 2 Shut Down.</description> 6362 <bitOffset>2</bitOffset> 6363 <bitWidth>1</bitWidth> 6364 <enumeratedValues> 6365 <enumeratedValue> 6366 <name>normal</name> 6367 <description>Normal Operating Mode.</description> 6368 <value>0</value> 6369 </enumeratedValue> 6370 <enumeratedValue> 6371 <name>shutdown</name> 6372 <description>Shutdown Mode.</description> 6373 <value>1</value> 6374 </enumeratedValue> 6375 </enumeratedValues> 6376 </field> 6377 <field> 6378 <name>RAM3</name> 6379 <description>System RAM block 3 Shut Down.</description> 6380 <bitOffset>3</bitOffset> 6381 <bitWidth>1</bitWidth> 6382 <enumeratedValues> 6383 <enumeratedValue> 6384 <name>normal</name> 6385 <description>Normal Operating Mode.</description> 6386 <value>0</value> 6387 </enumeratedValue> 6388 <enumeratedValue> 6389 <name>shutdown</name> 6390 <description>Shutdown Mode.</description> 6391 <value>1</value> 6392 </enumeratedValue> 6393 </enumeratedValues> 6394 </field> 6395 </fields> 6396 </register> 6397 <register> 6398 <name>GP0</name> 6399 <description>General Purpose Register 0</description> 6400 <addressOffset>0x48</addressOffset> 6401 </register> 6402 <register> 6403 <name>GP1</name> 6404 <description>General Purpose Register 1</description> 6405 <addressOffset>0x4C</addressOffset> 6406 </register> 6407 </registers> 6408 </peripheral> 6409<!--PWRSEQ Power Sequencer / Low Power Control Register.--> 6410 <peripheral> 6411 <name>RTC</name> 6412 <description>Real Time Clock and Alarm.</description> 6413 <baseAddress>0x40106000</baseAddress> 6414 <addressBlock> 6415 <offset>0x00</offset> 6416 <size>0x400</size> 6417 <usage>registers</usage> 6418 </addressBlock> 6419 <interrupt> 6420 <name>RTC</name> 6421 <description>RTC interrupt.</description> 6422 <value>3</value> 6423 </interrupt> 6424 <registers> 6425 <register> 6426 <name>SEC</name> 6427 <description>RTC Second Counter. This register contains the 32-bit second counter.</description> 6428 <addressOffset>0x00</addressOffset> 6429 <resetMask>0x00000000</resetMask> 6430 <fields> 6431 <field> 6432 <name>SEC</name> 6433 <description>Seconds Counter.</description> 6434 <bitOffset>0</bitOffset> 6435 <bitWidth>32</bitWidth> 6436 </field> 6437 </fields> 6438 </register> 6439 <register> 6440 <name>SSEC</name> 6441 <description>RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented when this register rolls over from 0xFF to 0x00.</description> 6442 <addressOffset>0x04</addressOffset> 6443 <resetMask>0x00000000</resetMask> 6444 <fields> 6445 <field> 6446 <name>SSEC</name> 6447 <description>Sub-Seconds Counter (12-bit).</description> 6448 <bitOffset>0</bitOffset> 6449 <bitWidth>12</bitWidth> 6450 </field> 6451 </fields> 6452 </register> 6453 <register> 6454 <name>TODA</name> 6455 <description>Time-of-day Alarm.</description> 6456 <addressOffset>0x08</addressOffset> 6457 <resetMask>0x00000000</resetMask> 6458 <fields> 6459 <field> 6460 <name>TOD_ALARM</name> 6461 <description>Time-of-day Alarm.</description> 6462 <bitOffset>0</bitOffset> 6463 <bitWidth>20</bitWidth> 6464 </field> 6465 </fields> 6466 </register> 6467 <register> 6468 <name>SSECA</name> 6469 <description>RTC sub-second alarm. This register contains the reload value for the sub-second alarm.</description> 6470 <addressOffset>0x0C</addressOffset> 6471 <resetMask>0x00000000</resetMask> 6472 <fields> 6473 <field> 6474 <name>SSEC_ALARM</name> 6475 <description>This register contains the reload value for the sub-second alarm.</description> 6476 <bitOffset>0</bitOffset> 6477 <bitWidth>32</bitWidth> 6478 </field> 6479 </fields> 6480 </register> 6481 <register> 6482 <name>CTRL</name> 6483 <description>RTC Control Register.</description> 6484 <addressOffset>0x10</addressOffset> 6485 <resetValue>0x00000008</resetValue> 6486 <resetMask>0xFFFFFF38</resetMask> 6487 <fields> 6488 <field> 6489 <name>EN</name> 6490 <description>Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0.</description> 6491 <bitOffset>0</bitOffset> 6492 <bitWidth>1</bitWidth> 6493 <enumeratedValues> 6494 <enumeratedValue> 6495 <name>dis</name> 6496 <description>Disable.</description> 6497 <value>0</value> 6498 </enumeratedValue> 6499 <enumeratedValue> 6500 <name>en</name> 6501 <description>Enable.</description> 6502 <value>1</value> 6503 </enumeratedValue> 6504 </enumeratedValues> 6505 </field> 6506 <field> 6507 <name>TOD_ALARM_IE</name> 6508 <description>Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0.</description> 6509 <bitOffset>1</bitOffset> 6510 <bitWidth>1</bitWidth> 6511 <enumeratedValues> 6512 <enumeratedValue> 6513 <name>dis</name> 6514 <description>Disable.</description> 6515 <value>0</value> 6516 </enumeratedValue> 6517 <enumeratedValue> 6518 <name>en</name> 6519 <description>Enable.</description> 6520 <value>1</value> 6521 </enumeratedValue> 6522 </enumeratedValues> 6523 </field> 6524 <field> 6525 <name>SSEC_ALARM_IE</name> 6526 <description>Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0.</description> 6527 <bitOffset>2</bitOffset> 6528 <bitWidth>1</bitWidth> 6529 <enumeratedValues> 6530 <enumeratedValue> 6531 <name>dis</name> 6532 <description>Disable.</description> 6533 <value>0</value> 6534 </enumeratedValue> 6535 <enumeratedValue> 6536 <name>en</name> 6537 <description>Enable.</description> 6538 <value>1</value> 6539 </enumeratedValue> 6540 </enumeratedValues> 6541 </field> 6542 <field> 6543 <name>BUSY</name> 6544 <description>RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware.</description> 6545 <bitOffset>3</bitOffset> 6546 <bitWidth>1</bitWidth> 6547 <access>read-only</access> 6548 <enumeratedValues> 6549 <enumeratedValue> 6550 <name>idle</name> 6551 <description>Idle.</description> 6552 <value>0</value> 6553 </enumeratedValue> 6554 <enumeratedValue> 6555 <name>busy</name> 6556 <description>Busy.</description> 6557 <value>1</value> 6558 </enumeratedValue> 6559 </enumeratedValues> 6560 </field> 6561 <field> 6562 <name>RDY</name> 6563 <description>RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register.</description> 6564 <bitOffset>4</bitOffset> 6565 <bitWidth>1</bitWidth> 6566 <enumeratedValues> 6567 <enumeratedValue> 6568 <name>busy</name> 6569 <description>Register has not updated.</description> 6570 <value>0</value> 6571 </enumeratedValue> 6572 <enumeratedValue> 6573 <name>ready</name> 6574 <description>Ready.</description> 6575 <value>1</value> 6576 </enumeratedValue> 6577 </enumeratedValues> 6578 </field> 6579 <field> 6580 <name>RDY_IE</name> 6581 <description>RTC Ready Interrupt Enable.</description> 6582 <bitOffset>5</bitOffset> 6583 <bitWidth>1</bitWidth> 6584 <enumeratedValues> 6585 <enumeratedValue> 6586 <name>dis</name> 6587 <description>Disable.</description> 6588 <value>0</value> 6589 </enumeratedValue> 6590 <enumeratedValue> 6591 <name>en</name> 6592 <description>Enable.</description> 6593 <value>1</value> 6594 </enumeratedValue> 6595 </enumeratedValues> 6596 </field> 6597 <field> 6598 <name>TOD_ALARM</name> 6599 <description>Time-of-Day Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor.</description> 6600 <bitOffset>6</bitOffset> 6601 <bitWidth>1</bitWidth> 6602 <access>read-only</access> 6603 <enumeratedValues> 6604 <enumeratedValue> 6605 <name>inactive</name> 6606 <description>Not active</description> 6607 <value>0</value> 6608 </enumeratedValue> 6609 <enumeratedValue> 6610 <name>Pending</name> 6611 <description>Active</description> 6612 <value>1</value> 6613 </enumeratedValue> 6614 </enumeratedValues> 6615 </field> 6616 <field> 6617 <name>SSEC_ALARM</name> 6618 <description>Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor.</description> 6619 <bitOffset>7</bitOffset> 6620 <bitWidth>1</bitWidth> 6621 <access>read-only</access> 6622 <enumeratedValues> 6623 <enumeratedValue> 6624 <name>inactive</name> 6625 <description>Not active</description> 6626 <value>0</value> 6627 </enumeratedValue> 6628 <enumeratedValue> 6629 <name>Pending</name> 6630 <description>Active</description> 6631 <value>1</value> 6632 </enumeratedValue> 6633 </enumeratedValues> 6634 </field> 6635 <field> 6636 <name>SQW_EN</name> 6637 <description>Square Wave Output Enable.</description> 6638 <bitOffset>8</bitOffset> 6639 <bitWidth>1</bitWidth> 6640 <enumeratedValues> 6641 <enumeratedValue> 6642 <name>inactive</name> 6643 <description>Not active</description> 6644 <value>0</value> 6645 </enumeratedValue> 6646 <enumeratedValue> 6647 <name>Pending</name> 6648 <description>Active</description> 6649 <value>1</value> 6650 </enumeratedValue> 6651 </enumeratedValues> 6652 </field> 6653 <field> 6654 <name>SQW_SEL</name> 6655 <description>Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin.</description> 6656 <bitOffset>9</bitOffset> 6657 <bitWidth>2</bitWidth> 6658 <enumeratedValues> 6659 <enumeratedValue> 6660 <name>freq1Hz</name> 6661 <description>1 Hz (Compensated).</description> 6662 <value>0</value> 6663 </enumeratedValue> 6664 <enumeratedValue> 6665 <name>freq512Hz</name> 6666 <description>512 Hz (Compensated).</description> 6667 <value>1</value> 6668 </enumeratedValue> 6669 <enumeratedValue> 6670 <name>freq4KHz</name> 6671 <description>4 KHz.</description> 6672 <value>2</value> 6673 </enumeratedValue> 6674 <enumeratedValue> 6675 <name>clkDiv8</name> 6676 <description>RTC Input Clock / 8.</description> 6677 <value>3</value> 6678 </enumeratedValue> 6679 </enumeratedValues> 6680 </field> 6681 <field> 6682 <name>RD_EN</name> 6683 <description>Asynchronous Counter Read Enable.</description> 6684 <bitOffset>14</bitOffset> 6685 <bitWidth>1</bitWidth> 6686 </field> 6687 <field> 6688 <name>WR_EN</name> 6689 <description>Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits.</description> 6690 <bitOffset>15</bitOffset> 6691 <bitWidth>1</bitWidth> 6692 <enumeratedValues> 6693 <enumeratedValue> 6694 <name>inactive</name> 6695 <description>Not active</description> 6696 <value>0</value> 6697 </enumeratedValue> 6698 <enumeratedValue> 6699 <name>Pending</name> 6700 <description>Active</description> 6701 <value>1</value> 6702 </enumeratedValue> 6703 </enumeratedValues> 6704 </field> 6705 </fields> 6706 </register> 6707 <register> 6708 <name>TRIM</name> 6709 <description>RTC Trim Register.</description> 6710 <addressOffset>0x14</addressOffset> 6711 <resetMask>0x00000000</resetMask> 6712 <fields> 6713 <field> 6714 <name>TRIM</name> 6715 <description>RTC Trim. This register contains the 2's complement value that specifies the trim resolution. Each increment or decrement of the bit adds or subtracts 1ppm at each 4KHz clock value, with a maximum correction of +/- 127ppm.</description> 6716 <bitOffset>0</bitOffset> 6717 <bitWidth>8</bitWidth> 6718 </field> 6719 <field> 6720 <name>VRTC_TMR</name> 6721 <description>VBAT Timer Value. When RTC is running off of VBAT, this field is incremented every 32 seconds.</description> 6722 <bitOffset>8</bitOffset> 6723 <bitWidth>24</bitWidth> 6724 </field> 6725 </fields> 6726 </register> 6727 <register> 6728 <name>OSCCTRL</name> 6729 <description>RTC Oscillator Control Register.</description> 6730 <addressOffset>0x18</addressOffset> 6731 <resetMask>0x00000000</resetMask> 6732 <fields> 6733 <field> 6734 <name>FILTER_EN</name> 6735 <description>Enables analog deglitch filter.</description> 6736 <bitOffset>0</bitOffset> 6737 <bitWidth>1</bitWidth> 6738 </field> 6739 <field> 6740 <name>IBIAS_SEL</name> 6741 <description>If IBIAS_EN is 1, selects 4x,2x mode.</description> 6742 <bitOffset>1</bitOffset> 6743 <bitWidth>1</bitWidth> 6744 </field> 6745 <field> 6746 <name>HYST_EN</name> 6747 <description>Enables high current hysteresis buffer.</description> 6748 <bitOffset>2</bitOffset> 6749 <bitWidth>1</bitWidth> 6750 </field> 6751 <field> 6752 <name>IBIAS_EN</name> 6753 <description>Enables higher 4x,2x current modes.</description> 6754 <bitOffset>3</bitOffset> 6755 <bitWidth>1</bitWidth> 6756 </field> 6757 <field> 6758 <name>BYPASS</name> 6759 <description>RTC Crystal Bypass</description> 6760 <bitOffset>4</bitOffset> 6761 <bitWidth>1</bitWidth> 6762 </field> 6763 <field> 6764 <name>SQW_32K</name> 6765 <description>RTC 32kHz Square Wave Output</description> 6766 <bitOffset>5</bitOffset> 6767 <bitWidth>1</bitWidth> 6768 </field> 6769 </fields> 6770 </register> 6771 </registers> 6772 </peripheral> 6773<!--RTC Real Time Clock and Alarm.--> 6774 <peripheral> 6775 <name>SIR</name> 6776 <description>System Initialization Registers.</description> 6777 <baseAddress>0x40000400</baseAddress> 6778 <access>read-only</access> 6779 <addressBlock> 6780 <offset>0x00</offset> 6781 <size>0x400</size> 6782 <usage>registers</usage> 6783 </addressBlock> 6784 <registers> 6785 <register> 6786 <name>SIR_STATUS</name> 6787 <description>System Initialization Status Register.</description> 6788 <addressOffset>0x00</addressOffset> 6789 <access>read-only</access> 6790 <fields> 6791 <field> 6792 <name>CFG_VALID</name> 6793 <description>Configuration Valid Flag.</description> 6794 <bitOffset>0</bitOffset> 6795 <bitWidth>1</bitWidth> 6796 <access>read-only</access> 6797 </field> 6798 <field> 6799 <name>CFG_ERR</name> 6800 <description>Configuration Error Flag.</description> 6801 <bitOffset>1</bitOffset> 6802 <bitWidth>1</bitWidth> 6803 <access>read-only</access> 6804 </field> 6805 </fields> 6806 </register> 6807 <register> 6808 <name>SIR_ADDR</name> 6809 <description>Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1).</description> 6810 <addressOffset>0x04</addressOffset> 6811 <access>read-only</access> 6812 <fields> 6813 <field> 6814 <name>ADDR</name> 6815 <bitOffset>0</bitOffset> 6816 <bitWidth>32</bitWidth> 6817 </field> 6818 </fields> 6819 </register> 6820 </registers> 6821 </peripheral> 6822<!--SIR System Initialization Registers.--> 6823 <peripheral> 6824 <name>SPI0</name> 6825 <description>SPI peripheral.</description> 6826 <baseAddress>0x40046000</baseAddress> 6827 <addressBlock> 6828 <offset>0x00</offset> 6829 <size>0x1000</size> 6830 <usage>registers</usage> 6831 </addressBlock> 6832 <interrupt> 6833 <name>SPI0</name> 6834 <value>16</value> 6835 </interrupt> 6836 <registers> 6837 <register> 6838 <name>FIFO32</name> 6839 <description>Register for reading and writing the FIFO.</description> 6840 <addressOffset>0x00</addressOffset> 6841 <size>32</size> 6842 <access>read-write</access> 6843 <fields> 6844 <field> 6845 <name>DATA</name> 6846 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 6847 <bitOffset>0</bitOffset> 6848 <bitWidth>32</bitWidth> 6849 </field> 6850 </fields> 6851 </register> 6852 <register> 6853 <dim>2</dim> 6854 <dimIncrement>2</dimIncrement> 6855 <name>FIFO16[%s]</name> 6856 <description>Register for reading and writing the FIFO.</description> 6857 <addressOffset>0x00</addressOffset> 6858 <size>16</size> 6859 <access>read-write</access> 6860 <fields> 6861 <field> 6862 <name>DATA</name> 6863 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 6864 <bitOffset>0</bitOffset> 6865 <bitWidth>16</bitWidth> 6866 </field> 6867 </fields> 6868 </register> 6869 <register> 6870 <dim>4</dim> 6871 <dimIncrement>1</dimIncrement> 6872 <name>FIFO8[%s]</name> 6873 <description>Register for reading and writing the FIFO.</description> 6874 <addressOffset>0x00</addressOffset> 6875 <size>8</size> 6876 <access>read-write</access> 6877 <fields> 6878 <field> 6879 <name>DATA</name> 6880 <description>Read to pull from RX FIFO, write to put into TX FIFO.</description> 6881 <bitOffset>0</bitOffset> 6882 <bitWidth>8</bitWidth> 6883 </field> 6884 </fields> 6885 </register> 6886 <register> 6887 <name>CTRL0</name> 6888 <description>Register for controlling SPI peripheral.</description> 6889 <addressOffset>0x04</addressOffset> 6890 <access>read-write</access> 6891 <fields> 6892 <field> 6893 <name>EN</name> 6894 <description>SPI Enable.</description> 6895 <bitOffset>0</bitOffset> 6896 <bitWidth>1</bitWidth> 6897 <enumeratedValues> 6898 <enumeratedValue> 6899 <name>dis</name> 6900 <description>SPI is disabled.</description> 6901 <value>0</value> 6902 </enumeratedValue> 6903 <enumeratedValue> 6904 <name>en</name> 6905 <description>SPI is enabled.</description> 6906 <value>1</value> 6907 </enumeratedValue> 6908 </enumeratedValues> 6909 </field> 6910 <field> 6911 <name>MST_MODE</name> 6912 <description>Master Mode Enable.</description> 6913 <bitOffset>1</bitOffset> 6914 <bitWidth>1</bitWidth> 6915 <enumeratedValues> 6916 <enumeratedValue> 6917 <name>dis</name> 6918 <description>SPI is Slave mode.</description> 6919 <value>0</value> 6920 </enumeratedValue> 6921 <enumeratedValue> 6922 <name>en</name> 6923 <description>SPI is Master mode.</description> 6924 <value>1</value> 6925 </enumeratedValue> 6926 </enumeratedValues> 6927 </field> 6928 <field> 6929 <name>SS_IO</name> 6930 <description>Slave Select 0, IO direction, to support Multi-Master mode,Slave Select 0 can be input in Master mode. This bit has no effect in slave mode.</description> 6931 <bitOffset>4</bitOffset> 6932 <bitWidth>1</bitWidth> 6933 <enumeratedValues> 6934 <enumeratedValue> 6935 <name>output</name> 6936 <description>Slave select 0 is output.</description> 6937 <value>0</value> 6938 </enumeratedValue> 6939 <enumeratedValue> 6940 <name>input</name> 6941 <description>Slave Select 0 is input, only valid if MMEN=1.</description> 6942 <value>1</value> 6943 </enumeratedValue> 6944 </enumeratedValues> 6945 </field> 6946 <field> 6947 <name>START</name> 6948 <description>Start Transmit.</description> 6949 <bitOffset>5</bitOffset> 6950 <bitWidth>1</bitWidth> 6951 <enumeratedValues> 6952 <enumeratedValue> 6953 <name>start</name> 6954 <description>Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction.</description> 6955 <value>1</value> 6956 </enumeratedValue> 6957 </enumeratedValues> 6958 </field> 6959 <field> 6960 <name>SS_CTRL</name> 6961 <description>Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction.</description> 6962 <bitOffset>8</bitOffset> 6963 <bitWidth>1</bitWidth> 6964 <enumeratedValues> 6965 <enumeratedValue> 6966 <name>DEASSERT</name> 6967 <description>SPI De-asserts Slave Select at the end of a transaction.</description> 6968 <value>0</value> 6969 </enumeratedValue> 6970 <enumeratedValue> 6971 <name>ASSERT</name> 6972 <description>SPI leaves Slave Select asserted at the end of a transaction.</description> 6973 <value>1</value> 6974 </enumeratedValue> 6975 </enumeratedValues> 6976 </field> 6977 <field> 6978 <name>SS_ACTIVE</name> 6979 <description>Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected.</description> 6980 <bitOffset>16</bitOffset> 6981 <bitWidth>4</bitWidth> 6982 <enumeratedValues> 6983 <enumeratedValue> 6984 <name>SS0</name> 6985 <description>SS0 is selected.</description> 6986 <value>0x1</value> 6987 </enumeratedValue> 6988 <enumeratedValue> 6989 <name>SS1</name> 6990 <description>SS1 is selected.</description> 6991 <value>0x2</value> 6992 </enumeratedValue> 6993 <enumeratedValue> 6994 <name>SS2</name> 6995 <description>SS2 is selected.</description> 6996 <value>0x4</value> 6997 </enumeratedValue> 6998 <enumeratedValue> 6999 <name>SS3</name> 7000 <description>SS3 is selected.</description> 7001 <value>0x8</value> 7002 </enumeratedValue> 7003 </enumeratedValues> 7004 </field> 7005 </fields> 7006 </register> 7007 <register> 7008 <name>CTRL1</name> 7009 <description>Register for controlling SPI peripheral.</description> 7010 <addressOffset>0x08</addressOffset> 7011 <access>read-write</access> 7012 <fields> 7013 <field> 7014 <name>TX_NUM_CHAR</name> 7015 <description>Nubmer of Characters to transmit.</description> 7016 <bitOffset>0</bitOffset> 7017 <bitWidth>16</bitWidth> 7018 </field> 7019 <field> 7020 <name>RX_NUM_CHAR</name> 7021 <description>Nubmer of Characters to receive.</description> 7022 <bitOffset>16</bitOffset> 7023 <bitWidth>16</bitWidth> 7024 </field> 7025 </fields> 7026 </register> 7027 <register> 7028 <name>CTRL2</name> 7029 <description>Register for controlling SPI peripheral.</description> 7030 <addressOffset>0x0C</addressOffset> 7031 <access>read-write</access> 7032 <fields> 7033 <field> 7034 <name>CLKPHA</name> 7035 <description>Clock Phase.</description> 7036 <bitOffset>0</bitOffset> 7037 <bitWidth>1</bitWidth> 7038 <enumeratedValues> 7039 <enumeratedValue> 7040 <name>Rising_Edge</name> 7041 <description>Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2 </description> 7042 <value>0</value> 7043 </enumeratedValue> 7044 <enumeratedValue> 7045 <name>Falling_Edge</name> 7046 <description>Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3</description> 7047 <value>1</value> 7048 </enumeratedValue> 7049 </enumeratedValues> 7050 </field> 7051 <field> 7052 <name>CLKPOL</name> 7053 <description>Clock Polarity.</description> 7054 <bitOffset>1</bitOffset> 7055 <bitWidth>1</bitWidth> 7056 <enumeratedValues> 7057 <enumeratedValue> 7058 <name>Normal</name> 7059 <description>Normal Clock. Use when in SPI Mode 0 and Mode 1</description> 7060 <value>0</value> 7061 </enumeratedValue> 7062 <enumeratedValue> 7063 <name>Inverted</name> 7064 <description>Inverted Clock. Use when in SPI Mode 2 and Mode 3</description> 7065 <value>1</value> 7066 </enumeratedValue> 7067 </enumeratedValues> 7068 </field> 7069 <field> 7070 <name>NUMBITS</name> 7071 <description>Number of Bits per character.</description> 7072 <bitOffset>8</bitOffset> 7073 <bitWidth>4</bitWidth> 7074 <enumeratedValues> 7075 <enumeratedValue> 7076 <name>0</name> 7077 <description>16 bits per character.</description> 7078 <value>0</value> 7079 </enumeratedValue> 7080 </enumeratedValues> 7081 </field> 7082 <field> 7083 <name>DATA_WIDTH</name> 7084 <description>SPI Data width.</description> 7085 <bitOffset>12</bitOffset> 7086 <bitWidth>2</bitWidth> 7087 <enumeratedValues> 7088 <enumeratedValue> 7089 <name>Mono</name> 7090 <description>1 data pin.</description> 7091 <value>0</value> 7092 </enumeratedValue> 7093 <enumeratedValue> 7094 <name>Dual</name> 7095 <description>2 data pins.</description> 7096 <value>1</value> 7097 </enumeratedValue> 7098 <enumeratedValue> 7099 <name>Quad</name> 7100 <description>4 data pins.</description> 7101 <value>2</value> 7102 </enumeratedValue> 7103 </enumeratedValues> 7104 </field> 7105 <field> 7106 <name>THREE_WIRE</name> 7107 <description>Three Wire mode. MOSI/MISO pin (s) shared. Only Mono mode suports Four-Wire.</description> 7108 <bitOffset>15</bitOffset> 7109 <bitWidth>1</bitWidth> 7110 <enumeratedValues> 7111 <enumeratedValue> 7112 <name>dis</name> 7113 <description>Use four wire mode (Mono only).</description> 7114 <value>0</value> 7115 </enumeratedValue> 7116 <enumeratedValue> 7117 <name>en</name> 7118 <description>Use three wire mode.</description> 7119 <value>1</value> 7120 </enumeratedValue> 7121 </enumeratedValues> 7122 </field> 7123 <field> 7124 <name>SS_POL</name> 7125 <description>Slave Select Polarity, each Slave Select can have unique polarity.</description> 7126 <bitOffset>16</bitOffset> 7127 <bitWidth>8</bitWidth> 7128 <enumeratedValues> 7129 <enumeratedValue> 7130 <name>SS0_high</name> 7131 <description>SS0 active high.</description> 7132 <value>0x1</value> 7133 </enumeratedValue> 7134 <enumeratedValue> 7135 <name>SS1_high</name> 7136 <description>SS1 active high.</description> 7137 <value>0x2</value> 7138 </enumeratedValue> 7139 <enumeratedValue> 7140 <name>SS2_high</name> 7141 <description>SS2 active high.</description> 7142 <value>0x4</value> 7143 </enumeratedValue> 7144 <enumeratedValue> 7145 <name>SS3_high</name> 7146 <description>SS3 active high.</description> 7147 <value>0x8</value> 7148 </enumeratedValue> 7149 </enumeratedValues> 7150 </field> 7151 </fields> 7152 </register> 7153 <register> 7154 <name>SSTIME</name> 7155 <description>Register for controlling SPI peripheral/Slave Select Timing.</description> 7156 <addressOffset>0x10</addressOffset> 7157 <access>read-write</access> 7158 <fields> 7159 <field> 7160 <name>PRE</name> 7161 <description>Slave Select Pre delay 1.</description> 7162 <bitOffset>0</bitOffset> 7163 <bitWidth>8</bitWidth> 7164 <enumeratedValues> 7165 <enumeratedValue> 7166 <name>256</name> 7167 <description>256 system clocks between SS active and first serial clock edge.</description> 7168 <value>0</value> 7169 </enumeratedValue> 7170 </enumeratedValues> 7171 </field> 7172 <field> 7173 <name>POST</name> 7174 <description>Slave Select Post delay 2.</description> 7175 <bitOffset>8</bitOffset> 7176 <bitWidth>8</bitWidth> 7177 <enumeratedValues> 7178 <enumeratedValue> 7179 <name>256</name> 7180 <description>256 system clocks between last serial clock edge and SS inactive.</description> 7181 <value>0</value> 7182 </enumeratedValue> 7183 </enumeratedValues> 7184 </field> 7185 <field> 7186 <name>INACT</name> 7187 <description>Slave Select Inactive delay.</description> 7188 <bitOffset>16</bitOffset> 7189 <bitWidth>8</bitWidth> 7190 <enumeratedValues> 7191 <enumeratedValue> 7192 <name>256</name> 7193 <description>256 system clocks between transactions.</description> 7194 <value>0</value> 7195 </enumeratedValue> 7196 </enumeratedValues> 7197 </field> 7198 </fields> 7199 </register> 7200 <register> 7201 <name>CLKCTRL</name> 7202 <description>Register for controlling SPI clock rate.</description> 7203 <addressOffset>0x14</addressOffset> 7204 <access>read-write</access> 7205 <fields> 7206 <field> 7207 <name>LO</name> 7208 <description>Low duty cycle control. In timer mode, reload[7:0].</description> 7209 <bitOffset>0</bitOffset> 7210 <bitWidth>8</bitWidth> 7211 <enumeratedValues> 7212 <enumeratedValue> 7213 <name>Dis</name> 7214 <description>Duty cycle control of serial clock generation is disabled.</description> 7215 <value>0</value> 7216 </enumeratedValue> 7217 </enumeratedValues> 7218 </field> 7219 <field> 7220 <name>HI</name> 7221 <description>High duty cycle control. In timer mode, reload[15:8].</description> 7222 <bitOffset>8</bitOffset> 7223 <bitWidth>8</bitWidth> 7224 <enumeratedValues> 7225 <enumeratedValue> 7226 <name>Dis</name> 7227 <description>Duty cycle control of serial clock generation is disabled.</description> 7228 <value>0</value> 7229 </enumeratedValue> 7230 </enumeratedValues> 7231 </field> 7232 <field> 7233 <name>CLKDIV</name> 7234 <description>System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock.</description> 7235 <bitOffset>16</bitOffset> 7236 <bitWidth>4</bitWidth> 7237 </field> 7238 </fields> 7239 </register> 7240 <register> 7241 <name>DMA</name> 7242 <description>Register for controlling DMA.</description> 7243 <addressOffset>0x1C</addressOffset> 7244 <access>read-write</access> 7245 <fields> 7246 <field> 7247 <name>TX_THD_VAL</name> 7248 <description>Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered.</description> 7249 <bitOffset>0</bitOffset> 7250 <bitWidth>5</bitWidth> 7251 </field> 7252 <field> 7253 <name>TX_FIFO_EN</name> 7254 <description>Transmit FIFO enabled for SPI transactions.</description> 7255 <bitOffset>6</bitOffset> 7256 <bitWidth>1</bitWidth> 7257 <enumeratedValues> 7258 <enumeratedValue> 7259 <name>dis</name> 7260 <description>Transmit FIFO is not enabled.</description> 7261 <value>0</value> 7262 </enumeratedValue> 7263 <enumeratedValue> 7264 <name>en</name> 7265 <description>Transmit FIFO is enabled.</description> 7266 <value>1</value> 7267 </enumeratedValue> 7268 </enumeratedValues> 7269 </field> 7270 <field> 7271 <name>TX_FLUSH</name> 7272 <description>Clear TX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side.</description> 7273 <bitOffset>7</bitOffset> 7274 <bitWidth>1</bitWidth> 7275 <enumeratedValues> 7276 <enumeratedValue> 7277 <name>CLEAR</name> 7278 <description>Clear the Transmit FIFO, clears any pending TX FIFO status.</description> 7279 <value>1</value> 7280 </enumeratedValue> 7281 </enumeratedValues> 7282 </field> 7283 <field> 7284 <name>TX_LVL</name> 7285 <description>Count of entries in TX FIFO.</description> 7286 <bitOffset>8</bitOffset> 7287 <bitWidth>6</bitWidth> 7288 <access>read-only</access> 7289 </field> 7290 <field> 7291 <name>DMA_TX_EN</name> 7292 <description>TX DMA Enable.</description> 7293 <bitOffset>15</bitOffset> 7294 <bitWidth>1</bitWidth> 7295 <enumeratedValues> 7296 <enumeratedValue> 7297 <name>DIS</name> 7298 <description>TX DMA requests are disabled, andy pending DMA requests are cleared.</description> 7299 <value>0</value> 7300 </enumeratedValue> 7301 <enumeratedValue> 7302 <name>en</name> 7303 <description>TX DMA requests are enabled.</description> 7304 <value>1</value> 7305 </enumeratedValue> 7306 </enumeratedValues> 7307 </field> 7308 <field> 7309 <name>RX_THD_VAL</name> 7310 <description>Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered.</description> 7311 <bitOffset>16</bitOffset> 7312 <bitWidth>5</bitWidth> 7313 </field> 7314 <field> 7315 <name>RX_FIFO_EN</name> 7316 <description>Receive FIFO enabled for SPI transactions.</description> 7317 <bitOffset>22</bitOffset> 7318 <bitWidth>1</bitWidth> 7319 <enumeratedValues> 7320 <enumeratedValue> 7321 <name>DIS</name> 7322 <description>Receive FIFO is not enabled.</description> 7323 <value>0</value> 7324 </enumeratedValue> 7325 <enumeratedValue> 7326 <name>en</name> 7327 <description>Receive FIFO is enabled.</description> 7328 <value>1</value> 7329 </enumeratedValue> 7330 </enumeratedValues> 7331 </field> 7332 <field> 7333 <name>RX_FLUSH</name> 7334 <description>Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side.</description> 7335 <bitOffset>23</bitOffset> 7336 <bitWidth>1</bitWidth> 7337 <enumeratedValues> 7338 <enumeratedValue> 7339 <name>CLEAR</name> 7340 <description>Clear the Receive FIFO, clears any pending RX FIFO status.</description> 7341 <value>1</value> 7342 </enumeratedValue> 7343 </enumeratedValues> 7344 </field> 7345 <field> 7346 <name>RX_LVL</name> 7347 <description>Count of entries in RX FIFO.</description> 7348 <bitOffset>24</bitOffset> 7349 <bitWidth>6</bitWidth> 7350 <access>read-only</access> 7351 </field> 7352 <field> 7353 <name>DMA_RX_EN</name> 7354 <description>RX DMA Enable.</description> 7355 <bitOffset>31</bitOffset> 7356 <bitWidth>1</bitWidth> 7357 <enumeratedValues> 7358 <enumeratedValue> 7359 <name>dis</name> 7360 <description>RX DMA requests are disabled, any pending DMA requests are cleared.</description> 7361 <value>0</value> 7362 </enumeratedValue> 7363 <enumeratedValue> 7364 <name>en</name> 7365 <description>RX DMA requests are enabled.</description> 7366 <value>1</value> 7367 </enumeratedValue> 7368 </enumeratedValues> 7369 </field> 7370 </fields> 7371 </register> 7372 <register> 7373 <name>INTFL</name> 7374 <description>Register for reading and clearing interrupt flags. All bits are write 1 to clear.</description> 7375 <addressOffset>0x20</addressOffset> 7376 <access>read-write</access> 7377 <fields> 7378 <field> 7379 <name>TX_THD</name> 7380 <description>TX FIFO Threshold Crossed.</description> 7381 <bitOffset>0</bitOffset> 7382 <bitWidth>1</bitWidth> 7383 <enumeratedValues> 7384 <enumeratedValue> 7385 <name>clear</name> 7386 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 7387 <value>1</value> 7388 </enumeratedValue> 7389 </enumeratedValues> 7390 </field> 7391 <field> 7392 <name>TX_EM</name> 7393 <description>TX FIFO Empty.</description> 7394 <bitOffset>1</bitOffset> 7395 <bitWidth>1</bitWidth> 7396 <enumeratedValues> 7397 <enumeratedValue> 7398 <name>clear</name> 7399 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 7400 <value>1</value> 7401 </enumeratedValue> 7402 </enumeratedValues> 7403 </field> 7404 <field> 7405 <name>RX_THD</name> 7406 <description>RX FIFO Threshold Crossed.</description> 7407 <bitOffset>2</bitOffset> 7408 <bitWidth>1</bitWidth> 7409 <enumeratedValues> 7410 <enumeratedValue> 7411 <name>clear</name> 7412 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 7413 <value>1</value> 7414 </enumeratedValue> 7415 </enumeratedValues> 7416 </field> 7417 <field> 7418 <name>RX_FULL</name> 7419 <description>RX FIFO FULL.</description> 7420 <bitOffset>3</bitOffset> 7421 <bitWidth>1</bitWidth> 7422 <enumeratedValues> 7423 <enumeratedValue> 7424 <name>clear</name> 7425 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 7426 <value>1</value> 7427 </enumeratedValue> 7428 </enumeratedValues> 7429 </field> 7430 <field> 7431 <name>SSA</name> 7432 <description>Slave Select Asserted.</description> 7433 <bitOffset>4</bitOffset> 7434 <bitWidth>1</bitWidth> 7435 <enumeratedValues> 7436 <enumeratedValue> 7437 <name>clear</name> 7438 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 7439 <value>1</value> 7440 </enumeratedValue> 7441 </enumeratedValues> 7442 </field> 7443 <field> 7444 <name>SSD</name> 7445 <description>Slave Select Deasserted.</description> 7446 <bitOffset>5</bitOffset> 7447 <bitWidth>1</bitWidth> 7448 <enumeratedValues> 7449 <enumeratedValue> 7450 <name>clear</name> 7451 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 7452 <value>1</value> 7453 </enumeratedValue> 7454 </enumeratedValues> 7455 </field> 7456 <field> 7457 <name>FAULT</name> 7458 <description>Multi-Master Mode Fault.</description> 7459 <bitOffset>8</bitOffset> 7460 <bitWidth>1</bitWidth> 7461 <enumeratedValues> 7462 <enumeratedValue> 7463 <name>clear</name> 7464 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 7465 <value>1</value> 7466 </enumeratedValue> 7467 </enumeratedValues> 7468 </field> 7469 <field> 7470 <name>ABORT</name> 7471 <description>Slave Abort Detected.</description> 7472 <bitOffset>9</bitOffset> 7473 <bitWidth>1</bitWidth> 7474 <enumeratedValues> 7475 <enumeratedValue> 7476 <name>clear</name> 7477 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 7478 <value>1</value> 7479 </enumeratedValue> 7480 </enumeratedValues> 7481 </field> 7482 <field> 7483 <name>MST_DONE</name> 7484 <description>Master Done, set when SPI Master has completed any transactions.</description> 7485 <bitOffset>11</bitOffset> 7486 <bitWidth>1</bitWidth> 7487 <enumeratedValues> 7488 <enumeratedValue> 7489 <name>clear</name> 7490 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 7491 <value>1</value> 7492 </enumeratedValue> 7493 </enumeratedValues> 7494 </field> 7495 <field> 7496 <name>TX_OV</name> 7497 <description>Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO.</description> 7498 <bitOffset>12</bitOffset> 7499 <bitWidth>1</bitWidth> 7500 <enumeratedValues> 7501 <enumeratedValue> 7502 <name>clear</name> 7503 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 7504 <value>1</value> 7505 </enumeratedValue> 7506 </enumeratedValues> 7507 </field> 7508 <field> 7509 <name>TX_UN</name> 7510 <description>Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO.</description> 7511 <bitOffset>13</bitOffset> 7512 <bitWidth>1</bitWidth> 7513 <enumeratedValues> 7514 <enumeratedValue> 7515 <name>clear</name> 7516 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 7517 <value>1</value> 7518 </enumeratedValue> 7519 </enumeratedValues> 7520 </field> 7521 <field> 7522 <name>RX_OV</name> 7523 <description>Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO.</description> 7524 <bitOffset>14</bitOffset> 7525 <bitWidth>1</bitWidth> 7526 <enumeratedValues> 7527 <enumeratedValue> 7528 <name>clear</name> 7529 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 7530 <value>1</value> 7531 </enumeratedValue> 7532 </enumeratedValues> 7533 </field> 7534 <field> 7535 <name>RX_UN</name> 7536 <description>Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO.</description> 7537 <bitOffset>15</bitOffset> 7538 <bitWidth>1</bitWidth> 7539 <enumeratedValues> 7540 <enumeratedValue> 7541 <name>clear</name> 7542 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 7543 <value>1</value> 7544 </enumeratedValue> 7545 </enumeratedValues> 7546 </field> 7547 </fields> 7548 </register> 7549 <register> 7550 <name>INTEN</name> 7551 <description>Register for enabling interrupts.</description> 7552 <addressOffset>0x24</addressOffset> 7553 <access>read-write</access> 7554 <fields> 7555 <field> 7556 <name>TX_THD</name> 7557 <description>TX FIFO Threshold interrupt enable.</description> 7558 <bitOffset>0</bitOffset> 7559 <bitWidth>1</bitWidth> 7560 <enumeratedValues> 7561 <enumeratedValue> 7562 <name>dis</name> 7563 <description>Interrupt is disabled.</description> 7564 <value>0</value> 7565 </enumeratedValue> 7566 <enumeratedValue> 7567 <name>en</name> 7568 <description>Interrupt is enabled.</description> 7569 <value>1</value> 7570 </enumeratedValue> 7571 </enumeratedValues> 7572 </field> 7573 <field> 7574 <name>TX_EM</name> 7575 <description>TX FIFO Empty interrupt enable.</description> 7576 <bitOffset>1</bitOffset> 7577 <bitWidth>1</bitWidth> 7578 <enumeratedValues> 7579 <enumeratedValue> 7580 <name>dis</name> 7581 <description>Interrupt is disabled.</description> 7582 <value>0</value> 7583 </enumeratedValue> 7584 <enumeratedValue> 7585 <name>en</name> 7586 <description>Interrupt is enabled.</description> 7587 <value>1</value> 7588 </enumeratedValue> 7589 </enumeratedValues> 7590 </field> 7591 <field> 7592 <name>RX_THD</name> 7593 <description>RX FIFO Threshold Crossed interrupt enable.</description> 7594 <bitOffset>2</bitOffset> 7595 <bitWidth>1</bitWidth> 7596 <enumeratedValues> 7597 <enumeratedValue> 7598 <name>dis</name> 7599 <description>Interrupt is disabled.</description> 7600 <value>0</value> 7601 </enumeratedValue> 7602 <enumeratedValue> 7603 <name>en</name> 7604 <description>Interrupt is enabled.</description> 7605 <value>1</value> 7606 </enumeratedValue> 7607 </enumeratedValues> 7608 </field> 7609 <field> 7610 <name>RX_FULL</name> 7611 <description>RX FIFO FULL interrupt enable.</description> 7612 <bitOffset>3</bitOffset> 7613 <bitWidth>1</bitWidth> 7614 <enumeratedValues> 7615 <enumeratedValue> 7616 <name>dis</name> 7617 <description>Interrupt is disabled.</description> 7618 <value>0</value> 7619 </enumeratedValue> 7620 <enumeratedValue> 7621 <name>en</name> 7622 <description>Interrupt is enabled.</description> 7623 <value>1</value> 7624 </enumeratedValue> 7625 </enumeratedValues> 7626 </field> 7627 <field> 7628 <name>SSA</name> 7629 <description>Slave Select Asserted interrupt enable.</description> 7630 <bitOffset>4</bitOffset> 7631 <bitWidth>1</bitWidth> 7632 <enumeratedValues> 7633 <enumeratedValue> 7634 <name>dis</name> 7635 <description>Interrupt is disabled.</description> 7636 <value>0</value> 7637 </enumeratedValue> 7638 <enumeratedValue> 7639 <name>en</name> 7640 <description>Interrupt is enabled.</description> 7641 <value>1</value> 7642 </enumeratedValue> 7643 </enumeratedValues> 7644 </field> 7645 <field> 7646 <name>SSD</name> 7647 <description>Slave Select Deasserted interrupt enable.</description> 7648 <bitOffset>5</bitOffset> 7649 <bitWidth>1</bitWidth> 7650 <enumeratedValues> 7651 <enumeratedValue> 7652 <name>dis</name> 7653 <description>Interrupt is disabled.</description> 7654 <value>0</value> 7655 </enumeratedValue> 7656 <enumeratedValue> 7657 <name>en</name> 7658 <description>Interrupt is enabled.</description> 7659 <value>1</value> 7660 </enumeratedValue> 7661 </enumeratedValues> 7662 </field> 7663 <field> 7664 <name>FAULT</name> 7665 <description>Multi-Master Mode Fault interrupt enable.</description> 7666 <bitOffset>8</bitOffset> 7667 <bitWidth>1</bitWidth> 7668 <enumeratedValues> 7669 <enumeratedValue> 7670 <name>dis</name> 7671 <description>Interrupt is disabled.</description> 7672 <value>0</value> 7673 </enumeratedValue> 7674 <enumeratedValue> 7675 <name>en</name> 7676 <description>Interrupt is enabled.</description> 7677 <value>1</value> 7678 </enumeratedValue> 7679 </enumeratedValues> 7680 </field> 7681 <field> 7682 <name>ABORT</name> 7683 <description>Slave Abort Detected interrupt enable.</description> 7684 <bitOffset>9</bitOffset> 7685 <bitWidth>1</bitWidth> 7686 <enumeratedValues> 7687 <enumeratedValue> 7688 <name>dis</name> 7689 <description>Interrupt is disabled.</description> 7690 <value>0</value> 7691 </enumeratedValue> 7692 <enumeratedValue> 7693 <name>en</name> 7694 <description>Interrupt is enabled.</description> 7695 <value>1</value> 7696 </enumeratedValue> 7697 </enumeratedValues> 7698 </field> 7699 <field> 7700 <name>MST_DONE</name> 7701 <description>Master Done interrupt enable.</description> 7702 <bitOffset>11</bitOffset> 7703 <bitWidth>1</bitWidth> 7704 <enumeratedValues> 7705 <enumeratedValue> 7706 <name>dis</name> 7707 <description>Interrupt is disabled.</description> 7708 <value>0</value> 7709 </enumeratedValue> 7710 <enumeratedValue> 7711 <name>en</name> 7712 <description>Interrupt is enabled.</description> 7713 <value>1</value> 7714 </enumeratedValue> 7715 </enumeratedValues> 7716 </field> 7717 <field> 7718 <name>TX_OV</name> 7719 <description>Transmit FIFO Overrun interrupt enable.</description> 7720 <bitOffset>12</bitOffset> 7721 <bitWidth>1</bitWidth> 7722 <enumeratedValues> 7723 <enumeratedValue> 7724 <name>dis</name> 7725 <description>Interrupt is disabled.</description> 7726 <value>0</value> 7727 </enumeratedValue> 7728 <enumeratedValue> 7729 <name>en</name> 7730 <description>Interrupt is enabled.</description> 7731 <value>1</value> 7732 </enumeratedValue> 7733 </enumeratedValues> 7734 </field> 7735 <field> 7736 <name>TX_UN</name> 7737 <description>Transmit FIFO Underrun interrupt enable.</description> 7738 <bitOffset>13</bitOffset> 7739 <bitWidth>1</bitWidth> 7740 <enumeratedValues> 7741 <enumeratedValue> 7742 <name>dis</name> 7743 <description>Interrupt is disabled.</description> 7744 <value>0</value> 7745 </enumeratedValue> 7746 <enumeratedValue> 7747 <name>en</name> 7748 <description>Interrupt is enabled.</description> 7749 <value>1</value> 7750 </enumeratedValue> 7751 </enumeratedValues> 7752 </field> 7753 <field> 7754 <name>RX_OV</name> 7755 <description>Receive FIFO Overrun interrupt enable.</description> 7756 <bitOffset>14</bitOffset> 7757 <bitWidth>1</bitWidth> 7758 <enumeratedValues> 7759 <enumeratedValue> 7760 <name>dis</name> 7761 <description>Interrupt is disabled.</description> 7762 <value>0</value> 7763 </enumeratedValue> 7764 <enumeratedValue> 7765 <name>en</name> 7766 <description>Interrupt is enabled.</description> 7767 <value>1</value> 7768 </enumeratedValue> 7769 </enumeratedValues> 7770 </field> 7771 <field> 7772 <name>RX_UN</name> 7773 <description>Receive FIFO Underrun interrupt enable.</description> 7774 <bitOffset>15</bitOffset> 7775 <bitWidth>1</bitWidth> 7776 <enumeratedValues> 7777 <enumeratedValue> 7778 <name>dis</name> 7779 <description>Interrupt is disabled.</description> 7780 <value>0</value> 7781 </enumeratedValue> 7782 <enumeratedValue> 7783 <name>en</name> 7784 <description>Interrupt is enabled.</description> 7785 <value>1</value> 7786 </enumeratedValue> 7787 </enumeratedValues> 7788 </field> 7789 </fields> 7790 </register> 7791 <register> 7792 <name>WKFL</name> 7793 <description>Register for wake up flags. All bits in this register are write 1 to clear.</description> 7794 <addressOffset>0x28</addressOffset> 7795 <access>read-write</access> 7796 <fields> 7797 <field> 7798 <name>TX_THD</name> 7799 <description>Wake on TX FIFO Threshold Crossed.</description> 7800 <bitOffset>0</bitOffset> 7801 <bitWidth>1</bitWidth> 7802 <enumeratedValues> 7803 <enumeratedValue> 7804 <name>clear</name> 7805 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 7806 <value>1</value> 7807 </enumeratedValue> 7808 </enumeratedValues> 7809 </field> 7810 <field> 7811 <name>TX_EM</name> 7812 <description>Wake on TX FIFO Empty.</description> 7813 <bitOffset>1</bitOffset> 7814 <bitWidth>1</bitWidth> 7815 <enumeratedValues> 7816 <enumeratedValue> 7817 <name>clear</name> 7818 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 7819 <value>1</value> 7820 </enumeratedValue> 7821 </enumeratedValues> 7822 </field> 7823 <field> 7824 <name>RX_THD</name> 7825 <description>Wake on RX FIFO Threshold Crossed.</description> 7826 <bitOffset>2</bitOffset> 7827 <bitWidth>1</bitWidth> 7828 <enumeratedValues> 7829 <enumeratedValue> 7830 <name>clear</name> 7831 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 7832 <value>1</value> 7833 </enumeratedValue> 7834 </enumeratedValues> 7835 </field> 7836 <field> 7837 <name>RX_FULL</name> 7838 <description>Wake on RX FIFO Full.</description> 7839 <bitOffset>3</bitOffset> 7840 <bitWidth>1</bitWidth> 7841 <enumeratedValues> 7842 <enumeratedValue> 7843 <name>clear</name> 7844 <description>Flag is set when value read is 1. Write 1 to clear this flag.</description> 7845 <value>1</value> 7846 </enumeratedValue> 7847 </enumeratedValues> 7848 </field> 7849 </fields> 7850 </register> 7851 <register> 7852 <name>WKEN</name> 7853 <description>Register for wake up enable.</description> 7854 <addressOffset>0x2C</addressOffset> 7855 <access>read-write</access> 7856 <fields> 7857 <field> 7858 <name>TX_THD</name> 7859 <description>Wake on TX FIFO Threshold Crossed Enable.</description> 7860 <bitOffset>0</bitOffset> 7861 <bitWidth>1</bitWidth> 7862 <enumeratedValues> 7863 <enumeratedValue> 7864 <name>dis</name> 7865 <description>Wakeup source disabled.</description> 7866 <value>0</value> 7867 </enumeratedValue> 7868 <enumeratedValue> 7869 <name>en</name> 7870 <description>Wakeup source enabled.</description> 7871 <value>1</value> 7872 </enumeratedValue> 7873 </enumeratedValues> 7874 </field> 7875 <field> 7876 <name>TX_EM</name> 7877 <description>Wake on TX FIFO Empty Enable.</description> 7878 <bitOffset>1</bitOffset> 7879 <bitWidth>1</bitWidth> 7880 <enumeratedValues> 7881 <enumeratedValue> 7882 <name>dis</name> 7883 <description>Wakeup source disabled.</description> 7884 <value>0</value> 7885 </enumeratedValue> 7886 <enumeratedValue> 7887 <name>en</name> 7888 <description>Wakeup source enabled.</description> 7889 <value>1</value> 7890 </enumeratedValue> 7891 </enumeratedValues> 7892 </field> 7893 <field> 7894 <name>RX_THD</name> 7895 <description>Wake on RX FIFO Threshold Crossed Enable.</description> 7896 <bitOffset>2</bitOffset> 7897 <bitWidth>1</bitWidth> 7898 <enumeratedValues> 7899 <enumeratedValue> 7900 <name>dis</name> 7901 <description>Wakeup source disabled.</description> 7902 <value>0</value> 7903 </enumeratedValue> 7904 <enumeratedValue> 7905 <name>en</name> 7906 <description>Wakeup source enabled.</description> 7907 <value>1</value> 7908 </enumeratedValue> 7909 </enumeratedValues> 7910 </field> 7911 <field> 7912 <name>RX_FULL</name> 7913 <description>Wake on RX FIFO Full Enable.</description> 7914 <bitOffset>3</bitOffset> 7915 <bitWidth>1</bitWidth> 7916 <enumeratedValues> 7917 <enumeratedValue> 7918 <name>dis</name> 7919 <description>Wakeup source disabled.</description> 7920 <value>0</value> 7921 </enumeratedValue> 7922 <enumeratedValue> 7923 <name>en</name> 7924 <description>Wakeup source enabled.</description> 7925 <value>1</value> 7926 </enumeratedValue> 7927 </enumeratedValues> 7928 </field> 7929 </fields> 7930 </register> 7931 <register> 7932 <name>STAT</name> 7933 <description>SPI Status register.</description> 7934 <addressOffset>0x30</addressOffset> 7935 <access>read-only</access> 7936 <fields> 7937 <field> 7938 <name>BUSY</name> 7939 <description>SPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. </description> 7940 <bitOffset>0</bitOffset> 7941 <bitWidth>1</bitWidth> 7942 <enumeratedValues> 7943 <enumeratedValue> 7944 <name>not</name> 7945 <description>SPI not active.</description> 7946 <value>0</value> 7947 </enumeratedValue> 7948 <enumeratedValue> 7949 <name>active</name> 7950 <description>SPI active.</description> 7951 <value>1</value> 7952 </enumeratedValue> 7953 </enumeratedValues> 7954 </field> 7955 </fields> 7956 </register> 7957 </registers> 7958 </peripheral> 7959<!--SPI0 SPI peripheral.--> 7960 <peripheral derivedFrom="SPI0"> 7961 <name>SPI1</name> 7962 <description>SPI peripheral. 1</description> 7963 <baseAddress>0x40047000</baseAddress> 7964 <interrupt> 7965 <name>SPI1</name> 7966 <description>SPI1 IRQ</description> 7967 <value>17</value> 7968 </interrupt> 7969 </peripheral> 7970<!--SPI1 SPI peripheral. 1--> 7971 <peripheral derivedFrom="SPI0"> 7972 <name>SPI2</name> 7973 <description>SPI peripheral. 2</description> 7974 <baseAddress>0x40048000</baseAddress> 7975 <interrupt> 7976 <name>SPI2</name> 7977 <description>SPI2 IRQ</description> 7978 <value>18</value> 7979 </interrupt> 7980 </peripheral> 7981<!--SPI2 SPI peripheral. 2--> 7982 <peripheral> 7983 <name>TMR</name> 7984 <description>Low-Power Configurable Timer</description> 7985 <baseAddress>0x40010000</baseAddress> 7986 <addressBlock> 7987 <offset>0x00</offset> 7988 <size>0x1000</size> 7989 <usage>registers</usage> 7990 </addressBlock> 7991 <interrupt> 7992 <name>TMR</name> 7993 <value>5</value> 7994 </interrupt> 7995 <registers> 7996 <register> 7997 <name>CNT</name> 7998 <description>Timer Counter Register.</description> 7999 <addressOffset>0x00</addressOffset> 8000 <access>read-write</access> 8001 <fields> 8002 <field> 8003 <name>COUNT</name> 8004 <description>The current count value for the timer. This field increments as the timer counts.</description> 8005 <bitOffset>0</bitOffset> 8006 <bitWidth>32</bitWidth> 8007 </field> 8008 </fields> 8009 </register> 8010 <register> 8011 <name>CMP</name> 8012 <description>Timer Compare Register.</description> 8013 <addressOffset>0x04</addressOffset> 8014 <access>read-write</access> 8015 <fields> 8016 <field> 8017 <name>COMPARE</name> 8018 <description>The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer.</description> 8019 <bitOffset>0</bitOffset> 8020 <bitWidth>32</bitWidth> 8021 </field> 8022 </fields> 8023 </register> 8024 <register> 8025 <name>PWM</name> 8026 <description>Timer PWM Register.</description> 8027 <addressOffset>0x08</addressOffset> 8028 <access>read-write</access> 8029 <fields> 8030 <field> 8031 <name>PWM</name> 8032 <description>Timer PWM Match: 8033 In PWM Mode, this field sets the count value for the first transition period of the PWM cycle. At the end of the cycle where CNT equals PWM, the PWM output transitions to the second period of the PWM cycle. The second PWM period count is stored in the CMP register. The value set for PWM must me less than the value set in CMP for PWM mode operation. Timer Capture Value: 8034 In Capture, Compare, and Capture/Compare modes, this field is used to store the CNT value when a Capture, Compare, or Capture/Compare event occurs.</description> 8035 <bitOffset>0</bitOffset> 8036 <bitWidth>32</bitWidth> 8037 </field> 8038 </fields> 8039 </register> 8040 <register> 8041 <name>INTFL</name> 8042 <description>Timer Interrupt Status Register.</description> 8043 <addressOffset>0x0C</addressOffset> 8044 <access>read-write</access> 8045 <fields> 8046 <field> 8047 <name>IRQ_A</name> 8048 <description>Interrupt Flag for Timer A.</description> 8049 <bitOffset>0</bitOffset> 8050 <bitWidth>1</bitWidth> 8051 </field> 8052 <field> 8053 <name>WRDONE_A</name> 8054 <description>Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain.</description> 8055 <bitOffset>8</bitOffset> 8056 <bitWidth>1</bitWidth> 8057 </field> 8058 <field> 8059 <name>WR_DIS_A</name> 8060 <description>Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration.</description> 8061 <bitOffset>9</bitOffset> 8062 <bitWidth>1</bitWidth> 8063 </field> 8064 <field> 8065 <name>IRQ_B</name> 8066 <description>Interrupt Flag for Timer B.</description> 8067 <bitOffset>16</bitOffset> 8068 <bitWidth>1</bitWidth> 8069 </field> 8070 <field> 8071 <name>WRDONE_B</name> 8072 <description>Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain.</description> 8073 <bitOffset>24</bitOffset> 8074 <bitWidth>1</bitWidth> 8075 </field> 8076 <field> 8077 <name>WR_DIS_B</name> 8078 <description>Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration.</description> 8079 <bitOffset>25</bitOffset> 8080 <bitWidth>1</bitWidth> 8081 </field> 8082 </fields> 8083 </register> 8084 <register> 8085 <name>CTRL0</name> 8086 <description>Timer Control Register.</description> 8087 <addressOffset>0x10</addressOffset> 8088 <access>read-write</access> 8089 <fields> 8090 <field> 8091 <name>MODE_A</name> 8092 <description>Mode Select for Timer A</description> 8093 <bitOffset>0</bitOffset> 8094 <bitWidth>4</bitWidth> 8095 <enumeratedValues> 8096 <enumeratedValue> 8097 <name>ONE_SHOT</name> 8098 <description>One-Shot Mode</description> 8099 <value>0</value> 8100 </enumeratedValue> 8101 <enumeratedValue> 8102 <name>CONTINUOUS</name> 8103 <description>Continuous Mode</description> 8104 <value>1</value> 8105 </enumeratedValue> 8106 <enumeratedValue> 8107 <name>COUNTER</name> 8108 <description>Counter Mode</description> 8109 <value>2</value> 8110 </enumeratedValue> 8111 <enumeratedValue> 8112 <name>PWM</name> 8113 <description>PWM Mode</description> 8114 <value>3</value> 8115 </enumeratedValue> 8116 <enumeratedValue> 8117 <name>CAPTURE</name> 8118 <description>Capture Mode</description> 8119 <value>4</value> 8120 </enumeratedValue> 8121 <enumeratedValue> 8122 <name>COMPARE</name> 8123 <description>Compare Mode</description> 8124 <value>5</value> 8125 </enumeratedValue> 8126 <enumeratedValue> 8127 <name>GATED</name> 8128 <description>Gated Mode</description> 8129 <value>6</value> 8130 </enumeratedValue> 8131 <enumeratedValue> 8132 <name>CAPCOMP</name> 8133 <description>Capture/Compare Mode</description> 8134 <value>7</value> 8135 </enumeratedValue> 8136 <enumeratedValue> 8137 <name>DUAL_EDGE</name> 8138 <description>Dual Edge Capture Mode</description> 8139 <value>8</value> 8140 </enumeratedValue> 8141 <enumeratedValue> 8142 <name>IGATED</name> 8143 <description>Inactive Gated Mode</description> 8144 <value>14</value> 8145 </enumeratedValue> 8146 </enumeratedValues> 8147 </field> 8148 <field> 8149 <name>CLKDIV_A</name> 8150 <description>Clock Divider Select for Timer A</description> 8151 <bitOffset>4</bitOffset> 8152 <bitWidth>4</bitWidth> 8153 <enumeratedValues> 8154 <enumeratedValue> 8155 <name>DIV_BY_1</name> 8156 <description>Prescaler Divide-By-1</description> 8157 <value>0</value> 8158 </enumeratedValue> 8159 <enumeratedValue> 8160 <name>DIV_BY_2</name> 8161 <description>Prescaler Divide-By-2</description> 8162 <value>1</value> 8163 </enumeratedValue> 8164 <enumeratedValue> 8165 <name>DIV_BY_4</name> 8166 <description>Prescaler Divide-By-4</description> 8167 <value>2</value> 8168 </enumeratedValue> 8169 <enumeratedValue> 8170 <name>DIV_BY_8</name> 8171 <description>Prescaler Divide-By-8</description> 8172 <value>3</value> 8173 </enumeratedValue> 8174 <enumeratedValue> 8175 <name>DIV_BY_16</name> 8176 <description>Prescaler Divide-By-16</description> 8177 <value>4</value> 8178 </enumeratedValue> 8179 <enumeratedValue> 8180 <name>DIV_BY_32</name> 8181 <description>Prescaler Divide-By-32</description> 8182 <value>5</value> 8183 </enumeratedValue> 8184 <enumeratedValue> 8185 <name>DIV_BY_64</name> 8186 <description>Prescaler Divide-By-64</description> 8187 <value>6</value> 8188 </enumeratedValue> 8189 <enumeratedValue> 8190 <name>DIV_BY_128</name> 8191 <description>Prescaler Divide-By-128</description> 8192 <value>7</value> 8193 </enumeratedValue> 8194 <enumeratedValue> 8195 <name>DIV_BY_256</name> 8196 <description>Prescaler Divide-By-256</description> 8197 <value>8</value> 8198 </enumeratedValue> 8199 <enumeratedValue> 8200 <name>DIV_BY_512</name> 8201 <description>Prescaler Divide-By-512</description> 8202 <value>9</value> 8203 </enumeratedValue> 8204 <enumeratedValue> 8205 <name>DIV_BY_1024</name> 8206 <description>Prescaler Divide-By-1024</description> 8207 <value>10</value> 8208 </enumeratedValue> 8209 <enumeratedValue> 8210 <name>DIV_BY_2048</name> 8211 <description>Prescaler Divide-By-2048</description> 8212 <value>11</value> 8213 </enumeratedValue> 8214 <enumeratedValue> 8215 <name>DIV_BY_4096</name> 8216 <description>TBD</description> 8217 <value>12</value> 8218 </enumeratedValue> 8219 </enumeratedValues> 8220 </field> 8221 <field> 8222 <name>POL_A</name> 8223 <description>Timer Polarity for Timer A</description> 8224 <bitOffset>8</bitOffset> 8225 <bitWidth>1</bitWidth> 8226 </field> 8227 <field> 8228 <name>PWMSYNC_A</name> 8229 <description>PWM Synchronization Mode for Timer A</description> 8230 <bitOffset>9</bitOffset> 8231 <bitWidth>1</bitWidth> 8232 </field> 8233 <field> 8234 <name>NOLHPOL_A</name> 8235 <description>PWM Phase A (Non-Overlapping High) Polarity for Timer A</description> 8236 <bitOffset>10</bitOffset> 8237 <bitWidth>1</bitWidth> 8238 </field> 8239 <field> 8240 <name>NOLLPOL_A</name> 8241 <description>PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A</description> 8242 <bitOffset>11</bitOffset> 8243 <bitWidth>1</bitWidth> 8244 </field> 8245 <field> 8246 <name>PWMCKBD_A</name> 8247 <description>PWM Phase A-Prime Output Disable for Timer A</description> 8248 <bitOffset>12</bitOffset> 8249 <bitWidth>1</bitWidth> 8250 </field> 8251 <field> 8252 <name>RST_A</name> 8253 <description>Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears.</description> 8254 <bitOffset>13</bitOffset> 8255 <bitWidth>1</bitWidth> 8256 </field> 8257 <field> 8258 <name>CLKEN_A</name> 8259 <description>Write 1 to Enable CLK_TMR for Timer A</description> 8260 <bitOffset>14</bitOffset> 8261 <bitWidth>1</bitWidth> 8262 </field> 8263 <field> 8264 <name>EN_A</name> 8265 <description>Enable for Timer A</description> 8266 <bitOffset>15</bitOffset> 8267 <bitWidth>1</bitWidth> 8268 </field> 8269 <field> 8270 <name>MODE_B</name> 8271 <description>Mode Select for Timer B</description> 8272 <bitOffset>16</bitOffset> 8273 <bitWidth>4</bitWidth> 8274 <enumeratedValues> 8275 <enumeratedValue> 8276 <name>ONE_SHOT</name> 8277 <description>One-Shot Mode</description> 8278 <value>0</value> 8279 </enumeratedValue> 8280 <enumeratedValue> 8281 <name>CONTINUOUS</name> 8282 <description>Continuous Mode</description> 8283 <value>1</value> 8284 </enumeratedValue> 8285 <enumeratedValue> 8286 <name>COUNTER</name> 8287 <description>Counter Mode</description> 8288 <value>2</value> 8289 </enumeratedValue> 8290 <enumeratedValue> 8291 <name>PWM</name> 8292 <description>PWM Mode</description> 8293 <value>3</value> 8294 </enumeratedValue> 8295 <enumeratedValue> 8296 <name>CAPTURE</name> 8297 <description>Capture Mode</description> 8298 <value>4</value> 8299 </enumeratedValue> 8300 <enumeratedValue> 8301 <name>COMPARE</name> 8302 <description>Compare Mode</description> 8303 <value>5</value> 8304 </enumeratedValue> 8305 <enumeratedValue> 8306 <name>GATED</name> 8307 <description>Gated Mode</description> 8308 <value>6</value> 8309 </enumeratedValue> 8310 <enumeratedValue> 8311 <name>CAPCOMP</name> 8312 <description>Capture/Compare Mode</description> 8313 <value>7</value> 8314 </enumeratedValue> 8315 <enumeratedValue> 8316 <name>DUAL_EDGE</name> 8317 <description>Dual Edge Capture Mode</description> 8318 <value>8</value> 8319 </enumeratedValue> 8320 <enumeratedValue> 8321 <name>IGATED</name> 8322 <description>Inactive Gated Mode</description> 8323 <value>14</value> 8324 </enumeratedValue> 8325 </enumeratedValues> 8326 </field> 8327 <field> 8328 <name>CLKDIV_B</name> 8329 <description>Clock Divider Select for Timer B</description> 8330 <bitOffset>20</bitOffset> 8331 <bitWidth>4</bitWidth> 8332 <enumeratedValues> 8333 <enumeratedValue> 8334 <name>DIV_BY_1</name> 8335 <description>Prescaler Divide-By-1</description> 8336 <value>0</value> 8337 </enumeratedValue> 8338 <enumeratedValue> 8339 <name>DIV_BY_2</name> 8340 <description>Prescaler Divide-By-2</description> 8341 <value>1</value> 8342 </enumeratedValue> 8343 <enumeratedValue> 8344 <name>DIV_BY_4</name> 8345 <description>Prescaler Divide-By-4</description> 8346 <value>2</value> 8347 </enumeratedValue> 8348 <enumeratedValue> 8349 <name>DIV_BY_8</name> 8350 <description>Prescaler Divide-By-8</description> 8351 <value>3</value> 8352 </enumeratedValue> 8353 <enumeratedValue> 8354 <name>DIV_BY_16</name> 8355 <description>Prescaler Divide-By-16</description> 8356 <value>4</value> 8357 </enumeratedValue> 8358 <enumeratedValue> 8359 <name>DIV_BY_32</name> 8360 <description>Prescaler Divide-By-32</description> 8361 <value>5</value> 8362 </enumeratedValue> 8363 <enumeratedValue> 8364 <name>DIV_BY_64</name> 8365 <description>Prescaler Divide-By-64</description> 8366 <value>6</value> 8367 </enumeratedValue> 8368 <enumeratedValue> 8369 <name>DIV_BY_128</name> 8370 <description>Prescaler Divide-By-128</description> 8371 <value>7</value> 8372 </enumeratedValue> 8373 <enumeratedValue> 8374 <name>DIV_BY_256</name> 8375 <description>Prescaler Divide-By-256</description> 8376 <value>8</value> 8377 </enumeratedValue> 8378 <enumeratedValue> 8379 <name>DIV_BY_512</name> 8380 <description>Prescaler Divide-By-512</description> 8381 <value>9</value> 8382 </enumeratedValue> 8383 <enumeratedValue> 8384 <name>DIV_BY_1024</name> 8385 <description>Prescaler Divide-By-1024</description> 8386 <value>10</value> 8387 </enumeratedValue> 8388 <enumeratedValue> 8389 <name>DIV_BY_2048</name> 8390 <description>Prescaler Divide-By-2048</description> 8391 <value>11</value> 8392 </enumeratedValue> 8393 <enumeratedValue> 8394 <name>DIV_BY_4096</name> 8395 <description>TBD</description> 8396 <value>12</value> 8397 </enumeratedValue> 8398 </enumeratedValues> 8399 </field> 8400 <field> 8401 <name>POL_B</name> 8402 <description>Timer Polarity for Timer B</description> 8403 <bitOffset>24</bitOffset> 8404 <bitWidth>1</bitWidth> 8405 </field> 8406 <field> 8407 <name>PWMSYNC_B</name> 8408 <description>PWM Synchronization Mode for Timer B</description> 8409 <bitOffset>25</bitOffset> 8410 <bitWidth>1</bitWidth> 8411 </field> 8412 <field> 8413 <name>NOLHPOL_B</name> 8414 <description>PWM Phase A (Non-Overlapping High) Polarity for Timer B</description> 8415 <bitOffset>26</bitOffset> 8416 <bitWidth>1</bitWidth> 8417 </field> 8418 <field> 8419 <name>NOLLPOL_B</name> 8420 <description>PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B</description> 8421 <bitOffset>27</bitOffset> 8422 <bitWidth>1</bitWidth> 8423 </field> 8424 <field> 8425 <name>PWMCKBD_B</name> 8426 <description>PWM Phase A-Prime Output Disable for Timer B</description> 8427 <bitOffset>28</bitOffset> 8428 <bitWidth>1</bitWidth> 8429 </field> 8430 <field> 8431 <name>RST_B</name> 8432 <description>Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears.</description> 8433 <bitOffset>29</bitOffset> 8434 <bitWidth>1</bitWidth> 8435 </field> 8436 <field> 8437 <name>CLKEN_B</name> 8438 <description>Write 1 to Enable CLK_TMR for Timer B</description> 8439 <bitOffset>30</bitOffset> 8440 <bitWidth>1</bitWidth> 8441 </field> 8442 <field> 8443 <name>EN_B</name> 8444 <description>Enable for Timer B</description> 8445 <bitOffset>31</bitOffset> 8446 <bitWidth>1</bitWidth> 8447 </field> 8448 </fields> 8449 </register> 8450 <register> 8451 <name>NOLCMP</name> 8452 <description>Timer Non-Overlapping Compare Register.</description> 8453 <addressOffset>0x14</addressOffset> 8454 <access>read-write</access> 8455 <fields> 8456 <field> 8457 <name>LO_A</name> 8458 <description>Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime.</description> 8459 <bitOffset>0</bitOffset> 8460 <bitWidth>8</bitWidth> 8461 </field> 8462 <field> 8463 <name>HI_A</name> 8464 <description>Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A.</description> 8465 <bitOffset>8</bitOffset> 8466 <bitWidth>8</bitWidth> 8467 </field> 8468 <field> 8469 <name>LO_B</name> 8470 <description>Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime.</description> 8471 <bitOffset>16</bitOffset> 8472 <bitWidth>8</bitWidth> 8473 </field> 8474 <field> 8475 <name>HI_B</name> 8476 <description>Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A.</description> 8477 <bitOffset>24</bitOffset> 8478 <bitWidth>8</bitWidth> 8479 </field> 8480 </fields> 8481 </register> 8482 <register> 8483 <name>CTRL1</name> 8484 <description>Timer Configuration Register.</description> 8485 <addressOffset>0x18</addressOffset> 8486 <access>read-write</access> 8487 <fields> 8488 <field> 8489 <name>CLKSEL_A</name> 8490 <description>Timer Clock Select for Timer A</description> 8491 <bitOffset>0</bitOffset> 8492 <bitWidth>2</bitWidth> 8493 </field> 8494 <field> 8495 <name>CLKEN_A</name> 8496 <description>Timer A Enable Status</description> 8497 <bitOffset>2</bitOffset> 8498 <bitWidth>1</bitWidth> 8499 </field> 8500 <field> 8501 <name>CLKRDY_A</name> 8502 <description>CLK_TMR Ready Flag for Timer A</description> 8503 <bitOffset>3</bitOffset> 8504 <bitWidth>1</bitWidth> 8505 </field> 8506 <field> 8507 <name>EVENT_SEL_A</name> 8508 <description>Event Select for Timer A</description> 8509 <bitOffset>4</bitOffset> 8510 <bitWidth>3</bitWidth> 8511 </field> 8512 <field> 8513 <name>NEGTRIG_A</name> 8514 <description>Negative Edge Trigger for Event for Timer A</description> 8515 <bitOffset>7</bitOffset> 8516 <bitWidth>1</bitWidth> 8517 </field> 8518 <field> 8519 <name>IE_A</name> 8520 <description>Interrupt Enable for Timer A</description> 8521 <bitOffset>8</bitOffset> 8522 <bitWidth>1</bitWidth> 8523 </field> 8524 <field> 8525 <name>CAPEVENT_SEL_A</name> 8526 <description>Capture Event Select for Timer A</description> 8527 <bitOffset>9</bitOffset> 8528 <bitWidth>2</bitWidth> 8529 </field> 8530 <field> 8531 <name>SW_CAPEVENT_A</name> 8532 <description>Software Capture Event for Timer A</description> 8533 <bitOffset>11</bitOffset> 8534 <bitWidth>1</bitWidth> 8535 </field> 8536 <field> 8537 <name>WE_A</name> 8538 <description>Wake-Up Enable for Timer A</description> 8539 <bitOffset>12</bitOffset> 8540 <bitWidth>1</bitWidth> 8541 </field> 8542 <field> 8543 <name>OUTEN_A</name> 8544 <description>OUT_OE_O Enable for Modes 0, 1,and 5 for Timer A</description> 8545 <bitOffset>13</bitOffset> 8546 <bitWidth>1</bitWidth> 8547 </field> 8548 <field> 8549 <name>OUTBEN_A</name> 8550 <description>PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A</description> 8551 <bitOffset>14</bitOffset> 8552 <bitWidth>1</bitWidth> 8553 </field> 8554 <field> 8555 <name>CLKSEL_B</name> 8556 <description>Timer Clock Select for Timer B</description> 8557 <bitOffset>16</bitOffset> 8558 <bitWidth>2</bitWidth> 8559 </field> 8560 <field> 8561 <name>CLKEN_B</name> 8562 <description>Timer B Enable Status</description> 8563 <bitOffset>18</bitOffset> 8564 <bitWidth>1</bitWidth> 8565 </field> 8566 <field> 8567 <name>CLKRDY_B</name> 8568 <description>CLK_TMR Ready Flag for Timer B</description> 8569 <bitOffset>19</bitOffset> 8570 <bitWidth>1</bitWidth> 8571 </field> 8572 <field> 8573 <name>EVENT_SEL_B</name> 8574 <description>Event Select for Timer B</description> 8575 <bitOffset>20</bitOffset> 8576 <bitWidth>3</bitWidth> 8577 </field> 8578 <field> 8579 <name>NEGTRIG_B</name> 8580 <description>Negative Edge Trigger for Event for Timer B</description> 8581 <bitOffset>23</bitOffset> 8582 <bitWidth>1</bitWidth> 8583 </field> 8584 <field> 8585 <name>IE_B</name> 8586 <description>Interrupt Enable for Timer B</description> 8587 <bitOffset>24</bitOffset> 8588 <bitWidth>1</bitWidth> 8589 </field> 8590 <field> 8591 <name>CAPEVENT_SEL_B</name> 8592 <description>Capture Event Select for Timer B</description> 8593 <bitOffset>25</bitOffset> 8594 <bitWidth>2</bitWidth> 8595 </field> 8596 <field> 8597 <name>SW_CAPEVENT_B</name> 8598 <description>Software Capture Event for Timer B</description> 8599 <bitOffset>27</bitOffset> 8600 <bitWidth>1</bitWidth> 8601 </field> 8602 <field> 8603 <name>WE_B</name> 8604 <description>Wake-Up Enable for Timer B</description> 8605 <bitOffset>28</bitOffset> 8606 <bitWidth>1</bitWidth> 8607 </field> 8608 <field> 8609 <name>CASCADE</name> 8610 <description>Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1.</description> 8611 <bitOffset>31</bitOffset> 8612 <bitWidth>1</bitWidth> 8613 </field> 8614 </fields> 8615 </register> 8616 <register> 8617 <name>WKFL</name> 8618 <description>Timer Wakeup Status Register.</description> 8619 <addressOffset>0x1C</addressOffset> 8620 <access>read-write</access> 8621 <fields> 8622 <field> 8623 <name>A</name> 8624 <description>Wake-Up Flag for Timer A</description> 8625 <bitOffset>0</bitOffset> 8626 <bitWidth>1</bitWidth> 8627 </field> 8628 <field> 8629 <name>B</name> 8630 <description>Wake-Up Flag for Timer B</description> 8631 <bitOffset>16</bitOffset> 8632 <bitWidth>1</bitWidth> 8633 </field> 8634 </fields> 8635 </register> 8636 </registers> 8637 </peripheral> 8638<!--TMR Low-Power Configurable Timer--> 8639 <peripheral derivedFrom="TMR"> 8640 <name>TMR1</name> 8641 <description>Low-Power Configurable Timer 1</description> 8642 <baseAddress>0x40011000</baseAddress> 8643 <interrupt> 8644 <name>TMR1</name> 8645 <description>TMR1 IRQ</description> 8646 <value>6</value> 8647 </interrupt> 8648 </peripheral> 8649<!--TMR1 Low-Power Configurable Timer 1--> 8650 <peripheral derivedFrom="TMR"> 8651 <name>TMR2</name> 8652 <description>Low-Power Configurable Timer 2</description> 8653 <baseAddress>0x40012000</baseAddress> 8654 <interrupt> 8655 <name>TMR2</name> 8656 <description>TMR2 IRQ</description> 8657 <value>7</value> 8658 </interrupt> 8659 </peripheral> 8660<!--TMR2 Low-Power Configurable Timer 2--> 8661 <peripheral derivedFrom="TMR"> 8662 <name>TMR3</name> 8663 <description>Low-Power Configurable Timer 3</description> 8664 <baseAddress>0x40013000</baseAddress> 8665 <interrupt> 8666 <name>TMR3</name> 8667 <description>TMR3 IRQ</description> 8668 <value>8</value> 8669 </interrupt> 8670 </peripheral> 8671<!--TMR3 Low-Power Configurable Timer 3--> 8672 <peripheral derivedFrom="TMR"> 8673 <name>TMR4</name> 8674 <description>Low-Power Configurable Timer 4</description> 8675 <baseAddress>0x40114000</baseAddress> 8676 <interrupt> 8677 <name>TMR4</name> 8678 <description>TMR4 IRQ</description> 8679 <value>9</value> 8680 </interrupt> 8681 </peripheral> 8682<!--TMR4 Low-Power Configurable Timer 4--> 8683 <peripheral derivedFrom="TMR"> 8684 <name>TMR5</name> 8685 <description>Low-Power Configurable Timer 5</description> 8686 <baseAddress>0x40115000</baseAddress> 8687 <interrupt> 8688 <name>TMR5</name> 8689 <description>TMR5 IRQ</description> 8690 <value>10</value> 8691 </interrupt> 8692 </peripheral> 8693<!--TMR5 Low-Power Configurable Timer 5--> 8694 <peripheral> 8695 <name>ECC</name> 8696 <description>Trim System Initilazation Registers. ECC Registers for MAX32670.</description> 8697 <baseAddress>0x40105400</baseAddress> 8698 <addressBlock> 8699 <offset>0x00</offset> 8700 <size>0x400</size> 8701 <usage>registers</usage> 8702 </addressBlock> 8703 <registers> 8704 <register> 8705 <name>EN</name> 8706 <description>ECC Enable Register.</description> 8707 <addressOffset>0x08</addressOffset> 8708 <fields> 8709 <field> 8710 <name>SRAM</name> 8711 <description>System RAM0 ECC Enable.</description> 8712 <bitOffset>8</bitOffset> 8713 <bitWidth>1</bitWidth> 8714 </field> 8715 <field> 8716 <name>ICC</name> 8717 <description>ICC0 ECC Enable.</description> 8718 <bitOffset>9</bitOffset> 8719 <bitWidth>1</bitWidth> 8720 </field> 8721 <field> 8722 <name>FLASH</name> 8723 <description>Flash ECC Enable.</description> 8724 <bitOffset>10</bitOffset> 8725 <bitWidth>1</bitWidth> 8726 </field> 8727 </fields> 8728 </register> 8729 </registers> 8730 </peripheral> 8731<!--ECC Trim System Initilazation Registers. ECC Registers for MAX32670.--> 8732 <peripheral> 8733 <name>TRNG</name> 8734 <description>Random Number Generator.</description> 8735 <baseAddress>0x4004D000</baseAddress> 8736 <addressBlock> 8737 <offset>0x00</offset> 8738 <size>0x1000</size> 8739 <usage>registers</usage> 8740 </addressBlock> 8741 <interrupt> 8742 <name>TRNG</name> 8743 <description>TRNG interrupt.</description> 8744 <value>4</value> 8745 </interrupt> 8746 <registers> 8747 <register> 8748 <name>CTRL</name> 8749 <description>TRNG Control Register.</description> 8750 <addressOffset>0x00</addressOffset> 8751 <resetValue>0x00000003</resetValue> 8752 <fields> 8753 <field> 8754 <name>ODHT</name> 8755 <description>Start On-Demand health test.</description> 8756 <bitOffset>0</bitOffset> 8757 <bitWidth>1</bitWidth> 8758 </field> 8759 <field> 8760 <name>RND_IE</name> 8761 <description>To enable IRQ generation when a new 32-bit Random number is ready.</description> 8762 <bitOffset>1</bitOffset> 8763 <bitWidth>1</bitWidth> 8764 <enumeratedValues> 8765 <enumeratedValue> 8766 <name>disable</name> 8767 <description>Disable</description> 8768 <value>0</value> 8769 </enumeratedValue> 8770 <enumeratedValue> 8771 <name>enable</name> 8772 <description>Enable</description> 8773 <value>1</value> 8774 </enumeratedValue> 8775 </enumeratedValues> 8776 </field> 8777 <field> 8778 <name>HEALTH_EN</name> 8779 <description>Enable IRQ generation when a health test fails.</description> 8780 <bitOffset>2</bitOffset> 8781 <bitWidth>1</bitWidth> 8782 </field> 8783 <field> 8784 <name>AESKG_USR</name> 8785 <description>AES Key Generate. When enabled, the key for securing NVSRAM is generated and transferred to the secure key register automatically without user visibility or intervention. This bit is cleared by hardware once the key has been transferred to the secure key register.</description> 8786 <bitOffset>3</bitOffset> 8787 <bitWidth>1</bitWidth> 8788 </field> 8789 <field> 8790 <name>AESKG_SYS</name> 8791 <description>AESKG_SYS.</description> 8792 <bitOffset>4</bitOffset> 8793 <bitWidth>1</bitWidth> 8794 </field> 8795 <field> 8796 <name>KEYWIPE</name> 8797 <description>To wipe the Battery Backed key.</description> 8798 <bitOffset>15</bitOffset> 8799 <bitWidth>1</bitWidth> 8800 </field> 8801 </fields> 8802 </register> 8803 <register> 8804 <name>STATUS</name> 8805 <description>Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000.</description> 8806 <addressOffset>0x04</addressOffset> 8807 <fields> 8808 <field> 8809 <name>RDY</name> 8810 <description>32-bit random data is ready to read from TRNG_DATA register. Reading TRNG_DATA when RND_RDY=0 will return all 0's. IRQ is generated when RND_RDY=1 if TRNG_CN.RND_IRQ_EN=1.</description> 8811 <bitOffset>0</bitOffset> 8812 <bitWidth>1</bitWidth> 8813 <enumeratedValues> 8814 <enumeratedValue> 8815 <name>Busy</name> 8816 <description>TRNG Busy</description> 8817 <value>0</value> 8818 </enumeratedValue> 8819 <enumeratedValue> 8820 <name>Ready</name> 8821 <description>32 bit random data is ready</description> 8822 <value>1</value> 8823 </enumeratedValue> 8824 </enumeratedValues> 8825 </field> 8826 <field> 8827 <name>ODHT</name> 8828 <description>On-Demand health test status.</description> 8829 <bitOffset>1</bitOffset> 8830 <bitWidth>1</bitWidth> 8831 </field> 8832 <field> 8833 <name>HT</name> 8834 <description>Health test status.</description> 8835 <bitOffset>2</bitOffset> 8836 <bitWidth>1</bitWidth> 8837 </field> 8838 <field> 8839 <name>SRCFAIL</name> 8840 <description>Entropy source has failed.</description> 8841 <bitOffset>3</bitOffset> 8842 <bitWidth>1</bitWidth> 8843 </field> 8844 <field> 8845 <name>AESKGD</name> 8846 <description>AESKGD.</description> 8847 <bitOffset>4</bitOffset> 8848 <bitWidth>1</bitWidth> 8849 </field> 8850 <field> 8851 <name>LD_CNT</name> 8852 <description>LD_CNT.</description> 8853 <bitOffset>24</bitOffset> 8854 <bitWidth>8</bitWidth> 8855 </field> 8856 </fields> 8857 </register> 8858 <register> 8859 <name>DATA</name> 8860 <description>Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000.</description> 8861 <addressOffset>0x08</addressOffset> 8862 <access>read-only</access> 8863 <fields> 8864 <field> 8865 <name>DATA</name> 8866 <description>Data. The content of this register is valid only when RNG_IS =1. When TNRG is disabled, read returns 0x0000 0000.</description> 8867 <bitOffset>0</bitOffset> 8868 <bitWidth>32</bitWidth> 8869 </field> 8870 </fields> 8871 </register> 8872 </registers> 8873 </peripheral> 8874<!--TRNG Random Number Generator.--> 8875 <peripheral> 8876 <name>UART</name> 8877 <description>UART Low Power Registers</description> 8878 <baseAddress>0x40042000</baseAddress> 8879 <addressBlock> 8880 <offset>0x00</offset> 8881 <size>0x1000</size> 8882 <usage>registers</usage> 8883 </addressBlock> 8884 <registers> 8885 <register> 8886 <name>CTRL</name> 8887 <description>Control register</description> 8888 <addressOffset>0x0000</addressOffset> 8889 <fields> 8890 <field> 8891 <name>RX_THD_VAL</name> 8892 <description>This field specifies the depth of receive FIFO for interrupt generation (value 0 and > 16 are ignored) </description> 8893 <bitOffset>0</bitOffset> 8894 <bitWidth>4</bitWidth> 8895 </field> 8896 <field> 8897 <name>PAR_EN</name> 8898 <description>Parity Enable</description> 8899 <bitOffset>4</bitOffset> 8900 <bitWidth>1</bitWidth> 8901 </field> 8902 <field> 8903 <name>PAR_EO</name> 8904 <description>when PAREN=1 selects odd or even parity odd is 1 even is 0</description> 8905 <bitOffset>5</bitOffset> 8906 <bitWidth>1</bitWidth> 8907 </field> 8908 <field> 8909 <name>PAR_MD</name> 8910 <description>Selects parity based on 1s or 0s count (when PAREN=1) </description> 8911 <bitOffset>6</bitOffset> 8912 <bitWidth>1</bitWidth> 8913 </field> 8914 <field> 8915 <name>CTS_DIS</name> 8916 <description>CTS Sampling Disable </description> 8917 <bitOffset>7</bitOffset> 8918 <bitWidth>1</bitWidth> 8919 </field> 8920 <field> 8921 <name>TX_FLUSH</name> 8922 <description>Flushes the TX FIFO buffer. This bit is automatically cleared by hardware when flush is completed.</description> 8923 <bitOffset>8</bitOffset> 8924 <bitWidth>1</bitWidth> 8925 </field> 8926 <field> 8927 <name>RX_FLUSH</name> 8928 <description>Flushes the RX FIFO buffer. This bit is automatically cleared by hardware when flush is completed.</description> 8929 <bitOffset>9</bitOffset> 8930 <bitWidth>1</bitWidth> 8931 </field> 8932 <field> 8933 <name>CHAR_SIZE</name> 8934 <description>Selects UART character size</description> 8935 <bitOffset>10</bitOffset> 8936 <bitWidth>2</bitWidth> 8937 <enumeratedValues> 8938 <enumeratedValue> 8939 <name>5bits</name> 8940 <description>5 bits</description> 8941 <value>0</value> 8942 </enumeratedValue> 8943 <enumeratedValue> 8944 <name>6bits</name> 8945 <description>6 bits</description> 8946 <value>1</value> 8947 </enumeratedValue> 8948 <enumeratedValue> 8949 <name>7bits</name> 8950 <description>7 bits</description> 8951 <value>2</value> 8952 </enumeratedValue> 8953 <enumeratedValue> 8954 <name>8bits</name> 8955 <description>8 bits</description> 8956 <value>3</value> 8957 </enumeratedValue> 8958 </enumeratedValues> 8959 </field> 8960 <field> 8961 <name>STOPBITS</name> 8962 <description>Selects the number of stop bits that will be generated</description> 8963 <bitOffset>12</bitOffset> 8964 <bitWidth>1</bitWidth> 8965 </field> 8966 <field> 8967 <name>HFC_EN</name> 8968 <description>Enables/disables hardware flow control</description> 8969 <bitOffset>13</bitOffset> 8970 <bitWidth>1</bitWidth> 8971 </field> 8972 <field> 8973 <name>RTSDC</name> 8974 <description>Hardware Flow Control RTS Mode</description> 8975 <bitOffset>14</bitOffset> 8976 <bitWidth>1</bitWidth> 8977 </field> 8978 <field> 8979 <name>BCLKEN</name> 8980 <description>Baud clock enable</description> 8981 <bitOffset>15</bitOffset> 8982 <bitWidth>1</bitWidth> 8983 </field> 8984 <field> 8985 <name>BCLKSRC</name> 8986 <description>To select the UART clock source for the UART engine (except APB registers). Secondary clock (used for baud rate generator) can be asynchronous from APB clock.</description> 8987 <bitOffset>16</bitOffset> 8988 <bitWidth>2</bitWidth> 8989 <enumeratedValues> 8990 <enumeratedValue> 8991 <name>Peripheral_Clock</name> 8992 <description>apb clock</description> 8993 <value>0</value> 8994 </enumeratedValue> 8995 <enumeratedValue> 8996 <name>External_Clock</name> 8997 <description>Clock 1</description> 8998 <value>1</value> 8999 </enumeratedValue> 9000 <enumeratedValue> 9001 <name>CLK2</name> 9002 <description>Clock 2</description> 9003 <value>2</value> 9004 </enumeratedValue> 9005 <enumeratedValue> 9006 <name>CLK3</name> 9007 <description>Clock 3</description> 9008 <value>3</value> 9009 </enumeratedValue> 9010 </enumeratedValues> 9011 </field> 9012 <field> 9013 <name>DPFE_EN</name> 9014 <description>Data/Parity bit frame error detection enable</description> 9015 <bitOffset>18</bitOffset> 9016 <bitWidth>1</bitWidth> 9017 </field> 9018 <field> 9019 <name>BCLKRDY</name> 9020 <description>Baud clock Ready read only bit</description> 9021 <bitOffset>19</bitOffset> 9022 <bitWidth>1</bitWidth> 9023 </field> 9024 <field> 9025 <name>UCAGM</name> 9026 <description>UART Clock Auto Gating mode</description> 9027 <bitOffset>20</bitOffset> 9028 <bitWidth>1</bitWidth> 9029 </field> 9030 <field> 9031 <name>FDM</name> 9032 <description>Fractional Division Mode</description> 9033 <bitOffset>21</bitOffset> 9034 <bitWidth>1</bitWidth> 9035 </field> 9036 <field> 9037 <name>DESM</name> 9038 <description>RX Dual Edge Sampling Mode</description> 9039 <bitOffset>22</bitOffset> 9040 <bitWidth>1</bitWidth> 9041 </field> 9042 </fields> 9043 </register> 9044 <register> 9045 <name>STATUS</name> 9046 <description>Status register</description> 9047 <addressOffset>0x0004</addressOffset> 9048 <access>read-only</access> 9049 <fields> 9050 <field> 9051 <name>TX_BUSY</name> 9052 <description>Read-only flag indicating the UART transmit status</description> 9053 <bitOffset>0</bitOffset> 9054 <bitWidth>1</bitWidth> 9055 </field> 9056 <field> 9057 <name>RX_BUSY</name> 9058 <description>Read-only flag indicating the UART receiver status</description> 9059 <bitOffset>1</bitOffset> 9060 <bitWidth>1</bitWidth> 9061 </field> 9062 <field> 9063 <name>RX_EM</name> 9064 <description>Read-only flag indicating the RX FIFO state</description> 9065 <bitOffset>4</bitOffset> 9066 <bitWidth>1</bitWidth> 9067 </field> 9068 <field> 9069 <name>RX_FULL</name> 9070 <description>Read-only flag indicating the RX FIFO state</description> 9071 <bitOffset>5</bitOffset> 9072 <bitWidth>1</bitWidth> 9073 </field> 9074 <field> 9075 <name>TX_EM</name> 9076 <description>Read-only flag indicating the TX FIFO state</description> 9077 <bitOffset>6</bitOffset> 9078 <bitWidth>1</bitWidth> 9079 </field> 9080 <field> 9081 <name>TX_FULL</name> 9082 <description>Read-only flag indicating the TX FIFO state</description> 9083 <bitOffset>7</bitOffset> 9084 <bitWidth>1</bitWidth> 9085 </field> 9086 <field> 9087 <name>RX_LVL</name> 9088 <description>Indicates the number of bytes currently in the RX FIFO (0-RX FIFO_ELTS) </description> 9089 <bitOffset>8</bitOffset> 9090 <bitWidth>4</bitWidth> 9091 </field> 9092 <field> 9093 <name>TX_LVL</name> 9094 <description>Indicates the number of bytes currently in the TX FIFO (0-TX FIFO_ELTS) </description> 9095 <bitOffset>12</bitOffset> 9096 <bitWidth>4</bitWidth> 9097 </field> 9098 </fields> 9099 </register> 9100 <register> 9101 <name>INT_EN</name> 9102 <description>Interrupt Enable control register</description> 9103 <addressOffset>0x0008</addressOffset> 9104 <fields> 9105 <field> 9106 <name>RX_FERR</name> 9107 <description>Enable Interrupt For RX Frame Error</description> 9108 <bitOffset>0</bitOffset> 9109 <bitWidth>1</bitWidth> 9110 </field> 9111 <field> 9112 <name>RX_PAR</name> 9113 <description>Enable Interrupt For RX Parity Error</description> 9114 <bitOffset>1</bitOffset> 9115 <bitWidth>1</bitWidth> 9116 </field> 9117 <field> 9118 <name>CTS_EV</name> 9119 <description>Enable Interrupt For CTS signal change Error</description> 9120 <bitOffset>2</bitOffset> 9121 <bitWidth>1</bitWidth> 9122 </field> 9123 <field> 9124 <name>RX_OV</name> 9125 <description>Enable Interrupt For RX FIFO Overrun Error</description> 9126 <bitOffset>3</bitOffset> 9127 <bitWidth>1</bitWidth> 9128 </field> 9129 <field> 9130 <name>RX_THD</name> 9131 <description>Enable Interrupt For RX FIFO reaches the number of bytes configured by RXTHD</description> 9132 <bitOffset>4</bitOffset> 9133 <bitWidth>1</bitWidth> 9134 </field> 9135 <field> 9136 <name>TX_OB</name> 9137 <description>Enable Interrupt For TX FIFO has one byte remaining</description> 9138 <bitOffset>5</bitOffset> 9139 <bitWidth>1</bitWidth> 9140 </field> 9141 <field> 9142 <name>TX_HE</name> 9143 <description>Enable Interrupt For TX FIFO has half empty</description> 9144 <bitOffset>6</bitOffset> 9145 <bitWidth>1</bitWidth> 9146 </field> 9147 </fields> 9148 </register> 9149 <register> 9150 <name>INT_FL</name> 9151 <description>Interrupt status flags Control register</description> 9152 <addressOffset>0x000C</addressOffset> 9153 <fields> 9154 <field> 9155 <name>RX_FERR</name> 9156 <description>Flag for RX Frame Error Interrupt.</description> 9157 <bitOffset>0</bitOffset> 9158 <bitWidth>1</bitWidth> 9159 </field> 9160 <field> 9161 <name>RX_PAR</name> 9162 <description>Flag for RX Parity Error interrupt</description> 9163 <bitOffset>1</bitOffset> 9164 <bitWidth>1</bitWidth> 9165 </field> 9166 <field> 9167 <name>CTS_EV</name> 9168 <description>Flag for CTS signal change interrupt (hardware flow control disabled) </description> 9169 <bitOffset>2</bitOffset> 9170 <bitWidth>1</bitWidth> 9171 </field> 9172 <field> 9173 <name>RX_OV</name> 9174 <description>Flag for RX FIFO Overrun interrupt</description> 9175 <bitOffset>3</bitOffset> 9176 <bitWidth>1</bitWidth> 9177 </field> 9178 <field> 9179 <name>RX_THD</name> 9180 <description>Flag for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field</description> 9181 <bitOffset>4</bitOffset> 9182 <bitWidth>1</bitWidth> 9183 </field> 9184 <field> 9185 <name>TX_OB</name> 9186 <description>Flag for interrupt when TX FIFO has one byte remaining</description> 9187 <bitOffset>5</bitOffset> 9188 <bitWidth>1</bitWidth> 9189 </field> 9190 <field> 9191 <name>TX_HE</name> 9192 <description>Flag for interrupt when TX FIFO is half empty</description> 9193 <bitOffset>6</bitOffset> 9194 <bitWidth>1</bitWidth> 9195 </field> 9196 </fields> 9197 </register> 9198 <register> 9199 <name>CLKDIV</name> 9200 <description>Clock Divider register</description> 9201 <addressOffset>0x0010</addressOffset> 9202 <fields> 9203 <field> 9204 <name>CLKDIV</name> 9205 <description>Baud rate divisor value</description> 9206 <bitOffset>0</bitOffset> 9207 <bitWidth>20</bitWidth> 9208 </field> 9209 </fields> 9210 </register> 9211 <register> 9212 <name>OSR</name> 9213 <description>Over Sampling Rate register</description> 9214 <addressOffset>0x0014</addressOffset> 9215 <fields> 9216 <field> 9217 <name>OSR</name> 9218 <description>OSR</description> 9219 <bitOffset>0</bitOffset> 9220 <bitWidth>3</bitWidth> 9221 </field> 9222 </fields> 9223 </register> 9224 <register> 9225 <name>TXPEEK</name> 9226 <description>TX FIFO Output Peek register</description> 9227 <addressOffset>0x0018</addressOffset> 9228 <fields> 9229 <field> 9230 <name>DATA</name> 9231 <description>Read TX FIFO next data. Reading from this field does not affect the contents of TX FIFO. Note that the parity bit is available from this field.</description> 9232 <bitOffset>0</bitOffset> 9233 <bitWidth>8</bitWidth> 9234 </field> 9235 </fields> 9236 </register> 9237 <register> 9238 <name>PNR</name> 9239 <description> Pin register</description> 9240 <addressOffset>0x001C</addressOffset> 9241 <fields> 9242 <field> 9243 <name>CTS</name> 9244 <description>Current sampled value of CTS IO</description> 9245 <bitOffset>0</bitOffset> 9246 <bitWidth>1</bitWidth> 9247 <access>read-only</access> 9248 </field> 9249 <field> 9250 <name>RTS</name> 9251 <description>This bit controls the value to apply on the RTS IO. If set to 1, the RTS IO is set to high level. If set to 0, the RTS IO is set to low level.</description> 9252 <bitOffset>1</bitOffset> 9253 <bitWidth>1</bitWidth> 9254 </field> 9255 </fields> 9256 </register> 9257 <register> 9258 <name>FIFO</name> 9259 <description>FIFO Read/Write register</description> 9260 <addressOffset>0x0020</addressOffset> 9261 <fields> 9262 <field> 9263 <name>DATA</name> 9264 <description>Load/unload location for TX and RX FIFO buffers.</description> 9265 <bitOffset>0</bitOffset> 9266 <bitWidth>8</bitWidth> 9267 </field> 9268 <field> 9269 <name>RX_PAR</name> 9270 <description>Parity error flag for next byte to be read from FIFO.</description> 9271 <bitOffset>8</bitOffset> 9272 <bitWidth>1</bitWidth> 9273 </field> 9274 </fields> 9275 </register> 9276 <register> 9277 <name>DMA</name> 9278 <description>DMA Configuration register</description> 9279 <addressOffset>0x0030</addressOffset> 9280 <fields> 9281 <field> 9282 <name>TX_THD_VAL</name> 9283 <description>TX FIFO Level DMA Trigger If the TX FIFO level is less than this value, then the TX FIFO DMA interface will send a signal to system DMA to notify that TX FIFO is ready to receive data from memory.</description> 9284 <bitOffset>0</bitOffset> 9285 <bitWidth>4</bitWidth> 9286 </field> 9287 <field> 9288 <name>TX_EN</name> 9289 <description>TX DMA channel enable</description> 9290 <bitOffset>4</bitOffset> 9291 <bitWidth>1</bitWidth> 9292 </field> 9293 <field> 9294 <name>RX_THD_VAL</name> 9295 <description>Rx FIFO Level DMA Trigger If the RX FIFO level is greater than this value, then the RX FIFO DMA interface will send a signal to the system DMA to notify that RX FIFO has characters to transfer to memory.</description> 9296 <bitOffset>5</bitOffset> 9297 <bitWidth>4</bitWidth> 9298 </field> 9299 <field> 9300 <name>RX_EN</name> 9301 <description>RX DMA channel enable</description> 9302 <bitOffset>9</bitOffset> 9303 <bitWidth>1</bitWidth> 9304 </field> 9305 </fields> 9306 </register> 9307 <register> 9308 <name>WKEN</name> 9309 <description>Wake up enable Control register</description> 9310 <addressOffset>0x0034</addressOffset> 9311 <fields> 9312 <field> 9313 <name>RX_NE</name> 9314 <description>Wake-Up Enable for RX FIFO Not Empty</description> 9315 <bitOffset>0</bitOffset> 9316 <bitWidth>1</bitWidth> 9317 </field> 9318 <field> 9319 <name>RX_FULL</name> 9320 <description>Wake-Up Enable for RX FIFO Full</description> 9321 <bitOffset>1</bitOffset> 9322 <bitWidth>1</bitWidth> 9323 </field> 9324 <field> 9325 <name>RX_THD</name> 9326 <description>Wake-Up Enable for RX FIFO Threshold Met</description> 9327 <bitOffset>2</bitOffset> 9328 <bitWidth>1</bitWidth> 9329 </field> 9330 </fields> 9331 </register> 9332 <register> 9333 <name>WKFL</name> 9334 <description>Wake up Flags register</description> 9335 <addressOffset>0x0038</addressOffset> 9336 <fields> 9337 <field> 9338 <name>RX_NE</name> 9339 <description>Wake-Up Flag for RX FIFO Not Empty</description> 9340 <bitOffset>0</bitOffset> 9341 <bitWidth>1</bitWidth> 9342 </field> 9343 <field> 9344 <name>RX_FULL</name> 9345 <description>Wake-Up Flag for RX FIFO Full</description> 9346 <bitOffset>1</bitOffset> 9347 <bitWidth>1</bitWidth> 9348 </field> 9349 <field> 9350 <name>RX_THD</name> 9351 <description>Wake-Up Flag for RX FIFO Threshold Met</description> 9352 <bitOffset>2</bitOffset> 9353 <bitWidth>1</bitWidth> 9354 </field> 9355 </fields> 9356 </register> 9357 </registers> 9358 </peripheral> 9359<!--UART UART Low Power Registers--> 9360 <peripheral derivedFrom="UART"> 9361 <name>UART1</name> 9362 <description>UART Low Power Registers 1</description> 9363 <baseAddress>0x40043000</baseAddress> 9364 </peripheral> 9365<!--UART1 UART Low Power Registers 1--> 9366 <peripheral derivedFrom="UART"> 9367 <name>UART2</name> 9368 <description>UART Low Power Registers 2</description> 9369 <baseAddress>0x40044000</baseAddress> 9370 </peripheral> 9371<!--UART2 UART Low Power Registers 2--> 9372 <peripheral derivedFrom="UART"> 9373 <name>UART3</name> 9374 <description>UART Low Power Registers 3</description> 9375 <baseAddress>0x40145000</baseAddress> 9376 </peripheral> 9377<!--UART3 UART Low Power Registers 3--> 9378 <peripheral> 9379 <name>WDT</name> 9380 <description>Windowed Watchdog Timer</description> 9381 <baseAddress>0x40003000</baseAddress> 9382 <addressBlock> 9383 <offset>0x00</offset> 9384 <size>0x0400</size> 9385 <usage>registers</usage> 9386 </addressBlock> 9387 <interrupt> 9388 <name>WWDT</name> 9389 <value>1</value> 9390 </interrupt> 9391 <registers> 9392 <register> 9393 <name>CTRL</name> 9394 <description>Watchdog Timer Control Register.</description> 9395 <addressOffset>0x00</addressOffset> 9396 <access>read-write</access> 9397 <fields> 9398 <field> 9399 <name>INT_LATE_VAL</name> 9400 <description>Windowed Watchdog Interrupt Upper Limit. Sets the number of WDTCLK cycles until a windowed watchdog timer interrupt is generated (if enabled) if the CPU does not write the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset.</description> 9401 <bitOffset>0</bitOffset> 9402 <bitWidth>4</bitWidth> 9403 <enumeratedValues> 9404 <enumeratedValue> 9405 <name>wdt2pow31</name> 9406 <description>2**31 clock cycles.</description> 9407 <value>0</value> 9408 </enumeratedValue> 9409 <enumeratedValue> 9410 <name>wdt2pow30</name> 9411 <description>2**30 clock cycles.</description> 9412 <value>1</value> 9413 </enumeratedValue> 9414 <enumeratedValue> 9415 <name>wdt2pow29</name> 9416 <description>2**29 clock cycles.</description> 9417 <value>2</value> 9418 </enumeratedValue> 9419 <enumeratedValue> 9420 <name>wdt2pow28</name> 9421 <description>2**28 clock cycles.</description> 9422 <value>3</value> 9423 </enumeratedValue> 9424 <enumeratedValue> 9425 <name>wdt2pow27</name> 9426 <description>2^27 clock cycles.</description> 9427 <value>4</value> 9428 </enumeratedValue> 9429 <enumeratedValue> 9430 <name>wdt2pow26</name> 9431 <description>2**26 clock cycles.</description> 9432 <value>5</value> 9433 </enumeratedValue> 9434 <enumeratedValue> 9435 <name>wdt2pow25</name> 9436 <description>2**25 clock cycles.</description> 9437 <value>6</value> 9438 </enumeratedValue> 9439 <enumeratedValue> 9440 <name>wdt2pow24</name> 9441 <description>2**24 clock cycles.</description> 9442 <value>7</value> 9443 </enumeratedValue> 9444 <enumeratedValue> 9445 <name>wdt2pow23</name> 9446 <description>2**23 clock cycles.</description> 9447 <value>8</value> 9448 </enumeratedValue> 9449 <enumeratedValue> 9450 <name>wdt2pow22</name> 9451 <description>2**22 clock cycles.</description> 9452 <value>9</value> 9453 </enumeratedValue> 9454 <enumeratedValue> 9455 <name>wdt2pow21</name> 9456 <description>2**21 clock cycles.</description> 9457 <value>10</value> 9458 </enumeratedValue> 9459 <enumeratedValue> 9460 <name>wdt2pow20</name> 9461 <description>2**20 clock cycles.</description> 9462 <value>11</value> 9463 </enumeratedValue> 9464 <enumeratedValue> 9465 <name>wdt2pow19</name> 9466 <description>2**19 clock cycles.</description> 9467 <value>12</value> 9468 </enumeratedValue> 9469 <enumeratedValue> 9470 <name>wdt2pow18</name> 9471 <description>2**18 clock cycles.</description> 9472 <value>13</value> 9473 </enumeratedValue> 9474 <enumeratedValue> 9475 <name>wdt2pow17</name> 9476 <description>2**17 clock cycles.</description> 9477 <value>14</value> 9478 </enumeratedValue> 9479 <enumeratedValue> 9480 <name>wdt2pow16</name> 9481 <description>2**16 clock cycles.</description> 9482 <value>15</value> 9483 </enumeratedValue> 9484 </enumeratedValues> 9485 </field> 9486 <field> 9487 <name>RST_LATE_VAL</name> 9488 <description>Windowed Watchdog Reset Upper Limit. Sets the number of WDTCLK cycles until a system reset occurs (if enabled) if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset.</description> 9489 <bitOffset>4</bitOffset> 9490 <bitWidth>4</bitWidth> 9491 <enumeratedValues> 9492 <enumeratedValue> 9493 <name>wdt2pow31</name> 9494 <description>2**31 clock cycles.</description> 9495 <value>0</value> 9496 </enumeratedValue> 9497 <enumeratedValue> 9498 <name>wdt2pow30</name> 9499 <description>2**30 clock cycles.</description> 9500 <value>1</value> 9501 </enumeratedValue> 9502 <enumeratedValue> 9503 <name>wdt2pow29</name> 9504 <description>2**29 clock cycles.</description> 9505 <value>2</value> 9506 </enumeratedValue> 9507 <enumeratedValue> 9508 <name>wdt2pow28</name> 9509 <description>2**28 clock cycles.</description> 9510 <value>3</value> 9511 </enumeratedValue> 9512 <enumeratedValue> 9513 <name>wdt2pow27</name> 9514 <description>2^27 clock cycles.</description> 9515 <value>4</value> 9516 </enumeratedValue> 9517 <enumeratedValue> 9518 <name>wdt2pow26</name> 9519 <description>2**26 clock cycles.</description> 9520 <value>5</value> 9521 </enumeratedValue> 9522 <enumeratedValue> 9523 <name>wdt2pow25</name> 9524 <description>2**25 clock cycles.</description> 9525 <value>6</value> 9526 </enumeratedValue> 9527 <enumeratedValue> 9528 <name>wdt2pow24</name> 9529 <description>2**24 clock cycles.</description> 9530 <value>7</value> 9531 </enumeratedValue> 9532 <enumeratedValue> 9533 <name>wdt2pow23</name> 9534 <description>2**23 clock cycles.</description> 9535 <value>8</value> 9536 </enumeratedValue> 9537 <enumeratedValue> 9538 <name>wdt2pow22</name> 9539 <description>2**22 clock cycles.</description> 9540 <value>9</value> 9541 </enumeratedValue> 9542 <enumeratedValue> 9543 <name>wdt2pow21</name> 9544 <description>2**21 clock cycles.</description> 9545 <value>10</value> 9546 </enumeratedValue> 9547 <enumeratedValue> 9548 <name>wdt2pow20</name> 9549 <description>2**20 clock cycles.</description> 9550 <value>11</value> 9551 </enumeratedValue> 9552 <enumeratedValue> 9553 <name>wdt2pow19</name> 9554 <description>2**19 clock cycles.</description> 9555 <value>12</value> 9556 </enumeratedValue> 9557 <enumeratedValue> 9558 <name>wdt2pow18</name> 9559 <description>2**18 clock cycles.</description> 9560 <value>13</value> 9561 </enumeratedValue> 9562 <enumeratedValue> 9563 <name>wdt2pow17</name> 9564 <description>2**17 clock cycles.</description> 9565 <value>14</value> 9566 </enumeratedValue> 9567 <enumeratedValue> 9568 <name>wdt2pow16</name> 9569 <description>2**16 clock cycles.</description> 9570 <value>15</value> 9571 </enumeratedValue> 9572 </enumeratedValues> 9573 </field> 9574 <field> 9575 <name>EN</name> 9576 <description>Windowed Watchdog Timer Enable.</description> 9577 <bitOffset>8</bitOffset> 9578 <bitWidth>1</bitWidth> 9579 <enumeratedValues> 9580 <enumeratedValue> 9581 <name>dis</name> 9582 <description>Disable.</description> 9583 <value>0</value> 9584 </enumeratedValue> 9585 <enumeratedValue> 9586 <name>en</name> 9587 <description>Enable.</description> 9588 <value>1</value> 9589 </enumeratedValue> 9590 </enumeratedValues> 9591 </field> 9592 <field> 9593 <name>INT_LATE</name> 9594 <description>Windowed Watchdog Timer Interrupt Flag Too Late.</description> 9595 <bitOffset>9</bitOffset> 9596 <bitWidth>1</bitWidth> 9597 <enumeratedValues> 9598 <usage>read-write</usage> 9599 <enumeratedValue> 9600 <name>inactive</name> 9601 <description>No interrupt is pending.</description> 9602 <value>0</value> 9603 </enumeratedValue> 9604 <enumeratedValue> 9605 <name>pending</name> 9606 <description>An interrupt is pending.</description> 9607 <value>1</value> 9608 </enumeratedValue> 9609 </enumeratedValues> 9610 </field> 9611 <field> 9612 <name>WDT_INT_EN</name> 9613 <description>Windowed Watchdog Timer Interrupt Enable.</description> 9614 <bitOffset>10</bitOffset> 9615 <bitWidth>1</bitWidth> 9616 <enumeratedValues> 9617 <enumeratedValue> 9618 <name>dis</name> 9619 <description>Disable.</description> 9620 <value>0</value> 9621 </enumeratedValue> 9622 <enumeratedValue> 9623 <name>en</name> 9624 <description>Enable.</description> 9625 <value>1</value> 9626 </enumeratedValue> 9627 </enumeratedValues> 9628 </field> 9629 <field> 9630 <name>WDT_RST_EN</name> 9631 <description>Windowed Watchdog Timer Reset Enable.</description> 9632 <bitOffset>11</bitOffset> 9633 <bitWidth>1</bitWidth> 9634 <enumeratedValues> 9635 <enumeratedValue> 9636 <name>dis</name> 9637 <description>Disable.</description> 9638 <value>0</value> 9639 </enumeratedValue> 9640 <enumeratedValue> 9641 <name>en</name> 9642 <description>Enable.</description> 9643 <value>1</value> 9644 </enumeratedValue> 9645 </enumeratedValues> 9646 </field> 9647 <field> 9648 <name>INT_EARLY</name> 9649 <description>Windowed Watchdog Timer Interrupt Flag Too Soon.</description> 9650 <bitOffset>12</bitOffset> 9651 <bitWidth>1</bitWidth> 9652 <enumeratedValues> 9653 <usage>read-write</usage> 9654 <enumeratedValue> 9655 <name>inactive</name> 9656 <description>No interrupt is pending.</description> 9657 <value>0</value> 9658 </enumeratedValue> 9659 <enumeratedValue> 9660 <name>pending</name> 9661 <description>An interrupt is pending.</description> 9662 <value>1</value> 9663 </enumeratedValue> 9664 </enumeratedValues> 9665 </field> 9666 <field> 9667 <name>INT_EARLY_VAL</name> 9668 <description>Windowed Watchdog Interrupt Lower Limit. Sets the number of WDTCLK cycles that establishes the lower boundary of the watchdog window. A windowed watchdog timer interrupt is generated (if enabled) if the CPU writes the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset.</description> 9669 <bitOffset>16</bitOffset> 9670 <bitWidth>4</bitWidth> 9671 <enumeratedValues> 9672 <enumeratedValue> 9673 <name>wdt2pow31</name> 9674 <description>2**31 clock cycles.</description> 9675 <value>0</value> 9676 </enumeratedValue> 9677 <enumeratedValue> 9678 <name>wdt2pow30</name> 9679 <description>2**30 clock cycles.</description> 9680 <value>1</value> 9681 </enumeratedValue> 9682 <enumeratedValue> 9683 <name>wdt2pow29</name> 9684 <description>2**29 clock cycles.</description> 9685 <value>2</value> 9686 </enumeratedValue> 9687 <enumeratedValue> 9688 <name>wdt2pow28</name> 9689 <description>2**28 clock cycles.</description> 9690 <value>3</value> 9691 </enumeratedValue> 9692 <enumeratedValue> 9693 <name>wdt2pow27</name> 9694 <description>2^27 clock cycles.</description> 9695 <value>4</value> 9696 </enumeratedValue> 9697 <enumeratedValue> 9698 <name>wdt2pow26</name> 9699 <description>2**26 clock cycles.</description> 9700 <value>5</value> 9701 </enumeratedValue> 9702 <enumeratedValue> 9703 <name>wdt2pow25</name> 9704 <description>2**25 clock cycles.</description> 9705 <value>6</value> 9706 </enumeratedValue> 9707 <enumeratedValue> 9708 <name>wdt2pow24</name> 9709 <description>2**24 clock cycles.</description> 9710 <value>7</value> 9711 </enumeratedValue> 9712 <enumeratedValue> 9713 <name>wdt2pow23</name> 9714 <description>2**23 clock cycles.</description> 9715 <value>8</value> 9716 </enumeratedValue> 9717 <enumeratedValue> 9718 <name>wdt2pow22</name> 9719 <description>2**22 clock cycles.</description> 9720 <value>9</value> 9721 </enumeratedValue> 9722 <enumeratedValue> 9723 <name>wdt2pow21</name> 9724 <description>2**21 clock cycles.</description> 9725 <value>10</value> 9726 </enumeratedValue> 9727 <enumeratedValue> 9728 <name>wdt2pow20</name> 9729 <description>2**20 clock cycles.</description> 9730 <value>11</value> 9731 </enumeratedValue> 9732 <enumeratedValue> 9733 <name>wdt2pow19</name> 9734 <description>2**19 clock cycles.</description> 9735 <value>12</value> 9736 </enumeratedValue> 9737 <enumeratedValue> 9738 <name>wdt2pow18</name> 9739 <description>2**18 clock cycles.</description> 9740 <value>13</value> 9741 </enumeratedValue> 9742 <enumeratedValue> 9743 <name>wdt2pow17</name> 9744 <description>2**17 clock cycles.</description> 9745 <value>14</value> 9746 </enumeratedValue> 9747 <enumeratedValue> 9748 <name>wdt2pow16</name> 9749 <description>2**16 clock cycles.</description> 9750 <value>15</value> 9751 </enumeratedValue> 9752 </enumeratedValues> 9753 </field> 9754 <field> 9755 <name>RST_EARLY_VAL</name> 9756 <description>Windowed Watchdog Reset Lower Limit. Sets the number of WDTCLK cycles that establishes the lower boundary of the watchdog window. A system reset occurs (if enabled) if the CPU writes the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset.</description> 9757 <bitOffset>20</bitOffset> 9758 <bitWidth>4</bitWidth> 9759 <enumeratedValues> 9760 <enumeratedValue> 9761 <name>wdt2pow31</name> 9762 <description>2**31 clock cycles.</description> 9763 <value>0</value> 9764 </enumeratedValue> 9765 <enumeratedValue> 9766 <name>wdt2pow30</name> 9767 <description>2**30 clock cycles.</description> 9768 <value>1</value> 9769 </enumeratedValue> 9770 <enumeratedValue> 9771 <name>wdt2pow29</name> 9772 <description>2**29 clock cycles.</description> 9773 <value>2</value> 9774 </enumeratedValue> 9775 <enumeratedValue> 9776 <name>wdt2pow28</name> 9777 <description>2**28 clock cycles.</description> 9778 <value>3</value> 9779 </enumeratedValue> 9780 <enumeratedValue> 9781 <name>wdt2pow27</name> 9782 <description>2^27 clock cycles.</description> 9783 <value>4</value> 9784 </enumeratedValue> 9785 <enumeratedValue> 9786 <name>wdt2pow26</name> 9787 <description>2**26 clock cycles.</description> 9788 <value>5</value> 9789 </enumeratedValue> 9790 <enumeratedValue> 9791 <name>wdt2pow25</name> 9792 <description>2**25 clock cycles.</description> 9793 <value>6</value> 9794 </enumeratedValue> 9795 <enumeratedValue> 9796 <name>wdt2pow24</name> 9797 <description>2**24 clock cycles.</description> 9798 <value>7</value> 9799 </enumeratedValue> 9800 <enumeratedValue> 9801 <name>wdt2pow23</name> 9802 <description>2**23 clock cycles.</description> 9803 <value>8</value> 9804 </enumeratedValue> 9805 <enumeratedValue> 9806 <name>wdt2pow22</name> 9807 <description>2**22 clock cycles.</description> 9808 <value>9</value> 9809 </enumeratedValue> 9810 <enumeratedValue> 9811 <name>wdt2pow21</name> 9812 <description>2**21 clock cycles.</description> 9813 <value>10</value> 9814 </enumeratedValue> 9815 <enumeratedValue> 9816 <name>wdt2pow20</name> 9817 <description>2**20 clock cycles.</description> 9818 <value>11</value> 9819 </enumeratedValue> 9820 <enumeratedValue> 9821 <name>wdt2pow19</name> 9822 <description>2**19 clock cycles.</description> 9823 <value>12</value> 9824 </enumeratedValue> 9825 <enumeratedValue> 9826 <name>wdt2pow18</name> 9827 <description>2**18 clock cycles.</description> 9828 <value>13</value> 9829 </enumeratedValue> 9830 <enumeratedValue> 9831 <name>wdt2pow17</name> 9832 <description>2**17 clock cycles.</description> 9833 <value>14</value> 9834 </enumeratedValue> 9835 <enumeratedValue> 9836 <name>wdt2pow16</name> 9837 <description>2**16 clock cycles.</description> 9838 <value>15</value> 9839 </enumeratedValue> 9840 </enumeratedValues> 9841 </field> 9842 <field> 9843 <name>CLKRDY_IE</name> 9844 <description>Switch Ready Interrupt Enable. Fires an interrupt when it is safe to swithc the clock.</description> 9845 <bitOffset>27</bitOffset> 9846 <bitWidth>1</bitWidth> 9847 </field> 9848 <field> 9849 <name>CLKRDY</name> 9850 <description>Clock Status.</description> 9851 <bitOffset>28</bitOffset> 9852 <bitWidth>1</bitWidth> 9853 </field> 9854 <field> 9855 <name>WIN_EN</name> 9856 <description>Enables the Windowed Watchdog Function.</description> 9857 <bitOffset>29</bitOffset> 9858 <bitWidth>1</bitWidth> 9859 <enumeratedValues> 9860 <enumeratedValue> 9861 <name>dis</name> 9862 <description>Windowed Mode Disabled (i.e. Compatibility Mode).</description> 9863 <value>0</value> 9864 </enumeratedValue> 9865 <enumeratedValue> 9866 <name>en</name> 9867 <description>Windowed Mode Enabled.</description> 9868 <value>1</value> 9869 </enumeratedValue> 9870 </enumeratedValues> 9871 </field> 9872 <field> 9873 <name>RST_EARLY</name> 9874 <description>Windowed Watchdog Timer Reset Flag Too Soon.</description> 9875 <bitOffset>30</bitOffset> 9876 <bitWidth>1</bitWidth> 9877 <enumeratedValues> 9878 <usage>read-write</usage> 9879 <enumeratedValue> 9880 <name>noEvent</name> 9881 <description>The event has not occurred.</description> 9882 <value>0</value> 9883 </enumeratedValue> 9884 <enumeratedValue> 9885 <name>occurred</name> 9886 <description>The event has occurred.</description> 9887 <value>1</value> 9888 </enumeratedValue> 9889 </enumeratedValues> 9890 </field> 9891 <field> 9892 <name>RST_LATE</name> 9893 <description>Windowed Watchdog Timer Reset Flag Too Late.</description> 9894 <bitOffset>31</bitOffset> 9895 <bitWidth>1</bitWidth> 9896 <enumeratedValues> 9897 <usage>read-write</usage> 9898 <enumeratedValue> 9899 <name>noEvent</name> 9900 <description>The event has not occurred.</description> 9901 <value>0</value> 9902 </enumeratedValue> 9903 <enumeratedValue> 9904 <name>occurred</name> 9905 <description>The event has occurred.</description> 9906 <value>1</value> 9907 </enumeratedValue> 9908 </enumeratedValues> 9909 </field> 9910 </fields> 9911 </register> 9912 <register> 9913 <name>RST</name> 9914 <description>Windowed Watchdog Timer Reset Register.</description> 9915 <addressOffset>0x04</addressOffset> 9916 <access>write-only</access> 9917 <fields> 9918 <field> 9919 <name>RESET</name> 9920 <description>Writing the watchdog counter 'reset sequence' to this register resets the watchdog counter. If the watchdog count exceeds INT_PERIOD_UPPER_LIMIT then a watchdog interrupt will occur, if enabled. If the watchdog count exceeds RST_PERIOD_UPPER_LIMIT then a watchdog reset will occur, if enabled.</description> 9921 <bitOffset>0</bitOffset> 9922 <bitWidth>8</bitWidth> 9923 <enumeratedValues> 9924 <enumeratedValue> 9925 <name>seq0</name> 9926 <description>The first value to be written to reset the WDT.</description> 9927 <value>0x000000A5</value> 9928 </enumeratedValue> 9929 <enumeratedValue> 9930 <name>seq1</name> 9931 <description>The second value to be written to reset the WDT.</description> 9932 <value>0x0000005A</value> 9933 </enumeratedValue> 9934 </enumeratedValues> 9935 </field> 9936 </fields> 9937 </register> 9938 <register> 9939 <name>CLKSEL</name> 9940 <description>Windowed Watchdog Timer Clock Select Register.</description> 9941 <addressOffset>0x08</addressOffset> 9942 <access>read-write</access> 9943 <fields> 9944 <field> 9945 <name>SOURCE</name> 9946 <description>WWDT Clock Selection Register.</description> 9947 <bitOffset>0</bitOffset> 9948 <bitWidth>3</bitWidth> 9949 </field> 9950 </fields> 9951 </register> 9952 <register> 9953 <name>CNT</name> 9954 <description>Windowed Watchdog Timer Count Register.</description> 9955 <addressOffset>0x0C</addressOffset> 9956 <access>read-only</access> 9957 <fields> 9958 <field> 9959 <name>COUNT</name> 9960 <description>Current Value of the Windowed Watchdog Timer Counter.</description> 9961 <bitOffset>0</bitOffset> 9962 <bitWidth>32</bitWidth> 9963 </field> 9964 </fields> 9965 </register> 9966 </registers> 9967 </peripheral> 9968<!--WDT Windowed Watchdog Timer--> 9969 <peripheral derivedFrom="WDT"> 9970 <name>WDT1</name> 9971 <description>Windowed Watchdog Timer 1</description> 9972 <baseAddress>0x40003400</baseAddress> 9973 <interrupt> 9974 <name>WDT1</name> 9975 <description>WDT1 IRQ</description> 9976 <value>57</value> 9977 </interrupt> 9978 </peripheral> 9979<!--WDT1 Windowed Watchdog Timer 1--> 9980 </peripherals> 9981</device> 9982
