1 /** 2 * @file i2c_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup i2c_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32675_INCLUDE_I2C_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32675_INCLUDE_I2C_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup i2c 67 * @defgroup i2c_registers I2C_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module. 69 * @details Inter-Integrated Circuit. 70 */ 71 72 /** 73 * @ingroup i2c_registers 74 * Structure type to access the I2C Registers. 75 */ 76 typedef struct { 77 __IO uint32_t ctrl; /**< <tt>\b 0x00:</tt> I2C CTRL Register */ 78 __IO uint32_t status; /**< <tt>\b 0x04:</tt> I2C STATUS Register */ 79 __IO uint32_t intfl0; /**< <tt>\b 0x08:</tt> I2C INTFL0 Register */ 80 __IO uint32_t inten0; /**< <tt>\b 0x0C:</tt> I2C INTEN0 Register */ 81 __IO uint32_t intfl1; /**< <tt>\b 0x10:</tt> I2C INTFL1 Register */ 82 __IO uint32_t inten1; /**< <tt>\b 0x14:</tt> I2C INTEN1 Register */ 83 __IO uint32_t fifolen; /**< <tt>\b 0x18:</tt> I2C FIFOLEN Register */ 84 __IO uint32_t rxctrl0; /**< <tt>\b 0x1C:</tt> I2C RXCTRL0 Register */ 85 __IO uint32_t rxctrl1; /**< <tt>\b 0x20:</tt> I2C RXCTRL1 Register */ 86 __IO uint32_t txctrl0; /**< <tt>\b 0x24:</tt> I2C TXCTRL0 Register */ 87 __IO uint32_t txctrl1; /**< <tt>\b 0x28:</tt> I2C TXCTRL1 Register */ 88 __IO uint32_t fifo; /**< <tt>\b 0x2C:</tt> I2C FIFO Register */ 89 __IO uint32_t mstctrl; /**< <tt>\b 0x30:</tt> I2C MSTCTRL Register */ 90 __IO uint32_t clklo; /**< <tt>\b 0x34:</tt> I2C CLKLO Register */ 91 __IO uint32_t clkhi; /**< <tt>\b 0x38:</tt> I2C CLKHI Register */ 92 __IO uint32_t hsclk; /**< <tt>\b 0x3C:</tt> I2C HSCLK Register */ 93 __IO uint32_t timeout; /**< <tt>\b 0x40:</tt> I2C TIMEOUT Register */ 94 __IO uint32_t slave; /**< <tt>\b 0x44:</tt> I2C SLAVE Register */ 95 __IO uint32_t dma; /**< <tt>\b 0x48:</tt> I2C DMA Register */ 96 } mxc_i2c_regs_t; 97 98 /* Register offsets for module I2C */ 99 /** 100 * @ingroup i2c_registers 101 * @defgroup I2C_Register_Offsets Register Offsets 102 * @brief I2C Peripheral Register Offsets from the I2C Base Peripheral Address. 103 * @{ 104 */ 105 #define MXC_R_I2C_CTRL ((uint32_t)0x00000000UL) /**< Offset from I2C Base Address: <tt> 0x0000</tt> */ 106 #define MXC_R_I2C_STATUS ((uint32_t)0x00000004UL) /**< Offset from I2C Base Address: <tt> 0x0004</tt> */ 107 #define MXC_R_I2C_INTFL0 ((uint32_t)0x00000008UL) /**< Offset from I2C Base Address: <tt> 0x0008</tt> */ 108 #define MXC_R_I2C_INTEN0 ((uint32_t)0x0000000CUL) /**< Offset from I2C Base Address: <tt> 0x000C</tt> */ 109 #define MXC_R_I2C_INTFL1 ((uint32_t)0x00000010UL) /**< Offset from I2C Base Address: <tt> 0x0010</tt> */ 110 #define MXC_R_I2C_INTEN1 ((uint32_t)0x00000014UL) /**< Offset from I2C Base Address: <tt> 0x0014</tt> */ 111 #define MXC_R_I2C_FIFOLEN ((uint32_t)0x00000018UL) /**< Offset from I2C Base Address: <tt> 0x0018</tt> */ 112 #define MXC_R_I2C_RXCTRL0 ((uint32_t)0x0000001CUL) /**< Offset from I2C Base Address: <tt> 0x001C</tt> */ 113 #define MXC_R_I2C_RXCTRL1 ((uint32_t)0x00000020UL) /**< Offset from I2C Base Address: <tt> 0x0020</tt> */ 114 #define MXC_R_I2C_TXCTRL0 ((uint32_t)0x00000024UL) /**< Offset from I2C Base Address: <tt> 0x0024</tt> */ 115 #define MXC_R_I2C_TXCTRL1 ((uint32_t)0x00000028UL) /**< Offset from I2C Base Address: <tt> 0x0028</tt> */ 116 #define MXC_R_I2C_FIFO ((uint32_t)0x0000002CUL) /**< Offset from I2C Base Address: <tt> 0x002C</tt> */ 117 #define MXC_R_I2C_MSTCTRL ((uint32_t)0x00000030UL) /**< Offset from I2C Base Address: <tt> 0x0030</tt> */ 118 #define MXC_R_I2C_CLKLO ((uint32_t)0x00000034UL) /**< Offset from I2C Base Address: <tt> 0x0034</tt> */ 119 #define MXC_R_I2C_CLKHI ((uint32_t)0x00000038UL) /**< Offset from I2C Base Address: <tt> 0x0038</tt> */ 120 #define MXC_R_I2C_HSCLK ((uint32_t)0x0000003CUL) /**< Offset from I2C Base Address: <tt> 0x003C</tt> */ 121 #define MXC_R_I2C_TIMEOUT ((uint32_t)0x00000040UL) /**< Offset from I2C Base Address: <tt> 0x0040</tt> */ 122 #define MXC_R_I2C_SLAVE ((uint32_t)0x00000044UL) /**< Offset from I2C Base Address: <tt> 0x0044</tt> */ 123 #define MXC_R_I2C_DMA ((uint32_t)0x00000048UL) /**< Offset from I2C Base Address: <tt> 0x0048</tt> */ 124 /**@} end of group i2c_registers */ 125 126 /** 127 * @ingroup i2c_registers 128 * @defgroup I2C_CTRL I2C_CTRL 129 * @brief Control Register0. 130 * @{ 131 */ 132 #define MXC_F_I2C_CTRL_EN_POS 0 /**< CTRL_EN Position */ 133 #define MXC_F_I2C_CTRL_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_EN_POS)) /**< CTRL_EN Mask */ 134 135 #define MXC_F_I2C_CTRL_MST_MODE_POS 1 /**< CTRL_MST_MODE Position */ 136 #define MXC_F_I2C_CTRL_MST_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_MST_MODE_POS)) /**< CTRL_MST_MODE Mask */ 137 138 #define MXC_F_I2C_CTRL_GC_ADDR_EN_POS 2 /**< CTRL_GC_ADDR_EN Position */ 139 #define MXC_F_I2C_CTRL_GC_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_GC_ADDR_EN_POS)) /**< CTRL_GC_ADDR_EN Mask */ 140 141 #define MXC_F_I2C_CTRL_IRXM_EN_POS 3 /**< CTRL_IRXM_EN Position */ 142 #define MXC_F_I2C_CTRL_IRXM_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_IRXM_EN_POS)) /**< CTRL_IRXM_EN Mask */ 143 144 #define MXC_F_I2C_CTRL_IRXM_ACK_POS 4 /**< CTRL_IRXM_ACK Position */ 145 #define MXC_F_I2C_CTRL_IRXM_ACK ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_IRXM_ACK_POS)) /**< CTRL_IRXM_ACK Mask */ 146 147 #define MXC_F_I2C_CTRL_SCL_OUT_POS 6 /**< CTRL_SCL_OUT Position */ 148 #define MXC_F_I2C_CTRL_SCL_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_OUT_POS)) /**< CTRL_SCL_OUT Mask */ 149 150 #define MXC_F_I2C_CTRL_SDA_OUT_POS 7 /**< CTRL_SDA_OUT Position */ 151 #define MXC_F_I2C_CTRL_SDA_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_OUT_POS)) /**< CTRL_SDA_OUT Mask */ 152 153 #define MXC_F_I2C_CTRL_SCL_POS 8 /**< CTRL_SCL Position */ 154 #define MXC_F_I2C_CTRL_SCL ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_POS)) /**< CTRL_SCL Mask */ 155 156 #define MXC_F_I2C_CTRL_SDA_POS 9 /**< CTRL_SDA Position */ 157 #define MXC_F_I2C_CTRL_SDA ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_POS)) /**< CTRL_SDA Mask */ 158 159 #define MXC_F_I2C_CTRL_BB_MODE_POS 10 /**< CTRL_BB_MODE Position */ 160 #define MXC_F_I2C_CTRL_BB_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_BB_MODE_POS)) /**< CTRL_BB_MODE Mask */ 161 162 #define MXC_F_I2C_CTRL_READ_POS 11 /**< CTRL_READ Position */ 163 #define MXC_F_I2C_CTRL_READ ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_READ_POS)) /**< CTRL_READ Mask */ 164 165 #define MXC_F_I2C_CTRL_CLKSTR_DIS_POS 12 /**< CTRL_CLKSTR_DIS Position */ 166 #define MXC_F_I2C_CTRL_CLKSTR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_CLKSTR_DIS_POS)) /**< CTRL_CLKSTR_DIS Mask */ 167 168 #define MXC_F_I2C_CTRL_ONE_MST_MODE_POS 13 /**< CTRL_ONE_MST_MODE Position */ 169 #define MXC_F_I2C_CTRL_ONE_MST_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_ONE_MST_MODE_POS)) /**< CTRL_ONE_MST_MODE Mask */ 170 171 #define MXC_F_I2C_CTRL_HS_EN_POS 15 /**< CTRL_HS_EN Position */ 172 #define MXC_F_I2C_CTRL_HS_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_HS_EN_POS)) /**< CTRL_HS_EN Mask */ 173 174 /**@} end of group I2C_CTRL_Register */ 175 176 /** 177 * @ingroup i2c_registers 178 * @defgroup I2C_STATUS I2C_STATUS 179 * @brief Status Register. 180 * @{ 181 */ 182 #define MXC_F_I2C_STATUS_BUSY_POS 0 /**< STATUS_BUSY Position */ 183 #define MXC_F_I2C_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */ 184 185 #define MXC_F_I2C_STATUS_RX_EM_POS 1 /**< STATUS_RX_EM Position */ 186 #define MXC_F_I2C_STATUS_RX_EM ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_EM_POS)) /**< STATUS_RX_EM Mask */ 187 188 #define MXC_F_I2C_STATUS_RX_FULL_POS 2 /**< STATUS_RX_FULL Position */ 189 #define MXC_F_I2C_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */ 190 191 #define MXC_F_I2C_STATUS_TX_EM_POS 3 /**< STATUS_TX_EM Position */ 192 #define MXC_F_I2C_STATUS_TX_EM ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_EM_POS)) /**< STATUS_TX_EM Mask */ 193 194 #define MXC_F_I2C_STATUS_TX_FULL_POS 4 /**< STATUS_TX_FULL Position */ 195 #define MXC_F_I2C_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */ 196 197 #define MXC_F_I2C_STATUS_MST_BUSY_POS 5 /**< STATUS_MST_BUSY Position */ 198 #define MXC_F_I2C_STATUS_MST_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_MST_BUSY_POS)) /**< STATUS_MST_BUSY Mask */ 199 200 /**@} end of group I2C_STATUS_Register */ 201 202 /** 203 * @ingroup i2c_registers 204 * @defgroup I2C_INTFL0 I2C_INTFL0 205 * @brief Interrupt Status Register. 206 * @{ 207 */ 208 #define MXC_F_I2C_INTFL0_DONE_POS 0 /**< INTFL0_DONE Position */ 209 #define MXC_F_I2C_INTFL0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DONE_POS)) /**< INTFL0_DONE Mask */ 210 211 #define MXC_F_I2C_INTFL0_IRXM_POS 1 /**< INTFL0_IRXM Position */ 212 #define MXC_F_I2C_INTFL0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_IRXM_POS)) /**< INTFL0_IRXM Mask */ 213 214 #define MXC_F_I2C_INTFL0_GC_ADDR_MATCH_POS 2 /**< INTFL0_GC_ADDR_MATCH Position */ 215 #define MXC_F_I2C_INTFL0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_GC_ADDR_MATCH_POS)) /**< INTFL0_GC_ADDR_MATCH Mask */ 216 217 #define MXC_F_I2C_INTFL0_ADDR_MATCH_POS 3 /**< INTFL0_ADDR_MATCH Position */ 218 #define MXC_F_I2C_INTFL0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADDR_MATCH_POS)) /**< INTFL0_ADDR_MATCH Mask */ 219 220 #define MXC_F_I2C_INTFL0_RX_THD_POS 4 /**< INTFL0_RX_THD Position */ 221 #define MXC_F_I2C_INTFL0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_RX_THD_POS)) /**< INTFL0_RX_THD Mask */ 222 223 #define MXC_F_I2C_INTFL0_TX_THD_POS 5 /**< INTFL0_TX_THD Position */ 224 #define MXC_F_I2C_INTFL0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TX_THD_POS)) /**< INTFL0_TX_THD Mask */ 225 226 #define MXC_F_I2C_INTFL0_STOP_POS 6 /**< INTFL0_STOP Position */ 227 #define MXC_F_I2C_INTFL0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STOP_POS)) /**< INTFL0_STOP Mask */ 228 229 #define MXC_F_I2C_INTFL0_ADDR_ACK_POS 7 /**< INTFL0_ADDR_ACK Position */ 230 #define MXC_F_I2C_INTFL0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADDR_ACK_POS)) /**< INTFL0_ADDR_ACK Mask */ 231 232 #define MXC_F_I2C_INTFL0_ARB_ERR_POS 8 /**< INTFL0_ARB_ERR Position */ 233 #define MXC_F_I2C_INTFL0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ARB_ERR_POS)) /**< INTFL0_ARB_ERR Mask */ 234 235 #define MXC_F_I2C_INTFL0_TO_ERR_POS 9 /**< INTFL0_TO_ERR Position */ 236 #define MXC_F_I2C_INTFL0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TO_ERR_POS)) /**< INTFL0_TO_ERR Mask */ 237 238 #define MXC_F_I2C_INTFL0_ADDR_NACK_ERR_POS 10 /**< INTFL0_ADDR_NACK_ERR Position */ 239 #define MXC_F_I2C_INTFL0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADDR_NACK_ERR_POS)) /**< INTFL0_ADDR_NACK_ERR Mask */ 240 241 #define MXC_F_I2C_INTFL0_DATA_ERR_POS 11 /**< INTFL0_DATA_ERR Position */ 242 #define MXC_F_I2C_INTFL0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DATA_ERR_POS)) /**< INTFL0_DATA_ERR Mask */ 243 244 #define MXC_F_I2C_INTFL0_DNR_ERR_POS 12 /**< INTFL0_DNR_ERR Position */ 245 #define MXC_F_I2C_INTFL0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DNR_ERR_POS)) /**< INTFL0_DNR_ERR Mask */ 246 247 #define MXC_F_I2C_INTFL0_START_ERR_POS 13 /**< INTFL0_START_ERR Position */ 248 #define MXC_F_I2C_INTFL0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_START_ERR_POS)) /**< INTFL0_START_ERR Mask */ 249 250 #define MXC_F_I2C_INTFL0_STOP_ERR_POS 14 /**< INTFL0_STOP_ERR Position */ 251 #define MXC_F_I2C_INTFL0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STOP_ERR_POS)) /**< INTFL0_STOP_ERR Mask */ 252 253 #define MXC_F_I2C_INTFL0_TX_LOCKOUT_POS 15 /**< INTFL0_TX_LOCKOUT Position */ 254 #define MXC_F_I2C_INTFL0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TX_LOCKOUT_POS)) /**< INTFL0_TX_LOCKOUT Mask */ 255 256 #define MXC_F_I2C_INTFL0_MAMI_POS 16 /**< INTFL0_MAMI Position */ 257 #define MXC_F_I2C_INTFL0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_INTFL0_MAMI_POS)) /**< INTFL0_MAMI Mask */ 258 259 #define MXC_F_I2C_INTFL0_RD_ADDR_MATCH_POS 22 /**< INTFL0_RD_ADDR_MATCH Position */ 260 #define MXC_F_I2C_INTFL0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_RD_ADDR_MATCH_POS)) /**< INTFL0_RD_ADDR_MATCH Mask */ 261 262 #define MXC_F_I2C_INTFL0_WR_ADDR_MATCH_POS 23 /**< INTFL0_WR_ADDR_MATCH Position */ 263 #define MXC_F_I2C_INTFL0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_WR_ADDR_MATCH_POS)) /**< INTFL0_WR_ADDR_MATCH Mask */ 264 265 /**@} end of group I2C_INTFL0_Register */ 266 267 /** 268 * @ingroup i2c_registers 269 * @defgroup I2C_INTEN0 I2C_INTEN0 270 * @brief Interrupt Enable Register. 271 * @{ 272 */ 273 #define MXC_F_I2C_INTEN0_DONE_POS 0 /**< INTEN0_DONE Position */ 274 #define MXC_F_I2C_INTEN0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DONE_POS)) /**< INTEN0_DONE Mask */ 275 276 #define MXC_F_I2C_INTEN0_IRXM_POS 1 /**< INTEN0_IRXM Position */ 277 #define MXC_F_I2C_INTEN0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_IRXM_POS)) /**< INTEN0_IRXM Mask */ 278 279 #define MXC_F_I2C_INTEN0_GC_ADDR_MATCH_POS 2 /**< INTEN0_GC_ADDR_MATCH Position */ 280 #define MXC_F_I2C_INTEN0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_GC_ADDR_MATCH_POS)) /**< INTEN0_GC_ADDR_MATCH Mask */ 281 282 #define MXC_F_I2C_INTEN0_ADDR_MATCH_POS 3 /**< INTEN0_ADDR_MATCH Position */ 283 #define MXC_F_I2C_INTEN0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADDR_MATCH_POS)) /**< INTEN0_ADDR_MATCH Mask */ 284 285 #define MXC_F_I2C_INTEN0_RX_THD_POS 4 /**< INTEN0_RX_THD Position */ 286 #define MXC_F_I2C_INTEN0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_RX_THD_POS)) /**< INTEN0_RX_THD Mask */ 287 288 #define MXC_F_I2C_INTEN0_TX_THD_POS 5 /**< INTEN0_TX_THD Position */ 289 #define MXC_F_I2C_INTEN0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TX_THD_POS)) /**< INTEN0_TX_THD Mask */ 290 291 #define MXC_F_I2C_INTEN0_STOP_POS 6 /**< INTEN0_STOP Position */ 292 #define MXC_F_I2C_INTEN0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOP_POS)) /**< INTEN0_STOP Mask */ 293 294 #define MXC_F_I2C_INTEN0_ADDR_ACK_POS 7 /**< INTEN0_ADDR_ACK Position */ 295 #define MXC_F_I2C_INTEN0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADDR_ACK_POS)) /**< INTEN0_ADDR_ACK Mask */ 296 297 #define MXC_F_I2C_INTEN0_ARB_ERR_POS 8 /**< INTEN0_ARB_ERR Position */ 298 #define MXC_F_I2C_INTEN0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ARB_ERR_POS)) /**< INTEN0_ARB_ERR Mask */ 299 300 #define MXC_F_I2C_INTEN0_TO_ERR_POS 9 /**< INTEN0_TO_ERR Position */ 301 #define MXC_F_I2C_INTEN0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TO_ERR_POS)) /**< INTEN0_TO_ERR Mask */ 302 303 #define MXC_F_I2C_INTEN0_ADDR_NACK_ERR_POS 10 /**< INTEN0_ADDR_NACK_ERR Position */ 304 #define MXC_F_I2C_INTEN0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADDR_NACK_ERR_POS)) /**< INTEN0_ADDR_NACK_ERR Mask */ 305 306 #define MXC_F_I2C_INTEN0_DATA_ERR_POS 11 /**< INTEN0_DATA_ERR Position */ 307 #define MXC_F_I2C_INTEN0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DATA_ERR_POS)) /**< INTEN0_DATA_ERR Mask */ 308 309 #define MXC_F_I2C_INTEN0_DNR_ERR_POS 12 /**< INTEN0_DNR_ERR Position */ 310 #define MXC_F_I2C_INTEN0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DNR_ERR_POS)) /**< INTEN0_DNR_ERR Mask */ 311 312 #define MXC_F_I2C_INTEN0_START_ERR_POS 13 /**< INTEN0_START_ERR Position */ 313 #define MXC_F_I2C_INTEN0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_START_ERR_POS)) /**< INTEN0_START_ERR Mask */ 314 315 #define MXC_F_I2C_INTEN0_STOP_ERR_POS 14 /**< INTEN0_STOP_ERR Position */ 316 #define MXC_F_I2C_INTEN0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOP_ERR_POS)) /**< INTEN0_STOP_ERR Mask */ 317 318 #define MXC_F_I2C_INTEN0_TX_LOCKOUT_POS 15 /**< INTEN0_TX_LOCKOUT Position */ 319 #define MXC_F_I2C_INTEN0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TX_LOCKOUT_POS)) /**< INTEN0_TX_LOCKOUT Mask */ 320 321 #define MXC_F_I2C_INTEN0_MAMI_POS 16 /**< INTEN0_MAMI Position */ 322 #define MXC_F_I2C_INTEN0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_INTEN0_MAMI_POS)) /**< INTEN0_MAMI Mask */ 323 324 #define MXC_F_I2C_INTEN0_RD_ADDR_MATCH_POS 22 /**< INTEN0_RD_ADDR_MATCH Position */ 325 #define MXC_F_I2C_INTEN0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_RD_ADDR_MATCH_POS)) /**< INTEN0_RD_ADDR_MATCH Mask */ 326 327 #define MXC_F_I2C_INTEN0_WR_ADDR_MATCH_POS 23 /**< INTEN0_WR_ADDR_MATCH Position */ 328 #define MXC_F_I2C_INTEN0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_WR_ADDR_MATCH_POS)) /**< INTEN0_WR_ADDR_MATCH Mask */ 329 330 /**@} end of group I2C_INTEN0_Register */ 331 332 /** 333 * @ingroup i2c_registers 334 * @defgroup I2C_INTFL1 I2C_INTFL1 335 * @brief Interrupt Status Register 1. 336 * @{ 337 */ 338 #define MXC_F_I2C_INTFL1_RX_OV_POS 0 /**< INTFL1_RX_OV Position */ 339 #define MXC_F_I2C_INTFL1_RX_OV ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_RX_OV_POS)) /**< INTFL1_RX_OV Mask */ 340 341 #define MXC_F_I2C_INTFL1_TX_UN_POS 1 /**< INTFL1_TX_UN Position */ 342 #define MXC_F_I2C_INTFL1_TX_UN ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_TX_UN_POS)) /**< INTFL1_TX_UN Mask */ 343 344 #define MXC_F_I2C_INTFL1_START_POS 2 /**< INTFL1_START Position */ 345 #define MXC_F_I2C_INTFL1_START ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_START_POS)) /**< INTFL1_START Mask */ 346 347 /**@} end of group I2C_INTFL1_Register */ 348 349 /** 350 * @ingroup i2c_registers 351 * @defgroup I2C_INTEN1 I2C_INTEN1 352 * @brief Interrupt Staus Register 1. 353 * @{ 354 */ 355 #define MXC_F_I2C_INTEN1_RX_OV_POS 0 /**< INTEN1_RX_OV Position */ 356 #define MXC_F_I2C_INTEN1_RX_OV ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_RX_OV_POS)) /**< INTEN1_RX_OV Mask */ 357 358 #define MXC_F_I2C_INTEN1_TX_UN_POS 1 /**< INTEN1_TX_UN Position */ 359 #define MXC_F_I2C_INTEN1_TX_UN ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_TX_UN_POS)) /**< INTEN1_TX_UN Mask */ 360 361 #define MXC_F_I2C_INTEN1_START_POS 2 /**< INTEN1_START Position */ 362 #define MXC_F_I2C_INTEN1_START ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_START_POS)) /**< INTEN1_START Mask */ 363 364 /**@} end of group I2C_INTEN1_Register */ 365 366 /** 367 * @ingroup i2c_registers 368 * @defgroup I2C_FIFOLEN I2C_FIFOLEN 369 * @brief FIFO Configuration Register. 370 * @{ 371 */ 372 #define MXC_F_I2C_FIFOLEN_RX_DEPTH_POS 0 /**< FIFOLEN_RX_DEPTH Position */ 373 #define MXC_F_I2C_FIFOLEN_RX_DEPTH ((uint32_t)(0xFFUL << MXC_F_I2C_FIFOLEN_RX_DEPTH_POS)) /**< FIFOLEN_RX_DEPTH Mask */ 374 375 #define MXC_F_I2C_FIFOLEN_TX_DEPTH_POS 8 /**< FIFOLEN_TX_DEPTH Position */ 376 #define MXC_F_I2C_FIFOLEN_TX_DEPTH ((uint32_t)(0xFFUL << MXC_F_I2C_FIFOLEN_TX_DEPTH_POS)) /**< FIFOLEN_TX_DEPTH Mask */ 377 378 /**@} end of group I2C_FIFOLEN_Register */ 379 380 /** 381 * @ingroup i2c_registers 382 * @defgroup I2C_RXCTRL0 I2C_RXCTRL0 383 * @brief Receive Control Register 0. 384 * @{ 385 */ 386 #define MXC_F_I2C_RXCTRL0_DNR_POS 0 /**< RXCTRL0_DNR Position */ 387 #define MXC_F_I2C_RXCTRL0_DNR ((uint32_t)(0x1UL << MXC_F_I2C_RXCTRL0_DNR_POS)) /**< RXCTRL0_DNR Mask */ 388 389 #define MXC_F_I2C_RXCTRL0_FLUSH_POS 7 /**< RXCTRL0_FLUSH Position */ 390 #define MXC_F_I2C_RXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_RXCTRL0_FLUSH_POS)) /**< RXCTRL0_FLUSH Mask */ 391 392 #define MXC_F_I2C_RXCTRL0_THD_LVL_POS 8 /**< RXCTRL0_THD_LVL Position */ 393 #define MXC_F_I2C_RXCTRL0_THD_LVL ((uint32_t)(0xFUL << MXC_F_I2C_RXCTRL0_THD_LVL_POS)) /**< RXCTRL0_THD_LVL Mask */ 394 395 /**@} end of group I2C_RXCTRL0_Register */ 396 397 /** 398 * @ingroup i2c_registers 399 * @defgroup I2C_RXCTRL1 I2C_RXCTRL1 400 * @brief Receive Control Register 1. 401 * @{ 402 */ 403 #define MXC_F_I2C_RXCTRL1_CNT_POS 0 /**< RXCTRL1_CNT Position */ 404 #define MXC_F_I2C_RXCTRL1_CNT ((uint32_t)(0xFFUL << MXC_F_I2C_RXCTRL1_CNT_POS)) /**< RXCTRL1_CNT Mask */ 405 406 #define MXC_F_I2C_RXCTRL1_LVL_POS 8 /**< RXCTRL1_LVL Position */ 407 #define MXC_F_I2C_RXCTRL1_LVL ((uint32_t)(0xFUL << MXC_F_I2C_RXCTRL1_LVL_POS)) /**< RXCTRL1_LVL Mask */ 408 409 /**@} end of group I2C_RXCTRL1_Register */ 410 411 /** 412 * @ingroup i2c_registers 413 * @defgroup I2C_TXCTRL0 I2C_TXCTRL0 414 * @brief Transmit Control Register 0. 415 * @{ 416 */ 417 #define MXC_F_I2C_TXCTRL0_PRELOAD_MODE_POS 0 /**< TXCTRL0_PRELOAD_MODE Position */ 418 #define MXC_F_I2C_TXCTRL0_PRELOAD_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_PRELOAD_MODE_POS)) /**< TXCTRL0_PRELOAD_MODE Mask */ 419 420 #define MXC_F_I2C_TXCTRL0_TX_READY_MODE_POS 1 /**< TXCTRL0_TX_READY_MODE Position */ 421 #define MXC_F_I2C_TXCTRL0_TX_READY_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_TX_READY_MODE_POS)) /**< TXCTRL0_TX_READY_MODE Mask */ 422 423 #define MXC_F_I2C_TXCTRL0_GC_ADDR_FLUSH_DIS_POS 2 /**< TXCTRL0_GC_ADDR_FLUSH_DIS Position */ 424 #define MXC_F_I2C_TXCTRL0_GC_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_GC_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_GC_ADDR_FLUSH_DIS Mask */ 425 426 #define MXC_F_I2C_TXCTRL0_WR_ADDR_FLUSH_DIS_POS 3 /**< TXCTRL0_WR_ADDR_FLUSH_DIS Position */ 427 #define MXC_F_I2C_TXCTRL0_WR_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_WR_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_WR_ADDR_FLUSH_DIS Mask */ 428 429 #define MXC_F_I2C_TXCTRL0_RD_ADDR_FLUSH_DIS_POS 4 /**< TXCTRL0_RD_ADDR_FLUSH_DIS Position */ 430 #define MXC_F_I2C_TXCTRL0_RD_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_RD_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_RD_ADDR_FLUSH_DIS Mask */ 431 432 #define MXC_F_I2C_TXCTRL0_NACK_FLUSH_DIS_POS 5 /**< TXCTRL0_NACK_FLUSH_DIS Position */ 433 #define MXC_F_I2C_TXCTRL0_NACK_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_NACK_FLUSH_DIS_POS)) /**< TXCTRL0_NACK_FLUSH_DIS Mask */ 434 435 #define MXC_F_I2C_TXCTRL0_FLUSH_POS 7 /**< TXCTRL0_FLUSH Position */ 436 #define MXC_F_I2C_TXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_FLUSH_POS)) /**< TXCTRL0_FLUSH Mask */ 437 438 #define MXC_F_I2C_TXCTRL0_THD_VAL_POS 8 /**< TXCTRL0_THD_VAL Position */ 439 #define MXC_F_I2C_TXCTRL0_THD_VAL ((uint32_t)(0xFUL << MXC_F_I2C_TXCTRL0_THD_VAL_POS)) /**< TXCTRL0_THD_VAL Mask */ 440 441 /**@} end of group I2C_TXCTRL0_Register */ 442 443 /** 444 * @ingroup i2c_registers 445 * @defgroup I2C_TXCTRL1 I2C_TXCTRL1 446 * @brief Transmit Control Register 1. 447 * @{ 448 */ 449 #define MXC_F_I2C_TXCTRL1_PRELOAD_RDY_POS 0 /**< TXCTRL1_PRELOAD_RDY Position */ 450 #define MXC_F_I2C_TXCTRL1_PRELOAD_RDY ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_PRELOAD_RDY_POS)) /**< TXCTRL1_PRELOAD_RDY Mask */ 451 452 #define MXC_F_I2C_TXCTRL1_LVL_POS 8 /**< TXCTRL1_LVL Position */ 453 #define MXC_F_I2C_TXCTRL1_LVL ((uint32_t)(0xFUL << MXC_F_I2C_TXCTRL1_LVL_POS)) /**< TXCTRL1_LVL Mask */ 454 455 /**@} end of group I2C_TXCTRL1_Register */ 456 457 /** 458 * @ingroup i2c_registers 459 * @defgroup I2C_FIFO I2C_FIFO 460 * @brief Data Register. 461 * @{ 462 */ 463 #define MXC_F_I2C_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ 464 #define MXC_F_I2C_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ 465 466 /**@} end of group I2C_FIFO_Register */ 467 468 /** 469 * @ingroup i2c_registers 470 * @defgroup I2C_MSTCTRL I2C_MSTCTRL 471 * @brief Master Control Register. 472 * @{ 473 */ 474 #define MXC_F_I2C_MSTCTRL_START_POS 0 /**< MSTCTRL_START Position */ 475 #define MXC_F_I2C_MSTCTRL_START ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_START_POS)) /**< MSTCTRL_START Mask */ 476 477 #define MXC_F_I2C_MSTCTRL_RESTART_POS 1 /**< MSTCTRL_RESTART Position */ 478 #define MXC_F_I2C_MSTCTRL_RESTART ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_RESTART_POS)) /**< MSTCTRL_RESTART Mask */ 479 480 #define MXC_F_I2C_MSTCTRL_STOP_POS 2 /**< MSTCTRL_STOP Position */ 481 #define MXC_F_I2C_MSTCTRL_STOP ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_STOP_POS)) /**< MSTCTRL_STOP Mask */ 482 483 #define MXC_F_I2C_MSTCTRL_EX_ADDR_EN_POS 7 /**< MSTCTRL_EX_ADDR_EN Position */ 484 #define MXC_F_I2C_MSTCTRL_EX_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_EX_ADDR_EN_POS)) /**< MSTCTRL_EX_ADDR_EN Mask */ 485 486 /**@} end of group I2C_MSTCTRL_Register */ 487 488 /** 489 * @ingroup i2c_registers 490 * @defgroup I2C_CLKLO I2C_CLKLO 491 * @brief Clock Low Register. 492 * @{ 493 */ 494 #define MXC_F_I2C_CLKLO_LO_POS 0 /**< CLKLO_LO Position */ 495 #define MXC_F_I2C_CLKLO_LO ((uint32_t)(0x1FFUL << MXC_F_I2C_CLKLO_LO_POS)) /**< CLKLO_LO Mask */ 496 497 /**@} end of group I2C_CLKLO_Register */ 498 499 /** 500 * @ingroup i2c_registers 501 * @defgroup I2C_CLKHI I2C_CLKHI 502 * @brief Clock high Register. 503 * @{ 504 */ 505 #define MXC_F_I2C_CLKHI_HI_POS 0 /**< CLKHI_HI Position */ 506 #define MXC_F_I2C_CLKHI_HI ((uint32_t)(0x1FFUL << MXC_F_I2C_CLKHI_HI_POS)) /**< CLKHI_HI Mask */ 507 508 /**@} end of group I2C_CLKHI_Register */ 509 510 /** 511 * @ingroup i2c_registers 512 * @defgroup I2C_HSCLK I2C_HSCLK 513 * @brief Clock high Register. 514 * @{ 515 */ 516 #define MXC_F_I2C_HSCLK_LO_POS 0 /**< HSCLK_LO Position */ 517 #define MXC_F_I2C_HSCLK_LO ((uint32_t)(0xFFUL << MXC_F_I2C_HSCLK_LO_POS)) /**< HSCLK_LO Mask */ 518 519 #define MXC_F_I2C_HSCLK_HI_POS 8 /**< HSCLK_HI Position */ 520 #define MXC_F_I2C_HSCLK_HI ((uint32_t)(0xFFUL << MXC_F_I2C_HSCLK_HI_POS)) /**< HSCLK_HI Mask */ 521 522 /**@} end of group I2C_HSCLK_Register */ 523 524 /** 525 * @ingroup i2c_registers 526 * @defgroup I2C_TIMEOUT I2C_TIMEOUT 527 * @brief Timeout Register 528 * @{ 529 */ 530 #define MXC_F_I2C_TIMEOUT_SCL_TO_VAL_POS 0 /**< TIMEOUT_SCL_TO_VAL Position */ 531 #define MXC_F_I2C_TIMEOUT_SCL_TO_VAL ((uint32_t)(0xFFFFUL << MXC_F_I2C_TIMEOUT_SCL_TO_VAL_POS)) /**< TIMEOUT_SCL_TO_VAL Mask */ 532 533 /**@} end of group I2C_TIMEOUT_Register */ 534 535 /** 536 * @ingroup i2c_registers 537 * @defgroup I2C_SLAVE I2C_SLAVE 538 * @brief Slave Address Register. 539 * @{ 540 */ 541 #define MXC_F_I2C_SLAVE_ADDR_POS 0 /**< SLAVE_ADDR Position */ 542 #define MXC_F_I2C_SLAVE_ADDR ((uint32_t)(0x3FFUL << MXC_F_I2C_SLAVE_ADDR_POS)) /**< SLAVE_ADDR Mask */ 543 544 #define MXC_F_I2C_SLAVE_DIS_POS 10 /**< SLAVE_DIS Position */ 545 #define MXC_F_I2C_SLAVE_DIS ((uint32_t)(0x1UL << MXC_F_I2C_SLAVE_DIS_POS)) /**< SLAVE_DIS Mask */ 546 547 #define MXC_F_I2C_SLAVE_IDX_POS 11 /**< SLAVE_IDX Position */ 548 #define MXC_F_I2C_SLAVE_IDX ((uint32_t)(0xFUL << MXC_F_I2C_SLAVE_IDX_POS)) /**< SLAVE_IDX Mask */ 549 550 #define MXC_F_I2C_SLAVE_EXT_ADDR_EN_POS 15 /**< SLAVE_EXT_ADDR_EN Position */ 551 #define MXC_F_I2C_SLAVE_EXT_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_SLAVE_EXT_ADDR_EN_POS)) /**< SLAVE_EXT_ADDR_EN Mask */ 552 553 /**@} end of group I2C_SLAVE_Register */ 554 555 /** 556 * @ingroup i2c_registers 557 * @defgroup I2C_DMA I2C_DMA 558 * @brief DMA Register. 559 * @{ 560 */ 561 #define MXC_F_I2C_DMA_TX_EN_POS 0 /**< DMA_TX_EN Position */ 562 #define MXC_F_I2C_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */ 563 564 #define MXC_F_I2C_DMA_RX_EN_POS 1 /**< DMA_RX_EN Position */ 565 #define MXC_F_I2C_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */ 566 567 /**@} end of group I2C_DMA_Register */ 568 569 #ifdef __cplusplus 570 } 571 #endif 572 573 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32675_INCLUDE_I2C_REGS_H_ 574
