1 /** 2 * @file qdec_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the QDEC Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup qdec_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_QDEC_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_QDEC_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup qdec 67 * @defgroup qdec_registers QDEC_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the QDEC Peripheral Module. 69 * @details Quadrature Encoder Interface 70 */ 71 72 /** 73 * @ingroup qdec_registers 74 * Structure type to access the QDEC Registers. 75 */ 76 typedef struct { 77 __IO uint32_t ctrl; /**< <tt>\b 0x0000:</tt> QDEC CTRL Register */ 78 __IO uint32_t intfl; /**< <tt>\b 0x0004:</tt> QDEC INTFL Register */ 79 __IO uint32_t inten; /**< <tt>\b 0x0008:</tt> QDEC INTEN Register */ 80 __IO uint32_t maxcnt; /**< <tt>\b 0x000C:</tt> QDEC MAXCNT Register */ 81 __IO uint32_t initial; /**< <tt>\b 0x0010:</tt> QDEC INITIAL Register */ 82 __IO uint32_t compare; /**< <tt>\b 0x0014:</tt> QDEC COMPARE Register */ 83 __I uint32_t index; /**< <tt>\b 0x0018:</tt> QDEC INDEX Register */ 84 __I uint32_t capture; /**< <tt>\b 0x001C:</tt> QDEC CAPTURE Register */ 85 __I uint32_t status; /**< <tt>\b 0x0020:</tt> QDEC STATUS Register */ 86 __IO uint32_t position; /**< <tt>\b 0x0024:</tt> QDEC POSITION Register */ 87 __IO uint32_t capdly; /**< <tt>\b 0x0028:</tt> QDEC CAPDLY Register */ 88 } mxc_qdec_regs_t; 89 90 /* Register offsets for module QDEC */ 91 /** 92 * @ingroup qdec_registers 93 * @defgroup QDEC_Register_Offsets Register Offsets 94 * @brief QDEC Peripheral Register Offsets from the QDEC Base Peripheral Address. 95 * @{ 96 */ 97 #define MXC_R_QDEC_CTRL ((uint32_t)0x00000000UL) /**< Offset from QDEC Base Address: <tt> 0x0000</tt> */ 98 #define MXC_R_QDEC_INTFL ((uint32_t)0x00000004UL) /**< Offset from QDEC Base Address: <tt> 0x0004</tt> */ 99 #define MXC_R_QDEC_INTEN ((uint32_t)0x00000008UL) /**< Offset from QDEC Base Address: <tt> 0x0008</tt> */ 100 #define MXC_R_QDEC_MAXCNT ((uint32_t)0x0000000CUL) /**< Offset from QDEC Base Address: <tt> 0x000C</tt> */ 101 #define MXC_R_QDEC_INITIAL ((uint32_t)0x00000010UL) /**< Offset from QDEC Base Address: <tt> 0x0010</tt> */ 102 #define MXC_R_QDEC_COMPARE ((uint32_t)0x00000014UL) /**< Offset from QDEC Base Address: <tt> 0x0014</tt> */ 103 #define MXC_R_QDEC_INDEX ((uint32_t)0x00000018UL) /**< Offset from QDEC Base Address: <tt> 0x0018</tt> */ 104 #define MXC_R_QDEC_CAPTURE ((uint32_t)0x0000001CUL) /**< Offset from QDEC Base Address: <tt> 0x001C</tt> */ 105 #define MXC_R_QDEC_STATUS ((uint32_t)0x00000020UL) /**< Offset from QDEC Base Address: <tt> 0x0020</tt> */ 106 #define MXC_R_QDEC_POSITION ((uint32_t)0x00000024UL) /**< Offset from QDEC Base Address: <tt> 0x0024</tt> */ 107 #define MXC_R_QDEC_CAPDLY ((uint32_t)0x00000028UL) /**< Offset from QDEC Base Address: <tt> 0x0028</tt> */ 108 /**@} end of group qdec_registers */ 109 110 /** 111 * @ingroup qdec_registers 112 * @defgroup QDEC_CTRL QDEC_CTRL 113 * @brief Control Register. 114 * @{ 115 */ 116 #define MXC_F_QDEC_CTRL_EN_POS 0 /**< CTRL_EN Position */ 117 #define MXC_F_QDEC_CTRL_EN ((uint32_t)(0x1UL << MXC_F_QDEC_CTRL_EN_POS)) /**< CTRL_EN Mask */ 118 119 #define MXC_F_QDEC_CTRL_MODE_POS 1 /**< CTRL_MODE Position */ 120 #define MXC_F_QDEC_CTRL_MODE ((uint32_t)(0x3UL << MXC_F_QDEC_CTRL_MODE_POS)) /**< CTRL_MODE Mask */ 121 #define MXC_V_QDEC_CTRL_MODE_X1MODE ((uint32_t)0x0UL) /**< CTRL_MODE_X1MODE Value */ 122 #define MXC_S_QDEC_CTRL_MODE_X1MODE (MXC_V_QDEC_CTRL_MODE_X1MODE << MXC_F_QDEC_CTRL_MODE_POS) /**< CTRL_MODE_X1MODE Setting */ 123 #define MXC_V_QDEC_CTRL_MODE_X2MODE ((uint32_t)0x1UL) /**< CTRL_MODE_X2MODE Value */ 124 #define MXC_S_QDEC_CTRL_MODE_X2MODE (MXC_V_QDEC_CTRL_MODE_X2MODE << MXC_F_QDEC_CTRL_MODE_POS) /**< CTRL_MODE_X2MODE Setting */ 125 #define MXC_V_QDEC_CTRL_MODE_X4MODE ((uint32_t)0x2UL) /**< CTRL_MODE_X4MODE Value */ 126 #define MXC_S_QDEC_CTRL_MODE_X4MODE (MXC_V_QDEC_CTRL_MODE_X4MODE << MXC_F_QDEC_CTRL_MODE_POS) /**< CTRL_MODE_X4MODE Setting */ 127 128 #define MXC_F_QDEC_CTRL_SWAP_POS 3 /**< CTRL_SWAP Position */ 129 #define MXC_F_QDEC_CTRL_SWAP ((uint32_t)(0x1UL << MXC_F_QDEC_CTRL_SWAP_POS)) /**< CTRL_SWAP Mask */ 130 131 #define MXC_F_QDEC_CTRL_FILTER_POS 4 /**< CTRL_FILTER Position */ 132 #define MXC_F_QDEC_CTRL_FILTER ((uint32_t)(0x3UL << MXC_F_QDEC_CTRL_FILTER_POS)) /**< CTRL_FILTER Mask */ 133 #define MXC_V_QDEC_CTRL_FILTER_1_SAMPLE ((uint32_t)0x0UL) /**< CTRL_FILTER_1_SAMPLE Value */ 134 #define MXC_S_QDEC_CTRL_FILTER_1_SAMPLE (MXC_V_QDEC_CTRL_FILTER_1_SAMPLE << MXC_F_QDEC_CTRL_FILTER_POS) /**< CTRL_FILTER_1_SAMPLE Setting */ 135 #define MXC_V_QDEC_CTRL_FILTER_2_SAMPLES ((uint32_t)0x1UL) /**< CTRL_FILTER_2_SAMPLES Value */ 136 #define MXC_S_QDEC_CTRL_FILTER_2_SAMPLES (MXC_V_QDEC_CTRL_FILTER_2_SAMPLES << MXC_F_QDEC_CTRL_FILTER_POS) /**< CTRL_FILTER_2_SAMPLES Setting */ 137 #define MXC_V_QDEC_CTRL_FILTER_3_SAMPLES ((uint32_t)0x2UL) /**< CTRL_FILTER_3_SAMPLES Value */ 138 #define MXC_S_QDEC_CTRL_FILTER_3_SAMPLES (MXC_V_QDEC_CTRL_FILTER_3_SAMPLES << MXC_F_QDEC_CTRL_FILTER_POS) /**< CTRL_FILTER_3_SAMPLES Setting */ 139 #define MXC_V_QDEC_CTRL_FILTER_4_SAMPLES ((uint32_t)0x3UL) /**< CTRL_FILTER_4_SAMPLES Value */ 140 #define MXC_S_QDEC_CTRL_FILTER_4_SAMPLES (MXC_V_QDEC_CTRL_FILTER_4_SAMPLES << MXC_F_QDEC_CTRL_FILTER_POS) /**< CTRL_FILTER_4_SAMPLES Setting */ 141 142 #define MXC_F_QDEC_CTRL_RST_INDEX_POS 6 /**< CTRL_RST_INDEX Position */ 143 #define MXC_F_QDEC_CTRL_RST_INDEX ((uint32_t)(0x1UL << MXC_F_QDEC_CTRL_RST_INDEX_POS)) /**< CTRL_RST_INDEX Mask */ 144 145 #define MXC_F_QDEC_CTRL_RST_MAXCNT_POS 7 /**< CTRL_RST_MAXCNT Position */ 146 #define MXC_F_QDEC_CTRL_RST_MAXCNT ((uint32_t)(0x1UL << MXC_F_QDEC_CTRL_RST_MAXCNT_POS)) /**< CTRL_RST_MAXCNT Mask */ 147 148 #define MXC_F_QDEC_CTRL_STICKY_POS 8 /**< CTRL_STICKY Position */ 149 #define MXC_F_QDEC_CTRL_STICKY ((uint32_t)(0x1UL << MXC_F_QDEC_CTRL_STICKY_POS)) /**< CTRL_STICKY Mask */ 150 151 #define MXC_F_QDEC_CTRL_PSC_POS 16 /**< CTRL_PSC Position */ 152 #define MXC_F_QDEC_CTRL_PSC ((uint32_t)(0x7UL << MXC_F_QDEC_CTRL_PSC_POS)) /**< CTRL_PSC Mask */ 153 #define MXC_V_QDEC_CTRL_PSC_DIV1 ((uint32_t)0x0UL) /**< CTRL_PSC_DIV1 Value */ 154 #define MXC_S_QDEC_CTRL_PSC_DIV1 (MXC_V_QDEC_CTRL_PSC_DIV1 << MXC_F_QDEC_CTRL_PSC_POS) /**< CTRL_PSC_DIV1 Setting */ 155 #define MXC_V_QDEC_CTRL_PSC_DIV2 ((uint32_t)0x1UL) /**< CTRL_PSC_DIV2 Value */ 156 #define MXC_S_QDEC_CTRL_PSC_DIV2 (MXC_V_QDEC_CTRL_PSC_DIV2 << MXC_F_QDEC_CTRL_PSC_POS) /**< CTRL_PSC_DIV2 Setting */ 157 #define MXC_V_QDEC_CTRL_PSC_DIV4 ((uint32_t)0x2UL) /**< CTRL_PSC_DIV4 Value */ 158 #define MXC_S_QDEC_CTRL_PSC_DIV4 (MXC_V_QDEC_CTRL_PSC_DIV4 << MXC_F_QDEC_CTRL_PSC_POS) /**< CTRL_PSC_DIV4 Setting */ 159 #define MXC_V_QDEC_CTRL_PSC_DIV8 ((uint32_t)0x3UL) /**< CTRL_PSC_DIV8 Value */ 160 #define MXC_S_QDEC_CTRL_PSC_DIV8 (MXC_V_QDEC_CTRL_PSC_DIV8 << MXC_F_QDEC_CTRL_PSC_POS) /**< CTRL_PSC_DIV8 Setting */ 161 #define MXC_V_QDEC_CTRL_PSC_DIV16 ((uint32_t)0x4UL) /**< CTRL_PSC_DIV16 Value */ 162 #define MXC_S_QDEC_CTRL_PSC_DIV16 (MXC_V_QDEC_CTRL_PSC_DIV16 << MXC_F_QDEC_CTRL_PSC_POS) /**< CTRL_PSC_DIV16 Setting */ 163 #define MXC_V_QDEC_CTRL_PSC_DIV32 ((uint32_t)0x5UL) /**< CTRL_PSC_DIV32 Value */ 164 #define MXC_S_QDEC_CTRL_PSC_DIV32 (MXC_V_QDEC_CTRL_PSC_DIV32 << MXC_F_QDEC_CTRL_PSC_POS) /**< CTRL_PSC_DIV32 Setting */ 165 #define MXC_V_QDEC_CTRL_PSC_DIV64 ((uint32_t)0x6UL) /**< CTRL_PSC_DIV64 Value */ 166 #define MXC_S_QDEC_CTRL_PSC_DIV64 (MXC_V_QDEC_CTRL_PSC_DIV64 << MXC_F_QDEC_CTRL_PSC_POS) /**< CTRL_PSC_DIV64 Setting */ 167 #define MXC_V_QDEC_CTRL_PSC_DIV128 ((uint32_t)0x7UL) /**< CTRL_PSC_DIV128 Value */ 168 #define MXC_S_QDEC_CTRL_PSC_DIV128 (MXC_V_QDEC_CTRL_PSC_DIV128 << MXC_F_QDEC_CTRL_PSC_POS) /**< CTRL_PSC_DIV128 Setting */ 169 170 /**@} end of group QDEC_CTRL_Register */ 171 172 /** 173 * @ingroup qdec_registers 174 * @defgroup QDEC_INTFL QDEC_INTFL 175 * @brief Interrupt Flag Register. 176 * @{ 177 */ 178 #define MXC_F_QDEC_INTFL_INDEX_POS 0 /**< INTFL_INDEX Position */ 179 #define MXC_F_QDEC_INTFL_INDEX ((uint32_t)(0x1UL << MXC_F_QDEC_INTFL_INDEX_POS)) /**< INTFL_INDEX Mask */ 180 181 #define MXC_F_QDEC_INTFL_QERR_POS 1 /**< INTFL_QERR Position */ 182 #define MXC_F_QDEC_INTFL_QERR ((uint32_t)(0x1UL << MXC_F_QDEC_INTFL_QERR_POS)) /**< INTFL_QERR Mask */ 183 184 #define MXC_F_QDEC_INTFL_COMPARE_POS 2 /**< INTFL_COMPARE Position */ 185 #define MXC_F_QDEC_INTFL_COMPARE ((uint32_t)(0x1UL << MXC_F_QDEC_INTFL_COMPARE_POS)) /**< INTFL_COMPARE Mask */ 186 187 #define MXC_F_QDEC_INTFL_MAXCNT_POS 3 /**< INTFL_MAXCNT Position */ 188 #define MXC_F_QDEC_INTFL_MAXCNT ((uint32_t)(0x1UL << MXC_F_QDEC_INTFL_MAXCNT_POS)) /**< INTFL_MAXCNT Mask */ 189 190 #define MXC_F_QDEC_INTFL_CAPTURE_POS 4 /**< INTFL_CAPTURE Position */ 191 #define MXC_F_QDEC_INTFL_CAPTURE ((uint32_t)(0x1UL << MXC_F_QDEC_INTFL_CAPTURE_POS)) /**< INTFL_CAPTURE Mask */ 192 193 #define MXC_F_QDEC_INTFL_DIR_POS 5 /**< INTFL_DIR Position */ 194 #define MXC_F_QDEC_INTFL_DIR ((uint32_t)(0x1UL << MXC_F_QDEC_INTFL_DIR_POS)) /**< INTFL_DIR Mask */ 195 196 #define MXC_F_QDEC_INTFL_MOVE_POS 6 /**< INTFL_MOVE Position */ 197 #define MXC_F_QDEC_INTFL_MOVE ((uint32_t)(0x1UL << MXC_F_QDEC_INTFL_MOVE_POS)) /**< INTFL_MOVE Mask */ 198 199 /**@} end of group QDEC_INTFL_Register */ 200 201 /** 202 * @ingroup qdec_registers 203 * @defgroup QDEC_INTEN QDEC_INTEN 204 * @brief Interrupt Enable Register. 205 * @{ 206 */ 207 #define MXC_F_QDEC_INTEN_INDEX_POS 0 /**< INTEN_INDEX Position */ 208 #define MXC_F_QDEC_INTEN_INDEX ((uint32_t)(0x1UL << MXC_F_QDEC_INTEN_INDEX_POS)) /**< INTEN_INDEX Mask */ 209 210 #define MXC_F_QDEC_INTEN_QERR_POS 1 /**< INTEN_QERR Position */ 211 #define MXC_F_QDEC_INTEN_QERR ((uint32_t)(0x1UL << MXC_F_QDEC_INTEN_QERR_POS)) /**< INTEN_QERR Mask */ 212 213 #define MXC_F_QDEC_INTEN_COMPARE_POS 2 /**< INTEN_COMPARE Position */ 214 #define MXC_F_QDEC_INTEN_COMPARE ((uint32_t)(0x1UL << MXC_F_QDEC_INTEN_COMPARE_POS)) /**< INTEN_COMPARE Mask */ 215 216 #define MXC_F_QDEC_INTEN_MAXCNT_POS 3 /**< INTEN_MAXCNT Position */ 217 #define MXC_F_QDEC_INTEN_MAXCNT ((uint32_t)(0x1UL << MXC_F_QDEC_INTEN_MAXCNT_POS)) /**< INTEN_MAXCNT Mask */ 218 219 #define MXC_F_QDEC_INTEN_CAPTURE_POS 4 /**< INTEN_CAPTURE Position */ 220 #define MXC_F_QDEC_INTEN_CAPTURE ((uint32_t)(0x1UL << MXC_F_QDEC_INTEN_CAPTURE_POS)) /**< INTEN_CAPTURE Mask */ 221 222 #define MXC_F_QDEC_INTEN_DIR_POS 5 /**< INTEN_DIR Position */ 223 #define MXC_F_QDEC_INTEN_DIR ((uint32_t)(0x1UL << MXC_F_QDEC_INTEN_DIR_POS)) /**< INTEN_DIR Mask */ 224 225 #define MXC_F_QDEC_INTEN_MOVE_POS 6 /**< INTEN_MOVE Position */ 226 #define MXC_F_QDEC_INTEN_MOVE ((uint32_t)(0x1UL << MXC_F_QDEC_INTEN_MOVE_POS)) /**< INTEN_MOVE Mask */ 227 228 /**@} end of group QDEC_INTEN_Register */ 229 230 /** 231 * @ingroup qdec_registers 232 * @defgroup QDEC_MAXCNT QDEC_MAXCNT 233 * @brief Maximum Count Register. 234 * @{ 235 */ 236 #define MXC_F_QDEC_MAXCNT_MAXCNT_POS 0 /**< MAXCNT_MAXCNT Position */ 237 #define MXC_F_QDEC_MAXCNT_MAXCNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_QDEC_MAXCNT_MAXCNT_POS)) /**< MAXCNT_MAXCNT Mask */ 238 239 /**@} end of group QDEC_MAXCNT_Register */ 240 241 /** 242 * @ingroup qdec_registers 243 * @defgroup QDEC_INITIAL QDEC_INITIAL 244 * @brief Initial Count Register. 245 * @{ 246 */ 247 #define MXC_F_QDEC_INITIAL_INITIAL_POS 0 /**< INITIAL_INITIAL Position */ 248 #define MXC_F_QDEC_INITIAL_INITIAL ((uint32_t)(0xFFFFFFFFUL << MXC_F_QDEC_INITIAL_INITIAL_POS)) /**< INITIAL_INITIAL Mask */ 249 250 /**@} end of group QDEC_INITIAL_Register */ 251 252 /** 253 * @ingroup qdec_registers 254 * @defgroup QDEC_COMPARE QDEC_COMPARE 255 * @brief Compare Register. 256 * @{ 257 */ 258 #define MXC_F_QDEC_COMPARE_COMPARE_POS 0 /**< COMPARE_COMPARE Position */ 259 #define MXC_F_QDEC_COMPARE_COMPARE ((uint32_t)(0xFFFFFFFFUL << MXC_F_QDEC_COMPARE_COMPARE_POS)) /**< COMPARE_COMPARE Mask */ 260 261 /**@} end of group QDEC_COMPARE_Register */ 262 263 /** 264 * @ingroup qdec_registers 265 * @defgroup QDEC_INDEX QDEC_INDEX 266 * @brief Index Register. count captured when QEI fired 267 * @{ 268 */ 269 #define MXC_F_QDEC_INDEX_INDEX_POS 0 /**< INDEX_INDEX Position */ 270 #define MXC_F_QDEC_INDEX_INDEX ((uint32_t)(0xFFFFFFFFUL << MXC_F_QDEC_INDEX_INDEX_POS)) /**< INDEX_INDEX Mask */ 271 272 /**@} end of group QDEC_INDEX_Register */ 273 274 /** 275 * @ingroup qdec_registers 276 * @defgroup QDEC_CAPTURE QDEC_CAPTURE 277 * @brief Capture Register. counter captured when QES fired 278 * @{ 279 */ 280 #define MXC_F_QDEC_CAPTURE_CAPTURE_POS 0 /**< CAPTURE_CAPTURE Position */ 281 #define MXC_F_QDEC_CAPTURE_CAPTURE ((uint32_t)(0xFFFFFFFFUL << MXC_F_QDEC_CAPTURE_CAPTURE_POS)) /**< CAPTURE_CAPTURE Mask */ 282 283 /**@} end of group QDEC_CAPTURE_Register */ 284 285 /** 286 * @ingroup qdec_registers 287 * @defgroup QDEC_STATUS QDEC_STATUS 288 * @brief Status Register. 289 * @{ 290 */ 291 #define MXC_F_QDEC_STATUS_DIR_POS 0 /**< STATUS_DIR Position */ 292 #define MXC_F_QDEC_STATUS_DIR ((uint32_t)(0x1UL << MXC_F_QDEC_STATUS_DIR_POS)) /**< STATUS_DIR Mask */ 293 294 /**@} end of group QDEC_STATUS_Register */ 295 296 /** 297 * @ingroup qdec_registers 298 * @defgroup QDEC_POSITION QDEC_POSITION 299 * @brief Count Register. raw counter value 300 * @{ 301 */ 302 #define MXC_F_QDEC_POSITION_POSITION_POS 0 /**< POSITION_POSITION Position */ 303 #define MXC_F_QDEC_POSITION_POSITION ((uint32_t)(0xFFFFFFFFUL << MXC_F_QDEC_POSITION_POSITION_POS)) /**< POSITION_POSITION Mask */ 304 305 /**@} end of group QDEC_POSITION_Register */ 306 307 /** 308 * @ingroup qdec_registers 309 * @defgroup QDEC_CAPDLY QDEC_CAPDLY 310 * @brief delay CAPTURE 311 * @{ 312 */ 313 #define MXC_F_QDEC_CAPDLY_CAPDLY_POS 0 /**< CAPDLY_CAPDLY Position */ 314 #define MXC_F_QDEC_CAPDLY_CAPDLY ((uint32_t)(0xFFFFFFFFUL << MXC_F_QDEC_CAPDLY_CAPDLY_POS)) /**< CAPDLY_CAPDLY Mask */ 315 316 /**@} end of group QDEC_CAPDLY_Register */ 317 318 #ifdef __cplusplus 319 } 320 #endif 321 322 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_QDEC_REGS_H_ 323
