1 /** 2 * @file fcr_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the FCR Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup fcr_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_FCR_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_FCR_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup fcr 67 * @defgroup fcr_registers FCR_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the FCR Peripheral Module. 69 * @details Function Control Register. 70 */ 71 72 /** 73 * @ingroup fcr_registers 74 * Structure type to access the FCR Registers. 75 */ 76 typedef struct { 77 __IO uint32_t fctrl0; /**< <tt>\b 0x00:</tt> FCR FCTRL0 Register */ 78 __IO uint32_t autocal0; /**< <tt>\b 0x04:</tt> FCR AUTOCAL0 Register */ 79 __IO uint32_t autocal1; /**< <tt>\b 0x08:</tt> FCR AUTOCAL1 Register */ 80 __IO uint32_t autocal2; /**< <tt>\b 0x0C:</tt> FCR AUTOCAL2 Register */ 81 __I uint32_t ts0; /**< <tt>\b 0x10:</tt> FCR TS0 Register */ 82 __I uint32_t ts1; /**< <tt>\b 0x14:</tt> FCR TS1 Register */ 83 __IO uint32_t adcreftrim0; /**< <tt>\b 0x18:</tt> FCR ADCREFTRIM0 Register */ 84 __IO uint32_t adcreftrim1; /**< <tt>\b 0x1C:</tt> FCR ADCREFTRIM1 Register */ 85 __IO uint32_t adcreftrim2; /**< <tt>\b 0x20:</tt> FCR ADCREFTRIM2 Register */ 86 __IO uint32_t erfoks; /**< <tt>\b 0x24:</tt> FCR ERFOKS Register */ 87 } mxc_fcr_regs_t; 88 89 /* Register offsets for module FCR */ 90 /** 91 * @ingroup fcr_registers 92 * @defgroup FCR_Register_Offsets Register Offsets 93 * @brief FCR Peripheral Register Offsets from the FCR Base Peripheral Address. 94 * @{ 95 */ 96 #define MXC_R_FCR_FCTRL0 ((uint32_t)0x00000000UL) /**< Offset from FCR Base Address: <tt> 0x0000</tt> */ 97 #define MXC_R_FCR_AUTOCAL0 ((uint32_t)0x00000004UL) /**< Offset from FCR Base Address: <tt> 0x0004</tt> */ 98 #define MXC_R_FCR_AUTOCAL1 ((uint32_t)0x00000008UL) /**< Offset from FCR Base Address: <tt> 0x0008</tt> */ 99 #define MXC_R_FCR_AUTOCAL2 ((uint32_t)0x0000000CUL) /**< Offset from FCR Base Address: <tt> 0x000C</tt> */ 100 #define MXC_R_FCR_TS0 ((uint32_t)0x00000010UL) /**< Offset from FCR Base Address: <tt> 0x0010</tt> */ 101 #define MXC_R_FCR_TS1 ((uint32_t)0x00000014UL) /**< Offset from FCR Base Address: <tt> 0x0014</tt> */ 102 #define MXC_R_FCR_ADCREFTRIM0 ((uint32_t)0x00000018UL) /**< Offset from FCR Base Address: <tt> 0x0018</tt> */ 103 #define MXC_R_FCR_ADCREFTRIM1 ((uint32_t)0x0000001CUL) /**< Offset from FCR Base Address: <tt> 0x001C</tt> */ 104 #define MXC_R_FCR_ADCREFTRIM2 ((uint32_t)0x00000020UL) /**< Offset from FCR Base Address: <tt> 0x0020</tt> */ 105 #define MXC_R_FCR_ERFOKS ((uint32_t)0x00000024UL) /**< Offset from FCR Base Address: <tt> 0x0024</tt> */ 106 /**@} end of group fcr_registers */ 107 108 /** 109 * @ingroup fcr_registers 110 * @defgroup FCR_FCTRL0 FCR_FCTRL0 111 * @brief Register 0. 112 * @{ 113 */ 114 #define MXC_F_FCR_FCTRL0_ERFO_RANGE_SEL_POS 0 /**< FCTRL0_ERFO_RANGE_SEL Position */ 115 #define MXC_F_FCR_FCTRL0_ERFO_RANGE_SEL ((uint32_t)(0x7UL << MXC_F_FCR_FCTRL0_ERFO_RANGE_SEL_POS)) /**< FCTRL0_ERFO_RANGE_SEL Mask */ 116 117 #define MXC_F_FCR_FCTRL0_KEYWIPE_SYS_POS 8 /**< FCTRL0_KEYWIPE_SYS Position */ 118 #define MXC_F_FCR_FCTRL0_KEYWIPE_SYS ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_KEYWIPE_SYS_POS)) /**< FCTRL0_KEYWIPE_SYS Mask */ 119 120 #define MXC_F_FCR_FCTRL0_I2C0_SDA_FILTER_EN_POS 20 /**< FCTRL0_I2C0_SDA_FILTER_EN Position */ 121 #define MXC_F_FCR_FCTRL0_I2C0_SDA_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0_SDA_FILTER_EN_POS)) /**< FCTRL0_I2C0_SDA_FILTER_EN Mask */ 122 123 #define MXC_F_FCR_FCTRL0_I2C0_SCL_FILTER_EN_POS 21 /**< FCTRL0_I2C0_SCL_FILTER_EN Position */ 124 #define MXC_F_FCR_FCTRL0_I2C0_SCL_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0_SCL_FILTER_EN_POS)) /**< FCTRL0_I2C0_SCL_FILTER_EN Mask */ 125 126 #define MXC_F_FCR_FCTRL0_I2C1_SDA_FILTER_EN_POS 22 /**< FCTRL0_I2C1_SDA_FILTER_EN Position */ 127 #define MXC_F_FCR_FCTRL0_I2C1_SDA_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1_SDA_FILTER_EN_POS)) /**< FCTRL0_I2C1_SDA_FILTER_EN Mask */ 128 129 #define MXC_F_FCR_FCTRL0_I2C1_SCL_FILTER_EN_POS 23 /**< FCTRL0_I2C1_SCL_FILTER_EN Position */ 130 #define MXC_F_FCR_FCTRL0_I2C1_SCL_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1_SCL_FILTER_EN_POS)) /**< FCTRL0_I2C1_SCL_FILTER_EN Mask */ 131 132 #define MXC_F_FCR_FCTRL0_I2C2_SDA_FILTER_EN_POS 24 /**< FCTRL0_I2C2_SDA_FILTER_EN Position */ 133 #define MXC_F_FCR_FCTRL0_I2C2_SDA_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2_SDA_FILTER_EN_POS)) /**< FCTRL0_I2C2_SDA_FILTER_EN Mask */ 134 135 #define MXC_F_FCR_FCTRL0_I2C2_SCL_FILTER_EN_POS 25 /**< FCTRL0_I2C2_SCL_FILTER_EN Position */ 136 #define MXC_F_FCR_FCTRL0_I2C2_SCL_FILTER_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2_SCL_FILTER_EN_POS)) /**< FCTRL0_I2C2_SCL_FILTER_EN Mask */ 137 138 /**@} end of group FCR_FCTRL0_Register */ 139 140 /** 141 * @ingroup fcr_registers 142 * @defgroup FCR_AUTOCAL0 FCR_AUTOCAL0 143 * @brief Register 1. 144 * @{ 145 */ 146 #define MXC_F_FCR_AUTOCAL0_SEL_POS 0 /**< AUTOCAL0_SEL Position */ 147 #define MXC_F_FCR_AUTOCAL0_SEL ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_SEL_POS)) /**< AUTOCAL0_SEL Mask */ 148 149 #define MXC_F_FCR_AUTOCAL0_EN_POS 1 /**< AUTOCAL0_EN Position */ 150 #define MXC_F_FCR_AUTOCAL0_EN ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_EN_POS)) /**< AUTOCAL0_EN Mask */ 151 152 #define MXC_F_FCR_AUTOCAL0_LOAD_POS 2 /**< AUTOCAL0_LOAD Position */ 153 #define MXC_F_FCR_AUTOCAL0_LOAD ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_LOAD_POS)) /**< AUTOCAL0_LOAD Mask */ 154 155 #define MXC_F_FCR_AUTOCAL0_INVERT_POS 3 /**< AUTOCAL0_INVERT Position */ 156 #define MXC_F_FCR_AUTOCAL0_INVERT ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_INVERT_POS)) /**< AUTOCAL0_INVERT Mask */ 157 158 #define MXC_F_FCR_AUTOCAL0_ATOMIC_POS 4 /**< AUTOCAL0_ATOMIC Position */ 159 #define MXC_F_FCR_AUTOCAL0_ATOMIC ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_ATOMIC_POS)) /**< AUTOCAL0_ATOMIC Mask */ 160 161 #define MXC_F_FCR_AUTOCAL0_GAIN_POS 8 /**< AUTOCAL0_GAIN Position */ 162 #define MXC_F_FCR_AUTOCAL0_GAIN ((uint32_t)(0xFFFUL << MXC_F_FCR_AUTOCAL0_GAIN_POS)) /**< AUTOCAL0_GAIN Mask */ 163 164 #define MXC_F_FCR_AUTOCAL0_TRIM_POS 23 /**< AUTOCAL0_TRIM Position */ 165 #define MXC_F_FCR_AUTOCAL0_TRIM ((uint32_t)(0x1FFUL << MXC_F_FCR_AUTOCAL0_TRIM_POS)) /**< AUTOCAL0_TRIM Mask */ 166 167 /**@} end of group FCR_AUTOCAL0_Register */ 168 169 /** 170 * @ingroup fcr_registers 171 * @defgroup FCR_AUTOCAL1 FCR_AUTOCAL1 172 * @brief Register 2. 173 * @{ 174 */ 175 #define MXC_F_FCR_AUTOCAL1_INITIAL_POS 0 /**< AUTOCAL1_INITIAL Position */ 176 #define MXC_F_FCR_AUTOCAL1_INITIAL ((uint32_t)(0x1FFUL << MXC_F_FCR_AUTOCAL1_INITIAL_POS)) /**< AUTOCAL1_INITIAL Mask */ 177 178 /**@} end of group FCR_AUTOCAL1_Register */ 179 180 /** 181 * @ingroup fcr_registers 182 * @defgroup FCR_AUTOCAL2 FCR_AUTOCAL2 183 * @brief Register 3. 184 * @{ 185 */ 186 #define MXC_F_FCR_AUTOCAL2_RUNTIME_POS 0 /**< AUTOCAL2_RUNTIME Position */ 187 #define MXC_F_FCR_AUTOCAL2_RUNTIME ((uint32_t)(0xFFUL << MXC_F_FCR_AUTOCAL2_RUNTIME_POS)) /**< AUTOCAL2_RUNTIME Mask */ 188 189 #define MXC_F_FCR_AUTOCAL2_DIV_POS 8 /**< AUTOCAL2_DIV Position */ 190 #define MXC_F_FCR_AUTOCAL2_DIV ((uint32_t)(0x1FFFUL << MXC_F_FCR_AUTOCAL2_DIV_POS)) /**< AUTOCAL2_DIV Mask */ 191 192 /**@} end of group FCR_AUTOCAL2_Register */ 193 194 /** 195 * @ingroup fcr_registers 196 * @defgroup FCR_TS0 FCR_TS0 197 * @brief Register 4. 198 * @{ 199 */ 200 #define MXC_F_FCR_TS0_GAIN_POS 0 /**< TS0_GAIN Position */ 201 #define MXC_F_FCR_TS0_GAIN ((uint32_t)(0xFFFUL << MXC_F_FCR_TS0_GAIN_POS)) /**< TS0_GAIN Mask */ 202 203 /**@} end of group FCR_TS0_Register */ 204 205 /** 206 * @ingroup fcr_registers 207 * @defgroup FCR_TS1 FCR_TS1 208 * @brief Register 5. 209 * @{ 210 */ 211 #define MXC_F_FCR_TS1_OFFSET_POS 0 /**< TS1_OFFSET Position */ 212 #define MXC_F_FCR_TS1_OFFSET ((uint32_t)(0xFFFFFFFFUL << MXC_F_FCR_TS1_OFFSET_POS)) /**< TS1_OFFSET Mask */ 213 214 /**@} end of group FCR_TS1_Register */ 215 216 /** 217 * @ingroup fcr_registers 218 * @defgroup FCR_ADCREFTRIM0 FCR_ADCREFTRIM0 219 * @brief ADC Reference Trim 0 220 * @{ 221 */ 222 #define MXC_F_FCR_ADCREFTRIM0_VREFP_POS 0 /**< ADCREFTRIM0_VREFP Position */ 223 #define MXC_F_FCR_ADCREFTRIM0_VREFP ((uint32_t)(0x7FUL << MXC_F_FCR_ADCREFTRIM0_VREFP_POS)) /**< ADCREFTRIM0_VREFP Mask */ 224 225 #define MXC_F_FCR_ADCREFTRIM0_VREFM_POS 8 /**< ADCREFTRIM0_VREFM Position */ 226 #define MXC_F_FCR_ADCREFTRIM0_VREFM ((uint32_t)(0x7FUL << MXC_F_FCR_ADCREFTRIM0_VREFM_POS)) /**< ADCREFTRIM0_VREFM Mask */ 227 228 #define MXC_F_FCR_ADCREFTRIM0_VCM_POS 16 /**< ADCREFTRIM0_VCM Position */ 229 #define MXC_F_FCR_ADCREFTRIM0_VCM ((uint32_t)(0x3UL << MXC_F_FCR_ADCREFTRIM0_VCM_POS)) /**< ADCREFTRIM0_VCM Mask */ 230 231 #define MXC_F_FCR_ADCREFTRIM0_VX2_TUNE_POS 24 /**< ADCREFTRIM0_VX2_TUNE Position */ 232 #define MXC_F_FCR_ADCREFTRIM0_VX2_TUNE ((uint32_t)(0x3FUL << MXC_F_FCR_ADCREFTRIM0_VX2_TUNE_POS)) /**< ADCREFTRIM0_VX2_TUNE Mask */ 233 234 /**@} end of group FCR_ADCREFTRIM0_Register */ 235 236 /** 237 * @ingroup fcr_registers 238 * @defgroup FCR_ADCREFTRIM1 FCR_ADCREFTRIM1 239 * @brief ADC Reference Trim 1 240 * @{ 241 */ 242 #define MXC_F_FCR_ADCREFTRIM1_VREFP_POS 0 /**< ADCREFTRIM1_VREFP Position */ 243 #define MXC_F_FCR_ADCREFTRIM1_VREFP ((uint32_t)(0x7FUL << MXC_F_FCR_ADCREFTRIM1_VREFP_POS)) /**< ADCREFTRIM1_VREFP Mask */ 244 245 #define MXC_F_FCR_ADCREFTRIM1_VREFM_POS 8 /**< ADCREFTRIM1_VREFM Position */ 246 #define MXC_F_FCR_ADCREFTRIM1_VREFM ((uint32_t)(0x7FUL << MXC_F_FCR_ADCREFTRIM1_VREFM_POS)) /**< ADCREFTRIM1_VREFM Mask */ 247 248 #define MXC_F_FCR_ADCREFTRIM1_VCM_POS 16 /**< ADCREFTRIM1_VCM Position */ 249 #define MXC_F_FCR_ADCREFTRIM1_VCM ((uint32_t)(0x3UL << MXC_F_FCR_ADCREFTRIM1_VCM_POS)) /**< ADCREFTRIM1_VCM Mask */ 250 251 #define MXC_F_FCR_ADCREFTRIM1_VX2_TUNE_POS 24 /**< ADCREFTRIM1_VX2_TUNE Position */ 252 #define MXC_F_FCR_ADCREFTRIM1_VX2_TUNE ((uint32_t)(0x3FUL << MXC_F_FCR_ADCREFTRIM1_VX2_TUNE_POS)) /**< ADCREFTRIM1_VX2_TUNE Mask */ 253 254 /**@} end of group FCR_ADCREFTRIM1_Register */ 255 256 /** 257 * @ingroup fcr_registers 258 * @defgroup FCR_ADCREFTRIM2 FCR_ADCREFTRIM2 259 * @brief ADC Reference Trim 2 260 * @{ 261 */ 262 #define MXC_F_FCR_ADCREFTRIM2_IDRV_1P25_POS 0 /**< ADCREFTRIM2_IDRV_1P25 Position */ 263 #define MXC_F_FCR_ADCREFTRIM2_IDRV_1P25 ((uint32_t)(0xFUL << MXC_F_FCR_ADCREFTRIM2_IDRV_1P25_POS)) /**< ADCREFTRIM2_IDRV_1P25 Mask */ 264 265 #define MXC_F_FCR_ADCREFTRIM2_IBOOST_1P25_POS 4 /**< ADCREFTRIM2_IBOOST_1P25 Position */ 266 #define MXC_F_FCR_ADCREFTRIM2_IBOOST_1P25 ((uint32_t)(0x1UL << MXC_F_FCR_ADCREFTRIM2_IBOOST_1P25_POS)) /**< ADCREFTRIM2_IBOOST_1P25 Mask */ 267 268 #define MXC_F_FCR_ADCREFTRIM2_IDRV_2P048_POS 8 /**< ADCREFTRIM2_IDRV_2P048 Position */ 269 #define MXC_F_FCR_ADCREFTRIM2_IDRV_2P048 ((uint32_t)(0xFUL << MXC_F_FCR_ADCREFTRIM2_IDRV_2P048_POS)) /**< ADCREFTRIM2_IDRV_2P048 Mask */ 270 271 #define MXC_F_FCR_ADCREFTRIM2_IBOOST_2P048_POS 12 /**< ADCREFTRIM2_IBOOST_2P048 Position */ 272 #define MXC_F_FCR_ADCREFTRIM2_IBOOST_2P048 ((uint32_t)(0x1UL << MXC_F_FCR_ADCREFTRIM2_IBOOST_2P048_POS)) /**< ADCREFTRIM2_IBOOST_2P048 Mask */ 273 274 #define MXC_F_FCR_ADCREFTRIM2_VCM_POS 16 /**< ADCREFTRIM2_VCM Position */ 275 #define MXC_F_FCR_ADCREFTRIM2_VCM ((uint32_t)(0x3UL << MXC_F_FCR_ADCREFTRIM2_VCM_POS)) /**< ADCREFTRIM2_VCM Mask */ 276 277 #define MXC_F_FCR_ADCREFTRIM2_VX2_TUNE_POS 24 /**< ADCREFTRIM2_VX2_TUNE Position */ 278 #define MXC_F_FCR_ADCREFTRIM2_VX2_TUNE ((uint32_t)(0x3FUL << MXC_F_FCR_ADCREFTRIM2_VX2_TUNE_POS)) /**< ADCREFTRIM2_VX2_TUNE Mask */ 279 280 /**@} end of group FCR_ADCREFTRIM2_Register */ 281 282 /** 283 * @ingroup fcr_registers 284 * @defgroup FCR_ERFOKS FCR_ERFOKS 285 * @brief External Radio Frequency Oscillator Kick Start Control Register. 286 * @{ 287 */ 288 #define MXC_F_FCR_ERFOKS_CTRL_POS 0 /**< ERFOKS_CTRL Position */ 289 #define MXC_F_FCR_ERFOKS_CTRL ((uint32_t)(0xFFFFUL << MXC_F_FCR_ERFOKS_CTRL_POS)) /**< ERFOKS_CTRL Mask */ 290 291 /**@} end of group FCR_ERFOKS_Register */ 292 293 #ifdef __cplusplus 294 } 295 #endif 296 297 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32672_INCLUDE_FCR_REGS_H_ 298
