1 /** 2 * @file mcr_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the MCR Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup mcr_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_MCR_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_MCR_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup mcr 67 * @defgroup mcr_registers MCR_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the MCR Peripheral Module. 69 * @details Miscellaneous Control Registers. 70 */ 71 72 /** 73 * @ingroup mcr_registers 74 * Structure type to access the MCR Registers. 75 */ 76 typedef struct { 77 __R uint32_t rsv_0x0; 78 __IO uint32_t rst; /**< <tt>\b 0x04:</tt> MCR RST Register */ 79 __R uint32_t rsv_0x8_0xf[2]; 80 __IO uint32_t lppioctrl; /**< <tt>\b 0x10:</tt> MCR LPPIOCTRL Register */ 81 __R uint32_t rsv_0x14_0x23[4]; 82 __IO uint32_t clkdis; /**< <tt>\b 0x24:</tt> MCR CLKDIS Register */ 83 } mxc_mcr_regs_t; 84 85 /* Register offsets for module MCR */ 86 /** 87 * @ingroup mcr_registers 88 * @defgroup MCR_Register_Offsets Register Offsets 89 * @brief MCR Peripheral Register Offsets from the MCR Base Peripheral Address. 90 * @{ 91 */ 92 #define MXC_R_MCR_RST ((uint32_t)0x00000004UL) /**< Offset from MCR Base Address: <tt> 0x0004</tt> */ 93 #define MXC_R_MCR_LPPIOCTRL ((uint32_t)0x00000010UL) /**< Offset from MCR Base Address: <tt> 0x0010</tt> */ 94 #define MXC_R_MCR_CLKDIS ((uint32_t)0x00000024UL) /**< Offset from MCR Base Address: <tt> 0x0024</tt> */ 95 /**@} end of group mcr_registers */ 96 97 /** 98 * @ingroup mcr_registers 99 * @defgroup MCR_RST MCR_RST 100 * @brief Reset control register 0. 101 * @{ 102 */ 103 #define MXC_F_MCR_RST_LPTMR0_POS 0 /**< RST_LPTMR0 Position */ 104 #define MXC_F_MCR_RST_LPTMR0 ((uint32_t)(0x1UL << MXC_F_MCR_RST_LPTMR0_POS)) /**< RST_LPTMR0 Mask */ 105 106 #define MXC_F_MCR_RST_LPTMR1_POS 1 /**< RST_LPTMR1 Position */ 107 #define MXC_F_MCR_RST_LPTMR1 ((uint32_t)(0x1UL << MXC_F_MCR_RST_LPTMR1_POS)) /**< RST_LPTMR1 Mask */ 108 109 #define MXC_F_MCR_RST_LPUART0_POS 2 /**< RST_LPUART0 Position */ 110 #define MXC_F_MCR_RST_LPUART0 ((uint32_t)(0x1UL << MXC_F_MCR_RST_LPUART0_POS)) /**< RST_LPUART0 Mask */ 111 112 #define MXC_F_MCR_RST_RTC_POS 3 /**< RST_RTC Position */ 113 #define MXC_F_MCR_RST_RTC ((uint32_t)(0x1UL << MXC_F_MCR_RST_RTC_POS)) /**< RST_RTC Mask */ 114 115 /**@} end of group MCR_RST_Register */ 116 117 /** 118 * @ingroup mcr_registers 119 * @defgroup MCR_LPPIOCTRL MCR_LPPIOCTRL 120 * @brief Low-power peripheral IO control. 121 * @{ 122 */ 123 #define MXC_F_MCR_LPPIOCTRL_LPTMR0_I_POS 0 /**< LPPIOCTRL_LPTMR0_I Position */ 124 #define MXC_F_MCR_LPPIOCTRL_LPTMR0_I ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPTMR0_I_POS)) /**< LPPIOCTRL_LPTMR0_I Mask */ 125 126 #define MXC_F_MCR_LPPIOCTRL_LPTMR0_O_POS 1 /**< LPPIOCTRL_LPTMR0_O Position */ 127 #define MXC_F_MCR_LPPIOCTRL_LPTMR0_O ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPTMR0_O_POS)) /**< LPPIOCTRL_LPTMR0_O Mask */ 128 129 #define MXC_F_MCR_LPPIOCTRL_LPTMR1_I_POS 2 /**< LPPIOCTRL_LPTMR1_I Position */ 130 #define MXC_F_MCR_LPPIOCTRL_LPTMR1_I ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPTMR1_I_POS)) /**< LPPIOCTRL_LPTMR1_I Mask */ 131 132 #define MXC_F_MCR_LPPIOCTRL_LPTMR1_O_POS 3 /**< LPPIOCTRL_LPTMR1_O Position */ 133 #define MXC_F_MCR_LPPIOCTRL_LPTMR1_O ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPTMR1_O_POS)) /**< LPPIOCTRL_LPTMR1_O Mask */ 134 135 #define MXC_F_MCR_LPPIOCTRL_LPUART0_RX_POS 4 /**< LPPIOCTRL_LPUART0_RX Position */ 136 #define MXC_F_MCR_LPPIOCTRL_LPUART0_RX ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPUART0_RX_POS)) /**< LPPIOCTRL_LPUART0_RX Mask */ 137 138 #define MXC_F_MCR_LPPIOCTRL_LPUART0_TX_POS 5 /**< LPPIOCTRL_LPUART0_TX Position */ 139 #define MXC_F_MCR_LPPIOCTRL_LPUART0_TX ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPUART0_TX_POS)) /**< LPPIOCTRL_LPUART0_TX Mask */ 140 141 #define MXC_F_MCR_LPPIOCTRL_LPUART0_CTS_POS 6 /**< LPPIOCTRL_LPUART0_CTS Position */ 142 #define MXC_F_MCR_LPPIOCTRL_LPUART0_CTS ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPUART0_CTS_POS)) /**< LPPIOCTRL_LPUART0_CTS Mask */ 143 144 #define MXC_F_MCR_LPPIOCTRL_LPUART0_RTS_POS 7 /**< LPPIOCTRL_LPUART0_RTS Position */ 145 #define MXC_F_MCR_LPPIOCTRL_LPUART0_RTS ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_LPUART0_RTS_POS)) /**< LPPIOCTRL_LPUART0_RTS Mask */ 146 147 /**@} end of group MCR_LPPIOCTRL_Register */ 148 149 /** 150 * @ingroup mcr_registers 151 * @defgroup MCR_CLKDIS MCR_CLKDIS 152 * @brief Peripheral clock control register. 153 * @{ 154 */ 155 #define MXC_F_MCR_CLKDIS_LPTMR0_POS 0 /**< CLKDIS_LPTMR0 Position */ 156 #define MXC_F_MCR_CLKDIS_LPTMR0 ((uint32_t)(0x1UL << MXC_F_MCR_CLKDIS_LPTMR0_POS)) /**< CLKDIS_LPTMR0 Mask */ 157 158 #define MXC_F_MCR_CLKDIS_LPTMR1_POS 1 /**< CLKDIS_LPTMR1 Position */ 159 #define MXC_F_MCR_CLKDIS_LPTMR1 ((uint32_t)(0x1UL << MXC_F_MCR_CLKDIS_LPTMR1_POS)) /**< CLKDIS_LPTMR1 Mask */ 160 161 #define MXC_F_MCR_CLKDIS_LPUART0_POS 2 /**< CLKDIS_LPUART0 Position */ 162 #define MXC_F_MCR_CLKDIS_LPUART0 ((uint32_t)(0x1UL << MXC_F_MCR_CLKDIS_LPUART0_POS)) /**< CLKDIS_LPUART0 Mask */ 163 164 /**@} end of group MCR_CLKDIS_Register */ 165 166 #ifdef __cplusplus 167 } 168 #endif 169 170 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_MCR_REGS_H_ 171
