1 /** 2 * @file gcr_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup gcr_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_GCR_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_GCR_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup gcr 67 * @defgroup gcr_registers GCR_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module. 69 * @details Global Control Registers. 70 */ 71 72 /** 73 * @ingroup gcr_registers 74 * Structure type to access the GCR Registers. 75 */ 76 typedef struct { 77 __IO uint32_t sysctrl; /**< <tt>\b 0x00:</tt> GCR SYSCTRL Register */ 78 __IO uint32_t rst0; /**< <tt>\b 0x04:</tt> GCR RST0 Register */ 79 __IO uint32_t clkctrl; /**< <tt>\b 0x08:</tt> GCR CLKCTRL Register */ 80 __IO uint32_t pm; /**< <tt>\b 0x0C:</tt> GCR PM Register */ 81 __R uint32_t rsv_0x10_0x17[2]; 82 __IO uint32_t pclkdiv; /**< <tt>\b 0x18:</tt> GCR PCLKDIV Register */ 83 __R uint32_t rsv_0x1c_0x23[2]; 84 __IO uint32_t pclkdis0; /**< <tt>\b 0x24:</tt> GCR PCLKDIS0 Register */ 85 __IO uint32_t memctrl; /**< <tt>\b 0x28:</tt> GCR MEMCTRL Register */ 86 __IO uint32_t memz; /**< <tt>\b 0x2C:</tt> GCR MEMZ Register */ 87 __R uint32_t rsv_0x30_0x3f[4]; 88 __IO uint32_t sysst; /**< <tt>\b 0x40:</tt> GCR SYSST Register */ 89 __IO uint32_t rst1; /**< <tt>\b 0x44:</tt> GCR RST1 Register */ 90 __IO uint32_t pclkdis1; /**< <tt>\b 0x48:</tt> GCR PCLKDIS1 Register */ 91 __IO uint32_t eventen; /**< <tt>\b 0x4C:</tt> GCR EVENTEN Register */ 92 __I uint32_t revision; /**< <tt>\b 0x50:</tt> GCR REVISION Register */ 93 __IO uint32_t sysie; /**< <tt>\b 0x54:</tt> GCR SYSIE Register */ 94 __R uint32_t rsv_0x58_0x63[3]; 95 __IO uint32_t eccerr; /**< <tt>\b 0x64:</tt> GCR ECCERR Register */ 96 __IO uint32_t eccced; /**< <tt>\b 0x68:</tt> GCR ECCCED Register */ 97 __IO uint32_t eccie; /**< <tt>\b 0x6C:</tt> GCR ECCIE Register */ 98 __IO uint32_t eccaddr; /**< <tt>\b 0x70:</tt> GCR ECCADDR Register */ 99 } mxc_gcr_regs_t; 100 101 /* Register offsets for module GCR */ 102 /** 103 * @ingroup gcr_registers 104 * @defgroup GCR_Register_Offsets Register Offsets 105 * @brief GCR Peripheral Register Offsets from the GCR Base Peripheral Address. 106 * @{ 107 */ 108 #define MXC_R_GCR_SYSCTRL ((uint32_t)0x00000000UL) /**< Offset from GCR Base Address: <tt> 0x0000</tt> */ 109 #define MXC_R_GCR_RST0 ((uint32_t)0x00000004UL) /**< Offset from GCR Base Address: <tt> 0x0004</tt> */ 110 #define MXC_R_GCR_CLKCTRL ((uint32_t)0x00000008UL) /**< Offset from GCR Base Address: <tt> 0x0008</tt> */ 111 #define MXC_R_GCR_PM ((uint32_t)0x0000000CUL) /**< Offset from GCR Base Address: <tt> 0x000C</tt> */ 112 #define MXC_R_GCR_PCLKDIV ((uint32_t)0x00000018UL) /**< Offset from GCR Base Address: <tt> 0x0018</tt> */ 113 #define MXC_R_GCR_PCLKDIS0 ((uint32_t)0x00000024UL) /**< Offset from GCR Base Address: <tt> 0x0024</tt> */ 114 #define MXC_R_GCR_MEMCTRL ((uint32_t)0x00000028UL) /**< Offset from GCR Base Address: <tt> 0x0028</tt> */ 115 #define MXC_R_GCR_MEMZ ((uint32_t)0x0000002CUL) /**< Offset from GCR Base Address: <tt> 0x002C</tt> */ 116 #define MXC_R_GCR_SYSST ((uint32_t)0x00000040UL) /**< Offset from GCR Base Address: <tt> 0x0040</tt> */ 117 #define MXC_R_GCR_RST1 ((uint32_t)0x00000044UL) /**< Offset from GCR Base Address: <tt> 0x0044</tt> */ 118 #define MXC_R_GCR_PCLKDIS1 ((uint32_t)0x00000048UL) /**< Offset from GCR Base Address: <tt> 0x0048</tt> */ 119 #define MXC_R_GCR_EVENTEN ((uint32_t)0x0000004CUL) /**< Offset from GCR Base Address: <tt> 0x004C</tt> */ 120 #define MXC_R_GCR_REVISION ((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: <tt> 0x0050</tt> */ 121 #define MXC_R_GCR_SYSIE ((uint32_t)0x00000054UL) /**< Offset from GCR Base Address: <tt> 0x0054</tt> */ 122 #define MXC_R_GCR_ECCERR ((uint32_t)0x00000064UL) /**< Offset from GCR Base Address: <tt> 0x0064</tt> */ 123 #define MXC_R_GCR_ECCCED ((uint32_t)0x00000068UL) /**< Offset from GCR Base Address: <tt> 0x0068</tt> */ 124 #define MXC_R_GCR_ECCIE ((uint32_t)0x0000006CUL) /**< Offset from GCR Base Address: <tt> 0x006C</tt> */ 125 #define MXC_R_GCR_ECCADDR ((uint32_t)0x00000070UL) /**< Offset from GCR Base Address: <tt> 0x0070</tt> */ 126 /**@} end of group gcr_registers */ 127 128 /** 129 * @ingroup gcr_registers 130 * @defgroup GCR_SYSCTRL GCR_SYSCTRL 131 * @brief System Control. 132 * @{ 133 */ 134 #define MXC_F_GCR_SYSCTRL_SBUSARB_POS 1 /**< SYSCTRL_SBUSARB Position */ 135 #define MXC_F_GCR_SYSCTRL_SBUSARB ((uint32_t)(0x3UL << MXC_F_GCR_SYSCTRL_SBUSARB_POS)) /**< SYSCTRL_SBUSARB Mask */ 136 #define MXC_V_GCR_SYSCTRL_SBUSARB_FIX ((uint32_t)0x0UL) /**< SYSCTRL_SBUSARB_FIX Value */ 137 #define MXC_S_GCR_SYSCTRL_SBUSARB_FIX (MXC_V_GCR_SYSCTRL_SBUSARB_FIX << MXC_F_GCR_SYSCTRL_SBUSARB_POS) /**< SYSCTRL_SBUSARB_FIX Setting */ 138 #define MXC_V_GCR_SYSCTRL_SBUSARB_ROUND ((uint32_t)0x1UL) /**< SYSCTRL_SBUSARB_ROUND Value */ 139 #define MXC_S_GCR_SYSCTRL_SBUSARB_ROUND (MXC_V_GCR_SYSCTRL_SBUSARB_ROUND << MXC_F_GCR_SYSCTRL_SBUSARB_POS) /**< SYSCTRL_SBUSARB_ROUND Setting */ 140 141 #define MXC_F_GCR_SYSCTRL_FPU_DIS_POS 5 /**< SYSCTRL_FPU_DIS Position */ 142 #define MXC_F_GCR_SYSCTRL_FPU_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_FPU_DIS_POS)) /**< SYSCTRL_FPU_DIS Mask */ 143 144 #define MXC_F_GCR_SYSCTRL_ICC0_FLUSH_POS 6 /**< SYSCTRL_ICC0_FLUSH Position */ 145 #define MXC_F_GCR_SYSCTRL_ICC0_FLUSH ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_ICC0_FLUSH_POS)) /**< SYSCTRL_ICC0_FLUSH Mask */ 146 147 #define MXC_F_GCR_SYSCTRL_ROMDONE_POS 12 /**< SYSCTRL_ROMDONE Position */ 148 #define MXC_F_GCR_SYSCTRL_ROMDONE ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_ROMDONE_POS)) /**< SYSCTRL_ROMDONE Mask */ 149 150 #define MXC_F_GCR_SYSCTRL_CCHK_POS 13 /**< SYSCTRL_CCHK Position */ 151 #define MXC_F_GCR_SYSCTRL_CCHK ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CCHK_POS)) /**< SYSCTRL_CCHK Mask */ 152 153 #define MXC_F_GCR_SYSCTRL_SWD_DIS_POS 14 /**< SYSCTRL_SWD_DIS Position */ 154 #define MXC_F_GCR_SYSCTRL_SWD_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_SWD_DIS_POS)) /**< SYSCTRL_SWD_DIS Mask */ 155 156 #define MXC_F_GCR_SYSCTRL_CHKRES_POS 15 /**< SYSCTRL_CHKRES Position */ 157 #define MXC_F_GCR_SYSCTRL_CHKRES ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CHKRES_POS)) /**< SYSCTRL_CHKRES Mask */ 158 159 /**@} end of group GCR_SYSCTRL_Register */ 160 161 /** 162 * @ingroup gcr_registers 163 * @defgroup GCR_RST0 GCR_RST0 164 * @brief Reset. 165 * @{ 166 */ 167 #define MXC_F_GCR_RST0_DMA_POS 0 /**< RST0_DMA Position */ 168 #define MXC_F_GCR_RST0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_RST0_DMA_POS)) /**< RST0_DMA Mask */ 169 170 #define MXC_F_GCR_RST0_WDT0_POS 1 /**< RST0_WDT0 Position */ 171 #define MXC_F_GCR_RST0_WDT0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_WDT0_POS)) /**< RST0_WDT0 Mask */ 172 173 #define MXC_F_GCR_RST0_GPIO0_POS 2 /**< RST0_GPIO0 Position */ 174 #define MXC_F_GCR_RST0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO0_POS)) /**< RST0_GPIO0 Mask */ 175 176 #define MXC_F_GCR_RST0_GPIO1_POS 3 /**< RST0_GPIO1 Position */ 177 #define MXC_F_GCR_RST0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO1_POS)) /**< RST0_GPIO1 Mask */ 178 179 #define MXC_F_GCR_RST0_TMR0_POS 5 /**< RST0_TMR0 Position */ 180 #define MXC_F_GCR_RST0_TMR0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR0_POS)) /**< RST0_TMR0 Mask */ 181 182 #define MXC_F_GCR_RST0_TMR1_POS 6 /**< RST0_TMR1 Position */ 183 #define MXC_F_GCR_RST0_TMR1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR1_POS)) /**< RST0_TMR1 Mask */ 184 185 #define MXC_F_GCR_RST0_TMR2_POS 7 /**< RST0_TMR2 Position */ 186 #define MXC_F_GCR_RST0_TMR2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR2_POS)) /**< RST0_TMR2 Mask */ 187 188 #define MXC_F_GCR_RST0_TMR3_POS 8 /**< RST0_TMR3 Position */ 189 #define MXC_F_GCR_RST0_TMR3 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR3_POS)) /**< RST0_TMR3 Mask */ 190 191 #define MXC_F_GCR_RST0_UART0_POS 11 /**< RST0_UART0 Position */ 192 #define MXC_F_GCR_RST0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART0_POS)) /**< RST0_UART0 Mask */ 193 194 #define MXC_F_GCR_RST0_UART1_POS 12 /**< RST0_UART1 Position */ 195 #define MXC_F_GCR_RST0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART1_POS)) /**< RST0_UART1 Mask */ 196 197 #define MXC_F_GCR_RST0_SPI0_POS 13 /**< RST0_SPI0 Position */ 198 #define MXC_F_GCR_RST0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI0_POS)) /**< RST0_SPI0 Mask */ 199 200 #define MXC_F_GCR_RST0_SPI1_POS 14 /**< RST0_SPI1 Position */ 201 #define MXC_F_GCR_RST0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI1_POS)) /**< RST0_SPI1 Mask */ 202 203 #define MXC_F_GCR_RST0_SPI2_POS 15 /**< RST0_SPI2 Position */ 204 #define MXC_F_GCR_RST0_SPI2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI2_POS)) /**< RST0_SPI2 Mask */ 205 206 #define MXC_F_GCR_RST0_I2C0_POS 16 /**< RST0_I2C0 Position */ 207 #define MXC_F_GCR_RST0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_I2C0_POS)) /**< RST0_I2C0 Mask */ 208 209 #define MXC_F_GCR_RST0_RTC_POS 17 /**< RST0_RTC Position */ 210 #define MXC_F_GCR_RST0_RTC ((uint32_t)(0x1UL << MXC_F_GCR_RST0_RTC_POS)) /**< RST0_RTC Mask */ 211 212 #define MXC_F_GCR_RST0_TRNG_POS 24 /**< RST0_TRNG Position */ 213 #define MXC_F_GCR_RST0_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TRNG_POS)) /**< RST0_TRNG Mask */ 214 215 #define MXC_F_GCR_RST0_UART2_POS 28 /**< RST0_UART2 Position */ 216 #define MXC_F_GCR_RST0_UART2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART2_POS)) /**< RST0_UART2 Mask */ 217 218 #define MXC_F_GCR_RST0_SOFT_POS 29 /**< RST0_SOFT Position */ 219 #define MXC_F_GCR_RST0_SOFT ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SOFT_POS)) /**< RST0_SOFT Mask */ 220 221 #define MXC_F_GCR_RST0_PERIPH_POS 30 /**< RST0_PERIPH Position */ 222 #define MXC_F_GCR_RST0_PERIPH ((uint32_t)(0x1UL << MXC_F_GCR_RST0_PERIPH_POS)) /**< RST0_PERIPH Mask */ 223 224 #define MXC_F_GCR_RST0_SYS_POS 31 /**< RST0_SYS Position */ 225 #define MXC_F_GCR_RST0_SYS ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SYS_POS)) /**< RST0_SYS Mask */ 226 227 /**@} end of group GCR_RST0_Register */ 228 229 /** 230 * @ingroup gcr_registers 231 * @defgroup GCR_CLKCTRL GCR_CLKCTRL 232 * @brief Clock Control. 233 * @{ 234 */ 235 #define MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS 6 /**< CLKCTRL_SYSCLK_DIV Position */ 236 #define MXC_F_GCR_CLKCTRL_SYSCLK_DIV ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS)) /**< CLKCTRL_SYSCLK_DIV Mask */ 237 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV1 ((uint32_t)0x0UL) /**< CLKCTRL_SYSCLK_DIV_DIV1 Value */ 238 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV1 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV1 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV1 Setting */ 239 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV2 ((uint32_t)0x1UL) /**< CLKCTRL_SYSCLK_DIV_DIV2 Value */ 240 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV2 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV2 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV2 Setting */ 241 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV4 ((uint32_t)0x2UL) /**< CLKCTRL_SYSCLK_DIV_DIV4 Value */ 242 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV4 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV4 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV4 Setting */ 243 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV8 ((uint32_t)0x3UL) /**< CLKCTRL_SYSCLK_DIV_DIV8 Value */ 244 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV8 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV8 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV8 Setting */ 245 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV16 ((uint32_t)0x4UL) /**< CLKCTRL_SYSCLK_DIV_DIV16 Value */ 246 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV16 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV16 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV16 Setting */ 247 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV32 ((uint32_t)0x5UL) /**< CLKCTRL_SYSCLK_DIV_DIV32 Value */ 248 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV32 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV32 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV32 Setting */ 249 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV64 ((uint32_t)0x6UL) /**< CLKCTRL_SYSCLK_DIV_DIV64 Value */ 250 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV64 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV64 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV64 Setting */ 251 #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV128 ((uint32_t)0x7UL) /**< CLKCTRL_SYSCLK_DIV_DIV128 Value */ 252 #define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV128 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV128 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV128 Setting */ 253 254 #define MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS 9 /**< CLKCTRL_SYSCLK_SEL Position */ 255 #define MXC_F_GCR_CLKCTRL_SYSCLK_SEL ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS)) /**< CLKCTRL_SYSCLK_SEL Mask */ 256 #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO ((uint32_t)0x2UL) /**< CLKCTRL_SYSCLK_SEL_ERFO Value */ 257 #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERFO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_ERFO Setting */ 258 #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO ((uint32_t)0x3UL) /**< CLKCTRL_SYSCLK_SEL_INRO Value */ 259 #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_INRO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_INRO Setting */ 260 #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO ((uint32_t)0x4UL) /**< CLKCTRL_SYSCLK_SEL_IPO Value */ 261 #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_IPO Setting */ 262 #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO ((uint32_t)0x5UL) /**< CLKCTRL_SYSCLK_SEL_IBRO Value */ 263 #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IBRO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_IBRO Setting */ 264 #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO ((uint32_t)0x6UL) /**< CLKCTRL_SYSCLK_SEL_ERTCO Value */ 265 #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERTCO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_ERTCO Setting */ 266 #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK ((uint32_t)0x7UL) /**< CLKCTRL_SYSCLK_SEL_EXTCLK Value */ 267 #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_EXTCLK Setting */ 268 269 #define MXC_F_GCR_CLKCTRL_SYSCLK_RDY_POS 13 /**< CLKCTRL_SYSCLK_RDY Position */ 270 #define MXC_F_GCR_CLKCTRL_SYSCLK_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_SYSCLK_RDY_POS)) /**< CLKCTRL_SYSCLK_RDY Mask */ 271 272 #define MXC_F_GCR_CLKCTRL_IPO_DIV_POS 14 /**< CLKCTRL_IPO_DIV Position */ 273 #define MXC_F_GCR_CLKCTRL_IPO_DIV ((uint32_t)(0x3UL << MXC_F_GCR_CLKCTRL_IPO_DIV_POS)) /**< CLKCTRL_IPO_DIV Mask */ 274 #define MXC_V_GCR_CLKCTRL_IPO_DIV_DIV1 ((uint32_t)0x0UL) /**< CLKCTRL_IPO_DIV_DIV1 Value */ 275 #define MXC_S_GCR_CLKCTRL_IPO_DIV_DIV1 (MXC_V_GCR_CLKCTRL_IPO_DIV_DIV1 << MXC_F_GCR_CLKCTRL_IPO_DIV_POS) /**< CLKCTRL_IPO_DIV_DIV1 Setting */ 276 #define MXC_V_GCR_CLKCTRL_IPO_DIV_DIV2 ((uint32_t)0x1UL) /**< CLKCTRL_IPO_DIV_DIV2 Value */ 277 #define MXC_S_GCR_CLKCTRL_IPO_DIV_DIV2 (MXC_V_GCR_CLKCTRL_IPO_DIV_DIV2 << MXC_F_GCR_CLKCTRL_IPO_DIV_POS) /**< CLKCTRL_IPO_DIV_DIV2 Setting */ 278 #define MXC_V_GCR_CLKCTRL_IPO_DIV_DIV4 ((uint32_t)0x2UL) /**< CLKCTRL_IPO_DIV_DIV4 Value */ 279 #define MXC_S_GCR_CLKCTRL_IPO_DIV_DIV4 (MXC_V_GCR_CLKCTRL_IPO_DIV_DIV4 << MXC_F_GCR_CLKCTRL_IPO_DIV_POS) /**< CLKCTRL_IPO_DIV_DIV4 Setting */ 280 #define MXC_V_GCR_CLKCTRL_IPO_DIV_DIV8 ((uint32_t)0x3UL) /**< CLKCTRL_IPO_DIV_DIV8 Value */ 281 #define MXC_S_GCR_CLKCTRL_IPO_DIV_DIV8 (MXC_V_GCR_CLKCTRL_IPO_DIV_DIV8 << MXC_F_GCR_CLKCTRL_IPO_DIV_POS) /**< CLKCTRL_IPO_DIV_DIV8 Setting */ 282 283 #define MXC_F_GCR_CLKCTRL_ERFO_EN_POS 16 /**< CLKCTRL_ERFO_EN Position */ 284 #define MXC_F_GCR_CLKCTRL_ERFO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERFO_EN_POS)) /**< CLKCTRL_ERFO_EN Mask */ 285 286 #define MXC_F_GCR_CLKCTRL_ERTCO_EN_POS 17 /**< CLKCTRL_ERTCO_EN Position */ 287 #define MXC_F_GCR_CLKCTRL_ERTCO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERTCO_EN_POS)) /**< CLKCTRL_ERTCO_EN Mask */ 288 289 #define MXC_F_GCR_CLKCTRL_IPO_EN_POS 19 /**< CLKCTRL_IPO_EN Position */ 290 #define MXC_F_GCR_CLKCTRL_IPO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IPO_EN_POS)) /**< CLKCTRL_IPO_EN Mask */ 291 292 #define MXC_F_GCR_CLKCTRL_IBRO_EN_POS 20 /**< CLKCTRL_IBRO_EN Position */ 293 #define MXC_F_GCR_CLKCTRL_IBRO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_EN_POS)) /**< CLKCTRL_IBRO_EN Mask */ 294 295 #define MXC_F_GCR_CLKCTRL_IBRO_VS_POS 21 /**< CLKCTRL_IBRO_VS Position */ 296 #define MXC_F_GCR_CLKCTRL_IBRO_VS ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_VS_POS)) /**< CLKCTRL_IBRO_VS Mask */ 297 298 #define MXC_F_GCR_CLKCTRL_ERFO_RDY_POS 24 /**< CLKCTRL_ERFO_RDY Position */ 299 #define MXC_F_GCR_CLKCTRL_ERFO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERFO_RDY_POS)) /**< CLKCTRL_ERFO_RDY Mask */ 300 301 #define MXC_F_GCR_CLKCTRL_ERTCO_RDY_POS 25 /**< CLKCTRL_ERTCO_RDY Position */ 302 #define MXC_F_GCR_CLKCTRL_ERTCO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERTCO_RDY_POS)) /**< CLKCTRL_ERTCO_RDY Mask */ 303 304 #define MXC_F_GCR_CLKCTRL_IPO_RDY_POS 27 /**< CLKCTRL_IPO_RDY Position */ 305 #define MXC_F_GCR_CLKCTRL_IPO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IPO_RDY_POS)) /**< CLKCTRL_IPO_RDY Mask */ 306 307 #define MXC_F_GCR_CLKCTRL_IBRO_RDY_POS 28 /**< CLKCTRL_IBRO_RDY Position */ 308 #define MXC_F_GCR_CLKCTRL_IBRO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_RDY_POS)) /**< CLKCTRL_IBRO_RDY Mask */ 309 310 #define MXC_F_GCR_CLKCTRL_INRO_RDY_POS 29 /**< CLKCTRL_INRO_RDY Position */ 311 #define MXC_F_GCR_CLKCTRL_INRO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_INRO_RDY_POS)) /**< CLKCTRL_INRO_RDY Mask */ 312 313 #define MXC_F_GCR_CLKCTRL_EXTCLK_RDY_POS 31 /**< CLKCTRL_EXTCLK_RDY Position */ 314 #define MXC_F_GCR_CLKCTRL_EXTCLK_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_EXTCLK_RDY_POS)) /**< CLKCTRL_EXTCLK_RDY Mask */ 315 316 /**@} end of group GCR_CLKCTRL_Register */ 317 318 /** 319 * @ingroup gcr_registers 320 * @defgroup GCR_PM GCR_PM 321 * @brief Power Management. 322 * @{ 323 */ 324 #define MXC_F_GCR_PM_MODE_POS 0 /**< PM_MODE Position */ 325 #define MXC_F_GCR_PM_MODE ((uint32_t)(0x7UL << MXC_F_GCR_PM_MODE_POS)) /**< PM_MODE Mask */ 326 #define MXC_V_GCR_PM_MODE_ACTIVE ((uint32_t)0x0UL) /**< PM_MODE_ACTIVE Value */ 327 #define MXC_S_GCR_PM_MODE_ACTIVE (MXC_V_GCR_PM_MODE_ACTIVE << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_ACTIVE Setting */ 328 #define MXC_V_GCR_PM_MODE_SHUTDOWN ((uint32_t)0x3UL) /**< PM_MODE_SHUTDOWN Value */ 329 #define MXC_S_GCR_PM_MODE_SHUTDOWN (MXC_V_GCR_PM_MODE_SHUTDOWN << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_SHUTDOWN Setting */ 330 #define MXC_V_GCR_PM_MODE_BACKUP ((uint32_t)0x4UL) /**< PM_MODE_BACKUP Value */ 331 #define MXC_S_GCR_PM_MODE_BACKUP (MXC_V_GCR_PM_MODE_BACKUP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_BACKUP Setting */ 332 333 #define MXC_F_GCR_PM_GPIO_WE_POS 4 /**< PM_GPIO_WE Position */ 334 #define MXC_F_GCR_PM_GPIO_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_GPIO_WE_POS)) /**< PM_GPIO_WE Mask */ 335 336 #define MXC_F_GCR_PM_RTC_WE_POS 5 /**< PM_RTC_WE Position */ 337 #define MXC_F_GCR_PM_RTC_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_RTC_WE_POS)) /**< PM_RTC_WE Mask */ 338 339 #define MXC_F_GCR_PM_LPTMR0_WE_POS 6 /**< PM_LPTMR0_WE Position */ 340 #define MXC_F_GCR_PM_LPTMR0_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_LPTMR0_WE_POS)) /**< PM_LPTMR0_WE Mask */ 341 342 #define MXC_F_GCR_PM_LPTMR1_WE_POS 7 /**< PM_LPTMR1_WE Position */ 343 #define MXC_F_GCR_PM_LPTMR1_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_LPTMR1_WE_POS)) /**< PM_LPTMR1_WE Mask */ 344 345 #define MXC_F_GCR_PM_LPUART0_WE_POS 8 /**< PM_LPUART0_WE Position */ 346 #define MXC_F_GCR_PM_LPUART0_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_LPUART0_WE_POS)) /**< PM_LPUART0_WE Mask */ 347 348 #define MXC_F_GCR_PM_ERFO_PD_POS 12 /**< PM_ERFO_PD Position */ 349 #define MXC_F_GCR_PM_ERFO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_ERFO_PD_POS)) /**< PM_ERFO_PD Mask */ 350 351 #define MXC_F_GCR_PM_IPO_PD_POS 16 /**< PM_IPO_PD Position */ 352 #define MXC_F_GCR_PM_IPO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_IPO_PD_POS)) /**< PM_IPO_PD Mask */ 353 354 #define MXC_F_GCR_PM_IBRO_PD_POS 17 /**< PM_IBRO_PD Position */ 355 #define MXC_F_GCR_PM_IBRO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_IBRO_PD_POS)) /**< PM_IBRO_PD Mask */ 356 357 #define MXC_F_GCR_PM_ERFO_BP_POS 20 /**< PM_ERFO_BP Position */ 358 #define MXC_F_GCR_PM_ERFO_BP ((uint32_t)(0x1UL << MXC_F_GCR_PM_ERFO_BP_POS)) /**< PM_ERFO_BP Mask */ 359 360 /**@} end of group GCR_PM_Register */ 361 362 /** 363 * @ingroup gcr_registers 364 * @defgroup GCR_PCLKDIV GCR_PCLKDIV 365 * @brief Peripheral Clock Divider. 366 * @{ 367 */ 368 #define MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS 0 /**< PCLKDIV_AON_CLKDIV Position */ 369 #define MXC_F_GCR_PCLKDIV_AON_CLKDIV ((uint32_t)(0x3UL << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS)) /**< PCLKDIV_AON_CLKDIV Mask */ 370 #define MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV4 ((uint32_t)0x0UL) /**< PCLKDIV_AON_CLKDIV_DIV4 Value */ 371 #define MXC_S_GCR_PCLKDIV_AON_CLKDIV_DIV4 (MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV4 << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS) /**< PCLKDIV_AON_CLKDIV_DIV4 Setting */ 372 #define MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV8 ((uint32_t)0x1UL) /**< PCLKDIV_AON_CLKDIV_DIV8 Value */ 373 #define MXC_S_GCR_PCLKDIV_AON_CLKDIV_DIV8 (MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV8 << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS) /**< PCLKDIV_AON_CLKDIV_DIV8 Setting */ 374 #define MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV16 ((uint32_t)0x2UL) /**< PCLKDIV_AON_CLKDIV_DIV16 Value */ 375 #define MXC_S_GCR_PCLKDIV_AON_CLKDIV_DIV16 (MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV16 << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS) /**< PCLKDIV_AON_CLKDIV_DIV16 Setting */ 376 #define MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV32 ((uint32_t)0x3UL) /**< PCLKDIV_AON_CLKDIV_DIV32 Value */ 377 #define MXC_S_GCR_PCLKDIV_AON_CLKDIV_DIV32 (MXC_V_GCR_PCLKDIV_AON_CLKDIV_DIV32 << MXC_F_GCR_PCLKDIV_AON_CLKDIV_POS) /**< PCLKDIV_AON_CLKDIV_DIV32 Setting */ 378 379 #define MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_CTRL_POS 14 /**< PCLKDIV_DIV_CLK_OUT_CTRL Position */ 380 #define MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_CTRL ((uint32_t)(0x3UL << MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_CTRL_POS)) /**< PCLKDIV_DIV_CLK_OUT_CTRL Mask */ 381 382 #define MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_EN_POS 16 /**< PCLKDIV_DIV_CLK_OUT_EN Position */ 383 #define MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_EN ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIV_DIV_CLK_OUT_EN_POS)) /**< PCLKDIV_DIV_CLK_OUT_EN Mask */ 384 385 /**@} end of group GCR_PCLKDIV_Register */ 386 387 /** 388 * @ingroup gcr_registers 389 * @defgroup GCR_PCLKDIS0 GCR_PCLKDIS0 390 * @brief Peripheral Clock Disable. 391 * @{ 392 */ 393 #define MXC_F_GCR_PCLKDIS0_GPIO0_POS 0 /**< PCLKDIS0_GPIO0 Position */ 394 #define MXC_F_GCR_PCLKDIS0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_GPIO0_POS)) /**< PCLKDIS0_GPIO0 Mask */ 395 396 #define MXC_F_GCR_PCLKDIS0_GPIO1_POS 1 /**< PCLKDIS0_GPIO1 Position */ 397 #define MXC_F_GCR_PCLKDIS0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_GPIO1_POS)) /**< PCLKDIS0_GPIO1 Mask */ 398 399 #define MXC_F_GCR_PCLKDIS0_DMA_POS 5 /**< PCLKDIS0_DMA Position */ 400 #define MXC_F_GCR_PCLKDIS0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_DMA_POS)) /**< PCLKDIS0_DMA Mask */ 401 402 #define MXC_F_GCR_PCLKDIS0_SPI0_POS 6 /**< PCLKDIS0_SPI0 Position */ 403 #define MXC_F_GCR_PCLKDIS0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI0_POS)) /**< PCLKDIS0_SPI0 Mask */ 404 405 #define MXC_F_GCR_PCLKDIS0_SPI1_POS 7 /**< PCLKDIS0_SPI1 Position */ 406 #define MXC_F_GCR_PCLKDIS0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI1_POS)) /**< PCLKDIS0_SPI1 Mask */ 407 408 #define MXC_F_GCR_PCLKDIS0_SPI2_POS 8 /**< PCLKDIS0_SPI2 Position */ 409 #define MXC_F_GCR_PCLKDIS0_SPI2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI2_POS)) /**< PCLKDIS0_SPI2 Mask */ 410 411 #define MXC_F_GCR_PCLKDIS0_UART0_POS 9 /**< PCLKDIS0_UART0 Position */ 412 #define MXC_F_GCR_PCLKDIS0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_UART0_POS)) /**< PCLKDIS0_UART0 Mask */ 413 414 #define MXC_F_GCR_PCLKDIS0_UART1_POS 10 /**< PCLKDIS0_UART1 Position */ 415 #define MXC_F_GCR_PCLKDIS0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_UART1_POS)) /**< PCLKDIS0_UART1 Mask */ 416 417 #define MXC_F_GCR_PCLKDIS0_I2C0_POS 13 /**< PCLKDIS0_I2C0 Position */ 418 #define MXC_F_GCR_PCLKDIS0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_I2C0_POS)) /**< PCLKDIS0_I2C0 Mask */ 419 420 #define MXC_F_GCR_PCLKDIS0_TMR0_POS 15 /**< PCLKDIS0_TMR0 Position */ 421 #define MXC_F_GCR_PCLKDIS0_TMR0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR0_POS)) /**< PCLKDIS0_TMR0 Mask */ 422 423 #define MXC_F_GCR_PCLKDIS0_TMR1_POS 16 /**< PCLKDIS0_TMR1 Position */ 424 #define MXC_F_GCR_PCLKDIS0_TMR1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR1_POS)) /**< PCLKDIS0_TMR1 Mask */ 425 426 #define MXC_F_GCR_PCLKDIS0_TMR2_POS 17 /**< PCLKDIS0_TMR2 Position */ 427 #define MXC_F_GCR_PCLKDIS0_TMR2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR2_POS)) /**< PCLKDIS0_TMR2 Mask */ 428 429 #define MXC_F_GCR_PCLKDIS0_TMR3_POS 18 /**< PCLKDIS0_TMR3 Position */ 430 #define MXC_F_GCR_PCLKDIS0_TMR3 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR3_POS)) /**< PCLKDIS0_TMR3 Mask */ 431 432 #define MXC_F_GCR_PCLKDIS0_I2C1_POS 28 /**< PCLKDIS0_I2C1 Position */ 433 #define MXC_F_GCR_PCLKDIS0_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_I2C1_POS)) /**< PCLKDIS0_I2C1 Mask */ 434 435 /**@} end of group GCR_PCLKDIS0_Register */ 436 437 /** 438 * @ingroup gcr_registers 439 * @defgroup GCR_MEMCTRL GCR_MEMCTRL 440 * @brief Memory Clock Control Register. 441 * @{ 442 */ 443 #define MXC_F_GCR_MEMCTRL_FWS_POS 0 /**< MEMCTRL_FWS Position */ 444 #define MXC_F_GCR_MEMCTRL_FWS ((uint32_t)(0x7UL << MXC_F_GCR_MEMCTRL_FWS_POS)) /**< MEMCTRL_FWS Mask */ 445 446 #define MXC_F_GCR_MEMCTRL_RAMWS_EN_POS 4 /**< MEMCTRL_RAMWS_EN Position */ 447 #define MXC_F_GCR_MEMCTRL_RAMWS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAMWS_EN_POS)) /**< MEMCTRL_RAMWS_EN Mask */ 448 449 #define MXC_F_GCR_MEMCTRL_RAM0LS_EN_POS 8 /**< MEMCTRL_RAM0LS_EN Position */ 450 #define MXC_F_GCR_MEMCTRL_RAM0LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM0LS_EN_POS)) /**< MEMCTRL_RAM0LS_EN Mask */ 451 452 #define MXC_F_GCR_MEMCTRL_RAM1LS_EN_POS 9 /**< MEMCTRL_RAM1LS_EN Position */ 453 #define MXC_F_GCR_MEMCTRL_RAM1LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM1LS_EN_POS)) /**< MEMCTRL_RAM1LS_EN Mask */ 454 455 #define MXC_F_GCR_MEMCTRL_RAM2LS_EN_POS 10 /**< MEMCTRL_RAM2LS_EN Position */ 456 #define MXC_F_GCR_MEMCTRL_RAM2LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM2LS_EN_POS)) /**< MEMCTRL_RAM2LS_EN Mask */ 457 458 #define MXC_F_GCR_MEMCTRL_RAM3LS_EN_POS 11 /**< MEMCTRL_RAM3LS_EN Position */ 459 #define MXC_F_GCR_MEMCTRL_RAM3LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM3LS_EN_POS)) /**< MEMCTRL_RAM3LS_EN Mask */ 460 461 #define MXC_F_GCR_MEMCTRL_ICC0LS_EN_POS 12 /**< MEMCTRL_ICC0LS_EN Position */ 462 #define MXC_F_GCR_MEMCTRL_ICC0LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_ICC0LS_EN_POS)) /**< MEMCTRL_ICC0LS_EN Mask */ 463 464 #define MXC_F_GCR_MEMCTRL_ROMLS_EN_POS 13 /**< MEMCTRL_ROMLS_EN Position */ 465 #define MXC_F_GCR_MEMCTRL_ROMLS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_ROMLS_EN_POS)) /**< MEMCTRL_ROMLS_EN Mask */ 466 467 /**@} end of group GCR_MEMCTRL_Register */ 468 469 /** 470 * @ingroup gcr_registers 471 * @defgroup GCR_MEMZ GCR_MEMZ 472 * @brief Memory Zeroize Control. 473 * @{ 474 */ 475 #define MXC_F_GCR_MEMZ_RAM_POS 0 /**< MEMZ_RAM Position */ 476 #define MXC_F_GCR_MEMZ_RAM ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM_POS)) /**< MEMZ_RAM Mask */ 477 478 #define MXC_F_GCR_MEMZ_RAMCB_POS 1 /**< MEMZ_RAMCB Position */ 479 #define MXC_F_GCR_MEMZ_RAMCB ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAMCB_POS)) /**< MEMZ_RAMCB Mask */ 480 481 #define MXC_F_GCR_MEMZ_ICC0_POS 2 /**< MEMZ_ICC0 Position */ 482 #define MXC_F_GCR_MEMZ_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_ICC0_POS)) /**< MEMZ_ICC0 Mask */ 483 484 /**@} end of group GCR_MEMZ_Register */ 485 486 /** 487 * @ingroup gcr_registers 488 * @defgroup GCR_SYSST GCR_SYSST 489 * @brief System Status Register. 490 * @{ 491 */ 492 #define MXC_F_GCR_SYSST_ICELOCK_POS 0 /**< SYSST_ICELOCK Position */ 493 #define MXC_F_GCR_SYSST_ICELOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_ICELOCK_POS)) /**< SYSST_ICELOCK Mask */ 494 495 /**@} end of group GCR_SYSST_Register */ 496 497 /** 498 * @ingroup gcr_registers 499 * @defgroup GCR_RST1 GCR_RST1 500 * @brief Reset 1. 501 * @{ 502 */ 503 #define MXC_F_GCR_RST1_I2C1_POS 0 /**< RST1_I2C1 Position */ 504 #define MXC_F_GCR_RST1_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C1_POS)) /**< RST1_I2C1 Mask */ 505 506 #define MXC_F_GCR_RST1_WDT1_POS 8 /**< RST1_WDT1 Position */ 507 #define MXC_F_GCR_RST1_WDT1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_WDT1_POS)) /**< RST1_WDT1 Mask */ 508 509 #define MXC_F_GCR_RST1_CRC_POS 9 /**< RST1_CRC Position */ 510 #define MXC_F_GCR_RST1_CRC ((uint32_t)(0x1UL << MXC_F_GCR_RST1_CRC_POS)) /**< RST1_CRC Mask */ 511 512 #define MXC_F_GCR_RST1_AES_POS 10 /**< RST1_AES Position */ 513 #define MXC_F_GCR_RST1_AES ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AES_POS)) /**< RST1_AES Mask */ 514 515 #define MXC_F_GCR_RST1_AC_POS 14 /**< RST1_AC Position */ 516 #define MXC_F_GCR_RST1_AC ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AC_POS)) /**< RST1_AC Mask */ 517 518 #define MXC_F_GCR_RST1_I2C2_POS 17 /**< RST1_I2C2 Position */ 519 #define MXC_F_GCR_RST1_I2C2 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C2_POS)) /**< RST1_I2C2 Mask */ 520 521 #define MXC_F_GCR_RST1_I2S_POS 23 /**< RST1_I2S Position */ 522 #define MXC_F_GCR_RST1_I2S ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2S_POS)) /**< RST1_I2S Mask */ 523 524 /**@} end of group GCR_RST1_Register */ 525 526 /** 527 * @ingroup gcr_registers 528 * @defgroup GCR_PCLKDIS1 GCR_PCLKDIS1 529 * @brief Peripheral Clock Disable. 530 * @{ 531 */ 532 #define MXC_F_GCR_PCLKDIS1_UART2_POS 1 /**< PCLKDIS1_UART2 Position */ 533 #define MXC_F_GCR_PCLKDIS1_UART2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_UART2_POS)) /**< PCLKDIS1_UART2 Mask */ 534 535 #define MXC_F_GCR_PCLKDIS1_TRNG_POS 2 /**< PCLKDIS1_TRNG Position */ 536 #define MXC_F_GCR_PCLKDIS1_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_TRNG_POS)) /**< PCLKDIS1_TRNG Mask */ 537 538 #define MXC_F_GCR_PCLKDIS1_WWDT0_POS 4 /**< PCLKDIS1_WWDT0 Position */ 539 #define MXC_F_GCR_PCLKDIS1_WWDT0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_WWDT0_POS)) /**< PCLKDIS1_WWDT0 Mask */ 540 541 #define MXC_F_GCR_PCLKDIS1_WWDT1_POS 5 /**< PCLKDIS1_WWDT1 Position */ 542 #define MXC_F_GCR_PCLKDIS1_WWDT1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_WWDT1_POS)) /**< PCLKDIS1_WWDT1 Mask */ 543 544 #define MXC_F_GCR_PCLKDIS1_ICC0_POS 11 /**< PCLKDIS1_ICC0 Position */ 545 #define MXC_F_GCR_PCLKDIS1_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_ICC0_POS)) /**< PCLKDIS1_ICC0 Mask */ 546 547 #define MXC_F_GCR_PCLKDIS1_CRC_POS 14 /**< PCLKDIS1_CRC Position */ 548 #define MXC_F_GCR_PCLKDIS1_CRC ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_CRC_POS)) /**< PCLKDIS1_CRC Mask */ 549 550 #define MXC_F_GCR_PCLKDIS1_AES_POS 15 /**< PCLKDIS1_AES Position */ 551 #define MXC_F_GCR_PCLKDIS1_AES ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_AES_POS)) /**< PCLKDIS1_AES Mask */ 552 553 #define MXC_F_GCR_PCLKDIS1_I2C2_POS 21 /**< PCLKDIS1_I2C2 Position */ 554 #define MXC_F_GCR_PCLKDIS1_I2C2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_I2C2_POS)) /**< PCLKDIS1_I2C2 Mask */ 555 556 #define MXC_F_GCR_PCLKDIS1_I2S_POS 23 /**< PCLKDIS1_I2S Position */ 557 #define MXC_F_GCR_PCLKDIS1_I2S ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_I2S_POS)) /**< PCLKDIS1_I2S Mask */ 558 559 /**@} end of group GCR_PCLKDIS1_Register */ 560 561 /** 562 * @ingroup gcr_registers 563 * @defgroup GCR_EVENTEN GCR_EVENTEN 564 * @brief Event Enable Register. 565 * @{ 566 */ 567 #define MXC_F_GCR_EVENTEN_DMA_POS 0 /**< EVENTEN_DMA Position */ 568 #define MXC_F_GCR_EVENTEN_DMA ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_DMA_POS)) /**< EVENTEN_DMA Mask */ 569 570 #define MXC_F_GCR_EVENTEN_RX_POS 1 /**< EVENTEN_RX Position */ 571 #define MXC_F_GCR_EVENTEN_RX ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_RX_POS)) /**< EVENTEN_RX Mask */ 572 573 #define MXC_F_GCR_EVENTEN_TX_POS 2 /**< EVENTEN_TX Position */ 574 #define MXC_F_GCR_EVENTEN_TX ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_TX_POS)) /**< EVENTEN_TX Mask */ 575 576 /**@} end of group GCR_EVENTEN_Register */ 577 578 /** 579 * @ingroup gcr_registers 580 * @defgroup GCR_REVISION GCR_REVISION 581 * @brief Revision Register. 582 * @{ 583 */ 584 #define MXC_F_GCR_REVISION_REVISION_POS 0 /**< REVISION_REVISION Position */ 585 #define MXC_F_GCR_REVISION_REVISION ((uint32_t)(0xFFFFUL << MXC_F_GCR_REVISION_REVISION_POS)) /**< REVISION_REVISION Mask */ 586 587 /**@} end of group GCR_REVISION_Register */ 588 589 /** 590 * @ingroup gcr_registers 591 * @defgroup GCR_SYSIE GCR_SYSIE 592 * @brief System Status Interrupt Enable Register. 593 * @{ 594 */ 595 #define MXC_F_GCR_SYSIE_ICEUNLOCK_POS 0 /**< SYSIE_ICEUNLOCK Position */ 596 #define MXC_F_GCR_SYSIE_ICEUNLOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYSIE_ICEUNLOCK_POS)) /**< SYSIE_ICEUNLOCK Mask */ 597 598 /**@} end of group GCR_SYSIE_Register */ 599 600 /** 601 * @ingroup gcr_registers 602 * @defgroup GCR_ECCERR GCR_ECCERR 603 * @brief ECC Error Register 604 * @{ 605 */ 606 #define MXC_F_GCR_ECCERR_RAM_POS 0 /**< ECCERR_RAM Position */ 607 #define MXC_F_GCR_ECCERR_RAM ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM_POS)) /**< ECCERR_RAM Mask */ 608 609 #define MXC_F_GCR_ECCERR_ICC0_POS 1 /**< ECCERR_ICC0 Position */ 610 #define MXC_F_GCR_ECCERR_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_ICC0_POS)) /**< ECCERR_ICC0 Mask */ 611 612 #define MXC_F_GCR_ECCERR_FLASH_POS 2 /**< ECCERR_FLASH Position */ 613 #define MXC_F_GCR_ECCERR_FLASH ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_FLASH_POS)) /**< ECCERR_FLASH Mask */ 614 615 /**@} end of group GCR_ECCERR_Register */ 616 617 /** 618 * @ingroup gcr_registers 619 * @defgroup GCR_ECCCED GCR_ECCCED 620 * @brief ECC Not Double Error Detect Register 621 * @{ 622 */ 623 #define MXC_F_GCR_ECCCED_RAM_POS 0 /**< ECCCED_RAM Position */ 624 #define MXC_F_GCR_ECCCED_RAM ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM_POS)) /**< ECCCED_RAM Mask */ 625 626 #define MXC_F_GCR_ECCCED_ICC0_POS 1 /**< ECCCED_ICC0 Position */ 627 #define MXC_F_GCR_ECCCED_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_ICC0_POS)) /**< ECCCED_ICC0 Mask */ 628 629 #define MXC_F_GCR_ECCCED_FLASH_POS 2 /**< ECCCED_FLASH Position */ 630 #define MXC_F_GCR_ECCCED_FLASH ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_FLASH_POS)) /**< ECCCED_FLASH Mask */ 631 632 /**@} end of group GCR_ECCCED_Register */ 633 634 /** 635 * @ingroup gcr_registers 636 * @defgroup GCR_ECCIE GCR_ECCIE 637 * @brief ECC IRQ Enable Register 638 * @{ 639 */ 640 #define MXC_F_GCR_ECCIE_RAM_POS 0 /**< ECCIE_RAM Position */ 641 #define MXC_F_GCR_ECCIE_RAM ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_RAM_POS)) /**< ECCIE_RAM Mask */ 642 643 #define MXC_F_GCR_ECCIE_ICC0_POS 1 /**< ECCIE_ICC0 Position */ 644 #define MXC_F_GCR_ECCIE_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_ICC0_POS)) /**< ECCIE_ICC0 Mask */ 645 646 #define MXC_F_GCR_ECCIE_FLASH_POS 2 /**< ECCIE_FLASH Position */ 647 #define MXC_F_GCR_ECCIE_FLASH ((uint32_t)(0x1UL << MXC_F_GCR_ECCIE_FLASH_POS)) /**< ECCIE_FLASH Mask */ 648 649 /**@} end of group GCR_ECCIE_Register */ 650 651 /** 652 * @ingroup gcr_registers 653 * @defgroup GCR_ECCADDR GCR_ECCADDR 654 * @brief ECC Error Address Register 655 * @{ 656 */ 657 #define MXC_F_GCR_ECCADDR_DATARAMADDR_POS 0 /**< ECCADDR_DATARAMADDR Position */ 658 #define MXC_F_GCR_ECCADDR_DATARAMADDR ((uint32_t)(0x3FFFUL << MXC_F_GCR_ECCADDR_DATARAMADDR_POS)) /**< ECCADDR_DATARAMADDR Mask */ 659 660 #define MXC_F_GCR_ECCADDR_DATARAMBANK_POS 14 /**< ECCADDR_DATARAMBANK Position */ 661 #define MXC_F_GCR_ECCADDR_DATARAMBANK ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_DATARAMBANK_POS)) /**< ECCADDR_DATARAMBANK Mask */ 662 663 #define MXC_F_GCR_ECCADDR_DATARAMERR_POS 15 /**< ECCADDR_DATARAMERR Position */ 664 #define MXC_F_GCR_ECCADDR_DATARAMERR ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_DATARAMERR_POS)) /**< ECCADDR_DATARAMERR Mask */ 665 666 #define MXC_F_GCR_ECCADDR_TAGRAMADDR_POS 16 /**< ECCADDR_TAGRAMADDR Position */ 667 #define MXC_F_GCR_ECCADDR_TAGRAMADDR ((uint32_t)(0x3FFFUL << MXC_F_GCR_ECCADDR_TAGRAMADDR_POS)) /**< ECCADDR_TAGRAMADDR Mask */ 668 669 #define MXC_F_GCR_ECCADDR_TAGRAMBANK_POS 30 /**< ECCADDR_TAGRAMBANK Position */ 670 #define MXC_F_GCR_ECCADDR_TAGRAMBANK ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_TAGRAMBANK_POS)) /**< ECCADDR_TAGRAMBANK Mask */ 671 672 #define MXC_F_GCR_ECCADDR_TAGRAMERR_POS 31 /**< ECCADDR_TAGRAMERR Position */ 673 #define MXC_F_GCR_ECCADDR_TAGRAMERR ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_TAGRAMERR_POS)) /**< ECCADDR_TAGRAMERR Mask */ 674 675 /**@} end of group GCR_ECCADDR_Register */ 676 677 #ifdef __cplusplus 678 } 679 #endif 680 681 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_GCR_REGS_H_ 682
