1 /** 2 * @file flc_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup flc_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_FLC_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_FLC_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup flc 67 * @defgroup flc_registers FLC_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module. 69 * @details Flash Memory Control. 70 */ 71 72 /** 73 * @ingroup flc_registers 74 * Structure type to access the FLC Registers. 75 */ 76 typedef struct { 77 __IO uint32_t addr; /**< <tt>\b 0x00:</tt> FLC ADDR Register */ 78 __IO uint32_t clkdiv; /**< <tt>\b 0x04:</tt> FLC CLKDIV Register */ 79 __IO uint32_t ctrl; /**< <tt>\b 0x08:</tt> FLC CTRL Register */ 80 __R uint32_t rsv_0xc_0x23[6]; 81 __IO uint32_t intr; /**< <tt>\b 0x024:</tt> FLC INTR Register */ 82 __IO uint32_t eccdata; /**< <tt>\b 0x028:</tt> FLC ECCDATA Register */ 83 __R uint32_t rsv_0x2c; 84 __IO uint32_t data[4]; /**< <tt>\b 0x30:</tt> FLC DATA Register */ 85 __O uint32_t actrl; /**< <tt>\b 0x40:</tt> FLC ACTRL Register */ 86 __R uint32_t rsv_0x44_0x7f[15]; 87 __IO uint32_t welr0; /**< <tt>\b 0x80:</tt> FLC WELR0 Register */ 88 __R uint32_t rsv_0x84; 89 __IO uint32_t welr1; /**< <tt>\b 0x88:</tt> FLC WELR1 Register */ 90 __R uint32_t rsv_0x8c; 91 __IO uint32_t rlr0; /**< <tt>\b 0x90:</tt> FLC RLR0 Register */ 92 __R uint32_t rsv_0x94; 93 __IO uint32_t rlr1; /**< <tt>\b 0x98:</tt> FLC RLR1 Register */ 94 } mxc_flc_regs_t; 95 96 /* Register offsets for module FLC */ 97 /** 98 * @ingroup flc_registers 99 * @defgroup FLC_Register_Offsets Register Offsets 100 * @brief FLC Peripheral Register Offsets from the FLC Base Peripheral Address. 101 * @{ 102 */ 103 #define MXC_R_FLC_ADDR ((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: <tt> 0x0000</tt> */ 104 #define MXC_R_FLC_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: <tt> 0x0004</tt> */ 105 #define MXC_R_FLC_CTRL ((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: <tt> 0x0008</tt> */ 106 #define MXC_R_FLC_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: <tt> 0x0024</tt> */ 107 #define MXC_R_FLC_ECCDATA ((uint32_t)0x00000028UL) /**< Offset from FLC Base Address: <tt> 0x0028</tt> */ 108 #define MXC_R_FLC_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: <tt> 0x0030</tt> */ 109 #define MXC_R_FLC_ACTRL ((uint32_t)0x00000040UL) /**< Offset from FLC Base Address: <tt> 0x0040</tt> */ 110 #define MXC_R_FLC_WELR0 ((uint32_t)0x00000080UL) /**< Offset from FLC Base Address: <tt> 0x0080</tt> */ 111 #define MXC_R_FLC_WELR1 ((uint32_t)0x00000088UL) /**< Offset from FLC Base Address: <tt> 0x0088</tt> */ 112 #define MXC_R_FLC_RLR0 ((uint32_t)0x00000090UL) /**< Offset from FLC Base Address: <tt> 0x0090</tt> */ 113 #define MXC_R_FLC_RLR1 ((uint32_t)0x00000098UL) /**< Offset from FLC Base Address: <tt> 0x0098</tt> */ 114 /**@} end of group flc_registers */ 115 116 /** 117 * @ingroup flc_registers 118 * @defgroup FLC_ADDR FLC_ADDR 119 * @brief Flash Write Address. 120 * @{ 121 */ 122 #define MXC_F_FLC_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */ 123 #define MXC_F_FLC_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */ 124 125 /**@} end of group FLC_ADDR_Register */ 126 127 /** 128 * @ingroup flc_registers 129 * @defgroup FLC_CLKDIV FLC_CLKDIV 130 * @brief Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 131 * MHz clock for Flash controller. 132 * @{ 133 */ 134 #define MXC_F_FLC_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */ 135 #define MXC_F_FLC_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */ 136 137 /**@} end of group FLC_CLKDIV_Register */ 138 139 /** 140 * @ingroup flc_registers 141 * @defgroup FLC_CTRL FLC_CTRL 142 * @brief Flash Control Register. 143 * @{ 144 */ 145 #define MXC_F_FLC_CTRL_WR_POS 0 /**< CTRL_WR Position */ 146 #define MXC_F_FLC_CTRL_WR ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_WR_POS)) /**< CTRL_WR Mask */ 147 148 #define MXC_F_FLC_CTRL_ME_POS 1 /**< CTRL_ME Position */ 149 #define MXC_F_FLC_CTRL_ME ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_ME_POS)) /**< CTRL_ME Mask */ 150 151 #define MXC_F_FLC_CTRL_PGE_POS 2 /**< CTRL_PGE Position */ 152 #define MXC_F_FLC_CTRL_PGE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_PGE_POS)) /**< CTRL_PGE Mask */ 153 154 #define MXC_F_FLC_CTRL_ERASE_CODE_POS 8 /**< CTRL_ERASE_CODE Position */ 155 #define MXC_F_FLC_CTRL_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS)) /**< CTRL_ERASE_CODE Mask */ 156 #define MXC_V_FLC_CTRL_ERASE_CODE_NOP ((uint32_t)0x0UL) /**< CTRL_ERASE_CODE_NOP Value */ 157 #define MXC_S_FLC_CTRL_ERASE_CODE_NOP (MXC_V_FLC_CTRL_ERASE_CODE_NOP << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_NOP Setting */ 158 #define MXC_V_FLC_CTRL_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL) /**< CTRL_ERASE_CODE_ERASEPAGE Value */ 159 #define MXC_S_FLC_CTRL_ERASE_CODE_ERASEPAGE (MXC_V_FLC_CTRL_ERASE_CODE_ERASEPAGE << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEPAGE Setting */ 160 #define MXC_V_FLC_CTRL_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL) /**< CTRL_ERASE_CODE_ERASEALL Value */ 161 #define MXC_S_FLC_CTRL_ERASE_CODE_ERASEALL (MXC_V_FLC_CTRL_ERASE_CODE_ERASEALL << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEALL Setting */ 162 163 #define MXC_F_FLC_CTRL_PEND_POS 24 /**< CTRL_PEND Position */ 164 #define MXC_F_FLC_CTRL_PEND ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_PEND_POS)) /**< CTRL_PEND Mask */ 165 166 #define MXC_F_FLC_CTRL_LVE_POS 25 /**< CTRL_LVE Position */ 167 #define MXC_F_FLC_CTRL_LVE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_LVE_POS)) /**< CTRL_LVE Mask */ 168 169 #define MXC_F_FLC_CTRL_UNLOCK_POS 28 /**< CTRL_UNLOCK Position */ 170 #define MXC_F_FLC_CTRL_UNLOCK ((uint32_t)(0xFUL << MXC_F_FLC_CTRL_UNLOCK_POS)) /**< CTRL_UNLOCK Mask */ 171 #define MXC_V_FLC_CTRL_UNLOCK_UNLOCKED ((uint32_t)0x2UL) /**< CTRL_UNLOCK_UNLOCKED Value */ 172 #define MXC_S_FLC_CTRL_UNLOCK_UNLOCKED (MXC_V_FLC_CTRL_UNLOCK_UNLOCKED << MXC_F_FLC_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_UNLOCKED Setting */ 173 #define MXC_V_FLC_CTRL_UNLOCK_LOCKED ((uint32_t)0x3UL) /**< CTRL_UNLOCK_LOCKED Value */ 174 #define MXC_S_FLC_CTRL_UNLOCK_LOCKED (MXC_V_FLC_CTRL_UNLOCK_LOCKED << MXC_F_FLC_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_LOCKED Setting */ 175 176 /**@} end of group FLC_CTRL_Register */ 177 178 /** 179 * @ingroup flc_registers 180 * @defgroup FLC_INTR FLC_INTR 181 * @brief Flash Interrupt Register. 182 * @{ 183 */ 184 #define MXC_F_FLC_INTR_DONE_POS 0 /**< INTR_DONE Position */ 185 #define MXC_F_FLC_INTR_DONE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_POS)) /**< INTR_DONE Mask */ 186 187 #define MXC_F_FLC_INTR_AF_POS 1 /**< INTR_AF Position */ 188 #define MXC_F_FLC_INTR_AF ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AF_POS)) /**< INTR_AF Mask */ 189 190 #define MXC_F_FLC_INTR_DONEIE_POS 8 /**< INTR_DONEIE Position */ 191 #define MXC_F_FLC_INTR_DONEIE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask */ 192 193 #define MXC_F_FLC_INTR_AFIE_POS 9 /**< INTR_AFIE Position */ 194 #define MXC_F_FLC_INTR_AFIE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AFIE_POS)) /**< INTR_AFIE Mask */ 195 196 /**@} end of group FLC_INTR_Register */ 197 198 /** 199 * @ingroup flc_registers 200 * @defgroup FLC_ECCDATA FLC_ECCDATA 201 * @brief ECC Data Register. 202 * @{ 203 */ 204 #define MXC_F_FLC_ECCDATA_EVEN_POS 0 /**< ECCDATA_EVEN Position */ 205 #define MXC_F_FLC_ECCDATA_EVEN ((uint32_t)(0x1FFUL << MXC_F_FLC_ECCDATA_EVEN_POS)) /**< ECCDATA_EVEN Mask */ 206 207 #define MXC_F_FLC_ECCDATA_ODD_POS 16 /**< ECCDATA_ODD Position */ 208 #define MXC_F_FLC_ECCDATA_ODD ((uint32_t)(0x1FFUL << MXC_F_FLC_ECCDATA_ODD_POS)) /**< ECCDATA_ODD Mask */ 209 210 /**@} end of group FLC_ECCDATA_Register */ 211 212 /** 213 * @ingroup flc_registers 214 * @defgroup FLC_DATA FLC_DATA 215 * @brief Flash Write Data. 216 * @{ 217 */ 218 #define MXC_F_FLC_DATA_DATA_POS 0 /**< DATA_DATA Position */ 219 #define MXC_F_FLC_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_DATA_DATA_POS)) /**< DATA_DATA Mask */ 220 221 /**@} end of group FLC_DATA_Register */ 222 223 /** 224 * @ingroup flc_registers 225 * @defgroup FLC_ACTRL FLC_ACTRL 226 * @brief Access Control Register. Writing the ACTRL register with the following values in 227 * the order shown, allows read and write access to the system and user Information 228 * block: pflc-actrl = 0x3a7f5ca3; pflc-actrl = 0xa1e34f20; pflc-actrl 229 * = 0x9608b2c1. When unlocked, a write of any word will disable access to system 230 * and user information block. Readback of this register is always zero. 231 * @{ 232 */ 233 #define MXC_F_FLC_ACTRL_ACTRL_POS 0 /**< ACTRL_ACTRL Position */ 234 #define MXC_F_FLC_ACTRL_ACTRL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ACTRL_ACTRL_POS)) /**< ACTRL_ACTRL Mask */ 235 236 /**@} end of group FLC_ACTRL_Register */ 237 238 /** 239 * @ingroup flc_registers 240 * @defgroup FLC_WELR0 FLC_WELR0 241 * @brief WELR0 242 * @{ 243 */ 244 #define MXC_F_FLC_WELR0_WELR0_POS 0 /**< WELR0_WELR0 Position */ 245 #define MXC_F_FLC_WELR0_WELR0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_WELR0_WELR0_POS)) /**< WELR0_WELR0 Mask */ 246 247 /**@} end of group FLC_WELR0_Register */ 248 249 /** 250 * @ingroup flc_registers 251 * @defgroup FLC_WELR1 FLC_WELR1 252 * @brief WELR1 253 * @{ 254 */ 255 #define MXC_F_FLC_WELR1_WELR1_POS 0 /**< WELR1_WELR1 Position */ 256 #define MXC_F_FLC_WELR1_WELR1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_WELR1_WELR1_POS)) /**< WELR1_WELR1 Mask */ 257 258 /**@} end of group FLC_WELR1_Register */ 259 260 /** 261 * @ingroup flc_registers 262 * @defgroup FLC_RLR0 FLC_RLR0 263 * @brief RLR0 264 * @{ 265 */ 266 #define MXC_F_FLC_RLR0_RLR0_POS 0 /**< RLR0_RLR0 Position */ 267 #define MXC_F_FLC_RLR0_RLR0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_RLR0_RLR0_POS)) /**< RLR0_RLR0 Mask */ 268 269 /**@} end of group FLC_RLR0_Register */ 270 271 /** 272 * @ingroup flc_registers 273 * @defgroup FLC_RLR1 FLC_RLR1 274 * @brief RLR1 275 * @{ 276 */ 277 #define MXC_F_FLC_RLR1_RLR1_POS 0 /**< RLR1_RLR1 Position */ 278 #define MXC_F_FLC_RLR1_RLR1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_RLR1_RLR1_POS)) /**< RLR1_RLR1 Mask */ 279 280 /**@} end of group FLC_RLR1_Register */ 281 282 #ifdef __cplusplus 283 } 284 #endif 285 286 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32670_INCLUDE_FLC_REGS_H_ 287
