1 /******************************************************************************
2 *
3 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
4 * Analog Devices, Inc.),
5 * Copyright (C) 2023-2024 Analog Devices, Inc.
6 *
7 * Licensed under the Apache License, Version 2.0 (the "License");
8 * you may not use this file except in compliance with the License.
9 * You may obtain a copy of the License at
10 *
11 * http://www.apache.org/licenses/LICENSE-2.0
12 *
13 * Unless required by applicable law or agreed to in writing, software
14 * distributed under the License is distributed on an "AS IS" BASIS,
15 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 * See the License for the specific language governing permissions and
17 * limitations under the License.
18 *
19 ******************************************************************************/
20
21 #include <string.h>
22 #include <stdio.h>
23 #include <stdlib.h>
24 #include "max32665.h"
25 #include "mxc_sys.h"
26 #include "gcr_regs.h"
27 #include "icc_regs.h"
28 #include "pwrseq_regs.h"
29 #include "simo_regs.h"
30 #include "mcr_regs.h"
31 #include "lp.h"
32
33 // Backup mode entry point
34 extern void Reset_Handler(void);
35
36 extern void (*const __isr_vector[])(void);
37
38 // Part defaults to HIRC/2 out of reset
39 uint32_t SystemCoreClock = HIRC_FREQ >> 1;
40
41 /*
42 The libc implementation from GCC 11+ depends on _getpid and _kill in some places.
43 There is no concept of processes/PIDs in the baremetal PeriphDrivers, therefore
44 we implement stub functions that return an error code to resolve linker warnings.
45 */
_getpid(void)46 __weak int _getpid(void)
47 {
48 return E_NOT_SUPPORTED;
49 }
50
_kill(void)51 __weak int _kill(void)
52 {
53 return E_NOT_SUPPORTED;
54 }
55
SystemCoreClockUpdate(void)56 __weak void SystemCoreClockUpdate(void)
57 {
58 uint32_t base_freq, div, clk_src;
59
60 // Determine the clock source and frequency
61 clk_src = (MXC_GCR->clkcn & MXC_F_GCR_CLKCN_CLKSEL);
62 switch (clk_src) {
63 case MXC_S_GCR_CLKCN_CLKSEL_HIRC:
64 base_freq = HIRC_FREQ;
65 break;
66 case MXC_S_GCR_CLKCN_CLKSEL_XTAL32M:
67 base_freq = XTAL32M_FREQ;
68 break;
69 case MXC_S_GCR_CLKCN_CLKSEL_LIRC8:
70 base_freq = LIRC8_FREQ;
71 break;
72 case MXC_S_GCR_CLKCN_CLKSEL_HIRC96:
73 base_freq = HIRC96_FREQ;
74 break;
75 case MXC_S_GCR_CLKCN_CLKSEL_HIRC8:
76 base_freq = HIRC8_FREQ;
77 break;
78 case MXC_S_GCR_CLKCN_CLKSEL_XTAL32K:
79 base_freq = XTAL32K_FREQ;
80 break;
81 default:
82 // Values 001 and 111 are reserved, and should never be encountered.
83 base_freq = HIRC_FREQ;
84 break;
85 }
86 // Clock divider is retrieved to compute system clock
87 div = (MXC_GCR->clkcn & MXC_F_GCR_CLKCN_PSC) >> MXC_F_GCR_CLKCN_PSC_POS;
88
89 SystemCoreClock = base_freq >> div;
90 }
91
92 /* This function is called before C runtime initialization and can be
93 * implemented by the application for early initializations. If a value other
94 * than '0' is returned, the C runtime initialization will be skipped.
95 *
96 * You may over-ride this function in your program by defining a custom
97 * PreInit(), but care should be taken to reproduce the initialization steps
98 * or a non-functional system may result.
99 */
PreInit(void)100 __weak int PreInit(void)
101 {
102 uint32_t psc = MXC_GCR->clkcn & MXC_F_GCR_CLKCN_PSC;
103
104 /* Disable USB switch to minimize current consumption */
105 MXC_MCR->ctrl |= MXC_F_MCR_CTRL_USBSWEN_N;
106
107 /* Divide down system clock until SIMO is ready */
108 MXC_GCR->clkcn = (MXC_GCR->clkcn & ~(MXC_F_GCR_CLKCN_PSC)) | (MXC_S_GCR_CLKCN_PSC_DIV128);
109
110 while (!(MXC_SIMO->buck_out_ready & MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYA)) {}
111 while (!(MXC_SIMO->buck_out_ready & MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYB)) {}
112 while (!(MXC_SIMO->buck_out_ready & MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYC)) {}
113
114 /* Restore system clock divider */
115 MXC_GCR->clkcn = (MXC_GCR->clkcn & ~(MXC_F_GCR_CLKCN_PSC)) | (psc);
116
117 /* Set the proper OVR setting */
118 MXC_GCR->scon = (MXC_GCR->scon & ~(MXC_F_GCR_SCON_OVR)) | (MXC_S_GCR_SCON_OVR_1_1V);
119
120 return 0;
121 }
122
123 // This function can be implemented by the application to initialize the board
Board_Init(void)124 __weak int Board_Init(void)
125 {
126 // Do nothing
127 return 0;
128 }
129
PalSysInit(void)130 __weak void PalSysInit(void) {}
131
132 /* This function is called just before control is transferred to main().
133 *
134 * You may over-ride this function in your program by defining a custom
135 * SystemInit(), but care should be taken to reproduce the initialization
136 * steps or a non-functional system may result.
137 */
SystemInit(void)138 __weak void SystemInit(void)
139 {
140 /* Configure the interrupt controller to use the application vector
141 * table in flash. Initially, VTOR points to the ROM's table.
142 */
143 SCB->VTOR = (uint32_t)&__isr_vector;
144
145 /* We'd like to switch to the fast clock, but can only do so if the
146 * core's operating voltage (VregO_B) is high enough to support it
147 * Otherwise, we need to remain on the slow clock
148 */
149 if ((MXC_SIMO->vrego_b > 48) && (MXC_SIMO->buck_out_ready & 0x2)) {
150 // Switch to fast clock on startup
151 MXC_GCR->clkcn &= ~(MXC_S_GCR_CLKCN_PSC_DIV128);
152 MXC_SYS_Clock_Select(MXC_SYS_CLOCK_HIRC96);
153 }
154
155 /* Enable FPU on Cortex-M4, which occupies coprocessor slots 10 & 11
156 * Grant full access, per "Table B3-24 CPACR bit assignments".
157 * DDI0403D "ARMv7-M Architecture Reference Manual"
158 */
159 SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk;
160 __DSB();
161 __ISB();
162
163 // Initialize backup mode entry point to safe default value.
164 MXC_PWRSEQ->buretvec = (uint32_t)(Reset_Handler) | 1;
165
166 // FIXME Pre-production parts: Enable TME, disable ICache Read Buffer, disable TME
167 *(uint32_t *)0x40000c00 = 1;
168 *(uint32_t *)0x4000040c = (1 << 6);
169 *(uint32_t *)0x40000c00 = 0;
170
171 // Flush and enable instruction cache
172 MXC_ICC0->invalidate = 1;
173 while (!(MXC_ICC0->cache_ctrl & MXC_F_ICC_CACHE_CTRL_RDY)) {}
174 MXC_ICC0->cache_ctrl |= MXC_F_ICC_CACHE_CTRL_EN;
175 while (!(MXC_ICC0->cache_ctrl & MXC_F_ICC_CACHE_CTRL_RDY)) {}
176
177 SystemCoreClockUpdate();
178
179 // Set all GPIO to 25K pullup mode by default
180 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO0);
181 MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO1);
182 MXC_GPIO0->vssel |= 0xFFFFFFFF;
183 MXC_GPIO0->ps |= 0xFFFFFFFF;
184 MXC_GPIO0->pad_cfg1 |= 0xFFFFFFFF;
185 MXC_GPIO0->pad_cfg2 &= ~(0xFFFFFFFF);
186 MXC_GPIO1->vssel |= 0xFFFFFFFF;
187 MXC_GPIO1->ps |= 0xFFFFFFFF;
188 MXC_GPIO1->pad_cfg1 |= 0xFFFFFFFF;
189 MXC_GPIO1->pad_cfg2 &= ~(0xFFFFFFFF);
190
191 /* Disable fast wakeup due to issues with SIMO in wakeup */
192 MXC_PWRSEQ->lpcn &= ~MXC_F_PWRSEQ_LPCN_FWKM;
193
194 Board_Init();
195
196 PalSysInit();
197 }
198
199 #if defined(__CC_ARM)
200 /* Global variable initialization does not occur until post scatterload in Keil tools.*/
201
202 /* External function called after our post scatterload function implementation. */
203 extern void $Super$$__main_after_scatterload(void);
204
205 /**
206 * @brief Initialization function for SystemCoreClock and Board_Init.
207 * @details $Sub$$__main_after_scatterload is called during system startup in the Keil
208 * toolset. Global variable and static variable space must be set up by the compiler
209 * prior to using these memory spaces. Setting up the SystemCoreClock and Board_Init
210 * require global memory for variable storage and are called from this function in
211 * the Keil tool chain.
212 */
$Sub$$__main_after_scatterload(void)213 void $Sub$$__main_after_scatterload(void)
214 {
215 SystemInit();
216 $Super$$__main_after_scatterload();
217 while (1) {}
218 }
219 #endif /* __CC_ARM */
220
