1 /** 2 * @file spixr_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SPIXR Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup spixr_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_SPIXR_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_SPIXR_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup spixr 67 * @defgroup spixr_registers SPIXR_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the SPIXR Peripheral Module. 69 * @details SPIXR peripheral. 70 */ 71 72 /** 73 * @ingroup spixr_registers 74 * Structure type to access the SPIXR Registers. 75 */ 76 typedef struct { 77 union { 78 __IO uint32_t data32; /**< <tt>\b 0x00:</tt> SPIXR DATA32 Register */ 79 __IO uint16_t data16[2]; /**< <tt>\b 0x00:</tt> SPIXR DATA16 Register */ 80 __IO uint8_t data8[4]; /**< <tt>\b 0x00:</tt> SPIXR DATA8 Register */ 81 }; 82 __IO uint32_t ctrl1; /**< <tt>\b 0x04:</tt> SPIXR CTRL1 Register */ 83 __IO uint32_t ctrl2; /**< <tt>\b 0x08:</tt> SPIXR CTRL2 Register */ 84 __IO uint32_t ctrl3; /**< <tt>\b 0x0C:</tt> SPIXR CTRL3 Register */ 85 __IO uint32_t ctrl4; /**< <tt>\b 0x10:</tt> SPIXR CTRL4 Register */ 86 __IO uint32_t brg_ctrl; /**< <tt>\b 0x14:</tt> SPIXR BRG_CTRL Register */ 87 __R uint32_t rsv_0x18; 88 __IO uint32_t dma; /**< <tt>\b 0x1C:</tt> SPIXR DMA Register */ 89 __IO uint32_t irq; /**< <tt>\b 0x20:</tt> SPIXR IRQ Register */ 90 __IO uint32_t irqe; /**< <tt>\b 0x24:</tt> SPIXR IRQE Register */ 91 __IO uint32_t wake; /**< <tt>\b 0x28:</tt> SPIXR WAKE Register */ 92 __IO uint32_t wakee; /**< <tt>\b 0x2C:</tt> SPIXR WAKEE Register */ 93 __I uint32_t stat; /**< <tt>\b 0x30:</tt> SPIXR STAT Register */ 94 __IO uint32_t xmem_ctrl; /**< <tt>\b 0x34:</tt> SPIXR XMEM_CTRL Register */ 95 } mxc_spixr_regs_t; 96 97 /* Register offsets for module SPIXR */ 98 /** 99 * @ingroup spixr_registers 100 * @defgroup SPIXR_Register_Offsets Register Offsets 101 * @brief SPIXR Peripheral Register Offsets from the SPIXR Base Peripheral Address. 102 * @{ 103 */ 104 #define MXC_R_SPIXR_DATA32 ((uint32_t)0x00000000UL) /**< Offset from SPIXR Base Address: <tt> 0x0000</tt> */ 105 #define MXC_R_SPIXR_DATA16 ((uint32_t)0x00000000UL) /**< Offset from SPIXR Base Address: <tt> 0x0000</tt> */ 106 #define MXC_R_SPIXR_DATA8 ((uint32_t)0x00000000UL) /**< Offset from SPIXR Base Address: <tt> 0x0000</tt> */ 107 #define MXC_R_SPIXR_CTRL1 ((uint32_t)0x00000004UL) /**< Offset from SPIXR Base Address: <tt> 0x0004</tt> */ 108 #define MXC_R_SPIXR_CTRL2 ((uint32_t)0x00000008UL) /**< Offset from SPIXR Base Address: <tt> 0x0008</tt> */ 109 #define MXC_R_SPIXR_CTRL3 ((uint32_t)0x0000000CUL) /**< Offset from SPIXR Base Address: <tt> 0x000C</tt> */ 110 #define MXC_R_SPIXR_CTRL4 ((uint32_t)0x00000010UL) /**< Offset from SPIXR Base Address: <tt> 0x0010</tt> */ 111 #define MXC_R_SPIXR_BRG_CTRL ((uint32_t)0x00000014UL) /**< Offset from SPIXR Base Address: <tt> 0x0014</tt> */ 112 #define MXC_R_SPIXR_DMA ((uint32_t)0x0000001CUL) /**< Offset from SPIXR Base Address: <tt> 0x001C</tt> */ 113 #define MXC_R_SPIXR_IRQ ((uint32_t)0x00000020UL) /**< Offset from SPIXR Base Address: <tt> 0x0020</tt> */ 114 #define MXC_R_SPIXR_IRQE ((uint32_t)0x00000024UL) /**< Offset from SPIXR Base Address: <tt> 0x0024</tt> */ 115 #define MXC_R_SPIXR_WAKE ((uint32_t)0x00000028UL) /**< Offset from SPIXR Base Address: <tt> 0x0028</tt> */ 116 #define MXC_R_SPIXR_WAKEE ((uint32_t)0x0000002CUL) /**< Offset from SPIXR Base Address: <tt> 0x002C</tt> */ 117 #define MXC_R_SPIXR_STAT ((uint32_t)0x00000030UL) /**< Offset from SPIXR Base Address: <tt> 0x0030</tt> */ 118 #define MXC_R_SPIXR_XMEM_CTRL ((uint32_t)0x00000034UL) /**< Offset from SPIXR Base Address: <tt> 0x0034</tt> */ 119 /**@} end of group spixr_registers */ 120 121 /** 122 * @ingroup spixr_registers 123 * @defgroup SPIXR_DATA32 SPIXR_DATA32 124 * @brief Register for reading and writing the FIFO. 125 * @{ 126 */ 127 #define MXC_F_SPIXR_DATA32_DATA_POS 0 /**< DATA32_DATA Position */ 128 #define MXC_F_SPIXR_DATA32_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_SPIXR_DATA32_DATA_POS)) /**< DATA32_DATA Mask */ 129 130 /**@} end of group SPIXR_DATA32_Register */ 131 132 /** 133 * @ingroup spixr_registers 134 * @defgroup SPIXR_DATA16 SPIXR_DATA16 135 * @brief Register for reading and writing the FIFO. 136 * @{ 137 */ 138 #define MXC_F_SPIXR_DATA16_DATA_POS 0 /**< DATA16_DATA Position */ 139 #define MXC_F_SPIXR_DATA16_DATA ((uint16_t)(0xFFFFUL << MXC_F_SPIXR_DATA16_DATA_POS)) /**< DATA16_DATA Mask */ 140 141 /**@} end of group SPIXR_DATA16_Register */ 142 143 /** 144 * @ingroup spixr_registers 145 * @defgroup SPIXR_DATA8 SPIXR_DATA8 146 * @brief Register for reading and writing the FIFO. 147 * @{ 148 */ 149 #define MXC_F_SPIXR_DATA8_DATA_POS 0 /**< DATA8_DATA Position */ 150 #define MXC_F_SPIXR_DATA8_DATA ((uint8_t)(0xFFUL << MXC_F_SPIXR_DATA8_DATA_POS)) /**< DATA8_DATA Mask */ 151 152 /**@} end of group SPIXR_DATA8_Register */ 153 154 /** 155 * @ingroup spixr_registers 156 * @defgroup SPIXR_CTRL1 SPIXR_CTRL1 157 * @brief Register for controlling SPI peripheral. 158 * @{ 159 */ 160 #define MXC_F_SPIXR_CTRL1_SPIEN_POS 0 /**< CTRL1_SPIEN Position */ 161 #define MXC_F_SPIXR_CTRL1_SPIEN ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL1_SPIEN_POS)) /**< CTRL1_SPIEN Mask */ 162 163 #define MXC_F_SPIXR_CTRL1_MMEN_POS 1 /**< CTRL1_MMEN Position */ 164 #define MXC_F_SPIXR_CTRL1_MMEN ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL1_MMEN_POS)) /**< CTRL1_MMEN Mask */ 165 166 #define MXC_F_SPIXR_CTRL1_TIMER_POS 2 /**< CTRL1_TIMER Position */ 167 #define MXC_F_SPIXR_CTRL1_TIMER ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL1_TIMER_POS)) /**< CTRL1_TIMER Mask */ 168 169 #define MXC_F_SPIXR_CTRL1_FL_EN_POS 3 /**< CTRL1_FL_EN Position */ 170 #define MXC_F_SPIXR_CTRL1_FL_EN ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL1_FL_EN_POS)) /**< CTRL1_FL_EN Mask */ 171 172 #define MXC_F_SPIXR_CTRL1_SSIO_POS 4 /**< CTRL1_SSIO Position */ 173 #define MXC_F_SPIXR_CTRL1_SSIO ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL1_SSIO_POS)) /**< CTRL1_SSIO Mask */ 174 175 #define MXC_F_SPIXR_CTRL1_TX_START_POS 5 /**< CTRL1_TX_START Position */ 176 #define MXC_F_SPIXR_CTRL1_TX_START ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL1_TX_START_POS)) /**< CTRL1_TX_START Mask */ 177 178 #define MXC_F_SPIXR_CTRL1_SS_CTRL_POS 8 /**< CTRL1_SS_CTRL Position */ 179 #define MXC_F_SPIXR_CTRL1_SS_CTRL ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL1_SS_CTRL_POS)) /**< CTRL1_SS_CTRL Mask */ 180 181 #define MXC_F_SPIXR_CTRL1_SS_POS 16 /**< CTRL1_SS Position */ 182 #define MXC_F_SPIXR_CTRL1_SS ((uint32_t)(0xFFUL << MXC_F_SPIXR_CTRL1_SS_POS)) /**< CTRL1_SS Mask */ 183 #define MXC_V_SPIXR_CTRL1_SS_SS0 ((uint32_t)0x1UL) /**< CTRL1_SS_SS0 Value */ 184 #define MXC_S_SPIXR_CTRL1_SS_SS0 (MXC_V_SPIXR_CTRL1_SS_SS0 << MXC_F_SPIXR_CTRL1_SS_POS) /**< CTRL1_SS_SS0 Setting */ 185 #define MXC_V_SPIXR_CTRL1_SS_SS1 ((uint32_t)0x2UL) /**< CTRL1_SS_SS1 Value */ 186 #define MXC_S_SPIXR_CTRL1_SS_SS1 (MXC_V_SPIXR_CTRL1_SS_SS1 << MXC_F_SPIXR_CTRL1_SS_POS) /**< CTRL1_SS_SS1 Setting */ 187 #define MXC_V_SPIXR_CTRL1_SS_SS2 ((uint32_t)0x4UL) /**< CTRL1_SS_SS2 Value */ 188 #define MXC_S_SPIXR_CTRL1_SS_SS2 (MXC_V_SPIXR_CTRL1_SS_SS2 << MXC_F_SPIXR_CTRL1_SS_POS) /**< CTRL1_SS_SS2 Setting */ 189 #define MXC_V_SPIXR_CTRL1_SS_SS3 ((uint32_t)0x8UL) /**< CTRL1_SS_SS3 Value */ 190 #define MXC_S_SPIXR_CTRL1_SS_SS3 (MXC_V_SPIXR_CTRL1_SS_SS3 << MXC_F_SPIXR_CTRL1_SS_POS) /**< CTRL1_SS_SS3 Setting */ 191 #define MXC_V_SPIXR_CTRL1_SS_SS4 ((uint32_t)0x10UL) /**< CTRL1_SS_SS4 Value */ 192 #define MXC_S_SPIXR_CTRL1_SS_SS4 (MXC_V_SPIXR_CTRL1_SS_SS4 << MXC_F_SPIXR_CTRL1_SS_POS) /**< CTRL1_SS_SS4 Setting */ 193 #define MXC_V_SPIXR_CTRL1_SS_SS5 ((uint32_t)0x20UL) /**< CTRL1_SS_SS5 Value */ 194 #define MXC_S_SPIXR_CTRL1_SS_SS5 (MXC_V_SPIXR_CTRL1_SS_SS5 << MXC_F_SPIXR_CTRL1_SS_POS) /**< CTRL1_SS_SS5 Setting */ 195 #define MXC_V_SPIXR_CTRL1_SS_SS6 ((uint32_t)0x40UL) /**< CTRL1_SS_SS6 Value */ 196 #define MXC_S_SPIXR_CTRL1_SS_SS6 (MXC_V_SPIXR_CTRL1_SS_SS6 << MXC_F_SPIXR_CTRL1_SS_POS) /**< CTRL1_SS_SS6 Setting */ 197 #define MXC_V_SPIXR_CTRL1_SS_SS7 ((uint32_t)0x80UL) /**< CTRL1_SS_SS7 Value */ 198 #define MXC_S_SPIXR_CTRL1_SS_SS7 (MXC_V_SPIXR_CTRL1_SS_SS7 << MXC_F_SPIXR_CTRL1_SS_POS) /**< CTRL1_SS_SS7 Setting */ 199 200 /**@} end of group SPIXR_CTRL1_Register */ 201 202 /** 203 * @ingroup spixr_registers 204 * @defgroup SPIXR_CTRL2 SPIXR_CTRL2 205 * @brief Register for controlling SPI peripheral. 206 * @{ 207 */ 208 #define MXC_F_SPIXR_CTRL2_TX_NUM_CHAR_POS 0 /**< CTRL2_TX_NUM_CHAR Position */ 209 #define MXC_F_SPIXR_CTRL2_TX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPIXR_CTRL2_TX_NUM_CHAR_POS)) /**< CTRL2_TX_NUM_CHAR Mask */ 210 211 #define MXC_F_SPIXR_CTRL2_RX_NUM_CHAR_POS 16 /**< CTRL2_RX_NUM_CHAR Position */ 212 #define MXC_F_SPIXR_CTRL2_RX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPIXR_CTRL2_RX_NUM_CHAR_POS)) /**< CTRL2_RX_NUM_CHAR Mask */ 213 214 /**@} end of group SPIXR_CTRL2_Register */ 215 216 /** 217 * @ingroup spixr_registers 218 * @defgroup SPIXR_CTRL3 SPIXR_CTRL3 219 * @brief Register for controlling SPI peripheral. 220 * @{ 221 */ 222 #define MXC_F_SPIXR_CTRL3_CPHA_POS 0 /**< CTRL3_CPHA Position */ 223 #define MXC_F_SPIXR_CTRL3_CPHA ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL3_CPHA_POS)) /**< CTRL3_CPHA Mask */ 224 225 #define MXC_F_SPIXR_CTRL3_CPOL_POS 1 /**< CTRL3_CPOL Position */ 226 #define MXC_F_SPIXR_CTRL3_CPOL ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL3_CPOL_POS)) /**< CTRL3_CPOL Mask */ 227 228 #define MXC_F_SPIXR_CTRL3_SCLK_FB_INV_POS 4 /**< CTRL3_SCLK_FB_INV Position */ 229 #define MXC_F_SPIXR_CTRL3_SCLK_FB_INV ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL3_SCLK_FB_INV_POS)) /**< CTRL3_SCLK_FB_INV Mask */ 230 231 #define MXC_F_SPIXR_CTRL3_NUMBITS_POS 8 /**< CTRL3_NUMBITS Position */ 232 #define MXC_F_SPIXR_CTRL3_NUMBITS ((uint32_t)(0xFUL << MXC_F_SPIXR_CTRL3_NUMBITS_POS)) /**< CTRL3_NUMBITS Mask */ 233 #define MXC_V_SPIXR_CTRL3_NUMBITS_0 ((uint32_t)0x0UL) /**< CTRL3_NUMBITS_0 Value */ 234 #define MXC_S_SPIXR_CTRL3_NUMBITS_0 (MXC_V_SPIXR_CTRL3_NUMBITS_0 << MXC_F_SPIXR_CTRL3_NUMBITS_POS) /**< CTRL3_NUMBITS_0 Setting */ 235 236 #define MXC_F_SPIXR_CTRL3_DATA_WIDTH_POS 12 /**< CTRL3_DATA_WIDTH Position */ 237 #define MXC_F_SPIXR_CTRL3_DATA_WIDTH ((uint32_t)(0x3UL << MXC_F_SPIXR_CTRL3_DATA_WIDTH_POS)) /**< CTRL3_DATA_WIDTH Mask */ 238 #define MXC_V_SPIXR_CTRL3_DATA_WIDTH_MONO ((uint32_t)0x0UL) /**< CTRL3_DATA_WIDTH_MONO Value */ 239 #define MXC_S_SPIXR_CTRL3_DATA_WIDTH_MONO (MXC_V_SPIXR_CTRL3_DATA_WIDTH_MONO << MXC_F_SPIXR_CTRL3_DATA_WIDTH_POS) /**< CTRL3_DATA_WIDTH_MONO Setting */ 240 #define MXC_V_SPIXR_CTRL3_DATA_WIDTH_DUAL ((uint32_t)0x1UL) /**< CTRL3_DATA_WIDTH_DUAL Value */ 241 #define MXC_S_SPIXR_CTRL3_DATA_WIDTH_DUAL (MXC_V_SPIXR_CTRL3_DATA_WIDTH_DUAL << MXC_F_SPIXR_CTRL3_DATA_WIDTH_POS) /**< CTRL3_DATA_WIDTH_DUAL Setting */ 242 #define MXC_V_SPIXR_CTRL3_DATA_WIDTH_QUAD ((uint32_t)0x2UL) /**< CTRL3_DATA_WIDTH_QUAD Value */ 243 #define MXC_S_SPIXR_CTRL3_DATA_WIDTH_QUAD (MXC_V_SPIXR_CTRL3_DATA_WIDTH_QUAD << MXC_F_SPIXR_CTRL3_DATA_WIDTH_POS) /**< CTRL3_DATA_WIDTH_QUAD Setting */ 244 245 #define MXC_F_SPIXR_CTRL3_THREE_WIRE_POS 15 /**< CTRL3_THREE_WIRE Position */ 246 #define MXC_F_SPIXR_CTRL3_THREE_WIRE ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL3_THREE_WIRE_POS)) /**< CTRL3_THREE_WIRE Mask */ 247 248 #define MXC_F_SPIXR_CTRL3_SSPOL_POS 16 /**< CTRL3_SSPOL Position */ 249 #define MXC_F_SPIXR_CTRL3_SSPOL ((uint32_t)(0xFFUL << MXC_F_SPIXR_CTRL3_SSPOL_POS)) /**< CTRL3_SSPOL Mask */ 250 #define MXC_V_SPIXR_CTRL3_SSPOL_SS0_HIGH ((uint32_t)0x1UL) /**< CTRL3_SSPOL_SS0_HIGH Value */ 251 #define MXC_S_SPIXR_CTRL3_SSPOL_SS0_HIGH (MXC_V_SPIXR_CTRL3_SSPOL_SS0_HIGH << MXC_F_SPIXR_CTRL3_SSPOL_POS) /**< CTRL3_SSPOL_SS0_HIGH Setting */ 252 #define MXC_V_SPIXR_CTRL3_SSPOL_SS1_HIGH ((uint32_t)0x2UL) /**< CTRL3_SSPOL_SS1_HIGH Value */ 253 #define MXC_S_SPIXR_CTRL3_SSPOL_SS1_HIGH (MXC_V_SPIXR_CTRL3_SSPOL_SS1_HIGH << MXC_F_SPIXR_CTRL3_SSPOL_POS) /**< CTRL3_SSPOL_SS1_HIGH Setting */ 254 #define MXC_V_SPIXR_CTRL3_SSPOL_SS2_HIGH ((uint32_t)0x4UL) /**< CTRL3_SSPOL_SS2_HIGH Value */ 255 #define MXC_S_SPIXR_CTRL3_SSPOL_SS2_HIGH (MXC_V_SPIXR_CTRL3_SSPOL_SS2_HIGH << MXC_F_SPIXR_CTRL3_SSPOL_POS) /**< CTRL3_SSPOL_SS2_HIGH Setting */ 256 #define MXC_V_SPIXR_CTRL3_SSPOL_SS3_HIGH ((uint32_t)0x8UL) /**< CTRL3_SSPOL_SS3_HIGH Value */ 257 #define MXC_S_SPIXR_CTRL3_SSPOL_SS3_HIGH (MXC_V_SPIXR_CTRL3_SSPOL_SS3_HIGH << MXC_F_SPIXR_CTRL3_SSPOL_POS) /**< CTRL3_SSPOL_SS3_HIGH Setting */ 258 #define MXC_V_SPIXR_CTRL3_SSPOL_SS4_HIGH ((uint32_t)0x10UL) /**< CTRL3_SSPOL_SS4_HIGH Value */ 259 #define MXC_S_SPIXR_CTRL3_SSPOL_SS4_HIGH (MXC_V_SPIXR_CTRL3_SSPOL_SS4_HIGH << MXC_F_SPIXR_CTRL3_SSPOL_POS) /**< CTRL3_SSPOL_SS4_HIGH Setting */ 260 #define MXC_V_SPIXR_CTRL3_SSPOL_SS5_HIGH ((uint32_t)0x20UL) /**< CTRL3_SSPOL_SS5_HIGH Value */ 261 #define MXC_S_SPIXR_CTRL3_SSPOL_SS5_HIGH (MXC_V_SPIXR_CTRL3_SSPOL_SS5_HIGH << MXC_F_SPIXR_CTRL3_SSPOL_POS) /**< CTRL3_SSPOL_SS5_HIGH Setting */ 262 #define MXC_V_SPIXR_CTRL3_SSPOL_SS6_HIGH ((uint32_t)0x40UL) /**< CTRL3_SSPOL_SS6_HIGH Value */ 263 #define MXC_S_SPIXR_CTRL3_SSPOL_SS6_HIGH (MXC_V_SPIXR_CTRL3_SSPOL_SS6_HIGH << MXC_F_SPIXR_CTRL3_SSPOL_POS) /**< CTRL3_SSPOL_SS6_HIGH Setting */ 264 #define MXC_V_SPIXR_CTRL3_SSPOL_SS7_HIGH ((uint32_t)0x80UL) /**< CTRL3_SSPOL_SS7_HIGH Value */ 265 #define MXC_S_SPIXR_CTRL3_SSPOL_SS7_HIGH (MXC_V_SPIXR_CTRL3_SSPOL_SS7_HIGH << MXC_F_SPIXR_CTRL3_SSPOL_POS) /**< CTRL3_SSPOL_SS7_HIGH Setting */ 266 267 /**@} end of group SPIXR_CTRL3_Register */ 268 269 /** 270 * @ingroup spixr_registers 271 * @defgroup SPIXR_CTRL4 SPIXR_CTRL4 272 * @brief Register for controlling SPI peripheral. 273 * @{ 274 */ 275 #define MXC_F_SPIXR_CTRL4_SSACT1_POS 0 /**< CTRL4_SSACT1 Position */ 276 #define MXC_F_SPIXR_CTRL4_SSACT1 ((uint32_t)(0xFFUL << MXC_F_SPIXR_CTRL4_SSACT1_POS)) /**< CTRL4_SSACT1 Mask */ 277 #define MXC_V_SPIXR_CTRL4_SSACT1_256 ((uint32_t)0x0UL) /**< CTRL4_SSACT1_256 Value */ 278 #define MXC_S_SPIXR_CTRL4_SSACT1_256 (MXC_V_SPIXR_CTRL4_SSACT1_256 << MXC_F_SPIXR_CTRL4_SSACT1_POS) /**< CTRL4_SSACT1_256 Setting */ 279 280 #define MXC_F_SPIXR_CTRL4_SSACT2_POS 8 /**< CTRL4_SSACT2 Position */ 281 #define MXC_F_SPIXR_CTRL4_SSACT2 ((uint32_t)(0xFFUL << MXC_F_SPIXR_CTRL4_SSACT2_POS)) /**< CTRL4_SSACT2 Mask */ 282 #define MXC_V_SPIXR_CTRL4_SSACT2_256 ((uint32_t)0x0UL) /**< CTRL4_SSACT2_256 Value */ 283 #define MXC_S_SPIXR_CTRL4_SSACT2_256 (MXC_V_SPIXR_CTRL4_SSACT2_256 << MXC_F_SPIXR_CTRL4_SSACT2_POS) /**< CTRL4_SSACT2_256 Setting */ 284 285 #define MXC_F_SPIXR_CTRL4_SSINACT_POS 16 /**< CTRL4_SSINACT Position */ 286 #define MXC_F_SPIXR_CTRL4_SSINACT ((uint32_t)(0xFFUL << MXC_F_SPIXR_CTRL4_SSINACT_POS)) /**< CTRL4_SSINACT Mask */ 287 #define MXC_V_SPIXR_CTRL4_SSINACT_256 ((uint32_t)0x0UL) /**< CTRL4_SSINACT_256 Value */ 288 #define MXC_S_SPIXR_CTRL4_SSINACT_256 (MXC_V_SPIXR_CTRL4_SSINACT_256 << MXC_F_SPIXR_CTRL4_SSINACT_POS) /**< CTRL4_SSINACT_256 Setting */ 289 290 /**@} end of group SPIXR_CTRL4_Register */ 291 292 /** 293 * @ingroup spixr_registers 294 * @defgroup SPIXR_BRG_CTRL SPIXR_BRG_CTRL 295 * @brief Register for controlling SPI clock rate. 296 * @{ 297 */ 298 #define MXC_F_SPIXR_BRG_CTRL_LOW_POS 0 /**< BRG_CTRL_LOW Position */ 299 #define MXC_F_SPIXR_BRG_CTRL_LOW ((uint32_t)(0xFFUL << MXC_F_SPIXR_BRG_CTRL_LOW_POS)) /**< BRG_CTRL_LOW Mask */ 300 #define MXC_V_SPIXR_BRG_CTRL_LOW_DIS ((uint32_t)0x0UL) /**< BRG_CTRL_LOW_DIS Value */ 301 #define MXC_S_SPIXR_BRG_CTRL_LOW_DIS (MXC_V_SPIXR_BRG_CTRL_LOW_DIS << MXC_F_SPIXR_BRG_CTRL_LOW_POS) /**< BRG_CTRL_LOW_DIS Setting */ 302 303 #define MXC_F_SPIXR_BRG_CTRL_HI_POS 8 /**< BRG_CTRL_HI Position */ 304 #define MXC_F_SPIXR_BRG_CTRL_HI ((uint32_t)(0xFFUL << MXC_F_SPIXR_BRG_CTRL_HI_POS)) /**< BRG_CTRL_HI Mask */ 305 #define MXC_V_SPIXR_BRG_CTRL_HI_DIS ((uint32_t)0x0UL) /**< BRG_CTRL_HI_DIS Value */ 306 #define MXC_S_SPIXR_BRG_CTRL_HI_DIS (MXC_V_SPIXR_BRG_CTRL_HI_DIS << MXC_F_SPIXR_BRG_CTRL_HI_POS) /**< BRG_CTRL_HI_DIS Setting */ 307 308 #define MXC_F_SPIXR_BRG_CTRL_SCALE_POS 16 /**< BRG_CTRL_SCALE Position */ 309 #define MXC_F_SPIXR_BRG_CTRL_SCALE ((uint32_t)(0xFUL << MXC_F_SPIXR_BRG_CTRL_SCALE_POS)) /**< BRG_CTRL_SCALE Mask */ 310 311 /**@} end of group SPIXR_BRG_CTRL_Register */ 312 313 /** 314 * @ingroup spixr_registers 315 * @defgroup SPIXR_DMA SPIXR_DMA 316 * @brief Register for controlling DMA. 317 * @{ 318 */ 319 #define MXC_F_SPIXR_DMA_TX_FIFO_LEVEL_POS 0 /**< DMA_TX_FIFO_LEVEL Position */ 320 #define MXC_F_SPIXR_DMA_TX_FIFO_LEVEL ((uint32_t)(0x3FUL << MXC_F_SPIXR_DMA_TX_FIFO_LEVEL_POS)) /**< DMA_TX_FIFO_LEVEL Mask */ 321 322 #define MXC_F_SPIXR_DMA_TX_FIFO_EN_POS 6 /**< DMA_TX_FIFO_EN Position */ 323 #define MXC_F_SPIXR_DMA_TX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_TX_FIFO_EN_POS)) /**< DMA_TX_FIFO_EN Mask */ 324 325 #define MXC_F_SPIXR_DMA_TX_FIFO_CLEAR_POS 7 /**< DMA_TX_FIFO_CLEAR Position */ 326 #define MXC_F_SPIXR_DMA_TX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_TX_FIFO_CLEAR_POS)) /**< DMA_TX_FIFO_CLEAR Mask */ 327 328 #define MXC_F_SPIXR_DMA_TX_FIFO_CNT_POS 8 /**< DMA_TX_FIFO_CNT Position */ 329 #define MXC_F_SPIXR_DMA_TX_FIFO_CNT ((uint32_t)(0x1FUL << MXC_F_SPIXR_DMA_TX_FIFO_CNT_POS)) /**< DMA_TX_FIFO_CNT Mask */ 330 331 #define MXC_F_SPIXR_DMA_TX_DMA_EN_POS 15 /**< DMA_TX_DMA_EN Position */ 332 #define MXC_F_SPIXR_DMA_TX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_TX_DMA_EN_POS)) /**< DMA_TX_DMA_EN Mask */ 333 334 #define MXC_F_SPIXR_DMA_RX_FIFO_LEVEL_POS 16 /**< DMA_RX_FIFO_LEVEL Position */ 335 #define MXC_F_SPIXR_DMA_RX_FIFO_LEVEL ((uint32_t)(0x3FUL << MXC_F_SPIXR_DMA_RX_FIFO_LEVEL_POS)) /**< DMA_RX_FIFO_LEVEL Mask */ 336 337 #define MXC_F_SPIXR_DMA_RX_FIFO_EN_POS 22 /**< DMA_RX_FIFO_EN Position */ 338 #define MXC_F_SPIXR_DMA_RX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_RX_FIFO_EN_POS)) /**< DMA_RX_FIFO_EN Mask */ 339 340 #define MXC_F_SPIXR_DMA_RX_FIFO_CLEAR_POS 23 /**< DMA_RX_FIFO_CLEAR Position */ 341 #define MXC_F_SPIXR_DMA_RX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_RX_FIFO_CLEAR_POS)) /**< DMA_RX_FIFO_CLEAR Mask */ 342 343 #define MXC_F_SPIXR_DMA_RX_FIFO_CNT_POS 24 /**< DMA_RX_FIFO_CNT Position */ 344 #define MXC_F_SPIXR_DMA_RX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_SPIXR_DMA_RX_FIFO_CNT_POS)) /**< DMA_RX_FIFO_CNT Mask */ 345 346 #define MXC_F_SPIXR_DMA_RX_DMA_EN_POS 31 /**< DMA_RX_DMA_EN Position */ 347 #define MXC_F_SPIXR_DMA_RX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_RX_DMA_EN_POS)) /**< DMA_RX_DMA_EN Mask */ 348 349 /**@} end of group SPIXR_DMA_Register */ 350 351 /** 352 * @ingroup spixr_registers 353 * @defgroup SPIXR_IRQ SPIXR_IRQ 354 * @brief Register for reading and clearing interrupt flags. All bits are write 1 to 355 * clear. 356 * @{ 357 */ 358 #define MXC_F_SPIXR_IRQ_TX_THRESH_POS 0 /**< IRQ_TX_THRESH Position */ 359 #define MXC_F_SPIXR_IRQ_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_TX_THRESH_POS)) /**< IRQ_TX_THRESH Mask */ 360 361 #define MXC_F_SPIXR_IRQ_TX_EMPTY_POS 1 /**< IRQ_TX_EMPTY Position */ 362 #define MXC_F_SPIXR_IRQ_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_TX_EMPTY_POS)) /**< IRQ_TX_EMPTY Mask */ 363 364 #define MXC_F_SPIXR_IRQ_RX_THRESH_POS 2 /**< IRQ_RX_THRESH Position */ 365 #define MXC_F_SPIXR_IRQ_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_RX_THRESH_POS)) /**< IRQ_RX_THRESH Mask */ 366 367 #define MXC_F_SPIXR_IRQ_RX_FULL_POS 3 /**< IRQ_RX_FULL Position */ 368 #define MXC_F_SPIXR_IRQ_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_RX_FULL_POS)) /**< IRQ_RX_FULL Mask */ 369 370 #define MXC_F_SPIXR_IRQ_SSA_POS 4 /**< IRQ_SSA Position */ 371 #define MXC_F_SPIXR_IRQ_SSA ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_SSA_POS)) /**< IRQ_SSA Mask */ 372 373 #define MXC_F_SPIXR_IRQ_SSD_POS 5 /**< IRQ_SSD Position */ 374 #define MXC_F_SPIXR_IRQ_SSD ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_SSD_POS)) /**< IRQ_SSD Mask */ 375 376 #define MXC_F_SPIXR_IRQ_FAULT_POS 8 /**< IRQ_FAULT Position */ 377 #define MXC_F_SPIXR_IRQ_FAULT ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_FAULT_POS)) /**< IRQ_FAULT Mask */ 378 379 #define MXC_F_SPIXR_IRQ_ABORT_POS 9 /**< IRQ_ABORT Position */ 380 #define MXC_F_SPIXR_IRQ_ABORT ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_ABORT_POS)) /**< IRQ_ABORT Mask */ 381 382 #define MXC_F_SPIXR_IRQ_M_DONE_POS 11 /**< IRQ_M_DONE Position */ 383 #define MXC_F_SPIXR_IRQ_M_DONE ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_M_DONE_POS)) /**< IRQ_M_DONE Mask */ 384 385 #define MXC_F_SPIXR_IRQ_TX_OVR_POS 12 /**< IRQ_TX_OVR Position */ 386 #define MXC_F_SPIXR_IRQ_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_TX_OVR_POS)) /**< IRQ_TX_OVR Mask */ 387 388 #define MXC_F_SPIXR_IRQ_TX_UND_POS 13 /**< IRQ_TX_UND Position */ 389 #define MXC_F_SPIXR_IRQ_TX_UND ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_TX_UND_POS)) /**< IRQ_TX_UND Mask */ 390 391 #define MXC_F_SPIXR_IRQ_RX_OVR_POS 14 /**< IRQ_RX_OVR Position */ 392 #define MXC_F_SPIXR_IRQ_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_RX_OVR_POS)) /**< IRQ_RX_OVR Mask */ 393 394 #define MXC_F_SPIXR_IRQ_RX_UND_POS 15 /**< IRQ_RX_UND Position */ 395 #define MXC_F_SPIXR_IRQ_RX_UND ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_RX_UND_POS)) /**< IRQ_RX_UND Mask */ 396 397 /**@} end of group SPIXR_IRQ_Register */ 398 399 /** 400 * @ingroup spixr_registers 401 * @defgroup SPIXR_IRQE SPIXR_IRQE 402 * @brief Register for enabling interrupts. 403 * @{ 404 */ 405 #define MXC_F_SPIXR_IRQE_TX_THRESH_POS 0 /**< IRQE_TX_THRESH Position */ 406 #define MXC_F_SPIXR_IRQE_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_TX_THRESH_POS)) /**< IRQE_TX_THRESH Mask */ 407 408 #define MXC_F_SPIXR_IRQE_TX_EMPTY_POS 1 /**< IRQE_TX_EMPTY Position */ 409 #define MXC_F_SPIXR_IRQE_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_TX_EMPTY_POS)) /**< IRQE_TX_EMPTY Mask */ 410 411 #define MXC_F_SPIXR_IRQE_RX_THRESH_POS 2 /**< IRQE_RX_THRESH Position */ 412 #define MXC_F_SPIXR_IRQE_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_RX_THRESH_POS)) /**< IRQE_RX_THRESH Mask */ 413 414 #define MXC_F_SPIXR_IRQE_RX_FULL_POS 3 /**< IRQE_RX_FULL Position */ 415 #define MXC_F_SPIXR_IRQE_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_RX_FULL_POS)) /**< IRQE_RX_FULL Mask */ 416 417 #define MXC_F_SPIXR_IRQE_SSA_POS 4 /**< IRQE_SSA Position */ 418 #define MXC_F_SPIXR_IRQE_SSA ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_SSA_POS)) /**< IRQE_SSA Mask */ 419 420 #define MXC_F_SPIXR_IRQE_SSD_POS 5 /**< IRQE_SSD Position */ 421 #define MXC_F_SPIXR_IRQE_SSD ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_SSD_POS)) /**< IRQE_SSD Mask */ 422 423 #define MXC_F_SPIXR_IRQE_FAULT_POS 8 /**< IRQE_FAULT Position */ 424 #define MXC_F_SPIXR_IRQE_FAULT ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_FAULT_POS)) /**< IRQE_FAULT Mask */ 425 426 #define MXC_F_SPIXR_IRQE_ABORT_POS 9 /**< IRQE_ABORT Position */ 427 #define MXC_F_SPIXR_IRQE_ABORT ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_ABORT_POS)) /**< IRQE_ABORT Mask */ 428 429 #define MXC_F_SPIXR_IRQE_M_DONE_POS 11 /**< IRQE_M_DONE Position */ 430 #define MXC_F_SPIXR_IRQE_M_DONE ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_M_DONE_POS)) /**< IRQE_M_DONE Mask */ 431 432 #define MXC_F_SPIXR_IRQE_TX_OVR_POS 12 /**< IRQE_TX_OVR Position */ 433 #define MXC_F_SPIXR_IRQE_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_TX_OVR_POS)) /**< IRQE_TX_OVR Mask */ 434 435 #define MXC_F_SPIXR_IRQE_TX_UND_POS 13 /**< IRQE_TX_UND Position */ 436 #define MXC_F_SPIXR_IRQE_TX_UND ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_TX_UND_POS)) /**< IRQE_TX_UND Mask */ 437 438 #define MXC_F_SPIXR_IRQE_RX_OVR_POS 14 /**< IRQE_RX_OVR Position */ 439 #define MXC_F_SPIXR_IRQE_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_RX_OVR_POS)) /**< IRQE_RX_OVR Mask */ 440 441 #define MXC_F_SPIXR_IRQE_RX_UND_POS 15 /**< IRQE_RX_UND Position */ 442 #define MXC_F_SPIXR_IRQE_RX_UND ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_RX_UND_POS)) /**< IRQE_RX_UND Mask */ 443 444 /**@} end of group SPIXR_IRQE_Register */ 445 446 /** 447 * @ingroup spixr_registers 448 * @defgroup SPIXR_WAKE SPIXR_WAKE 449 * @brief Register for wake up flags. All bits in this register are write 1 to clear. 450 * @{ 451 */ 452 #define MXC_F_SPIXR_WAKE_TX_THRESH_POS 0 /**< WAKE_TX_THRESH Position */ 453 #define MXC_F_SPIXR_WAKE_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPIXR_WAKE_TX_THRESH_POS)) /**< WAKE_TX_THRESH Mask */ 454 455 #define MXC_F_SPIXR_WAKE_TX_EMPTY_POS 1 /**< WAKE_TX_EMPTY Position */ 456 #define MXC_F_SPIXR_WAKE_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPIXR_WAKE_TX_EMPTY_POS)) /**< WAKE_TX_EMPTY Mask */ 457 458 #define MXC_F_SPIXR_WAKE_RX_THRESH_POS 2 /**< WAKE_RX_THRESH Position */ 459 #define MXC_F_SPIXR_WAKE_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPIXR_WAKE_RX_THRESH_POS)) /**< WAKE_RX_THRESH Mask */ 460 461 #define MXC_F_SPIXR_WAKE_RX_FULL_POS 3 /**< WAKE_RX_FULL Position */ 462 #define MXC_F_SPIXR_WAKE_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPIXR_WAKE_RX_FULL_POS)) /**< WAKE_RX_FULL Mask */ 463 464 /**@} end of group SPIXR_WAKE_Register */ 465 466 /** 467 * @ingroup spixr_registers 468 * @defgroup SPIXR_WAKEE SPIXR_WAKEE 469 * @brief Register for wake up enable. 470 * @{ 471 */ 472 #define MXC_F_SPIXR_WAKEE_TX_THRESH_POS 0 /**< WAKEE_TX_THRESH Position */ 473 #define MXC_F_SPIXR_WAKEE_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPIXR_WAKEE_TX_THRESH_POS)) /**< WAKEE_TX_THRESH Mask */ 474 475 #define MXC_F_SPIXR_WAKEE_TX_EMPTY_POS 1 /**< WAKEE_TX_EMPTY Position */ 476 #define MXC_F_SPIXR_WAKEE_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPIXR_WAKEE_TX_EMPTY_POS)) /**< WAKEE_TX_EMPTY Mask */ 477 478 #define MXC_F_SPIXR_WAKEE_RX_THRESH_POS 2 /**< WAKEE_RX_THRESH Position */ 479 #define MXC_F_SPIXR_WAKEE_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPIXR_WAKEE_RX_THRESH_POS)) /**< WAKEE_RX_THRESH Mask */ 480 481 #define MXC_F_SPIXR_WAKEE_RX_FULL_POS 3 /**< WAKEE_RX_FULL Position */ 482 #define MXC_F_SPIXR_WAKEE_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPIXR_WAKEE_RX_FULL_POS)) /**< WAKEE_RX_FULL Mask */ 483 484 /**@} end of group SPIXR_WAKEE_Register */ 485 486 /** 487 * @ingroup spixr_registers 488 * @defgroup SPIXR_STAT SPIXR_STAT 489 * @brief SPI Status register. 490 * @{ 491 */ 492 #define MXC_F_SPIXR_STAT_BUSY_POS 0 /**< STAT_BUSY Position */ 493 #define MXC_F_SPIXR_STAT_BUSY ((uint32_t)(0x1UL << MXC_F_SPIXR_STAT_BUSY_POS)) /**< STAT_BUSY Mask */ 494 495 /**@} end of group SPIXR_STAT_Register */ 496 497 /** 498 * @ingroup spixr_registers 499 * @defgroup SPIXR_XMEM_CTRL SPIXR_XMEM_CTRL 500 * @brief Register to control external memory. 501 * @{ 502 */ 503 #define MXC_F_SPIXR_XMEM_CTRL_RD_CMD_POS 0 /**< XMEM_CTRL_RD_CMD Position */ 504 #define MXC_F_SPIXR_XMEM_CTRL_RD_CMD ((uint32_t)(0xFFUL << MXC_F_SPIXR_XMEM_CTRL_RD_CMD_POS)) /**< XMEM_CTRL_RD_CMD Mask */ 505 506 #define MXC_F_SPIXR_XMEM_CTRL_WR_CMD_POS 8 /**< XMEM_CTRL_WR_CMD Position */ 507 #define MXC_F_SPIXR_XMEM_CTRL_WR_CMD ((uint32_t)(0xFFUL << MXC_F_SPIXR_XMEM_CTRL_WR_CMD_POS)) /**< XMEM_CTRL_WR_CMD Mask */ 508 509 #define MXC_F_SPIXR_XMEM_CTRL_DUMMY_CLK_POS 16 /**< XMEM_CTRL_DUMMY_CLK Position */ 510 #define MXC_F_SPIXR_XMEM_CTRL_DUMMY_CLK ((uint32_t)(0xFFUL << MXC_F_SPIXR_XMEM_CTRL_DUMMY_CLK_POS)) /**< XMEM_CTRL_DUMMY_CLK Mask */ 511 512 #define MXC_F_SPIXR_XMEM_CTRL_XMEM_EN_POS 31 /**< XMEM_CTRL_XMEM_EN Position */ 513 #define MXC_F_SPIXR_XMEM_CTRL_XMEM_EN ((uint32_t)(0x1UL << MXC_F_SPIXR_XMEM_CTRL_XMEM_EN_POS)) /**< XMEM_CTRL_XMEM_EN Mask */ 514 515 /**@} end of group SPIXR_XMEM_CTRL_Register */ 516 517 #ifdef __cplusplus 518 } 519 #endif 520 521 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_SPIXR_REGS_H_ 522
