1 /** 2 * @file spixfm_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SPIXFM Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup spixfm_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_SPIXFM_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_SPIXFM_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup spixfm 67 * @defgroup spixfm_registers SPIXFM_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the SPIXFM Peripheral Module. 69 * @details SPIXF Master 70 */ 71 72 /** 73 * @ingroup spixfm_registers 74 * Structure type to access the SPIXFM Registers. 75 */ 76 typedef struct { 77 __IO uint32_t cfg; /**< <tt>\b 0x00:</tt> SPIXFM CFG Register */ 78 __IO uint32_t fetch_ctrl; /**< <tt>\b 0x04:</tt> SPIXFM FETCH_CTRL Register */ 79 __IO uint32_t mode_ctrl; /**< <tt>\b 0x08:</tt> SPIXFM MODE_CTRL Register */ 80 __IO uint32_t mode_data; /**< <tt>\b 0x0C:</tt> SPIXFM MODE_DATA Register */ 81 __IO uint32_t sclk_fb_ctrl; /**< <tt>\b 0x10:</tt> SPIXFM SCLK_FB_CTRL Register */ 82 __R uint32_t rsv_0x14_0x1b[2]; 83 __IO uint32_t io_ctrl; /**< <tt>\b 0x1C:</tt> SPIXFM IO_CTRL Register */ 84 __IO uint32_t memseccn; /**< <tt>\b 0x20:</tt> SPIXFM MEMSECCN Register */ 85 __IO uint32_t bus_idle; /**< <tt>\b 0x24:</tt> SPIXFM BUS_IDLE Register */ 86 } mxc_spixfm_regs_t; 87 88 /* Register offsets for module SPIXFM */ 89 /** 90 * @ingroup spixfm_registers 91 * @defgroup SPIXFM_Register_Offsets Register Offsets 92 * @brief SPIXFM Peripheral Register Offsets from the SPIXFM Base Peripheral Address. 93 * @{ 94 */ 95 #define MXC_R_SPIXFM_CFG ((uint32_t)0x00000000UL) /**< Offset from SPIXFM Base Address: <tt> 0x0000</tt> */ 96 #define MXC_R_SPIXFM_FETCH_CTRL ((uint32_t)0x00000004UL) /**< Offset from SPIXFM Base Address: <tt> 0x0004</tt> */ 97 #define MXC_R_SPIXFM_MODE_CTRL ((uint32_t)0x00000008UL) /**< Offset from SPIXFM Base Address: <tt> 0x0008</tt> */ 98 #define MXC_R_SPIXFM_MODE_DATA ((uint32_t)0x0000000CUL) /**< Offset from SPIXFM Base Address: <tt> 0x000C</tt> */ 99 #define MXC_R_SPIXFM_SCLK_FB_CTRL ((uint32_t)0x00000010UL) /**< Offset from SPIXFM Base Address: <tt> 0x0010</tt> */ 100 #define MXC_R_SPIXFM_IO_CTRL ((uint32_t)0x0000001CUL) /**< Offset from SPIXFM Base Address: <tt> 0x001C</tt> */ 101 #define MXC_R_SPIXFM_MEMSECCN ((uint32_t)0x00000020UL) /**< Offset from SPIXFM Base Address: <tt> 0x0020</tt> */ 102 #define MXC_R_SPIXFM_BUS_IDLE ((uint32_t)0x00000024UL) /**< Offset from SPIXFM Base Address: <tt> 0x0024</tt> */ 103 /**@} end of group spixfm_registers */ 104 105 /** 106 * @ingroup spixfm_registers 107 * @defgroup SPIXFM_CFG SPIXFM_CFG 108 * @brief SPIX Configuration Register. 109 * @{ 110 */ 111 #define MXC_F_SPIXFM_CFG_MODE_POS 0 /**< CFG_MODE Position */ 112 #define MXC_F_SPIXFM_CFG_MODE ((uint32_t)(0x3UL << MXC_F_SPIXFM_CFG_MODE_POS)) /**< CFG_MODE Mask */ 113 #define MXC_V_SPIXFM_CFG_MODE_SCLK_HI_SAMPLE_RISING ((uint32_t)0x0UL) /**< CFG_MODE_SCLK_HI_SAMPLE_RISING Value */ 114 #define MXC_S_SPIXFM_CFG_MODE_SCLK_HI_SAMPLE_RISING (MXC_V_SPIXFM_CFG_MODE_SCLK_HI_SAMPLE_RISING << MXC_F_SPIXFM_CFG_MODE_POS) /**< CFG_MODE_SCLK_HI_SAMPLE_RISING Setting */ 115 #define MXC_V_SPIXFM_CFG_MODE_SCLK_LO_SAMPLE_FAILLING ((uint32_t)0x3UL) /**< CFG_MODE_SCLK_LO_SAMPLE_FAILLING Value */ 116 #define MXC_S_SPIXFM_CFG_MODE_SCLK_LO_SAMPLE_FAILLING (MXC_V_SPIXFM_CFG_MODE_SCLK_LO_SAMPLE_FAILLING << MXC_F_SPIXFM_CFG_MODE_POS) /**< CFG_MODE_SCLK_LO_SAMPLE_FAILLING Setting */ 117 118 #define MXC_F_SPIXFM_CFG_SSPOL_POS 2 /**< CFG_SSPOL Position */ 119 #define MXC_F_SPIXFM_CFG_SSPOL ((uint32_t)(0x1UL << MXC_F_SPIXFM_CFG_SSPOL_POS)) /**< CFG_SSPOL Mask */ 120 121 #define MXC_F_SPIXFM_CFG_SSEL_POS 4 /**< CFG_SSEL Position */ 122 #define MXC_F_SPIXFM_CFG_SSEL ((uint32_t)(0x7UL << MXC_F_SPIXFM_CFG_SSEL_POS)) /**< CFG_SSEL Mask */ 123 124 #define MXC_F_SPIXFM_CFG_LO_CLK_POS 8 /**< CFG_LO_CLK Position */ 125 #define MXC_F_SPIXFM_CFG_LO_CLK ((uint32_t)(0xFUL << MXC_F_SPIXFM_CFG_LO_CLK_POS)) /**< CFG_LO_CLK Mask */ 126 127 #define MXC_F_SPIXFM_CFG_HI_CLK_POS 12 /**< CFG_HI_CLK Position */ 128 #define MXC_F_SPIXFM_CFG_HI_CLK ((uint32_t)(0xFUL << MXC_F_SPIXFM_CFG_HI_CLK_POS)) /**< CFG_HI_CLK Mask */ 129 130 #define MXC_F_SPIXFM_CFG_SSACT_POS 16 /**< CFG_SSACT Position */ 131 #define MXC_F_SPIXFM_CFG_SSACT ((uint32_t)(0x3UL << MXC_F_SPIXFM_CFG_SSACT_POS)) /**< CFG_SSACT Mask */ 132 #define MXC_V_SPIXFM_CFG_SSACT_OFF ((uint32_t)0x0UL) /**< CFG_SSACT_OFF Value */ 133 #define MXC_S_SPIXFM_CFG_SSACT_OFF (MXC_V_SPIXFM_CFG_SSACT_OFF << MXC_F_SPIXFM_CFG_SSACT_POS) /**< CFG_SSACT_OFF Setting */ 134 #define MXC_V_SPIXFM_CFG_SSACT_FOR_2_MOD_CLK ((uint32_t)0x1UL) /**< CFG_SSACT_FOR_2_MOD_CLK Value */ 135 #define MXC_S_SPIXFM_CFG_SSACT_FOR_2_MOD_CLK (MXC_V_SPIXFM_CFG_SSACT_FOR_2_MOD_CLK << MXC_F_SPIXFM_CFG_SSACT_POS) /**< CFG_SSACT_FOR_2_MOD_CLK Setting */ 136 #define MXC_V_SPIXFM_CFG_SSACT_FOR_4_MOD_CLK ((uint32_t)0x2UL) /**< CFG_SSACT_FOR_4_MOD_CLK Value */ 137 #define MXC_S_SPIXFM_CFG_SSACT_FOR_4_MOD_CLK (MXC_V_SPIXFM_CFG_SSACT_FOR_4_MOD_CLK << MXC_F_SPIXFM_CFG_SSACT_POS) /**< CFG_SSACT_FOR_4_MOD_CLK Setting */ 138 #define MXC_V_SPIXFM_CFG_SSACT_FOR_8_MOD_CLK ((uint32_t)0x3UL) /**< CFG_SSACT_FOR_8_MOD_CLK Value */ 139 #define MXC_S_SPIXFM_CFG_SSACT_FOR_8_MOD_CLK (MXC_V_SPIXFM_CFG_SSACT_FOR_8_MOD_CLK << MXC_F_SPIXFM_CFG_SSACT_POS) /**< CFG_SSACT_FOR_8_MOD_CLK Setting */ 140 141 #define MXC_F_SPIXFM_CFG_SSIACT_POS 18 /**< CFG_SSIACT Position */ 142 #define MXC_F_SPIXFM_CFG_SSIACT ((uint32_t)(0x3UL << MXC_F_SPIXFM_CFG_SSIACT_POS)) /**< CFG_SSIACT Mask */ 143 #define MXC_V_SPIXFM_CFG_SSIACT_FOR_1_MOD_CLK ((uint32_t)0x0UL) /**< CFG_SSIACT_FOR_1_MOD_CLK Value */ 144 #define MXC_S_SPIXFM_CFG_SSIACT_FOR_1_MOD_CLK (MXC_V_SPIXFM_CFG_SSIACT_FOR_1_MOD_CLK << MXC_F_SPIXFM_CFG_SSIACT_POS) /**< CFG_SSIACT_FOR_1_MOD_CLK Setting */ 145 #define MXC_V_SPIXFM_CFG_SSIACT_FOR_3_MOD_CLK ((uint32_t)0x1UL) /**< CFG_SSIACT_FOR_3_MOD_CLK Value */ 146 #define MXC_S_SPIXFM_CFG_SSIACT_FOR_3_MOD_CLK (MXC_V_SPIXFM_CFG_SSIACT_FOR_3_MOD_CLK << MXC_F_SPIXFM_CFG_SSIACT_POS) /**< CFG_SSIACT_FOR_3_MOD_CLK Setting */ 147 #define MXC_V_SPIXFM_CFG_SSIACT_FOR_5_MOD_CLK ((uint32_t)0x2UL) /**< CFG_SSIACT_FOR_5_MOD_CLK Value */ 148 #define MXC_S_SPIXFM_CFG_SSIACT_FOR_5_MOD_CLK (MXC_V_SPIXFM_CFG_SSIACT_FOR_5_MOD_CLK << MXC_F_SPIXFM_CFG_SSIACT_POS) /**< CFG_SSIACT_FOR_5_MOD_CLK Setting */ 149 #define MXC_V_SPIXFM_CFG_SSIACT_FOR_9_MOD_CLK ((uint32_t)0x3UL) /**< CFG_SSIACT_FOR_9_MOD_CLK Value */ 150 #define MXC_S_SPIXFM_CFG_SSIACT_FOR_9_MOD_CLK (MXC_V_SPIXFM_CFG_SSIACT_FOR_9_MOD_CLK << MXC_F_SPIXFM_CFG_SSIACT_POS) /**< CFG_SSIACT_FOR_9_MOD_CLK Setting */ 151 152 /**@} end of group SPIXFM_CFG_Register */ 153 154 /** 155 * @ingroup spixfm_registers 156 * @defgroup SPIXFM_FETCH_CTRL SPIXFM_FETCH_CTRL 157 * @brief SPIX Fetch Control Register. 158 * @{ 159 */ 160 #define MXC_F_SPIXFM_FETCH_CTRL_CMDVAL_POS 0 /**< FETCH_CTRL_CMDVAL Position */ 161 #define MXC_F_SPIXFM_FETCH_CTRL_CMDVAL ((uint32_t)(0xFFUL << MXC_F_SPIXFM_FETCH_CTRL_CMDVAL_POS)) /**< FETCH_CTRL_CMDVAL Mask */ 162 163 #define MXC_F_SPIXFM_FETCH_CTRL_CMD_WIDTH_POS 8 /**< FETCH_CTRL_CMD_WIDTH Position */ 164 #define MXC_F_SPIXFM_FETCH_CTRL_CMD_WIDTH ((uint32_t)(0x3UL << MXC_F_SPIXFM_FETCH_CTRL_CMD_WIDTH_POS)) /**< FETCH_CTRL_CMD_WIDTH Mask */ 165 #define MXC_V_SPIXFM_FETCH_CTRL_CMD_WIDTH_SINGLE ((uint32_t)0x0UL) /**< FETCH_CTRL_CMD_WIDTH_SINGLE Value */ 166 #define MXC_S_SPIXFM_FETCH_CTRL_CMD_WIDTH_SINGLE (MXC_V_SPIXFM_FETCH_CTRL_CMD_WIDTH_SINGLE << MXC_F_SPIXFM_FETCH_CTRL_CMD_WIDTH_POS) /**< FETCH_CTRL_CMD_WIDTH_SINGLE Setting */ 167 #define MXC_V_SPIXFM_FETCH_CTRL_CMD_WIDTH_DUAL_IO ((uint32_t)0x1UL) /**< FETCH_CTRL_CMD_WIDTH_DUAL_IO Value */ 168 #define MXC_S_SPIXFM_FETCH_CTRL_CMD_WIDTH_DUAL_IO (MXC_V_SPIXFM_FETCH_CTRL_CMD_WIDTH_DUAL_IO << MXC_F_SPIXFM_FETCH_CTRL_CMD_WIDTH_POS) /**< FETCH_CTRL_CMD_WIDTH_DUAL_IO Setting */ 169 #define MXC_V_SPIXFM_FETCH_CTRL_CMD_WIDTH_QUAD_IO ((uint32_t)0x2UL) /**< FETCH_CTRL_CMD_WIDTH_QUAD_IO Value */ 170 #define MXC_S_SPIXFM_FETCH_CTRL_CMD_WIDTH_QUAD_IO (MXC_V_SPIXFM_FETCH_CTRL_CMD_WIDTH_QUAD_IO << MXC_F_SPIXFM_FETCH_CTRL_CMD_WIDTH_POS) /**< FETCH_CTRL_CMD_WIDTH_QUAD_IO Setting */ 171 #define MXC_V_SPIXFM_FETCH_CTRL_CMD_WIDTH_INVALID ((uint32_t)0x3UL) /**< FETCH_CTRL_CMD_WIDTH_INVALID Value */ 172 #define MXC_S_SPIXFM_FETCH_CTRL_CMD_WIDTH_INVALID (MXC_V_SPIXFM_FETCH_CTRL_CMD_WIDTH_INVALID << MXC_F_SPIXFM_FETCH_CTRL_CMD_WIDTH_POS) /**< FETCH_CTRL_CMD_WIDTH_INVALID Setting */ 173 174 #define MXC_F_SPIXFM_FETCH_CTRL_ADDR_WIDTH_POS 10 /**< FETCH_CTRL_ADDR_WIDTH Position */ 175 #define MXC_F_SPIXFM_FETCH_CTRL_ADDR_WIDTH ((uint32_t)(0x3UL << MXC_F_SPIXFM_FETCH_CTRL_ADDR_WIDTH_POS)) /**< FETCH_CTRL_ADDR_WIDTH Mask */ 176 #define MXC_V_SPIXFM_FETCH_CTRL_ADDR_WIDTH_SINGLE ((uint32_t)0x0UL) /**< FETCH_CTRL_ADDR_WIDTH_SINGLE Value */ 177 #define MXC_S_SPIXFM_FETCH_CTRL_ADDR_WIDTH_SINGLE (MXC_V_SPIXFM_FETCH_CTRL_ADDR_WIDTH_SINGLE << MXC_F_SPIXFM_FETCH_CTRL_ADDR_WIDTH_POS) /**< FETCH_CTRL_ADDR_WIDTH_SINGLE Setting */ 178 #define MXC_V_SPIXFM_FETCH_CTRL_ADDR_WIDTH_DUAL_IO ((uint32_t)0x1UL) /**< FETCH_CTRL_ADDR_WIDTH_DUAL_IO Value */ 179 #define MXC_S_SPIXFM_FETCH_CTRL_ADDR_WIDTH_DUAL_IO (MXC_V_SPIXFM_FETCH_CTRL_ADDR_WIDTH_DUAL_IO << MXC_F_SPIXFM_FETCH_CTRL_ADDR_WIDTH_POS) /**< FETCH_CTRL_ADDR_WIDTH_DUAL_IO Setting */ 180 #define MXC_V_SPIXFM_FETCH_CTRL_ADDR_WIDTH_QUAD_IO ((uint32_t)0x2UL) /**< FETCH_CTRL_ADDR_WIDTH_QUAD_IO Value */ 181 #define MXC_S_SPIXFM_FETCH_CTRL_ADDR_WIDTH_QUAD_IO (MXC_V_SPIXFM_FETCH_CTRL_ADDR_WIDTH_QUAD_IO << MXC_F_SPIXFM_FETCH_CTRL_ADDR_WIDTH_POS) /**< FETCH_CTRL_ADDR_WIDTH_QUAD_IO Setting */ 182 #define MXC_V_SPIXFM_FETCH_CTRL_ADDR_WIDTH_INVALID ((uint32_t)0x3UL) /**< FETCH_CTRL_ADDR_WIDTH_INVALID Value */ 183 #define MXC_S_SPIXFM_FETCH_CTRL_ADDR_WIDTH_INVALID (MXC_V_SPIXFM_FETCH_CTRL_ADDR_WIDTH_INVALID << MXC_F_SPIXFM_FETCH_CTRL_ADDR_WIDTH_POS) /**< FETCH_CTRL_ADDR_WIDTH_INVALID Setting */ 184 185 #define MXC_F_SPIXFM_FETCH_CTRL_DATA_WIDTH_POS 12 /**< FETCH_CTRL_DATA_WIDTH Position */ 186 #define MXC_F_SPIXFM_FETCH_CTRL_DATA_WIDTH ((uint32_t)(0x3UL << MXC_F_SPIXFM_FETCH_CTRL_DATA_WIDTH_POS)) /**< FETCH_CTRL_DATA_WIDTH Mask */ 187 #define MXC_V_SPIXFM_FETCH_CTRL_DATA_WIDTH_SINGLE ((uint32_t)0x0UL) /**< FETCH_CTRL_DATA_WIDTH_SINGLE Value */ 188 #define MXC_S_SPIXFM_FETCH_CTRL_DATA_WIDTH_SINGLE (MXC_V_SPIXFM_FETCH_CTRL_DATA_WIDTH_SINGLE << MXC_F_SPIXFM_FETCH_CTRL_DATA_WIDTH_POS) /**< FETCH_CTRL_DATA_WIDTH_SINGLE Setting */ 189 #define MXC_V_SPIXFM_FETCH_CTRL_DATA_WIDTH_DUAL_IO ((uint32_t)0x1UL) /**< FETCH_CTRL_DATA_WIDTH_DUAL_IO Value */ 190 #define MXC_S_SPIXFM_FETCH_CTRL_DATA_WIDTH_DUAL_IO (MXC_V_SPIXFM_FETCH_CTRL_DATA_WIDTH_DUAL_IO << MXC_F_SPIXFM_FETCH_CTRL_DATA_WIDTH_POS) /**< FETCH_CTRL_DATA_WIDTH_DUAL_IO Setting */ 191 #define MXC_V_SPIXFM_FETCH_CTRL_DATA_WIDTH_QUAD_IO ((uint32_t)0x2UL) /**< FETCH_CTRL_DATA_WIDTH_QUAD_IO Value */ 192 #define MXC_S_SPIXFM_FETCH_CTRL_DATA_WIDTH_QUAD_IO (MXC_V_SPIXFM_FETCH_CTRL_DATA_WIDTH_QUAD_IO << MXC_F_SPIXFM_FETCH_CTRL_DATA_WIDTH_POS) /**< FETCH_CTRL_DATA_WIDTH_QUAD_IO Setting */ 193 #define MXC_V_SPIXFM_FETCH_CTRL_DATA_WIDTH_INVALID ((uint32_t)0x3UL) /**< FETCH_CTRL_DATA_WIDTH_INVALID Value */ 194 #define MXC_S_SPIXFM_FETCH_CTRL_DATA_WIDTH_INVALID (MXC_V_SPIXFM_FETCH_CTRL_DATA_WIDTH_INVALID << MXC_F_SPIXFM_FETCH_CTRL_DATA_WIDTH_POS) /**< FETCH_CTRL_DATA_WIDTH_INVALID Setting */ 195 196 #define MXC_F_SPIXFM_FETCH_CTRL_FOUR_BYTE_ADDR_POS 16 /**< FETCH_CTRL_FOUR_BYTE_ADDR Position */ 197 #define MXC_F_SPIXFM_FETCH_CTRL_FOUR_BYTE_ADDR ((uint32_t)(0x1UL << MXC_F_SPIXFM_FETCH_CTRL_FOUR_BYTE_ADDR_POS)) /**< FETCH_CTRL_FOUR_BYTE_ADDR Mask */ 198 199 /**@} end of group SPIXFM_FETCH_CTRL_Register */ 200 201 /** 202 * @ingroup spixfm_registers 203 * @defgroup SPIXFM_MODE_CTRL SPIXFM_MODE_CTRL 204 * @brief SPIX Mode Control Register. 205 * @{ 206 */ 207 #define MXC_F_SPIXFM_MODE_CTRL_MDCLK_POS 0 /**< MODE_CTRL_MDCLK Position */ 208 #define MXC_F_SPIXFM_MODE_CTRL_MDCLK ((uint32_t)(0xFUL << MXC_F_SPIXFM_MODE_CTRL_MDCLK_POS)) /**< MODE_CTRL_MDCLK Mask */ 209 210 #define MXC_F_SPIXFM_MODE_CTRL_NO_CMD_MODE_POS 8 /**< MODE_CTRL_NO_CMD_MODE Position */ 211 #define MXC_F_SPIXFM_MODE_CTRL_NO_CMD_MODE ((uint32_t)(0x1UL << MXC_F_SPIXFM_MODE_CTRL_NO_CMD_MODE_POS)) /**< MODE_CTRL_NO_CMD_MODE Mask */ 212 213 #define MXC_F_SPIXFM_MODE_CTRL_EXIT_NO_CMD_MODE_POS 9 /**< MODE_CTRL_EXIT_NO_CMD_MODE Position */ 214 #define MXC_F_SPIXFM_MODE_CTRL_EXIT_NO_CMD_MODE ((uint32_t)(0x1UL << MXC_F_SPIXFM_MODE_CTRL_EXIT_NO_CMD_MODE_POS)) /**< MODE_CTRL_EXIT_NO_CMD_MODE Mask */ 215 216 /**@} end of group SPIXFM_MODE_CTRL_Register */ 217 218 /** 219 * @ingroup spixfm_registers 220 * @defgroup SPIXFM_MODE_DATA SPIXFM_MODE_DATA 221 * @brief SPIX Mode Data Register. 222 * @{ 223 */ 224 #define MXC_F_SPIXFM_MODE_DATA_DATA_POS 0 /**< MODE_DATA_DATA Position */ 225 #define MXC_F_SPIXFM_MODE_DATA_DATA ((uint32_t)(0xFFFFUL << MXC_F_SPIXFM_MODE_DATA_DATA_POS)) /**< MODE_DATA_DATA Mask */ 226 227 #define MXC_F_SPIXFM_MODE_DATA_OUT_EN_POS 16 /**< MODE_DATA_OUT_EN Position */ 228 #define MXC_F_SPIXFM_MODE_DATA_OUT_EN ((uint32_t)(0xFFFFUL << MXC_F_SPIXFM_MODE_DATA_OUT_EN_POS)) /**< MODE_DATA_OUT_EN Mask */ 229 230 /**@} end of group SPIXFM_MODE_DATA_Register */ 231 232 /** 233 * @ingroup spixfm_registers 234 * @defgroup SPIXFM_SCLK_FB_CTRL SPIXFM_SCLK_FB_CTRL 235 * @brief SPIX Feedback Control Register. 236 * @{ 237 */ 238 #define MXC_F_SPIXFM_SCLK_FB_CTRL_FB_EN_POS 0 /**< SCLK_FB_CTRL_FB_EN Position */ 239 #define MXC_F_SPIXFM_SCLK_FB_CTRL_FB_EN ((uint32_t)(0x1UL << MXC_F_SPIXFM_SCLK_FB_CTRL_FB_EN_POS)) /**< SCLK_FB_CTRL_FB_EN Mask */ 240 241 #define MXC_F_SPIXFM_SCLK_FB_CTRL_INVERT_EN_POS 1 /**< SCLK_FB_CTRL_INVERT_EN Position */ 242 #define MXC_F_SPIXFM_SCLK_FB_CTRL_INVERT_EN ((uint32_t)(0x1UL << MXC_F_SPIXFM_SCLK_FB_CTRL_INVERT_EN_POS)) /**< SCLK_FB_CTRL_INVERT_EN Mask */ 243 244 /**@} end of group SPIXFM_SCLK_FB_CTRL_Register */ 245 246 /** 247 * @ingroup spixfm_registers 248 * @defgroup SPIXFM_IO_CTRL SPIXFM_IO_CTRL 249 * @brief SPIX IO Control Register. 250 * @{ 251 */ 252 #define MXC_F_SPIXFM_IO_CTRL_SCLK_DS_POS 0 /**< IO_CTRL_SCLK_DS Position */ 253 #define MXC_F_SPIXFM_IO_CTRL_SCLK_DS ((uint32_t)(0x1UL << MXC_F_SPIXFM_IO_CTRL_SCLK_DS_POS)) /**< IO_CTRL_SCLK_DS Mask */ 254 255 #define MXC_F_SPIXFM_IO_CTRL_SS_DS_POS 1 /**< IO_CTRL_SS_DS Position */ 256 #define MXC_F_SPIXFM_IO_CTRL_SS_DS ((uint32_t)(0x1UL << MXC_F_SPIXFM_IO_CTRL_SS_DS_POS)) /**< IO_CTRL_SS_DS Mask */ 257 258 #define MXC_F_SPIXFM_IO_CTRL_SDIO_DS_POS 2 /**< IO_CTRL_SDIO_DS Position */ 259 #define MXC_F_SPIXFM_IO_CTRL_SDIO_DS ((uint32_t)(0x1UL << MXC_F_SPIXFM_IO_CTRL_SDIO_DS_POS)) /**< IO_CTRL_SDIO_DS Mask */ 260 261 #define MXC_F_SPIXFM_IO_CTRL_PU_PD_CTRL_POS 3 /**< IO_CTRL_PU_PD_CTRL Position */ 262 #define MXC_F_SPIXFM_IO_CTRL_PU_PD_CTRL ((uint32_t)(0x3UL << MXC_F_SPIXFM_IO_CTRL_PU_PD_CTRL_POS)) /**< IO_CTRL_PU_PD_CTRL Mask */ 263 #define MXC_V_SPIXFM_IO_CTRL_PU_PD_CTRL_TRI_STATE ((uint32_t)0x0UL) /**< IO_CTRL_PU_PD_CTRL_TRI_STATE Value */ 264 #define MXC_S_SPIXFM_IO_CTRL_PU_PD_CTRL_TRI_STATE (MXC_V_SPIXFM_IO_CTRL_PU_PD_CTRL_TRI_STATE << MXC_F_SPIXFM_IO_CTRL_PU_PD_CTRL_POS) /**< IO_CTRL_PU_PD_CTRL_TRI_STATE Setting */ 265 #define MXC_V_SPIXFM_IO_CTRL_PU_PD_CTRL_PULL_UP ((uint32_t)0x1UL) /**< IO_CTRL_PU_PD_CTRL_PULL_UP Value */ 266 #define MXC_S_SPIXFM_IO_CTRL_PU_PD_CTRL_PULL_UP (MXC_V_SPIXFM_IO_CTRL_PU_PD_CTRL_PULL_UP << MXC_F_SPIXFM_IO_CTRL_PU_PD_CTRL_POS) /**< IO_CTRL_PU_PD_CTRL_PULL_UP Setting */ 267 #define MXC_V_SPIXFM_IO_CTRL_PU_PD_CTRL_PULL_DOWN ((uint32_t)0x2UL) /**< IO_CTRL_PU_PD_CTRL_PULL_DOWN Value */ 268 #define MXC_S_SPIXFM_IO_CTRL_PU_PD_CTRL_PULL_DOWN (MXC_V_SPIXFM_IO_CTRL_PU_PD_CTRL_PULL_DOWN << MXC_F_SPIXFM_IO_CTRL_PU_PD_CTRL_POS) /**< IO_CTRL_PU_PD_CTRL_PULL_DOWN Setting */ 269 270 /**@} end of group SPIXFM_IO_CTRL_Register */ 271 272 /** 273 * @ingroup spixfm_registers 274 * @defgroup SPIXFM_MEMSECCN SPIXFM_MEMSECCN 275 * @brief SPIX Memory Security Control Register. 276 * @{ 277 */ 278 #define MXC_F_SPIXFM_MEMSECCN_DECEN_POS 0 /**< MEMSECCN_DECEN Position */ 279 #define MXC_F_SPIXFM_MEMSECCN_DECEN ((uint32_t)(0x1UL << MXC_F_SPIXFM_MEMSECCN_DECEN_POS)) /**< MEMSECCN_DECEN Mask */ 280 281 #define MXC_F_SPIXFM_MEMSECCN_AUTH_DISABLE_POS 1 /**< MEMSECCN_AUTH_DISABLE Position */ 282 #define MXC_F_SPIXFM_MEMSECCN_AUTH_DISABLE ((uint32_t)(0x1UL << MXC_F_SPIXFM_MEMSECCN_AUTH_DISABLE_POS)) /**< MEMSECCN_AUTH_DISABLE Mask */ 283 284 #define MXC_F_SPIXFM_MEMSECCN_CNTOPTIEN_POS 2 /**< MEMSECCN_CNTOPTIEN Position */ 285 #define MXC_F_SPIXFM_MEMSECCN_CNTOPTIEN ((uint32_t)(0x1UL << MXC_F_SPIXFM_MEMSECCN_CNTOPTIEN_POS)) /**< MEMSECCN_CNTOPTIEN Mask */ 286 287 #define MXC_F_SPIXFM_MEMSECCN_INTERLDIS_POS 3 /**< MEMSECCN_INTERLDIS Position */ 288 #define MXC_F_SPIXFM_MEMSECCN_INTERLDIS ((uint32_t)(0x1UL << MXC_F_SPIXFM_MEMSECCN_INTERLDIS_POS)) /**< MEMSECCN_INTERLDIS Mask */ 289 290 #define MXC_F_SPIXFM_MEMSECCN_AUTHERR_POS 4 /**< MEMSECCN_AUTHERR Position */ 291 #define MXC_F_SPIXFM_MEMSECCN_AUTHERR ((uint32_t)(0x1UL << MXC_F_SPIXFM_MEMSECCN_AUTHERR_POS)) /**< MEMSECCN_AUTHERR Mask */ 292 293 /**@} end of group SPIXFM_MEMSECCN_Register */ 294 295 /** 296 * @ingroup spixfm_registers 297 * @defgroup SPIXFM_BUS_IDLE SPIXFM_BUS_IDLE 298 * @brief SPIXF Bus Idle Detection. 299 * @{ 300 */ 301 #define MXC_F_SPIXFM_BUS_IDLE_BUSIDLE_POS 0 /**< BUS_IDLE_BUSIDLE Position */ 302 #define MXC_F_SPIXFM_BUS_IDLE_BUSIDLE ((uint32_t)(0xFFFFUL << MXC_F_SPIXFM_BUS_IDLE_BUSIDLE_POS)) /**< BUS_IDLE_BUSIDLE Mask */ 303 304 /**@} end of group SPIXFM_BUS_IDLE_Register */ 305 306 #ifdef __cplusplus 307 } 308 #endif 309 310 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_SPIXFM_REGS_H_ 311
