1 /** 2 * @file spixfc_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SPIXFC Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup spixfc_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_SPIXFC_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_SPIXFC_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup spixfc 67 * @defgroup spixfc_registers SPIXFC_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the SPIXFC Peripheral Module. 69 * @details SPI XiP Flash Configuration Controller 70 */ 71 72 /** 73 * @ingroup spixfc_registers 74 * Structure type to access the SPIXFC Registers. 75 */ 76 typedef struct { 77 __IO uint32_t config; /**< <tt>\b 0x00:</tt> SPIXFC CONFIG Register */ 78 __IO uint32_t ss_pol; /**< <tt>\b 0x04:</tt> SPIXFC SS_POL Register */ 79 __IO uint32_t gen_ctrl; /**< <tt>\b 0x08:</tt> SPIXFC GEN_CTRL Register */ 80 __IO uint32_t fifo_ctrl; /**< <tt>\b 0x0C:</tt> SPIXFC FIFO_CTRL Register */ 81 __IO uint32_t spctrl; /**< <tt>\b 0x10:</tt> SPIXFC SPCTRL Register */ 82 __IO uint32_t intfl; /**< <tt>\b 0x14:</tt> SPIXFC INTFL Register */ 83 __IO uint32_t inten; /**< <tt>\b 0x18:</tt> SPIXFC INTEN Register */ 84 } mxc_spixfc_regs_t; 85 86 /* Register offsets for module SPIXFC */ 87 /** 88 * @ingroup spixfc_registers 89 * @defgroup SPIXFC_Register_Offsets Register Offsets 90 * @brief SPIXFC Peripheral Register Offsets from the SPIXFC Base Peripheral Address. 91 * @{ 92 */ 93 #define MXC_R_SPIXFC_CONFIG ((uint32_t)0x00000000UL) /**< Offset from SPIXFC Base Address: <tt> 0x0000</tt> */ 94 #define MXC_R_SPIXFC_SS_POL ((uint32_t)0x00000004UL) /**< Offset from SPIXFC Base Address: <tt> 0x0004</tt> */ 95 #define MXC_R_SPIXFC_GEN_CTRL ((uint32_t)0x00000008UL) /**< Offset from SPIXFC Base Address: <tt> 0x0008</tt> */ 96 #define MXC_R_SPIXFC_FIFO_CTRL ((uint32_t)0x0000000CUL) /**< Offset from SPIXFC Base Address: <tt> 0x000C</tt> */ 97 #define MXC_R_SPIXFC_SPCTRL ((uint32_t)0x00000010UL) /**< Offset from SPIXFC Base Address: <tt> 0x0010</tt> */ 98 #define MXC_R_SPIXFC_INTFL ((uint32_t)0x00000014UL) /**< Offset from SPIXFC Base Address: <tt> 0x0014</tt> */ 99 #define MXC_R_SPIXFC_INTEN ((uint32_t)0x00000018UL) /**< Offset from SPIXFC Base Address: <tt> 0x0018</tt> */ 100 /**@} end of group spixfc_registers */ 101 102 /** 103 * @ingroup spixfc_registers 104 * @defgroup SPIXFC_CONFIG SPIXFC_CONFIG 105 * @brief Configuration Register. 106 * @{ 107 */ 108 #define MXC_F_SPIXFC_CONFIG_SSEL_POS 0 /**< CONFIG_SSEL Position */ 109 #define MXC_F_SPIXFC_CONFIG_SSEL ((uint32_t)(0x7UL << MXC_F_SPIXFC_CONFIG_SSEL_POS)) /**< CONFIG_SSEL Mask */ 110 #define MXC_V_SPIXFC_CONFIG_SSEL_SLAVE_0 ((uint32_t)0x0UL) /**< CONFIG_SSEL_SLAVE_0 Value */ 111 #define MXC_S_SPIXFC_CONFIG_SSEL_SLAVE_0 (MXC_V_SPIXFC_CONFIG_SSEL_SLAVE_0 << MXC_F_SPIXFC_CONFIG_SSEL_POS) /**< CONFIG_SSEL_SLAVE_0 Setting */ 112 #define MXC_V_SPIXFC_CONFIG_SSEL_SLAVE_1 ((uint32_t)0x1UL) /**< CONFIG_SSEL_SLAVE_1 Value */ 113 #define MXC_S_SPIXFC_CONFIG_SSEL_SLAVE_1 (MXC_V_SPIXFC_CONFIG_SSEL_SLAVE_1 << MXC_F_SPIXFC_CONFIG_SSEL_POS) /**< CONFIG_SSEL_SLAVE_1 Setting */ 114 115 #define MXC_F_SPIXFC_CONFIG_MODE_POS 4 /**< CONFIG_MODE Position */ 116 #define MXC_F_SPIXFC_CONFIG_MODE ((uint32_t)(0x3UL << MXC_F_SPIXFC_CONFIG_MODE_POS)) /**< CONFIG_MODE Mask */ 117 #define MXC_V_SPIXFC_CONFIG_MODE_SPIX_MODE_0 ((uint32_t)0x0UL) /**< CONFIG_MODE_SPIX_MODE_0 Value */ 118 #define MXC_S_SPIXFC_CONFIG_MODE_SPIX_MODE_0 (MXC_V_SPIXFC_CONFIG_MODE_SPIX_MODE_0 << MXC_F_SPIXFC_CONFIG_MODE_POS) /**< CONFIG_MODE_SPIX_MODE_0 Setting */ 119 #define MXC_V_SPIXFC_CONFIG_MODE_SPIX_MODE_3 ((uint32_t)0x3UL) /**< CONFIG_MODE_SPIX_MODE_3 Value */ 120 #define MXC_S_SPIXFC_CONFIG_MODE_SPIX_MODE_3 (MXC_V_SPIXFC_CONFIG_MODE_SPIX_MODE_3 << MXC_F_SPIXFC_CONFIG_MODE_POS) /**< CONFIG_MODE_SPIX_MODE_3 Setting */ 121 122 #define MXC_F_SPIXFC_CONFIG_PAGE_SIZE_POS 6 /**< CONFIG_PAGE_SIZE Position */ 123 #define MXC_F_SPIXFC_CONFIG_PAGE_SIZE ((uint32_t)(0x3UL << MXC_F_SPIXFC_CONFIG_PAGE_SIZE_POS)) /**< CONFIG_PAGE_SIZE Mask */ 124 #define MXC_V_SPIXFC_CONFIG_PAGE_SIZE_4_BYTES ((uint32_t)0x0UL) /**< CONFIG_PAGE_SIZE_4_BYTES Value */ 125 #define MXC_S_SPIXFC_CONFIG_PAGE_SIZE_4_BYTES (MXC_V_SPIXFC_CONFIG_PAGE_SIZE_4_BYTES << MXC_F_SPIXFC_CONFIG_PAGE_SIZE_POS) /**< CONFIG_PAGE_SIZE_4_BYTES Setting */ 126 #define MXC_V_SPIXFC_CONFIG_PAGE_SIZE_8_BYTES ((uint32_t)0x1UL) /**< CONFIG_PAGE_SIZE_8_BYTES Value */ 127 #define MXC_S_SPIXFC_CONFIG_PAGE_SIZE_8_BYTES (MXC_V_SPIXFC_CONFIG_PAGE_SIZE_8_BYTES << MXC_F_SPIXFC_CONFIG_PAGE_SIZE_POS) /**< CONFIG_PAGE_SIZE_8_BYTES Setting */ 128 #define MXC_V_SPIXFC_CONFIG_PAGE_SIZE_16_BYTES ((uint32_t)0x2UL) /**< CONFIG_PAGE_SIZE_16_BYTES Value */ 129 #define MXC_S_SPIXFC_CONFIG_PAGE_SIZE_16_BYTES (MXC_V_SPIXFC_CONFIG_PAGE_SIZE_16_BYTES << MXC_F_SPIXFC_CONFIG_PAGE_SIZE_POS) /**< CONFIG_PAGE_SIZE_16_BYTES Setting */ 130 #define MXC_V_SPIXFC_CONFIG_PAGE_SIZE_32_BYTES ((uint32_t)0x3UL) /**< CONFIG_PAGE_SIZE_32_BYTES Value */ 131 #define MXC_S_SPIXFC_CONFIG_PAGE_SIZE_32_BYTES (MXC_V_SPIXFC_CONFIG_PAGE_SIZE_32_BYTES << MXC_F_SPIXFC_CONFIG_PAGE_SIZE_POS) /**< CONFIG_PAGE_SIZE_32_BYTES Setting */ 132 133 #define MXC_F_SPIXFC_CONFIG_HI_CLK_POS 8 /**< CONFIG_HI_CLK Position */ 134 #define MXC_F_SPIXFC_CONFIG_HI_CLK ((uint32_t)(0xFUL << MXC_F_SPIXFC_CONFIG_HI_CLK_POS)) /**< CONFIG_HI_CLK Mask */ 135 #define MXC_V_SPIXFC_CONFIG_HI_CLK_16_SCLK ((uint32_t)0x0UL) /**< CONFIG_HI_CLK_16_SCLK Value */ 136 #define MXC_S_SPIXFC_CONFIG_HI_CLK_16_SCLK (MXC_V_SPIXFC_CONFIG_HI_CLK_16_SCLK << MXC_F_SPIXFC_CONFIG_HI_CLK_POS) /**< CONFIG_HI_CLK_16_SCLK Setting */ 137 138 #define MXC_F_SPIXFC_CONFIG_LO_CLK_POS 12 /**< CONFIG_LO_CLK Position */ 139 #define MXC_F_SPIXFC_CONFIG_LO_CLK ((uint32_t)(0xFUL << MXC_F_SPIXFC_CONFIG_LO_CLK_POS)) /**< CONFIG_LO_CLK Mask */ 140 #define MXC_V_SPIXFC_CONFIG_LO_CLK_16_SCLK ((uint32_t)0x0UL) /**< CONFIG_LO_CLK_16_SCLK Value */ 141 #define MXC_S_SPIXFC_CONFIG_LO_CLK_16_SCLK (MXC_V_SPIXFC_CONFIG_LO_CLK_16_SCLK << MXC_F_SPIXFC_CONFIG_LO_CLK_POS) /**< CONFIG_LO_CLK_16_SCLK Setting */ 142 143 #define MXC_F_SPIXFC_CONFIG_SS_ACT_POS 16 /**< CONFIG_SS_ACT Position */ 144 #define MXC_F_SPIXFC_CONFIG_SS_ACT ((uint32_t)(0x3UL << MXC_F_SPIXFC_CONFIG_SS_ACT_POS)) /**< CONFIG_SS_ACT Mask */ 145 #define MXC_V_SPIXFC_CONFIG_SS_ACT_0_CLKS ((uint32_t)0x0UL) /**< CONFIG_SS_ACT_0_CLKS Value */ 146 #define MXC_S_SPIXFC_CONFIG_SS_ACT_0_CLKS (MXC_V_SPIXFC_CONFIG_SS_ACT_0_CLKS << MXC_F_SPIXFC_CONFIG_SS_ACT_POS) /**< CONFIG_SS_ACT_0_CLKS Setting */ 147 #define MXC_V_SPIXFC_CONFIG_SS_ACT_2_CLKS ((uint32_t)0x1UL) /**< CONFIG_SS_ACT_2_CLKS Value */ 148 #define MXC_S_SPIXFC_CONFIG_SS_ACT_2_CLKS (MXC_V_SPIXFC_CONFIG_SS_ACT_2_CLKS << MXC_F_SPIXFC_CONFIG_SS_ACT_POS) /**< CONFIG_SS_ACT_2_CLKS Setting */ 149 #define MXC_V_SPIXFC_CONFIG_SS_ACT_4_CLKS ((uint32_t)0x2UL) /**< CONFIG_SS_ACT_4_CLKS Value */ 150 #define MXC_S_SPIXFC_CONFIG_SS_ACT_4_CLKS (MXC_V_SPIXFC_CONFIG_SS_ACT_4_CLKS << MXC_F_SPIXFC_CONFIG_SS_ACT_POS) /**< CONFIG_SS_ACT_4_CLKS Setting */ 151 #define MXC_V_SPIXFC_CONFIG_SS_ACT_8_CLKS ((uint32_t)0x3UL) /**< CONFIG_SS_ACT_8_CLKS Value */ 152 #define MXC_S_SPIXFC_CONFIG_SS_ACT_8_CLKS (MXC_V_SPIXFC_CONFIG_SS_ACT_8_CLKS << MXC_F_SPIXFC_CONFIG_SS_ACT_POS) /**< CONFIG_SS_ACT_8_CLKS Setting */ 153 154 #define MXC_F_SPIXFC_CONFIG_SS_INACT_POS 18 /**< CONFIG_SS_INACT Position */ 155 #define MXC_F_SPIXFC_CONFIG_SS_INACT ((uint32_t)(0x3UL << MXC_F_SPIXFC_CONFIG_SS_INACT_POS)) /**< CONFIG_SS_INACT Mask */ 156 #define MXC_V_SPIXFC_CONFIG_SS_INACT_4_CLKS ((uint32_t)0x0UL) /**< CONFIG_SS_INACT_4_CLKS Value */ 157 #define MXC_S_SPIXFC_CONFIG_SS_INACT_4_CLKS (MXC_V_SPIXFC_CONFIG_SS_INACT_4_CLKS << MXC_F_SPIXFC_CONFIG_SS_INACT_POS) /**< CONFIG_SS_INACT_4_CLKS Setting */ 158 #define MXC_V_SPIXFC_CONFIG_SS_INACT_6_CLKS ((uint32_t)0x1UL) /**< CONFIG_SS_INACT_6_CLKS Value */ 159 #define MXC_S_SPIXFC_CONFIG_SS_INACT_6_CLKS (MXC_V_SPIXFC_CONFIG_SS_INACT_6_CLKS << MXC_F_SPIXFC_CONFIG_SS_INACT_POS) /**< CONFIG_SS_INACT_6_CLKS Setting */ 160 #define MXC_V_SPIXFC_CONFIG_SS_INACT_8_CLKS ((uint32_t)0x2UL) /**< CONFIG_SS_INACT_8_CLKS Value */ 161 #define MXC_S_SPIXFC_CONFIG_SS_INACT_8_CLKS (MXC_V_SPIXFC_CONFIG_SS_INACT_8_CLKS << MXC_F_SPIXFC_CONFIG_SS_INACT_POS) /**< CONFIG_SS_INACT_8_CLKS Setting */ 162 #define MXC_V_SPIXFC_CONFIG_SS_INACT_12_CLKS ((uint32_t)0x3UL) /**< CONFIG_SS_INACT_12_CLKS Value */ 163 #define MXC_S_SPIXFC_CONFIG_SS_INACT_12_CLKS (MXC_V_SPIXFC_CONFIG_SS_INACT_12_CLKS << MXC_F_SPIXFC_CONFIG_SS_INACT_POS) /**< CONFIG_SS_INACT_12_CLKS Setting */ 164 165 #define MXC_F_SPIXFC_CONFIG_IOSMPL_POS 20 /**< CONFIG_IOSMPL Position */ 166 #define MXC_F_SPIXFC_CONFIG_IOSMPL ((uint32_t)(0xFUL << MXC_F_SPIXFC_CONFIG_IOSMPL_POS)) /**< CONFIG_IOSMPL Mask */ 167 168 /**@} end of group SPIXFC_CONFIG_Register */ 169 170 /** 171 * @ingroup spixfc_registers 172 * @defgroup SPIXFC_SS_POL SPIXFC_SS_POL 173 * @brief SPIX Controller Slave Select Polarity Register. 174 * @{ 175 */ 176 #define MXC_F_SPIXFC_SS_POL_SSPOL_0_POS 0 /**< SS_POL_SSPOL_0 Position */ 177 #define MXC_F_SPIXFC_SS_POL_SSPOL_0 ((uint32_t)(0x1UL << MXC_F_SPIXFC_SS_POL_SSPOL_0_POS)) /**< SS_POL_SSPOL_0 Mask */ 178 179 /**@} end of group SPIXFC_SS_POL_Register */ 180 181 /** 182 * @ingroup spixfc_registers 183 * @defgroup SPIXFC_GEN_CTRL SPIXFC_GEN_CTRL 184 * @brief SPIX Controller General Controller Register. 185 * @{ 186 */ 187 #define MXC_F_SPIXFC_GEN_CTRL_ENABLE_POS 0 /**< GEN_CTRL_ENABLE Position */ 188 #define MXC_F_SPIXFC_GEN_CTRL_ENABLE ((uint32_t)(0x1UL << MXC_F_SPIXFC_GEN_CTRL_ENABLE_POS)) /**< GEN_CTRL_ENABLE Mask */ 189 190 #define MXC_F_SPIXFC_GEN_CTRL_TX_FIFO_EN_POS 1 /**< GEN_CTRL_TX_FIFO_EN Position */ 191 #define MXC_F_SPIXFC_GEN_CTRL_TX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPIXFC_GEN_CTRL_TX_FIFO_EN_POS)) /**< GEN_CTRL_TX_FIFO_EN Mask */ 192 193 #define MXC_F_SPIXFC_GEN_CTRL_RX_FIFO_EN_POS 2 /**< GEN_CTRL_RX_FIFO_EN Position */ 194 #define MXC_F_SPIXFC_GEN_CTRL_RX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPIXFC_GEN_CTRL_RX_FIFO_EN_POS)) /**< GEN_CTRL_RX_FIFO_EN Mask */ 195 196 #define MXC_F_SPIXFC_GEN_CTRL_BBMODE_POS 3 /**< GEN_CTRL_BBMODE Position */ 197 #define MXC_F_SPIXFC_GEN_CTRL_BBMODE ((uint32_t)(0x1UL << MXC_F_SPIXFC_GEN_CTRL_BBMODE_POS)) /**< GEN_CTRL_BBMODE Mask */ 198 199 #define MXC_F_SPIXFC_GEN_CTRL_SSDR_POS 4 /**< GEN_CTRL_SSDR Position */ 200 #define MXC_F_SPIXFC_GEN_CTRL_SSDR ((uint32_t)(0x1UL << MXC_F_SPIXFC_GEN_CTRL_SSDR_POS)) /**< GEN_CTRL_SSDR Mask */ 201 202 #define MXC_F_SPIXFC_GEN_CTRL_SCLK_DR_POS 6 /**< GEN_CTRL_SCLK_DR Position */ 203 #define MXC_F_SPIXFC_GEN_CTRL_SCLK_DR ((uint32_t)(0x1UL << MXC_F_SPIXFC_GEN_CTRL_SCLK_DR_POS)) /**< GEN_CTRL_SCLK_DR Mask */ 204 205 #define MXC_F_SPIXFC_GEN_CTRL_SDIO_DATA_IN_POS 8 /**< GEN_CTRL_SDIO_DATA_IN Position */ 206 #define MXC_F_SPIXFC_GEN_CTRL_SDIO_DATA_IN ((uint32_t)(0xFUL << MXC_F_SPIXFC_GEN_CTRL_SDIO_DATA_IN_POS)) /**< GEN_CTRL_SDIO_DATA_IN Mask */ 207 #define MXC_V_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO0 ((uint32_t)0x0UL) /**< GEN_CTRL_SDIO_DATA_IN_SDIO0 Value */ 208 #define MXC_S_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO0 (MXC_V_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO0 << MXC_F_SPIXFC_GEN_CTRL_SDIO_DATA_IN_POS) /**< GEN_CTRL_SDIO_DATA_IN_SDIO0 Setting */ 209 #define MXC_V_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO1 ((uint32_t)0x1UL) /**< GEN_CTRL_SDIO_DATA_IN_SDIO1 Value */ 210 #define MXC_S_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO1 (MXC_V_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO1 << MXC_F_SPIXFC_GEN_CTRL_SDIO_DATA_IN_POS) /**< GEN_CTRL_SDIO_DATA_IN_SDIO1 Setting */ 211 #define MXC_V_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO2 ((uint32_t)0x2UL) /**< GEN_CTRL_SDIO_DATA_IN_SDIO2 Value */ 212 #define MXC_S_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO2 (MXC_V_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO2 << MXC_F_SPIXFC_GEN_CTRL_SDIO_DATA_IN_POS) /**< GEN_CTRL_SDIO_DATA_IN_SDIO2 Setting */ 213 #define MXC_V_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO3 ((uint32_t)0x3UL) /**< GEN_CTRL_SDIO_DATA_IN_SDIO3 Value */ 214 #define MXC_S_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO3 (MXC_V_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO3 << MXC_F_SPIXFC_GEN_CTRL_SDIO_DATA_IN_POS) /**< GEN_CTRL_SDIO_DATA_IN_SDIO3 Setting */ 215 216 #define MXC_F_SPIXFC_GEN_CTRL_BB_DATA_POS 12 /**< GEN_CTRL_BB_DATA Position */ 217 #define MXC_F_SPIXFC_GEN_CTRL_BB_DATA ((uint32_t)(0xFUL << MXC_F_SPIXFC_GEN_CTRL_BB_DATA_POS)) /**< GEN_CTRL_BB_DATA Mask */ 218 #define MXC_V_SPIXFC_GEN_CTRL_BB_DATA_SDIO0 ((uint32_t)0x0UL) /**< GEN_CTRL_BB_DATA_SDIO0 Value */ 219 #define MXC_S_SPIXFC_GEN_CTRL_BB_DATA_SDIO0 (MXC_V_SPIXFC_GEN_CTRL_BB_DATA_SDIO0 << MXC_F_SPIXFC_GEN_CTRL_BB_DATA_POS) /**< GEN_CTRL_BB_DATA_SDIO0 Setting */ 220 #define MXC_V_SPIXFC_GEN_CTRL_BB_DATA_SDIO1 ((uint32_t)0x1UL) /**< GEN_CTRL_BB_DATA_SDIO1 Value */ 221 #define MXC_S_SPIXFC_GEN_CTRL_BB_DATA_SDIO1 (MXC_V_SPIXFC_GEN_CTRL_BB_DATA_SDIO1 << MXC_F_SPIXFC_GEN_CTRL_BB_DATA_POS) /**< GEN_CTRL_BB_DATA_SDIO1 Setting */ 222 #define MXC_V_SPIXFC_GEN_CTRL_BB_DATA_SDIO2 ((uint32_t)0x2UL) /**< GEN_CTRL_BB_DATA_SDIO2 Value */ 223 #define MXC_S_SPIXFC_GEN_CTRL_BB_DATA_SDIO2 (MXC_V_SPIXFC_GEN_CTRL_BB_DATA_SDIO2 << MXC_F_SPIXFC_GEN_CTRL_BB_DATA_POS) /**< GEN_CTRL_BB_DATA_SDIO2 Setting */ 224 #define MXC_V_SPIXFC_GEN_CTRL_BB_DATA_SDIO3 ((uint32_t)0x3UL) /**< GEN_CTRL_BB_DATA_SDIO3 Value */ 225 #define MXC_S_SPIXFC_GEN_CTRL_BB_DATA_SDIO3 (MXC_V_SPIXFC_GEN_CTRL_BB_DATA_SDIO3 << MXC_F_SPIXFC_GEN_CTRL_BB_DATA_POS) /**< GEN_CTRL_BB_DATA_SDIO3 Setting */ 226 227 #define MXC_F_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_POS 16 /**< GEN_CTRL_BB_DATA_OUT_EN Position */ 228 #define MXC_F_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN ((uint32_t)(0xFUL << MXC_F_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_POS)) /**< GEN_CTRL_BB_DATA_OUT_EN Mask */ 229 #define MXC_V_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO0 ((uint32_t)0x0UL) /**< GEN_CTRL_BB_DATA_OUT_EN_SDIO0 Value */ 230 #define MXC_S_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO0 (MXC_V_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO0 << MXC_F_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_POS) /**< GEN_CTRL_BB_DATA_OUT_EN_SDIO0 Setting */ 231 #define MXC_V_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO1 ((uint32_t)0x1UL) /**< GEN_CTRL_BB_DATA_OUT_EN_SDIO1 Value */ 232 #define MXC_S_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO1 (MXC_V_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO1 << MXC_F_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_POS) /**< GEN_CTRL_BB_DATA_OUT_EN_SDIO1 Setting */ 233 #define MXC_V_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO2 ((uint32_t)0x2UL) /**< GEN_CTRL_BB_DATA_OUT_EN_SDIO2 Value */ 234 #define MXC_S_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO2 (MXC_V_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO2 << MXC_F_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_POS) /**< GEN_CTRL_BB_DATA_OUT_EN_SDIO2 Setting */ 235 #define MXC_V_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO3 ((uint32_t)0x3UL) /**< GEN_CTRL_BB_DATA_OUT_EN_SDIO3 Value */ 236 #define MXC_S_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO3 (MXC_V_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO3 << MXC_F_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_POS) /**< GEN_CTRL_BB_DATA_OUT_EN_SDIO3 Setting */ 237 238 #define MXC_F_SPIXFC_GEN_CTRL_SIMPLE_POS 20 /**< GEN_CTRL_SIMPLE Position */ 239 #define MXC_F_SPIXFC_GEN_CTRL_SIMPLE ((uint32_t)(0x1UL << MXC_F_SPIXFC_GEN_CTRL_SIMPLE_POS)) /**< GEN_CTRL_SIMPLE Mask */ 240 241 #define MXC_F_SPIXFC_GEN_CTRL_SIMPLERX_POS 21 /**< GEN_CTRL_SIMPLERX Position */ 242 #define MXC_F_SPIXFC_GEN_CTRL_SIMPLERX ((uint32_t)(0x1UL << MXC_F_SPIXFC_GEN_CTRL_SIMPLERX_POS)) /**< GEN_CTRL_SIMPLERX Mask */ 243 244 #define MXC_F_SPIXFC_GEN_CTRL_SMPLSS_POS 22 /**< GEN_CTRL_SMPLSS Position */ 245 #define MXC_F_SPIXFC_GEN_CTRL_SMPLSS ((uint32_t)(0x1UL << MXC_F_SPIXFC_GEN_CTRL_SMPLSS_POS)) /**< GEN_CTRL_SMPLSS Mask */ 246 247 #define MXC_F_SPIXFC_GEN_CTRL_SCLK_FB_POS 24 /**< GEN_CTRL_SCLK_FB Position */ 248 #define MXC_F_SPIXFC_GEN_CTRL_SCLK_FB ((uint32_t)(0x1UL << MXC_F_SPIXFC_GEN_CTRL_SCLK_FB_POS)) /**< GEN_CTRL_SCLK_FB Mask */ 249 250 #define MXC_F_SPIXFC_GEN_CTRL_SCKFBINV_POS 25 /**< GEN_CTRL_SCKFBINV Position */ 251 #define MXC_F_SPIXFC_GEN_CTRL_SCKFBINV ((uint32_t)(0x1UL << MXC_F_SPIXFC_GEN_CTRL_SCKFBINV_POS)) /**< GEN_CTRL_SCKFBINV Mask */ 252 253 /**@} end of group SPIXFC_GEN_CTRL_Register */ 254 255 /** 256 * @ingroup spixfc_registers 257 * @defgroup SPIXFC_FIFO_CTRL SPIXFC_FIFO_CTRL 258 * @brief SPIX Controller FIFO Control and Status Register. 259 * @{ 260 */ 261 #define MXC_F_SPIXFC_FIFO_CTRL_TX_FIFO_AE_LVL_POS 0 /**< FIFO_CTRL_TX_FIFO_AE_LVL Position */ 262 #define MXC_F_SPIXFC_FIFO_CTRL_TX_FIFO_AE_LVL ((uint32_t)(0xFUL << MXC_F_SPIXFC_FIFO_CTRL_TX_FIFO_AE_LVL_POS)) /**< FIFO_CTRL_TX_FIFO_AE_LVL Mask */ 263 264 #define MXC_F_SPIXFC_FIFO_CTRL_TX_FIFO_CNT_POS 8 /**< FIFO_CTRL_TX_FIFO_CNT Position */ 265 #define MXC_F_SPIXFC_FIFO_CTRL_TX_FIFO_CNT ((uint32_t)(0x1FUL << MXC_F_SPIXFC_FIFO_CTRL_TX_FIFO_CNT_POS)) /**< FIFO_CTRL_TX_FIFO_CNT Mask */ 266 267 #define MXC_F_SPIXFC_FIFO_CTRL_RX_FIFO_AF_LVL_POS 16 /**< FIFO_CTRL_RX_FIFO_AF_LVL Position */ 268 #define MXC_F_SPIXFC_FIFO_CTRL_RX_FIFO_AF_LVL ((uint32_t)(0x1FUL << MXC_F_SPIXFC_FIFO_CTRL_RX_FIFO_AF_LVL_POS)) /**< FIFO_CTRL_RX_FIFO_AF_LVL Mask */ 269 270 #define MXC_F_SPIXFC_FIFO_CTRL_RX_FIFO_CNT_POS 24 /**< FIFO_CTRL_RX_FIFO_CNT Position */ 271 #define MXC_F_SPIXFC_FIFO_CTRL_RX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_SPIXFC_FIFO_CTRL_RX_FIFO_CNT_POS)) /**< FIFO_CTRL_RX_FIFO_CNT Mask */ 272 273 /**@} end of group SPIXFC_FIFO_CTRL_Register */ 274 275 /** 276 * @ingroup spixfc_registers 277 * @defgroup SPIXFC_SPCTRL SPIXFC_SPCTRL 278 * @brief SPIX Controller Special Control Register. 279 * @{ 280 */ 281 #define MXC_F_SPIXFC_SPCTRL_SAMPL_POS 0 /**< SPCTRL_SAMPL Position */ 282 #define MXC_F_SPIXFC_SPCTRL_SAMPL ((uint32_t)(0x1UL << MXC_F_SPIXFC_SPCTRL_SAMPL_POS)) /**< SPCTRL_SAMPL Mask */ 283 284 #define MXC_F_SPIXFC_SPCTRL_SDIOOUT_POS 4 /**< SPCTRL_SDIOOUT Position */ 285 #define MXC_F_SPIXFC_SPCTRL_SDIOOUT ((uint32_t)(0xFUL << MXC_F_SPIXFC_SPCTRL_SDIOOUT_POS)) /**< SPCTRL_SDIOOUT Mask */ 286 #define MXC_V_SPIXFC_SPCTRL_SDIOOUT_SDIO0 ((uint32_t)0x0UL) /**< SPCTRL_SDIOOUT_SDIO0 Value */ 287 #define MXC_S_SPIXFC_SPCTRL_SDIOOUT_SDIO0 (MXC_V_SPIXFC_SPCTRL_SDIOOUT_SDIO0 << MXC_F_SPIXFC_SPCTRL_SDIOOUT_POS) /**< SPCTRL_SDIOOUT_SDIO0 Setting */ 288 #define MXC_V_SPIXFC_SPCTRL_SDIOOUT_SDIO1 ((uint32_t)0x1UL) /**< SPCTRL_SDIOOUT_SDIO1 Value */ 289 #define MXC_S_SPIXFC_SPCTRL_SDIOOUT_SDIO1 (MXC_V_SPIXFC_SPCTRL_SDIOOUT_SDIO1 << MXC_F_SPIXFC_SPCTRL_SDIOOUT_POS) /**< SPCTRL_SDIOOUT_SDIO1 Setting */ 290 #define MXC_V_SPIXFC_SPCTRL_SDIOOUT_SDIO2 ((uint32_t)0x2UL) /**< SPCTRL_SDIOOUT_SDIO2 Value */ 291 #define MXC_S_SPIXFC_SPCTRL_SDIOOUT_SDIO2 (MXC_V_SPIXFC_SPCTRL_SDIOOUT_SDIO2 << MXC_F_SPIXFC_SPCTRL_SDIOOUT_POS) /**< SPCTRL_SDIOOUT_SDIO2 Setting */ 292 #define MXC_V_SPIXFC_SPCTRL_SDIOOUT_SDIO3 ((uint32_t)0x3UL) /**< SPCTRL_SDIOOUT_SDIO3 Value */ 293 #define MXC_S_SPIXFC_SPCTRL_SDIOOUT_SDIO3 (MXC_V_SPIXFC_SPCTRL_SDIOOUT_SDIO3 << MXC_F_SPIXFC_SPCTRL_SDIOOUT_POS) /**< SPCTRL_SDIOOUT_SDIO3 Setting */ 294 295 #define MXC_F_SPIXFC_SPCTRL_SDIOOE_POS 8 /**< SPCTRL_SDIOOE Position */ 296 #define MXC_F_SPIXFC_SPCTRL_SDIOOE ((uint32_t)(0xFUL << MXC_F_SPIXFC_SPCTRL_SDIOOE_POS)) /**< SPCTRL_SDIOOE Mask */ 297 #define MXC_V_SPIXFC_SPCTRL_SDIOOE_SDIO0 ((uint32_t)0x0UL) /**< SPCTRL_SDIOOE_SDIO0 Value */ 298 #define MXC_S_SPIXFC_SPCTRL_SDIOOE_SDIO0 (MXC_V_SPIXFC_SPCTRL_SDIOOE_SDIO0 << MXC_F_SPIXFC_SPCTRL_SDIOOE_POS) /**< SPCTRL_SDIOOE_SDIO0 Setting */ 299 #define MXC_V_SPIXFC_SPCTRL_SDIOOE_SDIO1 ((uint32_t)0x1UL) /**< SPCTRL_SDIOOE_SDIO1 Value */ 300 #define MXC_S_SPIXFC_SPCTRL_SDIOOE_SDIO1 (MXC_V_SPIXFC_SPCTRL_SDIOOE_SDIO1 << MXC_F_SPIXFC_SPCTRL_SDIOOE_POS) /**< SPCTRL_SDIOOE_SDIO1 Setting */ 301 #define MXC_V_SPIXFC_SPCTRL_SDIOOE_SDIO2 ((uint32_t)0x2UL) /**< SPCTRL_SDIOOE_SDIO2 Value */ 302 #define MXC_S_SPIXFC_SPCTRL_SDIOOE_SDIO2 (MXC_V_SPIXFC_SPCTRL_SDIOOE_SDIO2 << MXC_F_SPIXFC_SPCTRL_SDIOOE_POS) /**< SPCTRL_SDIOOE_SDIO2 Setting */ 303 #define MXC_V_SPIXFC_SPCTRL_SDIOOE_SDIO3 ((uint32_t)0x3UL) /**< SPCTRL_SDIOOE_SDIO3 Value */ 304 #define MXC_S_SPIXFC_SPCTRL_SDIOOE_SDIO3 (MXC_V_SPIXFC_SPCTRL_SDIOOE_SDIO3 << MXC_F_SPIXFC_SPCTRL_SDIOOE_POS) /**< SPCTRL_SDIOOE_SDIO3 Setting */ 305 306 #define MXC_F_SPIXFC_SPCTRL_SCLKINH3_POS 16 /**< SPCTRL_SCLKINH3 Position */ 307 #define MXC_F_SPIXFC_SPCTRL_SCLKINH3 ((uint32_t)(0x1UL << MXC_F_SPIXFC_SPCTRL_SCLKINH3_POS)) /**< SPCTRL_SCLKINH3 Mask */ 308 309 /**@} end of group SPIXFC_SPCTRL_Register */ 310 311 /** 312 * @ingroup spixfc_registers 313 * @defgroup SPIXFC_INTFL SPIXFC_INTFL 314 * @brief SPIX Controller Interrupt Status Register. 315 * @{ 316 */ 317 #define MXC_F_SPIXFC_INTFL_TX_STALLED_POS 0 /**< INTFL_TX_STALLED Position */ 318 #define MXC_F_SPIXFC_INTFL_TX_STALLED ((uint32_t)(0x1UL << MXC_F_SPIXFC_INTFL_TX_STALLED_POS)) /**< INTFL_TX_STALLED Mask */ 319 320 #define MXC_F_SPIXFC_INTFL_RX_STALLED_POS 1 /**< INTFL_RX_STALLED Position */ 321 #define MXC_F_SPIXFC_INTFL_RX_STALLED ((uint32_t)(0x1UL << MXC_F_SPIXFC_INTFL_RX_STALLED_POS)) /**< INTFL_RX_STALLED Mask */ 322 323 #define MXC_F_SPIXFC_INTFL_TX_READY_POS 2 /**< INTFL_TX_READY Position */ 324 #define MXC_F_SPIXFC_INTFL_TX_READY ((uint32_t)(0x1UL << MXC_F_SPIXFC_INTFL_TX_READY_POS)) /**< INTFL_TX_READY Mask */ 325 326 #define MXC_F_SPIXFC_INTFL_RX_DONE_POS 3 /**< INTFL_RX_DONE Position */ 327 #define MXC_F_SPIXFC_INTFL_RX_DONE ((uint32_t)(0x1UL << MXC_F_SPIXFC_INTFL_RX_DONE_POS)) /**< INTFL_RX_DONE Mask */ 328 329 #define MXC_F_SPIXFC_INTFL_TX_FIFO_AE_POS 4 /**< INTFL_TX_FIFO_AE Position */ 330 #define MXC_F_SPIXFC_INTFL_TX_FIFO_AE ((uint32_t)(0x1UL << MXC_F_SPIXFC_INTFL_TX_FIFO_AE_POS)) /**< INTFL_TX_FIFO_AE Mask */ 331 332 #define MXC_F_SPIXFC_INTFL_RX_FIFO_AF_POS 5 /**< INTFL_RX_FIFO_AF Position */ 333 #define MXC_F_SPIXFC_INTFL_RX_FIFO_AF ((uint32_t)(0x1UL << MXC_F_SPIXFC_INTFL_RX_FIFO_AF_POS)) /**< INTFL_RX_FIFO_AF Mask */ 334 335 /**@} end of group SPIXFC_INTFL_Register */ 336 337 /** 338 * @ingroup spixfc_registers 339 * @defgroup SPIXFC_INTEN SPIXFC_INTEN 340 * @brief SPIX Controller Interrupt Enable Register. 341 * @{ 342 */ 343 #define MXC_F_SPIXFC_INTEN_TX_STALLED_POS 0 /**< INTEN_TX_STALLED Position */ 344 #define MXC_F_SPIXFC_INTEN_TX_STALLED ((uint32_t)(0x1UL << MXC_F_SPIXFC_INTEN_TX_STALLED_POS)) /**< INTEN_TX_STALLED Mask */ 345 346 #define MXC_F_SPIXFC_INTEN_RX_STALLED_POS 1 /**< INTEN_RX_STALLED Position */ 347 #define MXC_F_SPIXFC_INTEN_RX_STALLED ((uint32_t)(0x1UL << MXC_F_SPIXFC_INTEN_RX_STALLED_POS)) /**< INTEN_RX_STALLED Mask */ 348 349 #define MXC_F_SPIXFC_INTEN_TX_READY_POS 2 /**< INTEN_TX_READY Position */ 350 #define MXC_F_SPIXFC_INTEN_TX_READY ((uint32_t)(0x1UL << MXC_F_SPIXFC_INTEN_TX_READY_POS)) /**< INTEN_TX_READY Mask */ 351 352 #define MXC_F_SPIXFC_INTEN_RX_DONE_POS 3 /**< INTEN_RX_DONE Position */ 353 #define MXC_F_SPIXFC_INTEN_RX_DONE ((uint32_t)(0x1UL << MXC_F_SPIXFC_INTEN_RX_DONE_POS)) /**< INTEN_RX_DONE Mask */ 354 355 #define MXC_F_SPIXFC_INTEN_TX_FIFO_AE_POS 4 /**< INTEN_TX_FIFO_AE Position */ 356 #define MXC_F_SPIXFC_INTEN_TX_FIFO_AE ((uint32_t)(0x1UL << MXC_F_SPIXFC_INTEN_TX_FIFO_AE_POS)) /**< INTEN_TX_FIFO_AE Mask */ 357 358 #define MXC_F_SPIXFC_INTEN_RX_FIFO_AF_POS 5 /**< INTEN_RX_FIFO_AF Position */ 359 #define MXC_F_SPIXFC_INTEN_RX_FIFO_AF ((uint32_t)(0x1UL << MXC_F_SPIXFC_INTEN_RX_FIFO_AF_POS)) /**< INTEN_RX_FIFO_AF Mask */ 360 361 /**@} end of group SPIXFC_INTEN_Register */ 362 363 #ifdef __cplusplus 364 } 365 #endif 366 367 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_SPIXFC_REGS_H_ 368
