1 /** 2 * @file spi_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SPI Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup spi_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_SPI_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_SPI_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup spi 67 * @defgroup spi_registers SPI_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the SPI Peripheral Module. 69 * @details SPI peripheral. 70 */ 71 72 /** 73 * @ingroup spi_registers 74 * Structure type to access the SPI Registers. 75 */ 76 typedef struct { 77 union { 78 __IO uint32_t data32; /**< <tt>\b 0x00:</tt> SPI DATA32 Register */ 79 __IO uint16_t data16[2]; /**< <tt>\b 0x00:</tt> SPI DATA16 Register */ 80 __IO uint8_t data8[4]; /**< <tt>\b 0x00:</tt> SPI DATA8 Register */ 81 }; 82 __IO uint32_t ctrl0; /**< <tt>\b 0x04:</tt> SPI CTRL0 Register */ 83 __IO uint32_t ctrl1; /**< <tt>\b 0x08:</tt> SPI CTRL1 Register */ 84 __IO uint32_t ctrl2; /**< <tt>\b 0x0C:</tt> SPI CTRL2 Register */ 85 __IO uint32_t ss_time; /**< <tt>\b 0x10:</tt> SPI SS_TIME Register */ 86 __IO uint32_t clk_cfg; /**< <tt>\b 0x14:</tt> SPI CLK_CFG Register */ 87 __R uint32_t rsv_0x18; 88 __IO uint32_t dma; /**< <tt>\b 0x1C:</tt> SPI DMA Register */ 89 __IO uint32_t int_fl; /**< <tt>\b 0x20:</tt> SPI INT_FL Register */ 90 __IO uint32_t int_en; /**< <tt>\b 0x24:</tt> SPI INT_EN Register */ 91 __IO uint32_t wake_fl; /**< <tt>\b 0x28:</tt> SPI WAKE_FL Register */ 92 __IO uint32_t wake_en; /**< <tt>\b 0x2C:</tt> SPI WAKE_EN Register */ 93 __I uint32_t stat; /**< <tt>\b 0x30:</tt> SPI STAT Register */ 94 } mxc_spi_regs_t; 95 96 /* Register offsets for module SPI */ 97 /** 98 * @ingroup spi_registers 99 * @defgroup SPI_Register_Offsets Register Offsets 100 * @brief SPI Peripheral Register Offsets from the SPI Base Peripheral Address. 101 * @{ 102 */ 103 #define MXC_R_SPI_DATA32 ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: <tt> 0x0000</tt> */ 104 #define MXC_R_SPI_DATA16 ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: <tt> 0x0000</tt> */ 105 #define MXC_R_SPI_DATA8 ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: <tt> 0x0000</tt> */ 106 #define MXC_R_SPI_CTRL0 ((uint32_t)0x00000004UL) /**< Offset from SPI Base Address: <tt> 0x0004</tt> */ 107 #define MXC_R_SPI_CTRL1 ((uint32_t)0x00000008UL) /**< Offset from SPI Base Address: <tt> 0x0008</tt> */ 108 #define MXC_R_SPI_CTRL2 ((uint32_t)0x0000000CUL) /**< Offset from SPI Base Address: <tt> 0x000C</tt> */ 109 #define MXC_R_SPI_SS_TIME ((uint32_t)0x00000010UL) /**< Offset from SPI Base Address: <tt> 0x0010</tt> */ 110 #define MXC_R_SPI_CLK_CFG ((uint32_t)0x00000014UL) /**< Offset from SPI Base Address: <tt> 0x0014</tt> */ 111 #define MXC_R_SPI_DMA ((uint32_t)0x0000001CUL) /**< Offset from SPI Base Address: <tt> 0x001C</tt> */ 112 #define MXC_R_SPI_INT_FL ((uint32_t)0x00000020UL) /**< Offset from SPI Base Address: <tt> 0x0020</tt> */ 113 #define MXC_R_SPI_INT_EN ((uint32_t)0x00000024UL) /**< Offset from SPI Base Address: <tt> 0x0024</tt> */ 114 #define MXC_R_SPI_WAKE_FL ((uint32_t)0x00000028UL) /**< Offset from SPI Base Address: <tt> 0x0028</tt> */ 115 #define MXC_R_SPI_WAKE_EN ((uint32_t)0x0000002CUL) /**< Offset from SPI Base Address: <tt> 0x002C</tt> */ 116 #define MXC_R_SPI_STAT ((uint32_t)0x00000030UL) /**< Offset from SPI Base Address: <tt> 0x0030</tt> */ 117 /**@} end of group spi_registers */ 118 119 /** 120 * @ingroup spi_registers 121 * @defgroup SPI_DATA32 SPI_DATA32 122 * @brief Register for reading and writing the FIFO. 123 * @{ 124 */ 125 #define MXC_F_SPI_DATA32_QSPIFIFO_POS 0 /**< DATA32_QSPIFIFO Position */ 126 #define MXC_F_SPI_DATA32_QSPIFIFO ((uint32_t)(0xFFFFFFFFUL << MXC_F_SPI_DATA32_QSPIFIFO_POS)) /**< DATA32_QSPIFIFO Mask */ 127 128 /**@} end of group SPI_DATA32_Register */ 129 130 /** 131 * @ingroup spi_registers 132 * @defgroup SPI_DATA16 SPI_DATA16 133 * @brief Register for reading and writing the FIFO. 134 * @{ 135 */ 136 #define MXC_F_SPI_DATA16_QSPIFIFO_POS 0 /**< DATA16_QSPIFIFO Position */ 137 #define MXC_F_SPI_DATA16_QSPIFIFO ((uint16_t)(0xFFFFUL << MXC_F_SPI_DATA16_QSPIFIFO_POS)) /**< DATA16_QSPIFIFO Mask */ 138 139 /**@} end of group SPI_DATA16_Register */ 140 141 /** 142 * @ingroup spi_registers 143 * @defgroup SPI_DATA8 SPI_DATA8 144 * @brief Register for reading and writing the FIFO. 145 * @{ 146 */ 147 #define MXC_F_SPI_DATA8_QSPIFIFO_POS 0 /**< DATA8_QSPIFIFO Position */ 148 #define MXC_F_SPI_DATA8_QSPIFIFO ((uint8_t)(0xFFUL << MXC_F_SPI_DATA8_QSPIFIFO_POS)) /**< DATA8_QSPIFIFO Mask */ 149 150 /**@} end of group SPI_DATA8_Register */ 151 152 /** 153 * @ingroup spi_registers 154 * @defgroup SPI_CTRL0 SPI_CTRL0 155 * @brief Register for controlling SPI peripheral. 156 * @{ 157 */ 158 #define MXC_F_SPI_CTRL0_EN_POS 0 /**< CTRL0_EN Position */ 159 #define MXC_F_SPI_CTRL0_EN ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_EN_POS)) /**< CTRL0_EN Mask */ 160 161 #define MXC_F_SPI_CTRL0_MASTER_POS 1 /**< CTRL0_MASTER Position */ 162 #define MXC_F_SPI_CTRL0_MASTER ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_MASTER_POS)) /**< CTRL0_MASTER Mask */ 163 164 #define MXC_F_SPI_CTRL0_SS_IO_POS 4 /**< CTRL0_SS_IO Position */ 165 #define MXC_F_SPI_CTRL0_SS_IO ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_IO_POS)) /**< CTRL0_SS_IO Mask */ 166 167 #define MXC_F_SPI_CTRL0_START_POS 5 /**< CTRL0_START Position */ 168 #define MXC_F_SPI_CTRL0_START ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_START_POS)) /**< CTRL0_START Mask */ 169 170 #define MXC_F_SPI_CTRL0_SS_CTRL_POS 8 /**< CTRL0_SS_CTRL Position */ 171 #define MXC_F_SPI_CTRL0_SS_CTRL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_CTRL_POS)) /**< CTRL0_SS_CTRL Mask */ 172 173 #define MXC_F_SPI_CTRL0_SS_POS 16 /**< CTRL0_SS Position */ 174 #define MXC_F_SPI_CTRL0_SS ((uint32_t)(0x7UL << MXC_F_SPI_CTRL0_SS_POS)) /**< CTRL0_SS Mask */ 175 #define MXC_V_SPI_CTRL0_SS_SS0 ((uint32_t)0x1UL) /**< CTRL0_SS_SS0 Value */ 176 #define MXC_S_SPI_CTRL0_SS_SS0 (MXC_V_SPI_CTRL0_SS_SS0 << MXC_F_SPI_CTRL0_SS_POS) /**< CTRL0_SS_SS0 Setting */ 177 #define MXC_V_SPI_CTRL0_SS_SS1 ((uint32_t)0x2UL) /**< CTRL0_SS_SS1 Value */ 178 #define MXC_S_SPI_CTRL0_SS_SS1 (MXC_V_SPI_CTRL0_SS_SS1 << MXC_F_SPI_CTRL0_SS_POS) /**< CTRL0_SS_SS1 Setting */ 179 #define MXC_V_SPI_CTRL0_SS_SS2 ((uint32_t)0x4UL) /**< CTRL0_SS_SS2 Value */ 180 #define MXC_S_SPI_CTRL0_SS_SS2 (MXC_V_SPI_CTRL0_SS_SS2 << MXC_F_SPI_CTRL0_SS_POS) /**< CTRL0_SS_SS2 Setting */ 181 182 /**@} end of group SPI_CTRL0_Register */ 183 184 /** 185 * @ingroup spi_registers 186 * @defgroup SPI_CTRL1 SPI_CTRL1 187 * @brief Register for controlling SPI peripheral. 188 * @{ 189 */ 190 #define MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS 0 /**< CTRL1_TX_NUM_CHAR Position */ 191 #define MXC_F_SPI_CTRL1_TX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS)) /**< CTRL1_TX_NUM_CHAR Mask */ 192 193 #define MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS 16 /**< CTRL1_RX_NUM_CHAR Position */ 194 #define MXC_F_SPI_CTRL1_RX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS)) /**< CTRL1_RX_NUM_CHAR Mask */ 195 196 /**@} end of group SPI_CTRL1_Register */ 197 198 /** 199 * @ingroup spi_registers 200 * @defgroup SPI_CTRL2 SPI_CTRL2 201 * @brief Register for controlling SPI peripheral. 202 * @{ 203 */ 204 #define MXC_F_SPI_CTRL2_CPHA_POS 0 /**< CTRL2_CPHA Position */ 205 #define MXC_F_SPI_CTRL2_CPHA ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CPHA_POS)) /**< CTRL2_CPHA Mask */ 206 207 #define MXC_F_SPI_CTRL2_CPOL_POS 1 /**< CTRL2_CPOL Position */ 208 #define MXC_F_SPI_CTRL2_CPOL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CPOL_POS)) /**< CTRL2_CPOL Mask */ 209 210 #define MXC_F_SPI_CTRL2_NUMBITS_POS 8 /**< CTRL2_NUMBITS Position */ 211 #define MXC_F_SPI_CTRL2_NUMBITS ((uint32_t)(0xFUL << MXC_F_SPI_CTRL2_NUMBITS_POS)) /**< CTRL2_NUMBITS Mask */ 212 #define MXC_V_SPI_CTRL2_NUMBITS_0 ((uint32_t)0x0UL) /**< CTRL2_NUMBITS_0 Value */ 213 #define MXC_S_SPI_CTRL2_NUMBITS_0 (MXC_V_SPI_CTRL2_NUMBITS_0 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_0 Setting */ 214 215 #define MXC_F_SPI_CTRL2_DATA_WIDTH_POS 12 /**< CTRL2_DATA_WIDTH Position */ 216 #define MXC_F_SPI_CTRL2_DATA_WIDTH ((uint32_t)(0x3UL << MXC_F_SPI_CTRL2_DATA_WIDTH_POS)) /**< CTRL2_DATA_WIDTH Mask */ 217 #define MXC_V_SPI_CTRL2_DATA_WIDTH_MONO ((uint32_t)0x0UL) /**< CTRL2_DATA_WIDTH_MONO Value */ 218 #define MXC_S_SPI_CTRL2_DATA_WIDTH_MONO (MXC_V_SPI_CTRL2_DATA_WIDTH_MONO << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_MONO Setting */ 219 #define MXC_V_SPI_CTRL2_DATA_WIDTH_DUAL ((uint32_t)0x1UL) /**< CTRL2_DATA_WIDTH_DUAL Value */ 220 #define MXC_S_SPI_CTRL2_DATA_WIDTH_DUAL (MXC_V_SPI_CTRL2_DATA_WIDTH_DUAL << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_DUAL Setting */ 221 #define MXC_V_SPI_CTRL2_DATA_WIDTH_QUAD ((uint32_t)0x2UL) /**< CTRL2_DATA_WIDTH_QUAD Value */ 222 #define MXC_S_SPI_CTRL2_DATA_WIDTH_QUAD (MXC_V_SPI_CTRL2_DATA_WIDTH_QUAD << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_QUAD Setting */ 223 224 #define MXC_F_SPI_CTRL2_THREE_WIRE_POS 15 /**< CTRL2_THREE_WIRE Position */ 225 #define MXC_F_SPI_CTRL2_THREE_WIRE ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_THREE_WIRE_POS)) /**< CTRL2_THREE_WIRE Mask */ 226 227 #define MXC_F_SPI_CTRL2_SS_POL_POS 16 /**< CTRL2_SS_POL Position */ 228 #define MXC_F_SPI_CTRL2_SS_POL ((uint32_t)(0xFUL << MXC_F_SPI_CTRL2_SS_POL_POS)) /**< CTRL2_SS_POL Mask */ 229 #define MXC_V_SPI_CTRL2_SS_POL_SS0_HIGH ((uint32_t)0x1UL) /**< CTRL2_SS_POL_SS0_HIGH Value */ 230 #define MXC_S_SPI_CTRL2_SS_POL_SS0_HIGH (MXC_V_SPI_CTRL2_SS_POL_SS0_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS0_HIGH Setting */ 231 #define MXC_V_SPI_CTRL2_SS_POL_SS1_HIGH ((uint32_t)0x2UL) /**< CTRL2_SS_POL_SS1_HIGH Value */ 232 #define MXC_S_SPI_CTRL2_SS_POL_SS1_HIGH (MXC_V_SPI_CTRL2_SS_POL_SS1_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS1_HIGH Setting */ 233 #define MXC_V_SPI_CTRL2_SS_POL_SS2_HIGH ((uint32_t)0x4UL) /**< CTRL2_SS_POL_SS2_HIGH Value */ 234 #define MXC_S_SPI_CTRL2_SS_POL_SS2_HIGH (MXC_V_SPI_CTRL2_SS_POL_SS2_HIGH << MXC_F_SPI_CTRL2_SS_POL_POS) /**< CTRL2_SS_POL_SS2_HIGH Setting */ 235 236 /**@} end of group SPI_CTRL2_Register */ 237 238 /** 239 * @ingroup spi_registers 240 * @defgroup SPI_SS_TIME SPI_SS_TIME 241 * @brief Register for controlling SPI peripheral/Slave Select Timing. 242 * @{ 243 */ 244 #define MXC_F_SPI_SS_TIME_PRE_POS 0 /**< SS_TIME_PRE Position */ 245 #define MXC_F_SPI_SS_TIME_PRE ((uint32_t)(0xFFUL << MXC_F_SPI_SS_TIME_PRE_POS)) /**< SS_TIME_PRE Mask */ 246 #define MXC_V_SPI_SS_TIME_PRE_256 ((uint32_t)0x0UL) /**< SS_TIME_PRE_256 Value */ 247 #define MXC_S_SPI_SS_TIME_PRE_256 (MXC_V_SPI_SS_TIME_PRE_256 << MXC_F_SPI_SS_TIME_PRE_POS) /**< SS_TIME_PRE_256 Setting */ 248 249 #define MXC_F_SPI_SS_TIME_POST_POS 8 /**< SS_TIME_POST Position */ 250 #define MXC_F_SPI_SS_TIME_POST ((uint32_t)(0xFFUL << MXC_F_SPI_SS_TIME_POST_POS)) /**< SS_TIME_POST Mask */ 251 #define MXC_V_SPI_SS_TIME_POST_256 ((uint32_t)0x0UL) /**< SS_TIME_POST_256 Value */ 252 #define MXC_S_SPI_SS_TIME_POST_256 (MXC_V_SPI_SS_TIME_POST_256 << MXC_F_SPI_SS_TIME_POST_POS) /**< SS_TIME_POST_256 Setting */ 253 254 #define MXC_F_SPI_SS_TIME_INACT_POS 16 /**< SS_TIME_INACT Position */ 255 #define MXC_F_SPI_SS_TIME_INACT ((uint32_t)(0xFFUL << MXC_F_SPI_SS_TIME_INACT_POS)) /**< SS_TIME_INACT Mask */ 256 #define MXC_V_SPI_SS_TIME_INACT_256 ((uint32_t)0x0UL) /**< SS_TIME_INACT_256 Value */ 257 #define MXC_S_SPI_SS_TIME_INACT_256 (MXC_V_SPI_SS_TIME_INACT_256 << MXC_F_SPI_SS_TIME_INACT_POS) /**< SS_TIME_INACT_256 Setting */ 258 259 /**@} end of group SPI_SS_TIME_Register */ 260 261 /** 262 * @ingroup spi_registers 263 * @defgroup SPI_CLK_CFG SPI_CLK_CFG 264 * @brief Register for controlling SPI clock rate. 265 * @{ 266 */ 267 #define MXC_F_SPI_CLK_CFG_LO_POS 0 /**< CLK_CFG_LO Position */ 268 #define MXC_F_SPI_CLK_CFG_LO ((uint32_t)(0xFFUL << MXC_F_SPI_CLK_CFG_LO_POS)) /**< CLK_CFG_LO Mask */ 269 #define MXC_V_SPI_CLK_CFG_LO_DIS ((uint32_t)0x0UL) /**< CLK_CFG_LO_DIS Value */ 270 #define MXC_S_SPI_CLK_CFG_LO_DIS (MXC_V_SPI_CLK_CFG_LO_DIS << MXC_F_SPI_CLK_CFG_LO_POS) /**< CLK_CFG_LO_DIS Setting */ 271 272 #define MXC_F_SPI_CLK_CFG_HI_POS 8 /**< CLK_CFG_HI Position */ 273 #define MXC_F_SPI_CLK_CFG_HI ((uint32_t)(0xFFUL << MXC_F_SPI_CLK_CFG_HI_POS)) /**< CLK_CFG_HI Mask */ 274 #define MXC_V_SPI_CLK_CFG_HI_DIS ((uint32_t)0x0UL) /**< CLK_CFG_HI_DIS Value */ 275 #define MXC_S_SPI_CLK_CFG_HI_DIS (MXC_V_SPI_CLK_CFG_HI_DIS << MXC_F_SPI_CLK_CFG_HI_POS) /**< CLK_CFG_HI_DIS Setting */ 276 277 #define MXC_F_SPI_CLK_CFG_SCALE_POS 16 /**< CLK_CFG_SCALE Position */ 278 #define MXC_F_SPI_CLK_CFG_SCALE ((uint32_t)(0xFUL << MXC_F_SPI_CLK_CFG_SCALE_POS)) /**< CLK_CFG_SCALE Mask */ 279 280 /**@} end of group SPI_CLK_CFG_Register */ 281 282 /** 283 * @ingroup spi_registers 284 * @defgroup SPI_DMA SPI_DMA 285 * @brief Register for controlling DMA. 286 * @{ 287 */ 288 #define MXC_F_SPI_DMA_TX_FIFO_LEVEL_POS 0 /**< DMA_TX_FIFO_LEVEL Position */ 289 #define MXC_F_SPI_DMA_TX_FIFO_LEVEL ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_TX_FIFO_LEVEL_POS)) /**< DMA_TX_FIFO_LEVEL Mask */ 290 291 #define MXC_F_SPI_DMA_TX_FIFO_EN_POS 6 /**< DMA_TX_FIFO_EN Position */ 292 #define MXC_F_SPI_DMA_TX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FIFO_EN_POS)) /**< DMA_TX_FIFO_EN Mask */ 293 294 #define MXC_F_SPI_DMA_TX_FIFO_CLEAR_POS 7 /**< DMA_TX_FIFO_CLEAR Position */ 295 #define MXC_F_SPI_DMA_TX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FIFO_CLEAR_POS)) /**< DMA_TX_FIFO_CLEAR Mask */ 296 297 #define MXC_F_SPI_DMA_TX_FIFO_CNT_POS 8 /**< DMA_TX_FIFO_CNT Position */ 298 #define MXC_F_SPI_DMA_TX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_TX_FIFO_CNT_POS)) /**< DMA_TX_FIFO_CNT Mask */ 299 300 #define MXC_F_SPI_DMA_TX_DMA_EN_POS 15 /**< DMA_TX_DMA_EN Position */ 301 #define MXC_F_SPI_DMA_TX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_DMA_EN_POS)) /**< DMA_TX_DMA_EN Mask */ 302 303 #define MXC_F_SPI_DMA_RX_FIFO_LEVEL_POS 16 /**< DMA_RX_FIFO_LEVEL Position */ 304 #define MXC_F_SPI_DMA_RX_FIFO_LEVEL ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_RX_FIFO_LEVEL_POS)) /**< DMA_RX_FIFO_LEVEL Mask */ 305 306 #define MXC_F_SPI_DMA_RX_FIFO_EN_POS 22 /**< DMA_RX_FIFO_EN Position */ 307 #define MXC_F_SPI_DMA_RX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FIFO_EN_POS)) /**< DMA_RX_FIFO_EN Mask */ 308 309 #define MXC_F_SPI_DMA_RX_FIFO_CLEAR_POS 23 /**< DMA_RX_FIFO_CLEAR Position */ 310 #define MXC_F_SPI_DMA_RX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FIFO_CLEAR_POS)) /**< DMA_RX_FIFO_CLEAR Mask */ 311 312 #define MXC_F_SPI_DMA_RX_FIFO_CNT_POS 24 /**< DMA_RX_FIFO_CNT Position */ 313 #define MXC_F_SPI_DMA_RX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_RX_FIFO_CNT_POS)) /**< DMA_RX_FIFO_CNT Mask */ 314 315 #define MXC_F_SPI_DMA_RX_DMA_EN_POS 31 /**< DMA_RX_DMA_EN Position */ 316 #define MXC_F_SPI_DMA_RX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_DMA_EN_POS)) /**< DMA_RX_DMA_EN Mask */ 317 318 /**@} end of group SPI_DMA_Register */ 319 320 /** 321 * @ingroup spi_registers 322 * @defgroup SPI_INT_FL SPI_INT_FL 323 * @brief Register for reading and clearing interrupt flags. All bits are write 1 to 324 * clear. 325 * @{ 326 */ 327 #define MXC_F_SPI_INT_FL_TX_THRESH_POS 0 /**< INT_FL_TX_THRESH Position */ 328 #define MXC_F_SPI_INT_FL_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_THRESH_POS)) /**< INT_FL_TX_THRESH Mask */ 329 330 #define MXC_F_SPI_INT_FL_TX_EMPTY_POS 1 /**< INT_FL_TX_EMPTY Position */ 331 #define MXC_F_SPI_INT_FL_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_EMPTY_POS)) /**< INT_FL_TX_EMPTY Mask */ 332 333 #define MXC_F_SPI_INT_FL_RX_THRESH_POS 2 /**< INT_FL_RX_THRESH Position */ 334 #define MXC_F_SPI_INT_FL_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_THRESH_POS)) /**< INT_FL_RX_THRESH Mask */ 335 336 #define MXC_F_SPI_INT_FL_RX_FULL_POS 3 /**< INT_FL_RX_FULL Position */ 337 #define MXC_F_SPI_INT_FL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_FULL_POS)) /**< INT_FL_RX_FULL Mask */ 338 339 #define MXC_F_SPI_INT_FL_SSA_POS 4 /**< INT_FL_SSA Position */ 340 #define MXC_F_SPI_INT_FL_SSA ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_SSA_POS)) /**< INT_FL_SSA Mask */ 341 342 #define MXC_F_SPI_INT_FL_SSD_POS 5 /**< INT_FL_SSD Position */ 343 #define MXC_F_SPI_INT_FL_SSD ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_SSD_POS)) /**< INT_FL_SSD Mask */ 344 345 #define MXC_F_SPI_INT_FL_FAULT_POS 8 /**< INT_FL_FAULT Position */ 346 #define MXC_F_SPI_INT_FL_FAULT ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_FAULT_POS)) /**< INT_FL_FAULT Mask */ 347 348 #define MXC_F_SPI_INT_FL_ABORT_POS 9 /**< INT_FL_ABORT Position */ 349 #define MXC_F_SPI_INT_FL_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_ABORT_POS)) /**< INT_FL_ABORT Mask */ 350 351 #define MXC_F_SPI_INT_FL_M_DONE_POS 11 /**< INT_FL_M_DONE Position */ 352 #define MXC_F_SPI_INT_FL_M_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_M_DONE_POS)) /**< INT_FL_M_DONE Mask */ 353 354 #define MXC_F_SPI_INT_FL_TX_OVR_POS 12 /**< INT_FL_TX_OVR Position */ 355 #define MXC_F_SPI_INT_FL_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_OVR_POS)) /**< INT_FL_TX_OVR Mask */ 356 357 #define MXC_F_SPI_INT_FL_TX_UND_POS 13 /**< INT_FL_TX_UND Position */ 358 #define MXC_F_SPI_INT_FL_TX_UND ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_UND_POS)) /**< INT_FL_TX_UND Mask */ 359 360 #define MXC_F_SPI_INT_FL_RX_OVR_POS 14 /**< INT_FL_RX_OVR Position */ 361 #define MXC_F_SPI_INT_FL_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_OVR_POS)) /**< INT_FL_RX_OVR Mask */ 362 363 #define MXC_F_SPI_INT_FL_RX_UND_POS 15 /**< INT_FL_RX_UND Position */ 364 #define MXC_F_SPI_INT_FL_RX_UND ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_UND_POS)) /**< INT_FL_RX_UND Mask */ 365 366 /**@} end of group SPI_INT_FL_Register */ 367 368 /** 369 * @ingroup spi_registers 370 * @defgroup SPI_INT_EN SPI_INT_EN 371 * @brief Register for enabling interrupts. 372 * @{ 373 */ 374 #define MXC_F_SPI_INT_EN_TX_THRESH_POS 0 /**< INT_EN_TX_THRESH Position */ 375 #define MXC_F_SPI_INT_EN_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_THRESH_POS)) /**< INT_EN_TX_THRESH Mask */ 376 377 #define MXC_F_SPI_INT_EN_TX_EMPTY_POS 1 /**< INT_EN_TX_EMPTY Position */ 378 #define MXC_F_SPI_INT_EN_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_EMPTY_POS)) /**< INT_EN_TX_EMPTY Mask */ 379 380 #define MXC_F_SPI_INT_EN_RX_THRESH_POS 2 /**< INT_EN_RX_THRESH Position */ 381 #define MXC_F_SPI_INT_EN_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_THRESH_POS)) /**< INT_EN_RX_THRESH Mask */ 382 383 #define MXC_F_SPI_INT_EN_RX_FULL_POS 3 /**< INT_EN_RX_FULL Position */ 384 #define MXC_F_SPI_INT_EN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_FULL_POS)) /**< INT_EN_RX_FULL Mask */ 385 386 #define MXC_F_SPI_INT_EN_SSA_POS 4 /**< INT_EN_SSA Position */ 387 #define MXC_F_SPI_INT_EN_SSA ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_SSA_POS)) /**< INT_EN_SSA Mask */ 388 389 #define MXC_F_SPI_INT_EN_SSD_POS 5 /**< INT_EN_SSD Position */ 390 #define MXC_F_SPI_INT_EN_SSD ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_SSD_POS)) /**< INT_EN_SSD Mask */ 391 392 #define MXC_F_SPI_INT_EN_FAULT_POS 8 /**< INT_EN_FAULT Position */ 393 #define MXC_F_SPI_INT_EN_FAULT ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_FAULT_POS)) /**< INT_EN_FAULT Mask */ 394 395 #define MXC_F_SPI_INT_EN_ABORT_POS 9 /**< INT_EN_ABORT Position */ 396 #define MXC_F_SPI_INT_EN_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_ABORT_POS)) /**< INT_EN_ABORT Mask */ 397 398 #define MXC_F_SPI_INT_EN_M_DONE_POS 11 /**< INT_EN_M_DONE Position */ 399 #define MXC_F_SPI_INT_EN_M_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_M_DONE_POS)) /**< INT_EN_M_DONE Mask */ 400 401 #define MXC_F_SPI_INT_EN_TX_OVR_POS 12 /**< INT_EN_TX_OVR Position */ 402 #define MXC_F_SPI_INT_EN_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_OVR_POS)) /**< INT_EN_TX_OVR Mask */ 403 404 #define MXC_F_SPI_INT_EN_TX_UND_POS 13 /**< INT_EN_TX_UND Position */ 405 #define MXC_F_SPI_INT_EN_TX_UND ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_TX_UND_POS)) /**< INT_EN_TX_UND Mask */ 406 407 #define MXC_F_SPI_INT_EN_RX_OVR_POS 14 /**< INT_EN_RX_OVR Position */ 408 #define MXC_F_SPI_INT_EN_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_OVR_POS)) /**< INT_EN_RX_OVR Mask */ 409 410 #define MXC_F_SPI_INT_EN_RX_UND_POS 15 /**< INT_EN_RX_UND Position */ 411 #define MXC_F_SPI_INT_EN_RX_UND ((uint32_t)(0x1UL << MXC_F_SPI_INT_EN_RX_UND_POS)) /**< INT_EN_RX_UND Mask */ 412 413 /**@} end of group SPI_INT_EN_Register */ 414 415 /** 416 * @ingroup spi_registers 417 * @defgroup SPI_WAKE_FL SPI_WAKE_FL 418 * @brief Register for wake up flags. All bits in this register are write 1 to clear. 419 * @{ 420 */ 421 #define MXC_F_SPI_WAKE_FL_TX_THRESH_POS 0 /**< WAKE_FL_TX_THRESH Position */ 422 #define MXC_F_SPI_WAKE_FL_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_TX_THRESH_POS)) /**< WAKE_FL_TX_THRESH Mask */ 423 424 #define MXC_F_SPI_WAKE_FL_TX_EMPTY_POS 1 /**< WAKE_FL_TX_EMPTY Position */ 425 #define MXC_F_SPI_WAKE_FL_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_TX_EMPTY_POS)) /**< WAKE_FL_TX_EMPTY Mask */ 426 427 #define MXC_F_SPI_WAKE_FL_RX_THRESH_POS 2 /**< WAKE_FL_RX_THRESH Position */ 428 #define MXC_F_SPI_WAKE_FL_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_RX_THRESH_POS)) /**< WAKE_FL_RX_THRESH Mask */ 429 430 #define MXC_F_SPI_WAKE_FL_RX_FULL_POS 3 /**< WAKE_FL_RX_FULL Position */ 431 #define MXC_F_SPI_WAKE_FL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_FL_RX_FULL_POS)) /**< WAKE_FL_RX_FULL Mask */ 432 433 /**@} end of group SPI_WAKE_FL_Register */ 434 435 /** 436 * @ingroup spi_registers 437 * @defgroup SPI_WAKE_EN SPI_WAKE_EN 438 * @brief Register for wake up enable. 439 * @{ 440 */ 441 #define MXC_F_SPI_WAKE_EN_TX_THRESH_POS 0 /**< WAKE_EN_TX_THRESH Position */ 442 #define MXC_F_SPI_WAKE_EN_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_TX_THRESH_POS)) /**< WAKE_EN_TX_THRESH Mask */ 443 444 #define MXC_F_SPI_WAKE_EN_TX_EMPTY_POS 1 /**< WAKE_EN_TX_EMPTY Position */ 445 #define MXC_F_SPI_WAKE_EN_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_TX_EMPTY_POS)) /**< WAKE_EN_TX_EMPTY Mask */ 446 447 #define MXC_F_SPI_WAKE_EN_RX_THRESH_POS 2 /**< WAKE_EN_RX_THRESH Position */ 448 #define MXC_F_SPI_WAKE_EN_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_RX_THRESH_POS)) /**< WAKE_EN_RX_THRESH Mask */ 449 450 #define MXC_F_SPI_WAKE_EN_RX_FULL_POS 3 /**< WAKE_EN_RX_FULL Position */ 451 #define MXC_F_SPI_WAKE_EN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_WAKE_EN_RX_FULL_POS)) /**< WAKE_EN_RX_FULL Mask */ 452 453 /**@} end of group SPI_WAKE_EN_Register */ 454 455 /** 456 * @ingroup spi_registers 457 * @defgroup SPI_STAT SPI_STAT 458 * @brief SPI Status register. 459 * @{ 460 */ 461 #define MXC_F_SPI_STAT_BUSY_POS 0 /**< STAT_BUSY Position */ 462 #define MXC_F_SPI_STAT_BUSY ((uint32_t)(0x1UL << MXC_F_SPI_STAT_BUSY_POS)) /**< STAT_BUSY Mask */ 463 464 /**@} end of group SPI_STAT_Register */ 465 466 #ifdef __cplusplus 467 } 468 #endif 469 470 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_SPI_REGS_H_ 471
