1 /** 2 * @file smon_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the SMON Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup smon_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_SMON_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_SMON_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup smon 67 * @defgroup smon_registers SMON_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the SMON Peripheral Module. 69 * @details The Security Monitor block used to monitor system threat conditions. 70 */ 71 72 /** 73 * @ingroup smon_registers 74 * Structure type to access the SMON Registers. 75 */ 76 typedef struct { 77 __IO uint32_t extscn; /**< <tt>\b 0x00:</tt> SMON EXTSCN Register */ 78 __IO uint32_t intscn; /**< <tt>\b 0x04:</tt> SMON INTSCN Register */ 79 __IO uint32_t secalm; /**< <tt>\b 0x08:</tt> SMON SECALM Register */ 80 __I uint32_t secdiag; /**< <tt>\b 0x0C:</tt> SMON SECDIAG Register */ 81 __I uint32_t dlrtc; /**< <tt>\b 0x10:</tt> SMON DLRTC Register */ 82 __R uint32_t rsv_0x14_0x23[4]; 83 __IO uint32_t meucfg; /**< <tt>\b 0x24:</tt> SMON MEUCFG Register */ 84 __R uint32_t rsv_0x28_0x33[3]; 85 __I uint32_t secst; /**< <tt>\b 0x34:</tt> SMON SECST Register */ 86 __IO uint32_t sdbe; /**< <tt>\b 0x38:</tt> SMON SDBE Register */ 87 } mxc_smon_regs_t; 88 89 /* Register offsets for module SMON */ 90 /** 91 * @ingroup smon_registers 92 * @defgroup SMON_Register_Offsets Register Offsets 93 * @brief SMON Peripheral Register Offsets from the SMON Base Peripheral Address. 94 * @{ 95 */ 96 #define MXC_R_SMON_EXTSCN ((uint32_t)0x00000000UL) /**< Offset from SMON Base Address: <tt> 0x0000</tt> */ 97 #define MXC_R_SMON_INTSCN ((uint32_t)0x00000004UL) /**< Offset from SMON Base Address: <tt> 0x0004</tt> */ 98 #define MXC_R_SMON_SECALM ((uint32_t)0x00000008UL) /**< Offset from SMON Base Address: <tt> 0x0008</tt> */ 99 #define MXC_R_SMON_SECDIAG ((uint32_t)0x0000000CUL) /**< Offset from SMON Base Address: <tt> 0x000C</tt> */ 100 #define MXC_R_SMON_DLRTC ((uint32_t)0x00000010UL) /**< Offset from SMON Base Address: <tt> 0x0010</tt> */ 101 #define MXC_R_SMON_MEUCFG ((uint32_t)0x00000024UL) /**< Offset from SMON Base Address: <tt> 0x0024</tt> */ 102 #define MXC_R_SMON_SECST ((uint32_t)0x00000034UL) /**< Offset from SMON Base Address: <tt> 0x0034</tt> */ 103 #define MXC_R_SMON_SDBE ((uint32_t)0x00000038UL) /**< Offset from SMON Base Address: <tt> 0x0038</tt> */ 104 /**@} end of group smon_registers */ 105 106 /** 107 * @ingroup smon_registers 108 * @defgroup SMON_EXTSCN SMON_EXTSCN 109 * @brief External Sensor Control Register. 110 * @{ 111 */ 112 #define MXC_F_SMON_EXTSCN_EXTS_EN0_POS 0 /**< EXTSCN_EXTS_EN0 Position */ 113 #define MXC_F_SMON_EXTSCN_EXTS_EN0 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN0_POS)) /**< EXTSCN_EXTS_EN0 Mask */ 114 115 #define MXC_F_SMON_EXTSCN_EXTS_EN1_POS 1 /**< EXTSCN_EXTS_EN1 Position */ 116 #define MXC_F_SMON_EXTSCN_EXTS_EN1 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN1_POS)) /**< EXTSCN_EXTS_EN1 Mask */ 117 118 #define MXC_F_SMON_EXTSCN_EXTS_EN2_POS 2 /**< EXTSCN_EXTS_EN2 Position */ 119 #define MXC_F_SMON_EXTSCN_EXTS_EN2 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN2_POS)) /**< EXTSCN_EXTS_EN2 Mask */ 120 121 #define MXC_F_SMON_EXTSCN_EXTS_EN3_POS 3 /**< EXTSCN_EXTS_EN3 Position */ 122 #define MXC_F_SMON_EXTSCN_EXTS_EN3 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN3_POS)) /**< EXTSCN_EXTS_EN3 Mask */ 123 124 #define MXC_F_SMON_EXTSCN_EXTS_EN4_POS 4 /**< EXTSCN_EXTS_EN4 Position */ 125 #define MXC_F_SMON_EXTSCN_EXTS_EN4 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN4_POS)) /**< EXTSCN_EXTS_EN4 Mask */ 126 127 #define MXC_F_SMON_EXTSCN_EXTS_EN5_POS 5 /**< EXTSCN_EXTS_EN5 Position */ 128 #define MXC_F_SMON_EXTSCN_EXTS_EN5 ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_EXTS_EN5_POS)) /**< EXTSCN_EXTS_EN5 Mask */ 129 130 #define MXC_F_SMON_EXTSCN_EXTCNT_POS 16 /**< EXTSCN_EXTCNT Position */ 131 #define MXC_F_SMON_EXTSCN_EXTCNT ((uint32_t)(0x1FUL << MXC_F_SMON_EXTSCN_EXTCNT_POS)) /**< EXTSCN_EXTCNT Mask */ 132 133 #define MXC_F_SMON_EXTSCN_EXTFRQ_POS 21 /**< EXTSCN_EXTFRQ Position */ 134 #define MXC_F_SMON_EXTSCN_EXTFRQ ((uint32_t)(0x7UL << MXC_F_SMON_EXTSCN_EXTFRQ_POS)) /**< EXTSCN_EXTFRQ Mask */ 135 #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ2000HZ ((uint32_t)0x0UL) /**< EXTSCN_EXTFRQ_FREQ2000HZ Value */ 136 #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ2000HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ2000HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ2000HZ Setting */ 137 #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ1000HZ ((uint32_t)0x1UL) /**< EXTSCN_EXTFRQ_FREQ1000HZ Value */ 138 #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ1000HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ1000HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ1000HZ Setting */ 139 #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ500HZ ((uint32_t)0x2UL) /**< EXTSCN_EXTFRQ_FREQ500HZ Value */ 140 #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ500HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ500HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ500HZ Setting */ 141 #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ250HZ ((uint32_t)0x3UL) /**< EXTSCN_EXTFRQ_FREQ250HZ Value */ 142 #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ250HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ250HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ250HZ Setting */ 143 #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ125HZ ((uint32_t)0x4UL) /**< EXTSCN_EXTFRQ_FREQ125HZ Value */ 144 #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ125HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ125HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ125HZ Setting */ 145 #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ63HZ ((uint32_t)0x5UL) /**< EXTSCN_EXTFRQ_FREQ63HZ Value */ 146 #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ63HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ63HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ63HZ Setting */ 147 #define MXC_V_SMON_EXTSCN_EXTFRQ_FREQ31HZ ((uint32_t)0x6UL) /**< EXTSCN_EXTFRQ_FREQ31HZ Value */ 148 #define MXC_S_SMON_EXTSCN_EXTFRQ_FREQ31HZ (MXC_V_SMON_EXTSCN_EXTFRQ_FREQ31HZ << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_FREQ31HZ Setting */ 149 #define MXC_V_SMON_EXTSCN_EXTFRQ_RFU ((uint32_t)0x7UL) /**< EXTSCN_EXTFRQ_RFU Value */ 150 #define MXC_S_SMON_EXTSCN_EXTFRQ_RFU (MXC_V_SMON_EXTSCN_EXTFRQ_RFU << MXC_F_SMON_EXTSCN_EXTFRQ_POS) /**< EXTSCN_EXTFRQ_RFU Setting */ 151 152 #define MXC_F_SMON_EXTSCN_DIVCLK_POS 24 /**< EXTSCN_DIVCLK Position */ 153 #define MXC_F_SMON_EXTSCN_DIVCLK ((uint32_t)(0x7UL << MXC_F_SMON_EXTSCN_DIVCLK_POS)) /**< EXTSCN_DIVCLK Mask */ 154 #define MXC_V_SMON_EXTSCN_DIVCLK_DIV1 ((uint32_t)0x0UL) /**< EXTSCN_DIVCLK_DIV1 Value */ 155 #define MXC_S_SMON_EXTSCN_DIVCLK_DIV1 (MXC_V_SMON_EXTSCN_DIVCLK_DIV1 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV1 Setting */ 156 #define MXC_V_SMON_EXTSCN_DIVCLK_DIV2 ((uint32_t)0x1UL) /**< EXTSCN_DIVCLK_DIV2 Value */ 157 #define MXC_S_SMON_EXTSCN_DIVCLK_DIV2 (MXC_V_SMON_EXTSCN_DIVCLK_DIV2 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV2 Setting */ 158 #define MXC_V_SMON_EXTSCN_DIVCLK_DIV4 ((uint32_t)0x2UL) /**< EXTSCN_DIVCLK_DIV4 Value */ 159 #define MXC_S_SMON_EXTSCN_DIVCLK_DIV4 (MXC_V_SMON_EXTSCN_DIVCLK_DIV4 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV4 Setting */ 160 #define MXC_V_SMON_EXTSCN_DIVCLK_DIV8 ((uint32_t)0x3UL) /**< EXTSCN_DIVCLK_DIV8 Value */ 161 #define MXC_S_SMON_EXTSCN_DIVCLK_DIV8 (MXC_V_SMON_EXTSCN_DIVCLK_DIV8 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV8 Setting */ 162 #define MXC_V_SMON_EXTSCN_DIVCLK_DIV16 ((uint32_t)0x4UL) /**< EXTSCN_DIVCLK_DIV16 Value */ 163 #define MXC_S_SMON_EXTSCN_DIVCLK_DIV16 (MXC_V_SMON_EXTSCN_DIVCLK_DIV16 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV16 Setting */ 164 #define MXC_V_SMON_EXTSCN_DIVCLK_DIV32 ((uint32_t)0x5UL) /**< EXTSCN_DIVCLK_DIV32 Value */ 165 #define MXC_S_SMON_EXTSCN_DIVCLK_DIV32 (MXC_V_SMON_EXTSCN_DIVCLK_DIV32 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV32 Setting */ 166 #define MXC_V_SMON_EXTSCN_DIVCLK_DIV64 ((uint32_t)0x6UL) /**< EXTSCN_DIVCLK_DIV64 Value */ 167 #define MXC_S_SMON_EXTSCN_DIVCLK_DIV64 (MXC_V_SMON_EXTSCN_DIVCLK_DIV64 << MXC_F_SMON_EXTSCN_DIVCLK_POS) /**< EXTSCN_DIVCLK_DIV64 Setting */ 168 169 #define MXC_F_SMON_EXTSCN_BUSY_POS 30 /**< EXTSCN_BUSY Position */ 170 #define MXC_F_SMON_EXTSCN_BUSY ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_BUSY_POS)) /**< EXTSCN_BUSY Mask */ 171 172 #define MXC_F_SMON_EXTSCN_LOCK_POS 31 /**< EXTSCN_LOCK Position */ 173 #define MXC_F_SMON_EXTSCN_LOCK ((uint32_t)(0x1UL << MXC_F_SMON_EXTSCN_LOCK_POS)) /**< EXTSCN_LOCK Mask */ 174 175 /**@} end of group SMON_EXTSCN_Register */ 176 177 /** 178 * @ingroup smon_registers 179 * @defgroup SMON_INTSCN SMON_INTSCN 180 * @brief Internal Sensor Control Register. 181 * @{ 182 */ 183 #define MXC_F_SMON_INTSCN_SHIELD_EN_POS 0 /**< INTSCN_SHIELD_EN Position */ 184 #define MXC_F_SMON_INTSCN_SHIELD_EN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_SHIELD_EN_POS)) /**< INTSCN_SHIELD_EN Mask */ 185 186 #define MXC_F_SMON_INTSCN_TEMP_EN_POS 1 /**< INTSCN_TEMP_EN Position */ 187 #define MXC_F_SMON_INTSCN_TEMP_EN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_TEMP_EN_POS)) /**< INTSCN_TEMP_EN Mask */ 188 189 #define MXC_F_SMON_INTSCN_VBAT_EN_POS 2 /**< INTSCN_VBAT_EN Position */ 190 #define MXC_F_SMON_INTSCN_VBAT_EN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VBAT_EN_POS)) /**< INTSCN_VBAT_EN Mask */ 191 192 #define MXC_F_SMON_INTSCN_DFD_EN_POS 3 /**< INTSCN_DFD_EN Position */ 193 #define MXC_F_SMON_INTSCN_DFD_EN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_DFD_EN_POS)) /**< INTSCN_DFD_EN Mask */ 194 195 #define MXC_F_SMON_INTSCN_DFD_NMI_POS 4 /**< INTSCN_DFD_NMI Position */ 196 #define MXC_F_SMON_INTSCN_DFD_NMI ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_DFD_NMI_POS)) /**< INTSCN_DFD_NMI Mask */ 197 198 #define MXC_F_SMON_INTSCN_DFD_STDBY_POS 8 /**< INTSCN_DFD_STDBY Position */ 199 #define MXC_F_SMON_INTSCN_DFD_STDBY ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_DFD_STDBY_POS)) /**< INTSCN_DFD_STDBY Mask */ 200 201 #define MXC_F_SMON_INTSCN_PUF_TRIM_ERASE_POS 10 /**< INTSCN_PUF_TRIM_ERASE Position */ 202 #define MXC_F_SMON_INTSCN_PUF_TRIM_ERASE ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_PUF_TRIM_ERASE_POS)) /**< INTSCN_PUF_TRIM_ERASE Mask */ 203 204 #define MXC_F_SMON_INTSCN_LOTEMP_SEL_POS 16 /**< INTSCN_LOTEMP_SEL Position */ 205 #define MXC_F_SMON_INTSCN_LOTEMP_SEL ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_LOTEMP_SEL_POS)) /**< INTSCN_LOTEMP_SEL Mask */ 206 207 #define MXC_F_SMON_INTSCN_VCORELOEN_POS 18 /**< INTSCN_VCORELOEN Position */ 208 #define MXC_F_SMON_INTSCN_VCORELOEN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VCORELOEN_POS)) /**< INTSCN_VCORELOEN Mask */ 209 210 #define MXC_F_SMON_INTSCN_VCOREHIEN_POS 19 /**< INTSCN_VCOREHIEN Position */ 211 #define MXC_F_SMON_INTSCN_VCOREHIEN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VCOREHIEN_POS)) /**< INTSCN_VCOREHIEN Mask */ 212 213 #define MXC_F_SMON_INTSCN_VDDLOEN_POS 20 /**< INTSCN_VDDLOEN Position */ 214 #define MXC_F_SMON_INTSCN_VDDLOEN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VDDLOEN_POS)) /**< INTSCN_VDDLOEN Mask */ 215 216 #define MXC_F_SMON_INTSCN_VDDHIEN_POS 21 /**< INTSCN_VDDHIEN Position */ 217 #define MXC_F_SMON_INTSCN_VDDHIEN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VDDHIEN_POS)) /**< INTSCN_VDDHIEN Mask */ 218 219 #define MXC_F_SMON_INTSCN_VGLEN_POS 22 /**< INTSCN_VGLEN Position */ 220 #define MXC_F_SMON_INTSCN_VGLEN ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_VGLEN_POS)) /**< INTSCN_VGLEN Mask */ 221 222 #define MXC_F_SMON_INTSCN_LOCK_POS 31 /**< INTSCN_LOCK Position */ 223 #define MXC_F_SMON_INTSCN_LOCK ((uint32_t)(0x1UL << MXC_F_SMON_INTSCN_LOCK_POS)) /**< INTSCN_LOCK Mask */ 224 225 /**@} end of group SMON_INTSCN_Register */ 226 227 /** 228 * @ingroup smon_registers 229 * @defgroup SMON_SECALM SMON_SECALM 230 * @brief Security Alarm Register. 231 * @{ 232 */ 233 #define MXC_F_SMON_SECALM_DRS_POS 0 /**< SECALM_DRS Position */ 234 #define MXC_F_SMON_SECALM_DRS ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_DRS_POS)) /**< SECALM_DRS Mask */ 235 236 #define MXC_F_SMON_SECALM_KEYWIPE_POS 1 /**< SECALM_KEYWIPE Position */ 237 #define MXC_F_SMON_SECALM_KEYWIPE ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_KEYWIPE_POS)) /**< SECALM_KEYWIPE Mask */ 238 239 #define MXC_F_SMON_SECALM_SHIELDF_POS 2 /**< SECALM_SHIELDF Position */ 240 #define MXC_F_SMON_SECALM_SHIELDF ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_SHIELDF_POS)) /**< SECALM_SHIELDF Mask */ 241 242 #define MXC_F_SMON_SECALM_LOTEMP_POS 3 /**< SECALM_LOTEMP Position */ 243 #define MXC_F_SMON_SECALM_LOTEMP ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_LOTEMP_POS)) /**< SECALM_LOTEMP Mask */ 244 245 #define MXC_F_SMON_SECALM_HITEMP_POS 4 /**< SECALM_HITEMP Position */ 246 #define MXC_F_SMON_SECALM_HITEMP ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_HITEMP_POS)) /**< SECALM_HITEMP Mask */ 247 248 #define MXC_F_SMON_SECALM_BATLO_POS 5 /**< SECALM_BATLO Position */ 249 #define MXC_F_SMON_SECALM_BATLO ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_BATLO_POS)) /**< SECALM_BATLO Mask */ 250 251 #define MXC_F_SMON_SECALM_BATHI_POS 6 /**< SECALM_BATHI Position */ 252 #define MXC_F_SMON_SECALM_BATHI ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_BATHI_POS)) /**< SECALM_BATHI Mask */ 253 254 #define MXC_F_SMON_SECALM_EXTF_POS 7 /**< SECALM_EXTF Position */ 255 #define MXC_F_SMON_SECALM_EXTF ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTF_POS)) /**< SECALM_EXTF Mask */ 256 257 #define MXC_F_SMON_SECALM_VDDLO_POS 8 /**< SECALM_VDDLO Position */ 258 #define MXC_F_SMON_SECALM_VDDLO ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VDDLO_POS)) /**< SECALM_VDDLO Mask */ 259 260 #define MXC_F_SMON_SECALM_VCORELO_POS 9 /**< SECALM_VCORELO Position */ 261 #define MXC_F_SMON_SECALM_VCORELO ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VCORELO_POS)) /**< SECALM_VCORELO Mask */ 262 263 #define MXC_F_SMON_SECALM_VCOREHI_POS 10 /**< SECALM_VCOREHI Position */ 264 #define MXC_F_SMON_SECALM_VCOREHI ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VCOREHI_POS)) /**< SECALM_VCOREHI Mask */ 265 266 #define MXC_F_SMON_SECALM_VDDHI_POS 11 /**< SECALM_VDDHI Position */ 267 #define MXC_F_SMON_SECALM_VDDHI ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VDDHI_POS)) /**< SECALM_VDDHI Mask */ 268 269 #define MXC_F_SMON_SECALM_VGL_POS 12 /**< SECALM_VGL Position */ 270 #define MXC_F_SMON_SECALM_VGL ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_VGL_POS)) /**< SECALM_VGL Mask */ 271 272 #define MXC_F_SMON_SECALM_EXTSTAT0_POS 16 /**< SECALM_EXTSTAT0 Position */ 273 #define MXC_F_SMON_SECALM_EXTSTAT0 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT0_POS)) /**< SECALM_EXTSTAT0 Mask */ 274 275 #define MXC_F_SMON_SECALM_EXTSTAT1_POS 17 /**< SECALM_EXTSTAT1 Position */ 276 #define MXC_F_SMON_SECALM_EXTSTAT1 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT1_POS)) /**< SECALM_EXTSTAT1 Mask */ 277 278 #define MXC_F_SMON_SECALM_EXTSTAT2_POS 18 /**< SECALM_EXTSTAT2 Position */ 279 #define MXC_F_SMON_SECALM_EXTSTAT2 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT2_POS)) /**< SECALM_EXTSTAT2 Mask */ 280 281 #define MXC_F_SMON_SECALM_EXTSTAT3_POS 19 /**< SECALM_EXTSTAT3 Position */ 282 #define MXC_F_SMON_SECALM_EXTSTAT3 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT3_POS)) /**< SECALM_EXTSTAT3 Mask */ 283 284 #define MXC_F_SMON_SECALM_EXTSTAT4_POS 20 /**< SECALM_EXTSTAT4 Position */ 285 #define MXC_F_SMON_SECALM_EXTSTAT4 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT4_POS)) /**< SECALM_EXTSTAT4 Mask */ 286 287 #define MXC_F_SMON_SECALM_EXTSTAT5_POS 21 /**< SECALM_EXTSTAT5 Position */ 288 #define MXC_F_SMON_SECALM_EXTSTAT5 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSTAT5_POS)) /**< SECALM_EXTSTAT5 Mask */ 289 290 #define MXC_F_SMON_SECALM_EXTSWARN0_POS 24 /**< SECALM_EXTSWARN0 Position */ 291 #define MXC_F_SMON_SECALM_EXTSWARN0 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN0_POS)) /**< SECALM_EXTSWARN0 Mask */ 292 293 #define MXC_F_SMON_SECALM_EXTSWARN1_POS 25 /**< SECALM_EXTSWARN1 Position */ 294 #define MXC_F_SMON_SECALM_EXTSWARN1 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN1_POS)) /**< SECALM_EXTSWARN1 Mask */ 295 296 #define MXC_F_SMON_SECALM_EXTSWARN2_POS 26 /**< SECALM_EXTSWARN2 Position */ 297 #define MXC_F_SMON_SECALM_EXTSWARN2 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN2_POS)) /**< SECALM_EXTSWARN2 Mask */ 298 299 #define MXC_F_SMON_SECALM_EXTSWARN3_POS 27 /**< SECALM_EXTSWARN3 Position */ 300 #define MXC_F_SMON_SECALM_EXTSWARN3 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN3_POS)) /**< SECALM_EXTSWARN3 Mask */ 301 302 #define MXC_F_SMON_SECALM_EXTSWARN4_POS 28 /**< SECALM_EXTSWARN4 Position */ 303 #define MXC_F_SMON_SECALM_EXTSWARN4 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN4_POS)) /**< SECALM_EXTSWARN4 Mask */ 304 305 #define MXC_F_SMON_SECALM_EXTSWARN5_POS 29 /**< SECALM_EXTSWARN5 Position */ 306 #define MXC_F_SMON_SECALM_EXTSWARN5 ((uint32_t)(0x1UL << MXC_F_SMON_SECALM_EXTSWARN5_POS)) /**< SECALM_EXTSWARN5 Mask */ 307 308 /**@} end of group SMON_SECALM_Register */ 309 310 /** 311 * @ingroup smon_registers 312 * @defgroup SMON_SECDIAG SMON_SECDIAG 313 * @brief Security Diagnostic Register. 314 * @{ 315 */ 316 #define MXC_F_SMON_SECDIAG_BORF_POS 0 /**< SECDIAG_BORF Position */ 317 #define MXC_F_SMON_SECDIAG_BORF ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_BORF_POS)) /**< SECDIAG_BORF Mask */ 318 319 #define MXC_F_SMON_SECDIAG_SHIELDF_POS 2 /**< SECDIAG_SHIELDF Position */ 320 #define MXC_F_SMON_SECDIAG_SHIELDF ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_SHIELDF_POS)) /**< SECDIAG_SHIELDF Mask */ 321 322 #define MXC_F_SMON_SECDIAG_LOTEMP_POS 3 /**< SECDIAG_LOTEMP Position */ 323 #define MXC_F_SMON_SECDIAG_LOTEMP ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_LOTEMP_POS)) /**< SECDIAG_LOTEMP Mask */ 324 325 #define MXC_F_SMON_SECDIAG_HITEMP_POS 4 /**< SECDIAG_HITEMP Position */ 326 #define MXC_F_SMON_SECDIAG_HITEMP ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_HITEMP_POS)) /**< SECDIAG_HITEMP Mask */ 327 328 #define MXC_F_SMON_SECDIAG_BATLO_POS 5 /**< SECDIAG_BATLO Position */ 329 #define MXC_F_SMON_SECDIAG_BATLO ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_BATLO_POS)) /**< SECDIAG_BATLO Mask */ 330 331 #define MXC_F_SMON_SECDIAG_BATHI_POS 6 /**< SECDIAG_BATHI Position */ 332 #define MXC_F_SMON_SECDIAG_BATHI ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_BATHI_POS)) /**< SECDIAG_BATHI Mask */ 333 334 #define MXC_F_SMON_SECDIAG_DYNF_POS 7 /**< SECDIAG_DYNF Position */ 335 #define MXC_F_SMON_SECDIAG_DYNF ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_DYNF_POS)) /**< SECDIAG_DYNF Mask */ 336 337 #define MXC_F_SMON_SECDIAG_AESKT_POS 8 /**< SECDIAG_AESKT Position */ 338 #define MXC_F_SMON_SECDIAG_AESKT ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_AESKT_POS)) /**< SECDIAG_AESKT Mask */ 339 340 #define MXC_F_SMON_SECDIAG_EXTSTAT0_POS 16 /**< SECDIAG_EXTSTAT0 Position */ 341 #define MXC_F_SMON_SECDIAG_EXTSTAT0 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT0_POS)) /**< SECDIAG_EXTSTAT0 Mask */ 342 343 #define MXC_F_SMON_SECDIAG_EXTSTAT1_POS 17 /**< SECDIAG_EXTSTAT1 Position */ 344 #define MXC_F_SMON_SECDIAG_EXTSTAT1 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT1_POS)) /**< SECDIAG_EXTSTAT1 Mask */ 345 346 #define MXC_F_SMON_SECDIAG_EXTSTAT2_POS 18 /**< SECDIAG_EXTSTAT2 Position */ 347 #define MXC_F_SMON_SECDIAG_EXTSTAT2 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT2_POS)) /**< SECDIAG_EXTSTAT2 Mask */ 348 349 #define MXC_F_SMON_SECDIAG_EXTSTAT3_POS 19 /**< SECDIAG_EXTSTAT3 Position */ 350 #define MXC_F_SMON_SECDIAG_EXTSTAT3 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT3_POS)) /**< SECDIAG_EXTSTAT3 Mask */ 351 352 #define MXC_F_SMON_SECDIAG_EXTSTAT4_POS 20 /**< SECDIAG_EXTSTAT4 Position */ 353 #define MXC_F_SMON_SECDIAG_EXTSTAT4 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT4_POS)) /**< SECDIAG_EXTSTAT4 Mask */ 354 355 #define MXC_F_SMON_SECDIAG_EXTSTAT5_POS 21 /**< SECDIAG_EXTSTAT5 Position */ 356 #define MXC_F_SMON_SECDIAG_EXTSTAT5 ((uint32_t)(0x1UL << MXC_F_SMON_SECDIAG_EXTSTAT5_POS)) /**< SECDIAG_EXTSTAT5 Mask */ 357 358 /**@} end of group SMON_SECDIAG_Register */ 359 360 /** 361 * @ingroup smon_registers 362 * @defgroup SMON_DLRTC SMON_DLRTC 363 * @brief DRS Log RTC Value. This register contains the 32 bit value in the RTC second 364 * register when the last DRS event occurred. 365 * @{ 366 */ 367 #define MXC_F_SMON_DLRTC_DLRTC_POS 0 /**< DLRTC_DLRTC Position */ 368 #define MXC_F_SMON_DLRTC_DLRTC ((uint32_t)(0xFFFFFFFFUL << MXC_F_SMON_DLRTC_DLRTC_POS)) /**< DLRTC_DLRTC Mask */ 369 370 /**@} end of group SMON_DLRTC_Register */ 371 372 /** 373 * @ingroup smon_registers 374 * @defgroup SMON_MEUCFG SMON_MEUCFG 375 * @brief MEU Configuration 376 * @{ 377 */ 378 #define MXC_F_SMON_MEUCFG_MEUCFG_POS 0 /**< MEUCFG_MEUCFG Position */ 379 #define MXC_F_SMON_MEUCFG_MEUCFG ((uint32_t)(0x7FUL << MXC_F_SMON_MEUCFG_MEUCFG_POS)) /**< MEUCFG_MEUCFG Mask */ 380 381 /**@} end of group SMON_MEUCFG_Register */ 382 383 /** 384 * @ingroup smon_registers 385 * @defgroup SMON_SECST SMON_SECST 386 * @brief Security Monitor Status Register. 387 * @{ 388 */ 389 #define MXC_F_SMON_SECST_EXTSRS_POS 0 /**< SECST_EXTSRS Position */ 390 #define MXC_F_SMON_SECST_EXTSRS ((uint32_t)(0x1UL << MXC_F_SMON_SECST_EXTSRS_POS)) /**< SECST_EXTSRS Mask */ 391 392 #define MXC_F_SMON_SECST_INTSRS_POS 1 /**< SECST_INTSRS Position */ 393 #define MXC_F_SMON_SECST_INTSRS ((uint32_t)(0x1UL << MXC_F_SMON_SECST_INTSRS_POS)) /**< SECST_INTSRS Mask */ 394 395 #define MXC_F_SMON_SECST_SECALRS_POS 2 /**< SECST_SECALRS Position */ 396 #define MXC_F_SMON_SECST_SECALRS ((uint32_t)(0x1UL << MXC_F_SMON_SECST_SECALRS_POS)) /**< SECST_SECALRS Mask */ 397 398 /**@} end of group SMON_SECST_Register */ 399 400 /** 401 * @ingroup smon_registers 402 * @defgroup SMON_SDBE SMON_SDBE 403 * @brief Security Monitor Self Destruct Byte. 404 * @{ 405 */ 406 #define MXC_F_SMON_SDBE_DBYTE_POS 0 /**< SDBE_DBYTE Position */ 407 #define MXC_F_SMON_SDBE_DBYTE ((uint32_t)(0xFFUL << MXC_F_SMON_SDBE_DBYTE_POS)) /**< SDBE_DBYTE Mask */ 408 409 #define MXC_F_SMON_SDBE_SBDEN_POS 31 /**< SDBE_SBDEN Position */ 410 #define MXC_F_SMON_SDBE_SBDEN ((uint32_t)(0x1UL << MXC_F_SMON_SDBE_SBDEN_POS)) /**< SDBE_SBDEN Mask */ 411 412 /**@} end of group SMON_SDBE_Register */ 413 414 #ifdef __cplusplus 415 } 416 #endif 417 418 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_SMON_REGS_H_ 419
