1 /** 2 * @file pwrseq_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup pwrseq_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_PWRSEQ_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_PWRSEQ_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup pwrseq 67 * @defgroup pwrseq_registers PWRSEQ_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module. 69 * @details Power Sequencer / Low Power Control Register. 70 */ 71 72 /** 73 * @ingroup pwrseq_registers 74 * Structure type to access the PWRSEQ Registers. 75 */ 76 typedef struct { 77 __IO uint32_t lpcn; /**< <tt>\b 0x00:</tt> PWRSEQ LPCN Register */ 78 __IO uint32_t lpwkst0; /**< <tt>\b 0x04:</tt> PWRSEQ LPWKST0 Register */ 79 __IO uint32_t lpwken0; /**< <tt>\b 0x08:</tt> PWRSEQ LPWKEN0 Register */ 80 __IO uint32_t lpwkst1; /**< <tt>\b 0x0C:</tt> PWRSEQ LPWKST1 Register */ 81 __IO uint32_t lpwken1; /**< <tt>\b 0x10:</tt> PWRSEQ LPWKEN1 Register */ 82 __R uint32_t rsv_0x14_0x2f[7]; 83 __IO uint32_t lppwst; /**< <tt>\b 0x30:</tt> PWRSEQ LPPWST Register */ 84 __IO uint32_t lppwen; /**< <tt>\b 0x34:</tt> PWRSEQ LPPWEN Register */ 85 __R uint32_t rsv_0x38_0x3f[2]; 86 __IO uint32_t lpmemsd; /**< <tt>\b 0x40:</tt> PWRSEQ LPMEMSD Register */ 87 __IO uint32_t lpvddpd; /**< <tt>\b 0x44:</tt> PWRSEQ LPVDDPD Register */ 88 __IO uint32_t buretvec; /**< <tt>\b 0x48:</tt> PWRSEQ BURETVEC Register */ 89 __IO uint32_t buaod; /**< <tt>\b 0x4C:</tt> PWRSEQ BUAOD Register */ 90 } mxc_pwrseq_regs_t; 91 92 /* Register offsets for module PWRSEQ */ 93 /** 94 * @ingroup pwrseq_registers 95 * @defgroup PWRSEQ_Register_Offsets Register Offsets 96 * @brief PWRSEQ Peripheral Register Offsets from the PWRSEQ Base Peripheral Address. 97 * @{ 98 */ 99 #define MXC_R_PWRSEQ_LPCN ((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0000</tt> */ 100 #define MXC_R_PWRSEQ_LPWKST0 ((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0004</tt> */ 101 #define MXC_R_PWRSEQ_LPWKEN0 ((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0008</tt> */ 102 #define MXC_R_PWRSEQ_LPWKST1 ((uint32_t)0x0000000CUL) /**< Offset from PWRSEQ Base Address: <tt> 0x000C</tt> */ 103 #define MXC_R_PWRSEQ_LPWKEN1 ((uint32_t)0x00000010UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0010</tt> */ 104 #define MXC_R_PWRSEQ_LPPWST ((uint32_t)0x00000030UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0030</tt> */ 105 #define MXC_R_PWRSEQ_LPPWEN ((uint32_t)0x00000034UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0034</tt> */ 106 #define MXC_R_PWRSEQ_LPMEMSD ((uint32_t)0x00000040UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0040</tt> */ 107 #define MXC_R_PWRSEQ_LPVDDPD ((uint32_t)0x00000044UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0044</tt> */ 108 #define MXC_R_PWRSEQ_BURETVEC ((uint32_t)0x00000048UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0048</tt> */ 109 #define MXC_R_PWRSEQ_BUAOD ((uint32_t)0x0000004CUL) /**< Offset from PWRSEQ Base Address: <tt> 0x004C</tt> */ 110 /**@} end of group pwrseq_registers */ 111 112 /** 113 * @ingroup pwrseq_registers 114 * @defgroup PWRSEQ_LPCN PWRSEQ_LPCN 115 * @brief Low Power Control Register. 116 * @{ 117 */ 118 #define MXC_F_PWRSEQ_LPCN_RAMRET_POS 0 /**< LPCN_RAMRET Position */ 119 #define MXC_F_PWRSEQ_LPCN_RAMRET ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPCN_RAMRET_POS)) /**< LPCN_RAMRET Mask */ 120 #define MXC_V_PWRSEQ_LPCN_RAMRET_DIS ((uint32_t)0x0UL) /**< LPCN_RAMRET_DIS Value */ 121 #define MXC_S_PWRSEQ_LPCN_RAMRET_DIS (MXC_V_PWRSEQ_LPCN_RAMRET_DIS << MXC_F_PWRSEQ_LPCN_RAMRET_POS) /**< LPCN_RAMRET_DIS Setting */ 122 #define MXC_V_PWRSEQ_LPCN_RAMRET_EN1 ((uint32_t)0x1UL) /**< LPCN_RAMRET_EN1 Value */ 123 #define MXC_S_PWRSEQ_LPCN_RAMRET_EN1 (MXC_V_PWRSEQ_LPCN_RAMRET_EN1 << MXC_F_PWRSEQ_LPCN_RAMRET_POS) /**< LPCN_RAMRET_EN1 Setting */ 124 #define MXC_V_PWRSEQ_LPCN_RAMRET_EN2 ((uint32_t)0x2UL) /**< LPCN_RAMRET_EN2 Value */ 125 #define MXC_S_PWRSEQ_LPCN_RAMRET_EN2 (MXC_V_PWRSEQ_LPCN_RAMRET_EN2 << MXC_F_PWRSEQ_LPCN_RAMRET_POS) /**< LPCN_RAMRET_EN2 Setting */ 126 #define MXC_V_PWRSEQ_LPCN_RAMRET_EN3 ((uint32_t)0x3UL) /**< LPCN_RAMRET_EN3 Value */ 127 #define MXC_S_PWRSEQ_LPCN_RAMRET_EN3 (MXC_V_PWRSEQ_LPCN_RAMRET_EN3 << MXC_F_PWRSEQ_LPCN_RAMRET_POS) /**< LPCN_RAMRET_EN3 Setting */ 128 129 #define MXC_F_PWRSEQ_LPCN_BCKGRND_POS 9 /**< LPCN_BCKGRND Position */ 130 #define MXC_F_PWRSEQ_LPCN_BCKGRND ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_BCKGRND_POS)) /**< LPCN_BCKGRND Mask */ 131 132 #define MXC_F_PWRSEQ_LPCN_FWKM_POS 10 /**< LPCN_FWKM Position */ 133 #define MXC_F_PWRSEQ_LPCN_FWKM ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_FWKM_POS)) /**< LPCN_FWKM Mask */ 134 135 #define MXC_F_PWRSEQ_LPCN_BGOFF_POS 11 /**< LPCN_BGOFF Position */ 136 #define MXC_F_PWRSEQ_LPCN_BGOFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_BGOFF_POS)) /**< LPCN_BGOFF Mask */ 137 138 #define MXC_F_PWRSEQ_LPCN_VCOREMD_POS 20 /**< LPCN_VCOREMD Position */ 139 #define MXC_F_PWRSEQ_LPCN_VCOREMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCOREMD_POS)) /**< LPCN_VCOREMD Mask */ 140 141 #define MXC_F_PWRSEQ_LPCN_VREGIMD_POS 21 /**< LPCN_VREGIMD Position */ 142 #define MXC_F_PWRSEQ_LPCN_VREGIMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VREGIMD_POS)) /**< LPCN_VREGIMD Mask */ 143 144 #define MXC_F_PWRSEQ_LPCN_VDDAMD_POS 22 /**< LPCN_VDDAMD Position */ 145 #define MXC_F_PWRSEQ_LPCN_VDDAMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDAMD_POS)) /**< LPCN_VDDAMD Mask */ 146 147 #define MXC_F_PWRSEQ_LPCN_VDDIOMD_POS 23 /**< LPCN_VDDIOMD Position */ 148 #define MXC_F_PWRSEQ_LPCN_VDDIOMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDIOMD_POS)) /**< LPCN_VDDIOMD Mask */ 149 150 #define MXC_F_PWRSEQ_LPCN_VDDIOHMD_POS 24 /**< LPCN_VDDIOHMD Position */ 151 #define MXC_F_PWRSEQ_LPCN_VDDIOHMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDIOHMD_POS)) /**< LPCN_VDDIOHMD Mask */ 152 153 #define MXC_F_PWRSEQ_LPCN_PORVDDIOMD_POS 25 /**< LPCN_PORVDDIOMD Position */ 154 #define MXC_F_PWRSEQ_LPCN_PORVDDIOMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_PORVDDIOMD_POS)) /**< LPCN_PORVDDIOMD Mask */ 155 156 #define MXC_F_PWRSEQ_LPCN_PORVDDIOHMD_POS 26 /**< LPCN_PORVDDIOHMD Position */ 157 #define MXC_F_PWRSEQ_LPCN_PORVDDIOHMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_PORVDDIOHMD_POS)) /**< LPCN_PORVDDIOHMD Mask */ 158 159 #define MXC_F_PWRSEQ_LPCN_VDDBMD_POS 27 /**< LPCN_VDDBMD Position */ 160 #define MXC_F_PWRSEQ_LPCN_VDDBMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDBMD_POS)) /**< LPCN_VDDBMD Mask */ 161 162 #define MXC_F_PWRSEQ_LPCN_VRXOUTMD_POS 28 /**< LPCN_VRXOUTMD Position */ 163 #define MXC_F_PWRSEQ_LPCN_VRXOUTMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VRXOUTMD_POS)) /**< LPCN_VRXOUTMD Mask */ 164 165 #define MXC_F_PWRSEQ_LPCN_VTXOUTMD_POS 29 /**< LPCN_VTXOUTMD Position */ 166 #define MXC_F_PWRSEQ_LPCN_VTXOUTMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VTXOUTMD_POS)) /**< LPCN_VTXOUTMD Mask */ 167 168 #define MXC_F_PWRSEQ_LPCN_PDOWNDSLEN_POS 30 /**< LPCN_PDOWNDSLEN Position */ 169 #define MXC_F_PWRSEQ_LPCN_PDOWNDSLEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_PDOWNDSLEN_POS)) /**< LPCN_PDOWNDSLEN Mask */ 170 171 /**@} end of group PWRSEQ_LPCN_Register */ 172 173 /** 174 * @ingroup pwrseq_registers 175 * @defgroup PWRSEQ_LPWKST0 PWRSEQ_LPWKST0 176 * @brief Low Power I/O Wakeup Status Register 0. This register indicates the low power 177 * wakeup status for GPIO0. 178 * @{ 179 */ 180 #define MXC_F_PWRSEQ_LPWKST0_WAKEST_POS 0 /**< LPWKST0_WAKEST Position */ 181 #define MXC_F_PWRSEQ_LPWKST0_WAKEST ((uint32_t)(0xFFFFFFFFUL << MXC_F_PWRSEQ_LPWKST0_WAKEST_POS)) /**< LPWKST0_WAKEST Mask */ 182 183 /**@} end of group PWRSEQ_LPWKST0_Register */ 184 185 /** 186 * @ingroup pwrseq_registers 187 * @defgroup PWRSEQ_LPWKEN0 PWRSEQ_LPWKEN0 188 * @brief Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup 189 * functionality for GPIO0. 190 * @{ 191 */ 192 #define MXC_F_PWRSEQ_LPWKEN0_WAKEEN_POS 0 /**< LPWKEN0_WAKEEN Position */ 193 #define MXC_F_PWRSEQ_LPWKEN0_WAKEEN ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRSEQ_LPWKEN0_WAKEEN_POS)) /**< LPWKEN0_WAKEEN Mask */ 194 195 /**@} end of group PWRSEQ_LPWKEN0_Register */ 196 197 /** 198 * @ingroup pwrseq_registers 199 * @defgroup PWRSEQ_LPWKST1 PWRSEQ_LPWKST1 200 * @brief Low Power I/O Wakeup Status Register 1. This register indicates the low power 201 * wakeup status for GPIO1. 202 * @{ 203 */ 204 #define MXC_F_PWRSEQ_LPWKST1_WAKEST_POS 0 /**< LPWKST1_WAKEST Position */ 205 #define MXC_F_PWRSEQ_LPWKST1_WAKEST ((uint32_t)(0x3FFFFUL << MXC_F_PWRSEQ_LPWKST1_WAKEST_POS)) /**< LPWKST1_WAKEST Mask */ 206 207 /**@} end of group PWRSEQ_LPWKST1_Register */ 208 209 /** 210 * @ingroup pwrseq_registers 211 * @defgroup PWRSEQ_LPWKEN1 PWRSEQ_LPWKEN1 212 * @brief Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup 213 * functionality for GPIO1. 214 * @{ 215 */ 216 #define MXC_F_PWRSEQ_LPWKEN1_WAKEEN_POS 0 /**< LPWKEN1_WAKEEN Position */ 217 #define MXC_F_PWRSEQ_LPWKEN1_WAKEEN ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRSEQ_LPWKEN1_WAKEEN_POS)) /**< LPWKEN1_WAKEEN Mask */ 218 219 /**@} end of group PWRSEQ_LPWKEN1_Register */ 220 221 /** 222 * @ingroup pwrseq_registers 223 * @defgroup PWRSEQ_LPPWST PWRSEQ_LPPWST 224 * @brief Low Power Peripheral Wakeup Status Register. 225 * @{ 226 */ 227 #define MXC_F_PWRSEQ_LPPWST_USBLSWKST_POS 0 /**< LPPWST_USBLSWKST Position */ 228 #define MXC_F_PWRSEQ_LPPWST_USBLSWKST ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPPWST_USBLSWKST_POS)) /**< LPPWST_USBLSWKST Mask */ 229 230 #define MXC_F_PWRSEQ_LPPWST_USBVBUSWKST_POS 2 /**< LPPWST_USBVBUSWKST Position */ 231 #define MXC_F_PWRSEQ_LPPWST_USBVBUSWKST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_USBVBUSWKST_POS)) /**< LPPWST_USBVBUSWKST Mask */ 232 233 #define MXC_F_PWRSEQ_LPPWST_SDMAWKST_POS 3 /**< LPPWST_SDMAWKST Position */ 234 #define MXC_F_PWRSEQ_LPPWST_SDMAWKST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_SDMAWKST_POS)) /**< LPPWST_SDMAWKST Mask */ 235 236 #define MXC_F_PWRSEQ_LPPWST_AINCOMP0WKST_POS 4 /**< LPPWST_AINCOMP0WKST Position */ 237 #define MXC_F_PWRSEQ_LPPWST_AINCOMP0WKST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_AINCOMP0WKST_POS)) /**< LPPWST_AINCOMP0WKST Mask */ 238 239 #define MXC_F_PWRSEQ_LPPWST_AINCOMP1WKST_POS 5 /**< LPPWST_AINCOMP1WKST Position */ 240 #define MXC_F_PWRSEQ_LPPWST_AINCOMP1WKST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_AINCOMP1WKST_POS)) /**< LPPWST_AINCOMP1WKST Mask */ 241 242 #define MXC_F_PWRSEQ_LPPWST_AINCOMP2WKST_POS 6 /**< LPPWST_AINCOMP2WKST Position */ 243 #define MXC_F_PWRSEQ_LPPWST_AINCOMP2WKST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_AINCOMP2WKST_POS)) /**< LPPWST_AINCOMP2WKST Mask */ 244 245 #define MXC_F_PWRSEQ_LPPWST_AINCOMP3WKST_POS 7 /**< LPPWST_AINCOMP3WKST Position */ 246 #define MXC_F_PWRSEQ_LPPWST_AINCOMP3WKST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_AINCOMP3WKST_POS)) /**< LPPWST_AINCOMP3WKST Mask */ 247 248 #define MXC_F_PWRSEQ_LPPWST_AINCOMP0ST_POS 8 /**< LPPWST_AINCOMP0ST Position */ 249 #define MXC_F_PWRSEQ_LPPWST_AINCOMP0ST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_AINCOMP0ST_POS)) /**< LPPWST_AINCOMP0ST Mask */ 250 251 #define MXC_F_PWRSEQ_LPPWST_AINCOMP1ST_POS 9 /**< LPPWST_AINCOMP1ST Position */ 252 #define MXC_F_PWRSEQ_LPPWST_AINCOMP1ST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_AINCOMP1ST_POS)) /**< LPPWST_AINCOMP1ST Mask */ 253 254 #define MXC_F_PWRSEQ_LPPWST_AINCOMP2ST_POS 10 /**< LPPWST_AINCOMP2ST Position */ 255 #define MXC_F_PWRSEQ_LPPWST_AINCOMP2ST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_AINCOMP2ST_POS)) /**< LPPWST_AINCOMP2ST Mask */ 256 257 #define MXC_F_PWRSEQ_LPPWST_AINCOMP3ST_POS 11 /**< LPPWST_AINCOMP3ST Position */ 258 #define MXC_F_PWRSEQ_LPPWST_AINCOMP3ST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_AINCOMP3ST_POS)) /**< LPPWST_AINCOMP3ST Mask */ 259 260 #define MXC_F_PWRSEQ_LPPWST_BBMODEST_POS 16 /**< LPPWST_BBMODEST Position */ 261 #define MXC_F_PWRSEQ_LPPWST_BBMODEST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_BBMODEST_POS)) /**< LPPWST_BBMODEST Mask */ 262 263 #define MXC_F_PWRSEQ_LPPWST_RSTWKST_POS 17 /**< LPPWST_RSTWKST Position */ 264 #define MXC_F_PWRSEQ_LPPWST_RSTWKST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_RSTWKST_POS)) /**< LPPWST_RSTWKST Mask */ 265 266 /**@} end of group PWRSEQ_LPPWST_Register */ 267 268 /** 269 * @ingroup pwrseq_registers 270 * @defgroup PWRSEQ_LPPWEN PWRSEQ_LPPWEN 271 * @brief Low Power Peripheral Wakeup Enable Register. 272 * @{ 273 */ 274 #define MXC_F_PWRSEQ_LPPWEN_USBLSWKEN_POS 0 /**< LPPWEN_USBLSWKEN Position */ 275 #define MXC_F_PWRSEQ_LPPWEN_USBLSWKEN ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPPWEN_USBLSWKEN_POS)) /**< LPPWEN_USBLSWKEN Mask */ 276 277 #define MXC_F_PWRSEQ_LPPWEN_USBVBUSWKEN_POS 2 /**< LPPWEN_USBVBUSWKEN Position */ 278 #define MXC_F_PWRSEQ_LPPWEN_USBVBUSWKEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_USBVBUSWKEN_POS)) /**< LPPWEN_USBVBUSWKEN Mask */ 279 280 #define MXC_F_PWRSEQ_LPPWEN_SDMAWKEN_POS 3 /**< LPPWEN_SDMAWKEN Position */ 281 #define MXC_F_PWRSEQ_LPPWEN_SDMAWKEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_SDMAWKEN_POS)) /**< LPPWEN_SDMAWKEN Mask */ 282 283 #define MXC_F_PWRSEQ_LPPWEN_AINCOMP0WKEN_POS 4 /**< LPPWEN_AINCOMP0WKEN Position */ 284 #define MXC_F_PWRSEQ_LPPWEN_AINCOMP0WKEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_AINCOMP0WKEN_POS)) /**< LPPWEN_AINCOMP0WKEN Mask */ 285 286 #define MXC_F_PWRSEQ_LPPWEN_AINCOMP1WKEN_POS 5 /**< LPPWEN_AINCOMP1WKEN Position */ 287 #define MXC_F_PWRSEQ_LPPWEN_AINCOMP1WKEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_AINCOMP1WKEN_POS)) /**< LPPWEN_AINCOMP1WKEN Mask */ 288 289 #define MXC_F_PWRSEQ_LPPWEN_AINCOMP2WKEN_POS 6 /**< LPPWEN_AINCOMP2WKEN Position */ 290 #define MXC_F_PWRSEQ_LPPWEN_AINCOMP2WKEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_AINCOMP2WKEN_POS)) /**< LPPWEN_AINCOMP2WKEN Mask */ 291 292 #define MXC_F_PWRSEQ_LPPWEN_AINCOMP3WKEN_POS 7 /**< LPPWEN_AINCOMP3WKEN Position */ 293 #define MXC_F_PWRSEQ_LPPWEN_AINCOMP3WKEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_AINCOMP3WKEN_POS)) /**< LPPWEN_AINCOMP3WKEN Mask */ 294 295 /**@} end of group PWRSEQ_LPPWEN_Register */ 296 297 /** 298 * @ingroup pwrseq_registers 299 * @defgroup PWRSEQ_LPMEMSD PWRSEQ_LPMEMSD 300 * @brief Low Power Memory Shutdown Control. 301 * @{ 302 */ 303 #define MXC_F_PWRSEQ_LPMEMSD_SRAM0SD_POS 0 /**< LPMEMSD_SRAM0SD Position */ 304 #define MXC_F_PWRSEQ_LPMEMSD_SRAM0SD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM0SD_POS)) /**< LPMEMSD_SRAM0SD Mask */ 305 306 #define MXC_F_PWRSEQ_LPMEMSD_SRAM1SD_POS 1 /**< LPMEMSD_SRAM1SD Position */ 307 #define MXC_F_PWRSEQ_LPMEMSD_SRAM1SD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM1SD_POS)) /**< LPMEMSD_SRAM1SD Mask */ 308 309 #define MXC_F_PWRSEQ_LPMEMSD_SRAM2SD_POS 2 /**< LPMEMSD_SRAM2SD Position */ 310 #define MXC_F_PWRSEQ_LPMEMSD_SRAM2SD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM2SD_POS)) /**< LPMEMSD_SRAM2SD Mask */ 311 312 #define MXC_F_PWRSEQ_LPMEMSD_SRAM3SD_POS 3 /**< LPMEMSD_SRAM3SD Position */ 313 #define MXC_F_PWRSEQ_LPMEMSD_SRAM3SD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM3SD_POS)) /**< LPMEMSD_SRAM3SD Mask */ 314 315 #define MXC_F_PWRSEQ_LPMEMSD_SRAM4SD_POS 4 /**< LPMEMSD_SRAM4SD Position */ 316 #define MXC_F_PWRSEQ_LPMEMSD_SRAM4SD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM4SD_POS)) /**< LPMEMSD_SRAM4SD Mask */ 317 318 #define MXC_F_PWRSEQ_LPMEMSD_SRAM5SD_POS 5 /**< LPMEMSD_SRAM5SD Position */ 319 #define MXC_F_PWRSEQ_LPMEMSD_SRAM5SD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM5SD_POS)) /**< LPMEMSD_SRAM5SD Mask */ 320 321 #define MXC_F_PWRSEQ_LPMEMSD_ICACHESD_POS 7 /**< LPMEMSD_ICACHESD Position */ 322 #define MXC_F_PWRSEQ_LPMEMSD_ICACHESD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ICACHESD_POS)) /**< LPMEMSD_ICACHESD Mask */ 323 324 #define MXC_F_PWRSEQ_LPMEMSD_ICACHEXIPSD_POS 8 /**< LPMEMSD_ICACHEXIPSD Position */ 325 #define MXC_F_PWRSEQ_LPMEMSD_ICACHEXIPSD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ICACHEXIPSD_POS)) /**< LPMEMSD_ICACHEXIPSD Mask */ 326 327 #define MXC_F_PWRSEQ_LPMEMSD_SRCCSD_POS 9 /**< LPMEMSD_SRCCSD Position */ 328 #define MXC_F_PWRSEQ_LPMEMSD_SRCCSD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRCCSD_POS)) /**< LPMEMSD_SRCCSD Mask */ 329 330 #define MXC_F_PWRSEQ_LPMEMSD_CRYPTOSD_POS 10 /**< LPMEMSD_CRYPTOSD Position */ 331 #define MXC_F_PWRSEQ_LPMEMSD_CRYPTOSD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_CRYPTOSD_POS)) /**< LPMEMSD_CRYPTOSD Mask */ 332 333 #define MXC_F_PWRSEQ_LPMEMSD_USBFIFOSD_POS 11 /**< LPMEMSD_USBFIFOSD Position */ 334 #define MXC_F_PWRSEQ_LPMEMSD_USBFIFOSD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_USBFIFOSD_POS)) /**< LPMEMSD_USBFIFOSD Mask */ 335 336 #define MXC_F_PWRSEQ_LPMEMSD_ROMSD_POS 12 /**< LPMEMSD_ROMSD Position */ 337 #define MXC_F_PWRSEQ_LPMEMSD_ROMSD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ROMSD_POS)) /**< LPMEMSD_ROMSD Mask */ 338 339 #define MXC_F_PWRSEQ_LPMEMSD_ROM1SD_POS 13 /**< LPMEMSD_ROM1SD Position */ 340 #define MXC_F_PWRSEQ_LPMEMSD_ROM1SD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ROM1SD_POS)) /**< LPMEMSD_ROM1SD Mask */ 341 342 #define MXC_F_PWRSEQ_LPMEMSD_IC1SD_POS 14 /**< LPMEMSD_IC1SD Position */ 343 #define MXC_F_PWRSEQ_LPMEMSD_IC1SD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_IC1SD_POS)) /**< LPMEMSD_IC1SD Mask */ 344 345 /**@} end of group PWRSEQ_LPMEMSD_Register */ 346 347 /** 348 * @ingroup pwrseq_registers 349 * @defgroup PWRSEQ_LPVDDPD PWRSEQ_LPVDDPD 350 * @brief Low Power VDD Domain Power Down Control. 351 * @{ 352 */ 353 #define MXC_F_PWRSEQ_LPVDDPD_VREGOBPD_POS 0 /**< LPVDDPD_VREGOBPD Position */ 354 #define MXC_F_PWRSEQ_LPVDDPD_VREGOBPD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPVDDPD_VREGOBPD_POS)) /**< LPVDDPD_VREGOBPD Mask */ 355 356 #define MXC_F_PWRSEQ_LPVDDPD_VREGODPD_POS 1 /**< LPVDDPD_VREGODPD Position */ 357 #define MXC_F_PWRSEQ_LPVDDPD_VREGODPD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPVDDPD_VREGODPD_POS)) /**< LPVDDPD_VREGODPD Mask */ 358 359 #define MXC_F_PWRSEQ_LPVDDPD_VDD2PD_POS 8 /**< LPVDDPD_VDD2PD Position */ 360 #define MXC_F_PWRSEQ_LPVDDPD_VDD2PD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPVDDPD_VDD2PD_POS)) /**< LPVDDPD_VDD2PD Mask */ 361 362 #define MXC_F_PWRSEQ_LPVDDPD_VDD3PD_POS 9 /**< LPVDDPD_VDD3PD Position */ 363 #define MXC_F_PWRSEQ_LPVDDPD_VDD3PD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPVDDPD_VDD3PD_POS)) /**< LPVDDPD_VDD3PD Mask */ 364 365 #define MXC_F_PWRSEQ_LPVDDPD_VDD4PD_POS 10 /**< LPVDDPD_VDD4PD Position */ 366 #define MXC_F_PWRSEQ_LPVDDPD_VDD4PD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPVDDPD_VDD4PD_POS)) /**< LPVDDPD_VDD4PD Mask */ 367 368 #define MXC_F_PWRSEQ_LPVDDPD_VDD5PD_POS 11 /**< LPVDDPD_VDD5PD Position */ 369 #define MXC_F_PWRSEQ_LPVDDPD_VDD5PD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPVDDPD_VDD5PD_POS)) /**< LPVDDPD_VDD5PD Mask */ 370 371 /**@} end of group PWRSEQ_LPVDDPD_Register */ 372 373 /** 374 * @ingroup pwrseq_registers 375 * @defgroup PWRSEQ_BURETVEC PWRSEQ_BURETVEC 376 * @brief BACKUP Return Vector Register 377 * @{ 378 */ 379 #define MXC_F_PWRSEQ_BURETVEC_GPR0_POS 0 /**< BURETVEC_GPR0 Position */ 380 #define MXC_F_PWRSEQ_BURETVEC_GPR0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_PWRSEQ_BURETVEC_GPR0_POS)) /**< BURETVEC_GPR0 Mask */ 381 382 /**@} end of group PWRSEQ_BURETVEC_Register */ 383 384 /** 385 * @ingroup pwrseq_registers 386 * @defgroup PWRSEQ_BUAOD PWRSEQ_BUAOD 387 * @brief BACKUP AoD Register 388 * @{ 389 */ 390 #define MXC_F_PWRSEQ_BUAOD_GPR1_POS 0 /**< BUAOD_GPR1 Position */ 391 #define MXC_F_PWRSEQ_BUAOD_GPR1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_PWRSEQ_BUAOD_GPR1_POS)) /**< BUAOD_GPR1 Mask */ 392 393 /**@} end of group PWRSEQ_BUAOD_Register */ 394 395 #ifdef __cplusplus 396 } 397 #endif 398 399 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_PWRSEQ_REGS_H_ 400
