1 /** 2 * @file mcr_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the MCR Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup mcr_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_MCR_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_MCR_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup mcr 67 * @defgroup mcr_registers MCR_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the MCR Peripheral Module. 69 * @details Misc Control. 70 */ 71 72 /** 73 * @ingroup mcr_registers 74 * Structure type to access the MCR Registers. 75 */ 76 typedef struct { 77 __IO uint32_t eccen; /**< <tt>\b 0x00:</tt> MCR ECCEN Register */ 78 __IO uint32_t hirc96m; /**< <tt>\b 0x04:</tt> MCR HIRC96M Register */ 79 __IO uint32_t outen; /**< <tt>\b 0x08:</tt> MCR OUTEN Register */ 80 __IO uint32_t aincomp; /**< <tt>\b 0x0C:</tt> MCR AINCOMP Register */ 81 __IO uint32_t ctrl; /**< <tt>\b 0x10:</tt> MCR CTRL Register */ 82 } mxc_mcr_regs_t; 83 84 /* Register offsets for module MCR */ 85 /** 86 * @ingroup mcr_registers 87 * @defgroup MCR_Register_Offsets Register Offsets 88 * @brief MCR Peripheral Register Offsets from the MCR Base Peripheral Address. 89 * @{ 90 */ 91 #define MXC_R_MCR_ECCEN ((uint32_t)0x00000000UL) /**< Offset from MCR Base Address: <tt> 0x0000</tt> */ 92 #define MXC_R_MCR_HIRC96M ((uint32_t)0x00000004UL) /**< Offset from MCR Base Address: <tt> 0x0004</tt> */ 93 #define MXC_R_MCR_OUTEN ((uint32_t)0x00000008UL) /**< Offset from MCR Base Address: <tt> 0x0008</tt> */ 94 #define MXC_R_MCR_AINCOMP ((uint32_t)0x0000000CUL) /**< Offset from MCR Base Address: <tt> 0x000C</tt> */ 95 #define MXC_R_MCR_CTRL ((uint32_t)0x00000010UL) /**< Offset from MCR Base Address: <tt> 0x0010</tt> */ 96 /**@} end of group mcr_registers */ 97 98 /** 99 * @ingroup mcr_registers 100 * @defgroup MCR_ECCEN MCR_ECCEN 101 * @brief ECC Enable Register 102 * @{ 103 */ 104 #define MXC_F_MCR_ECCEN_SYSRAM0ECCEN_POS 0 /**< ECCEN_SYSRAM0ECCEN Position */ 105 #define MXC_F_MCR_ECCEN_SYSRAM0ECCEN ((uint32_t)(0x1UL << MXC_F_MCR_ECCEN_SYSRAM0ECCEN_POS)) /**< ECCEN_SYSRAM0ECCEN Mask */ 106 107 #define MXC_F_MCR_ECCEN_SYSRAM1ECCEN_POS 1 /**< ECCEN_SYSRAM1ECCEN Position */ 108 #define MXC_F_MCR_ECCEN_SYSRAM1ECCEN ((uint32_t)(0x1UL << MXC_F_MCR_ECCEN_SYSRAM1ECCEN_POS)) /**< ECCEN_SYSRAM1ECCEN Mask */ 109 110 #define MXC_F_MCR_ECCEN_SYSRAM2ECCEN_POS 2 /**< ECCEN_SYSRAM2ECCEN Position */ 111 #define MXC_F_MCR_ECCEN_SYSRAM2ECCEN ((uint32_t)(0x1UL << MXC_F_MCR_ECCEN_SYSRAM2ECCEN_POS)) /**< ECCEN_SYSRAM2ECCEN Mask */ 112 113 #define MXC_F_MCR_ECCEN_SYSRAM3ECCEN_POS 3 /**< ECCEN_SYSRAM3ECCEN Position */ 114 #define MXC_F_MCR_ECCEN_SYSRAM3ECCEN ((uint32_t)(0x1UL << MXC_F_MCR_ECCEN_SYSRAM3ECCEN_POS)) /**< ECCEN_SYSRAM3ECCEN Mask */ 115 116 #define MXC_F_MCR_ECCEN_SYSRAM4ECCEN_POS 4 /**< ECCEN_SYSRAM4ECCEN Position */ 117 #define MXC_F_MCR_ECCEN_SYSRAM4ECCEN ((uint32_t)(0x1UL << MXC_F_MCR_ECCEN_SYSRAM4ECCEN_POS)) /**< ECCEN_SYSRAM4ECCEN Mask */ 118 119 #define MXC_F_MCR_ECCEN_SYSRAM5ECCEN_POS 5 /**< ECCEN_SYSRAM5ECCEN Position */ 120 #define MXC_F_MCR_ECCEN_SYSRAM5ECCEN ((uint32_t)(0x1UL << MXC_F_MCR_ECCEN_SYSRAM5ECCEN_POS)) /**< ECCEN_SYSRAM5ECCEN Mask */ 121 122 #define MXC_F_MCR_ECCEN_IC0ECCEN_POS 8 /**< ECCEN_IC0ECCEN Position */ 123 #define MXC_F_MCR_ECCEN_IC0ECCEN ((uint32_t)(0x1UL << MXC_F_MCR_ECCEN_IC0ECCEN_POS)) /**< ECCEN_IC0ECCEN Mask */ 124 125 #define MXC_F_MCR_ECCEN_IC1ECCEN_POS 9 /**< ECCEN_IC1ECCEN Position */ 126 #define MXC_F_MCR_ECCEN_IC1ECCEN ((uint32_t)(0x1UL << MXC_F_MCR_ECCEN_IC1ECCEN_POS)) /**< ECCEN_IC1ECCEN Mask */ 127 128 #define MXC_F_MCR_ECCEN_ICXIPFECCEN_POS 10 /**< ECCEN_ICXIPFECCEN Position */ 129 #define MXC_F_MCR_ECCEN_ICXIPFECCEN ((uint32_t)(0x1UL << MXC_F_MCR_ECCEN_ICXIPFECCEN_POS)) /**< ECCEN_ICXIPFECCEN Mask */ 130 131 #define MXC_F_MCR_ECCEN_FL0ECCEN_POS 11 /**< ECCEN_FL0ECCEN Position */ 132 #define MXC_F_MCR_ECCEN_FL0ECCEN ((uint32_t)(0x1UL << MXC_F_MCR_ECCEN_FL0ECCEN_POS)) /**< ECCEN_FL0ECCEN Mask */ 133 134 #define MXC_F_MCR_ECCEN_FL1ECCEN_POS 12 /**< ECCEN_FL1ECCEN Position */ 135 #define MXC_F_MCR_ECCEN_FL1ECCEN ((uint32_t)(0x1UL << MXC_F_MCR_ECCEN_FL1ECCEN_POS)) /**< ECCEN_FL1ECCEN Mask */ 136 137 /**@} end of group MCR_ECCEN_Register */ 138 139 /** 140 * @ingroup mcr_registers 141 * @defgroup MCR_HIRC96M MCR_HIRC96M 142 * @brief 96MHz High Frequency Clock Adjustment Register 143 * @{ 144 */ 145 #define MXC_F_MCR_HIRC96M_HIRC96MTR_POS 0 /**< HIRC96M_HIRC96MTR Position */ 146 #define MXC_F_MCR_HIRC96M_HIRC96MTR ((uint32_t)(0x1FFUL << MXC_F_MCR_HIRC96M_HIRC96MTR_POS)) /**< HIRC96M_HIRC96MTR Mask */ 147 #define MXC_V_MCR_HIRC96M_HIRC96MTR_DEFAULT ((uint32_t)0x100UL) /**< HIRC96M_HIRC96MTR_DEFAULT Value */ 148 #define MXC_S_MCR_HIRC96M_HIRC96MTR_DEFAULT (MXC_V_MCR_HIRC96M_HIRC96MTR_DEFAULT << MXC_F_MCR_HIRC96M_HIRC96MTR_POS) /**< HIRC96M_HIRC96MTR_DEFAULT Setting */ 149 150 /**@} end of group MCR_HIRC96M_Register */ 151 152 /** 153 * @ingroup mcr_registers 154 * @defgroup MCR_OUTEN MCR_OUTEN 155 * @brief GPIOOUT_EN Function Enable Register 156 * @{ 157 */ 158 #define MXC_F_MCR_OUTEN_SQWOUT0EN_POS 0 /**< OUTEN_SQWOUT0EN Position */ 159 #define MXC_F_MCR_OUTEN_SQWOUT0EN ((uint32_t)(0x1UL << MXC_F_MCR_OUTEN_SQWOUT0EN_POS)) /**< OUTEN_SQWOUT0EN Mask */ 160 161 #define MXC_F_MCR_OUTEN_SQWOUT1EN_POS 1 /**< OUTEN_SQWOUT1EN Position */ 162 #define MXC_F_MCR_OUTEN_SQWOUT1EN ((uint32_t)(0x1UL << MXC_F_MCR_OUTEN_SQWOUT1EN_POS)) /**< OUTEN_SQWOUT1EN Mask */ 163 164 #define MXC_F_MCR_OUTEN_PDOWNOUT0EN_POS 2 /**< OUTEN_PDOWNOUT0EN Position */ 165 #define MXC_F_MCR_OUTEN_PDOWNOUT0EN ((uint32_t)(0x1UL << MXC_F_MCR_OUTEN_PDOWNOUT0EN_POS)) /**< OUTEN_PDOWNOUT0EN Mask */ 166 167 #define MXC_F_MCR_OUTEN_PDOWNOUT1EN_POS 3 /**< OUTEN_PDOWNOUT1EN Position */ 168 #define MXC_F_MCR_OUTEN_PDOWNOUT1EN ((uint32_t)(0x1UL << MXC_F_MCR_OUTEN_PDOWNOUT1EN_POS)) /**< OUTEN_PDOWNOUT1EN Mask */ 169 170 /**@} end of group MCR_OUTEN_Register */ 171 172 /** 173 * @ingroup mcr_registers 174 * @defgroup MCR_AINCOMP MCR_AINCOMP 175 * @brief Comparator Power Control Register 176 * @{ 177 */ 178 #define MXC_F_MCR_AINCOMP_AINCOMP0PD_POS 0 /**< AINCOMP_AINCOMP0PD Position */ 179 #define MXC_F_MCR_AINCOMP_AINCOMP0PD ((uint32_t)(0x1UL << MXC_F_MCR_AINCOMP_AINCOMP0PD_POS)) /**< AINCOMP_AINCOMP0PD Mask */ 180 181 #define MXC_F_MCR_AINCOMP_AINCOMP1PD_POS 1 /**< AINCOMP_AINCOMP1PD Position */ 182 #define MXC_F_MCR_AINCOMP_AINCOMP1PD ((uint32_t)(0x1UL << MXC_F_MCR_AINCOMP_AINCOMP1PD_POS)) /**< AINCOMP_AINCOMP1PD Mask */ 183 184 #define MXC_F_MCR_AINCOMP_AINCOMP2PD_POS 2 /**< AINCOMP_AINCOMP2PD Position */ 185 #define MXC_F_MCR_AINCOMP_AINCOMP2PD ((uint32_t)(0x1UL << MXC_F_MCR_AINCOMP_AINCOMP2PD_POS)) /**< AINCOMP_AINCOMP2PD Mask */ 186 187 #define MXC_F_MCR_AINCOMP_AINCOMP3PD_POS 3 /**< AINCOMP_AINCOMP3PD Position */ 188 #define MXC_F_MCR_AINCOMP_AINCOMP3PD ((uint32_t)(0x1UL << MXC_F_MCR_AINCOMP_AINCOMP3PD_POS)) /**< AINCOMP_AINCOMP3PD Mask */ 189 190 #define MXC_F_MCR_AINCOMP_AINCOMPHYST_POS 4 /**< AINCOMP_AINCOMPHYST Position */ 191 #define MXC_F_MCR_AINCOMP_AINCOMPHYST ((uint32_t)(0x3UL << MXC_F_MCR_AINCOMP_AINCOMPHYST_POS)) /**< AINCOMP_AINCOMPHYST Mask */ 192 193 /**@} end of group MCR_AINCOMP_Register */ 194 195 /** 196 * @ingroup mcr_registers 197 * @defgroup MCR_CTRL MCR_CTRL 198 * @brief Misc Power State Control Register 199 * @{ 200 */ 201 #define MXC_F_MCR_CTRL_VDDCSWEN_POS 0 /**< CTRL_VDDCSWEN Position */ 202 #define MXC_F_MCR_CTRL_VDDCSWEN ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_VDDCSWEN_POS)) /**< CTRL_VDDCSWEN Mask */ 203 204 #define MXC_F_MCR_CTRL_VDDCSW_POS 1 /**< CTRL_VDDCSW Position */ 205 #define MXC_F_MCR_CTRL_VDDCSW ((uint32_t)(0x3UL << MXC_F_MCR_CTRL_VDDCSW_POS)) /**< CTRL_VDDCSW Mask */ 206 207 #define MXC_F_MCR_CTRL_USBSWEN_N_POS 3 /**< CTRL_USBSWEN_N Position */ 208 #define MXC_F_MCR_CTRL_USBSWEN_N ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_USBSWEN_N_POS)) /**< CTRL_USBSWEN_N Mask */ 209 210 #define MXC_F_MCR_CTRL_BUCKCLKSCALEN_POS 8 /**< CTRL_BUCKCLKSCALEN Position */ 211 #define MXC_F_MCR_CTRL_BUCKCLKSCALEN ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_BUCKCLKSCALEN_POS)) /**< CTRL_BUCKCLKSCALEN Mask */ 212 213 #define MXC_F_MCR_CTRL_P1M_POS 9 /**< CTRL_P1M Position */ 214 #define MXC_F_MCR_CTRL_P1M ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_P1M_POS)) /**< CTRL_P1M Mask */ 215 216 #define MXC_F_MCR_CTRL_RSTN_VOLTAGE_SEL_POS 10 /**< CTRL_RSTN_VOLTAGE_SEL Position */ 217 #define MXC_F_MCR_CTRL_RSTN_VOLTAGE_SEL ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_RSTN_VOLTAGE_SEL_POS)) /**< CTRL_RSTN_VOLTAGE_SEL Mask */ 218 219 /**@} end of group MCR_CTRL_Register */ 220 221 #ifdef __cplusplus 222 } 223 #endif 224 225 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_MCR_REGS_H_ 226
