1 /** 2 * @file i2c_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup i2c_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_I2C_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_I2C_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup i2c 67 * @defgroup i2c_registers I2C_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module. 69 * @details Inter-Integrated Circuit. 70 */ 71 72 /** 73 * @ingroup i2c_registers 74 * Structure type to access the I2C Registers. 75 */ 76 typedef struct { 77 __IO uint32_t ctrl; /**< <tt>\b 0x00:</tt> I2C CTRL Register */ 78 __IO uint32_t status; /**< <tt>\b 0x04:</tt> I2C STATUS Register */ 79 __IO uint32_t int_fl0; /**< <tt>\b 0x08:</tt> I2C INT_FL0 Register */ 80 __IO uint32_t int_en0; /**< <tt>\b 0x0C:</tt> I2C INT_EN0 Register */ 81 __IO uint32_t int_fl1; /**< <tt>\b 0x10:</tt> I2C INT_FL1 Register */ 82 __IO uint32_t int_en1; /**< <tt>\b 0x14:</tt> I2C INT_EN1 Register */ 83 __IO uint32_t fifo_len; /**< <tt>\b 0x18:</tt> I2C FIFO_LEN Register */ 84 __IO uint32_t rx_ctrl0; /**< <tt>\b 0x1C:</tt> I2C RX_CTRL0 Register */ 85 __IO uint32_t rx_ctrl1; /**< <tt>\b 0x20:</tt> I2C RX_CTRL1 Register */ 86 __IO uint32_t tx_ctrl0; /**< <tt>\b 0x24:</tt> I2C TX_CTRL0 Register */ 87 __IO uint32_t tx_ctrl1; /**< <tt>\b 0x28:</tt> I2C TX_CTRL1 Register */ 88 __IO uint32_t fifo; /**< <tt>\b 0x2C:</tt> I2C FIFO Register */ 89 __IO uint32_t master_ctrl; /**< <tt>\b 0x30:</tt> I2C MASTER_CTRL Register */ 90 __IO uint32_t clk_lo; /**< <tt>\b 0x34:</tt> I2C CLK_LO Register */ 91 __IO uint32_t clk_hi; /**< <tt>\b 0x38:</tt> I2C CLK_HI Register */ 92 __IO uint32_t hs_clk; /**< <tt>\b 0x3C:</tt> I2C HS_CLK Register */ 93 __IO uint32_t timeout; /**< <tt>\b 0x40:</tt> I2C TIMEOUT Register */ 94 __R uint32_t rsv_0x44; 95 __IO uint32_t dma; /**< <tt>\b 0x48:</tt> I2C DMA Register */ 96 __IO uint32_t slave_addr; /**< <tt>\b 0x4C:</tt> I2C SLAVE_ADDR Register */ 97 } mxc_i2c_regs_t; 98 99 /* Register offsets for module I2C */ 100 /** 101 * @ingroup i2c_registers 102 * @defgroup I2C_Register_Offsets Register Offsets 103 * @brief I2C Peripheral Register Offsets from the I2C Base Peripheral Address. 104 * @{ 105 */ 106 #define MXC_R_I2C_CTRL ((uint32_t)0x00000000UL) /**< Offset from I2C Base Address: <tt> 0x0000</tt> */ 107 #define MXC_R_I2C_STATUS ((uint32_t)0x00000004UL) /**< Offset from I2C Base Address: <tt> 0x0004</tt> */ 108 #define MXC_R_I2C_INT_FL0 ((uint32_t)0x00000008UL) /**< Offset from I2C Base Address: <tt> 0x0008</tt> */ 109 #define MXC_R_I2C_INT_EN0 ((uint32_t)0x0000000CUL) /**< Offset from I2C Base Address: <tt> 0x000C</tt> */ 110 #define MXC_R_I2C_INT_FL1 ((uint32_t)0x00000010UL) /**< Offset from I2C Base Address: <tt> 0x0010</tt> */ 111 #define MXC_R_I2C_INT_EN1 ((uint32_t)0x00000014UL) /**< Offset from I2C Base Address: <tt> 0x0014</tt> */ 112 #define MXC_R_I2C_FIFO_LEN ((uint32_t)0x00000018UL) /**< Offset from I2C Base Address: <tt> 0x0018</tt> */ 113 #define MXC_R_I2C_RX_CTRL0 ((uint32_t)0x0000001CUL) /**< Offset from I2C Base Address: <tt> 0x001C</tt> */ 114 #define MXC_R_I2C_RX_CTRL1 ((uint32_t)0x00000020UL) /**< Offset from I2C Base Address: <tt> 0x0020</tt> */ 115 #define MXC_R_I2C_TX_CTRL0 ((uint32_t)0x00000024UL) /**< Offset from I2C Base Address: <tt> 0x0024</tt> */ 116 #define MXC_R_I2C_TX_CTRL1 ((uint32_t)0x00000028UL) /**< Offset from I2C Base Address: <tt> 0x0028</tt> */ 117 #define MXC_R_I2C_FIFO ((uint32_t)0x0000002CUL) /**< Offset from I2C Base Address: <tt> 0x002C</tt> */ 118 #define MXC_R_I2C_MASTER_CTRL ((uint32_t)0x00000030UL) /**< Offset from I2C Base Address: <tt> 0x0030</tt> */ 119 #define MXC_R_I2C_CLK_LO ((uint32_t)0x00000034UL) /**< Offset from I2C Base Address: <tt> 0x0034</tt> */ 120 #define MXC_R_I2C_CLK_HI ((uint32_t)0x00000038UL) /**< Offset from I2C Base Address: <tt> 0x0038</tt> */ 121 #define MXC_R_I2C_HS_CLK ((uint32_t)0x0000003CUL) /**< Offset from I2C Base Address: <tt> 0x003C</tt> */ 122 #define MXC_R_I2C_TIMEOUT ((uint32_t)0x00000040UL) /**< Offset from I2C Base Address: <tt> 0x0040</tt> */ 123 #define MXC_R_I2C_DMA ((uint32_t)0x00000048UL) /**< Offset from I2C Base Address: <tt> 0x0048</tt> */ 124 #define MXC_R_I2C_SLAVE_ADDR ((uint32_t)0x0000004CUL) /**< Offset from I2C Base Address: <tt> 0x004C</tt> */ 125 /**@} end of group i2c_registers */ 126 127 /** 128 * @ingroup i2c_registers 129 * @defgroup I2C_CTRL I2C_CTRL 130 * @brief Control Register. 131 * @{ 132 */ 133 #define MXC_F_I2C_CTRL_I2C_EN_POS 0 /**< CTRL_I2C_EN Position */ 134 #define MXC_F_I2C_CTRL_I2C_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_I2C_EN_POS)) /**< CTRL_I2C_EN Mask */ 135 136 #define MXC_F_I2C_CTRL_MST_POS 1 /**< CTRL_MST Position */ 137 #define MXC_F_I2C_CTRL_MST ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_MST_POS)) /**< CTRL_MST Mask */ 138 139 #define MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS 2 /**< CTRL_GEN_CALL_ADDR Position */ 140 #define MXC_F_I2C_CTRL_GEN_CALL_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS)) /**< CTRL_GEN_CALL_ADDR Mask */ 141 142 #define MXC_F_I2C_CTRL_RX_MODE_POS 3 /**< CTRL_RX_MODE Position */ 143 #define MXC_F_I2C_CTRL_RX_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_RX_MODE_POS)) /**< CTRL_RX_MODE Mask */ 144 145 #define MXC_F_I2C_CTRL_RX_MODE_ACK_POS 4 /**< CTRL_RX_MODE_ACK Position */ 146 #define MXC_F_I2C_CTRL_RX_MODE_ACK ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_RX_MODE_ACK_POS)) /**< CTRL_RX_MODE_ACK Mask */ 147 148 #define MXC_F_I2C_CTRL_SCL_OUT_POS 6 /**< CTRL_SCL_OUT Position */ 149 #define MXC_F_I2C_CTRL_SCL_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_OUT_POS)) /**< CTRL_SCL_OUT Mask */ 150 151 #define MXC_F_I2C_CTRL_SDA_OUT_POS 7 /**< CTRL_SDA_OUT Position */ 152 #define MXC_F_I2C_CTRL_SDA_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_OUT_POS)) /**< CTRL_SDA_OUT Mask */ 153 154 #define MXC_F_I2C_CTRL_SCL_POS 8 /**< CTRL_SCL Position */ 155 #define MXC_F_I2C_CTRL_SCL ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_POS)) /**< CTRL_SCL Mask */ 156 157 #define MXC_F_I2C_CTRL_SDA_POS 9 /**< CTRL_SDA Position */ 158 #define MXC_F_I2C_CTRL_SDA ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_POS)) /**< CTRL_SDA Mask */ 159 160 #define MXC_F_I2C_CTRL_SW_OUT_EN_POS 10 /**< CTRL_SW_OUT_EN Position */ 161 #define MXC_F_I2C_CTRL_SW_OUT_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SW_OUT_EN_POS)) /**< CTRL_SW_OUT_EN Mask */ 162 163 #define MXC_F_I2C_CTRL_READ_POS 11 /**< CTRL_READ Position */ 164 #define MXC_F_I2C_CTRL_READ ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_READ_POS)) /**< CTRL_READ Mask */ 165 166 #define MXC_F_I2C_CTRL_SCL_CLK_STRETCH_DIS_POS 12 /**< CTRL_SCL_CLK_STRETCH_DIS Position */ 167 #define MXC_F_I2C_CTRL_SCL_CLK_STRETCH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_CLK_STRETCH_DIS_POS)) /**< CTRL_SCL_CLK_STRETCH_DIS Mask */ 168 169 #define MXC_F_I2C_CTRL_SCL_PP_MODE_POS 13 /**< CTRL_SCL_PP_MODE Position */ 170 #define MXC_F_I2C_CTRL_SCL_PP_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_PP_MODE_POS)) /**< CTRL_SCL_PP_MODE Mask */ 171 172 #define MXC_F_I2C_CTRL_HS_MODE_POS 15 /**< CTRL_HS_MODE Position */ 173 #define MXC_F_I2C_CTRL_HS_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_HS_MODE_POS)) /**< CTRL_HS_MODE Mask */ 174 175 /**@} end of group I2C_CTRL_Register */ 176 177 /** 178 * @ingroup i2c_registers 179 * @defgroup I2C_STATUS I2C_STATUS 180 * @brief Status Register. 181 * @{ 182 */ 183 #define MXC_F_I2C_STATUS_BUS_POS 0 /**< STATUS_BUS Position */ 184 #define MXC_F_I2C_STATUS_BUS ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_BUS_POS)) /**< STATUS_BUS Mask */ 185 186 #define MXC_F_I2C_STATUS_RX_EMPTY_POS 1 /**< STATUS_RX_EMPTY Position */ 187 #define MXC_F_I2C_STATUS_RX_EMPTY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_EMPTY_POS)) /**< STATUS_RX_EMPTY Mask */ 188 189 #define MXC_F_I2C_STATUS_RX_FULL_POS 2 /**< STATUS_RX_FULL Position */ 190 #define MXC_F_I2C_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */ 191 192 #define MXC_F_I2C_STATUS_TX_EMPTY_POS 3 /**< STATUS_TX_EMPTY Position */ 193 #define MXC_F_I2C_STATUS_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_EMPTY_POS)) /**< STATUS_TX_EMPTY Mask */ 194 195 #define MXC_F_I2C_STATUS_TX_FULL_POS 4 /**< STATUS_TX_FULL Position */ 196 #define MXC_F_I2C_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */ 197 198 #define MXC_F_I2C_STATUS_CLK_MODE_POS 5 /**< STATUS_CLK_MODE Position */ 199 #define MXC_F_I2C_STATUS_CLK_MODE ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_CLK_MODE_POS)) /**< STATUS_CLK_MODE Mask */ 200 201 /**@} end of group I2C_STATUS_Register */ 202 203 /** 204 * @ingroup i2c_registers 205 * @defgroup I2C_INT_FL0 I2C_INT_FL0 206 * @brief Interrupt Status Register. 207 * @{ 208 */ 209 #define MXC_F_I2C_INT_FL0_DONE_POS 0 /**< INT_FL0_DONE Position */ 210 #define MXC_F_I2C_INT_FL0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_DONE_POS)) /**< INT_FL0_DONE Mask */ 211 212 #define MXC_F_I2C_INT_FL0_RX_MODE_POS 1 /**< INT_FL0_RX_MODE Position */ 213 #define MXC_F_I2C_INT_FL0_RX_MODE ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_RX_MODE_POS)) /**< INT_FL0_RX_MODE Mask */ 214 215 #define MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS 2 /**< INT_FL0_GEN_CALL_ADDR Position */ 216 #define MXC_F_I2C_INT_FL0_GEN_CALL_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS)) /**< INT_FL0_GEN_CALL_ADDR Mask */ 217 218 #define MXC_F_I2C_INT_FL0_ADDR_MATCH_POS 3 /**< INT_FL0_ADDR_MATCH Position */ 219 #define MXC_F_I2C_INT_FL0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ADDR_MATCH_POS)) /**< INT_FL0_ADDR_MATCH Mask */ 220 221 #define MXC_F_I2C_INT_FL0_RX_THRESH_POS 4 /**< INT_FL0_RX_THRESH Position */ 222 #define MXC_F_I2C_INT_FL0_RX_THRESH ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_RX_THRESH_POS)) /**< INT_FL0_RX_THRESH Mask */ 223 224 #define MXC_F_I2C_INT_FL0_TX_THRESH_POS 5 /**< INT_FL0_TX_THRESH Position */ 225 #define MXC_F_I2C_INT_FL0_TX_THRESH ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_TX_THRESH_POS)) /**< INT_FL0_TX_THRESH Mask */ 226 227 #define MXC_F_I2C_INT_FL0_STOP_POS 6 /**< INT_FL0_STOP Position */ 228 #define MXC_F_I2C_INT_FL0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_STOP_POS)) /**< INT_FL0_STOP Mask */ 229 230 #define MXC_F_I2C_INT_FL0_ADDR_ACK_POS 7 /**< INT_FL0_ADDR_ACK Position */ 231 #define MXC_F_I2C_INT_FL0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ADDR_ACK_POS)) /**< INT_FL0_ADDR_ACK Mask */ 232 233 #define MXC_F_I2C_INT_FL0_ARB_ER_POS 8 /**< INT_FL0_ARB_ER Position */ 234 #define MXC_F_I2C_INT_FL0_ARB_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ARB_ER_POS)) /**< INT_FL0_ARB_ER Mask */ 235 236 #define MXC_F_I2C_INT_FL0_TO_ER_POS 9 /**< INT_FL0_TO_ER Position */ 237 #define MXC_F_I2C_INT_FL0_TO_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_TO_ER_POS)) /**< INT_FL0_TO_ER Mask */ 238 239 #define MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS 10 /**< INT_FL0_ADDR_NACK_ER Position */ 240 #define MXC_F_I2C_INT_FL0_ADDR_NACK_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS)) /**< INT_FL0_ADDR_NACK_ER Mask */ 241 242 #define MXC_F_I2C_INT_FL0_DATA_ER_POS 11 /**< INT_FL0_DATA_ER Position */ 243 #define MXC_F_I2C_INT_FL0_DATA_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_DATA_ER_POS)) /**< INT_FL0_DATA_ER Mask */ 244 245 #define MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS 12 /**< INT_FL0_DO_NOT_RESP_ER Position */ 246 #define MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS)) /**< INT_FL0_DO_NOT_RESP_ER Mask */ 247 248 #define MXC_F_I2C_INT_FL0_START_ER_POS 13 /**< INT_FL0_START_ER Position */ 249 #define MXC_F_I2C_INT_FL0_START_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_START_ER_POS)) /**< INT_FL0_START_ER Mask */ 250 251 #define MXC_F_I2C_INT_FL0_STOP_ER_POS 14 /**< INT_FL0_STOP_ER Position */ 252 #define MXC_F_I2C_INT_FL0_STOP_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_STOP_ER_POS)) /**< INT_FL0_STOP_ER Mask */ 253 254 #define MXC_F_I2C_INT_FL0_TX_LOCK_OUT_POS 15 /**< INT_FL0_TX_LOCK_OUT Position */ 255 #define MXC_F_I2C_INT_FL0_TX_LOCK_OUT ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_TX_LOCK_OUT_POS)) /**< INT_FL0_TX_LOCK_OUT Mask */ 256 257 #define MXC_F_I2C_INT_FL0_RD_ADDR_MATCH_POS 22 /**< INT_FL0_RD_ADDR_MATCH Position */ 258 #define MXC_F_I2C_INT_FL0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_RD_ADDR_MATCH_POS)) /**< INT_FL0_RD_ADDR_MATCH Mask */ 259 260 #define MXC_F_I2C_INT_FL0_WR_ADDR_MATCH_POS 23 /**< INT_FL0_WR_ADDR_MATCH Position */ 261 #define MXC_F_I2C_INT_FL0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_WR_ADDR_MATCH_POS)) /**< INT_FL0_WR_ADDR_MATCH Mask */ 262 263 /**@} end of group I2C_INT_FL0_Register */ 264 265 /** 266 * @ingroup i2c_registers 267 * @defgroup I2C_INT_EN0 I2C_INT_EN0 268 * @brief Interrupt Enable Register. 269 * @{ 270 */ 271 #define MXC_F_I2C_INT_EN0_DONE_POS 0 /**< INT_EN0_DONE Position */ 272 #define MXC_F_I2C_INT_EN0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_DONE_POS)) /**< INT_EN0_DONE Mask */ 273 274 #define MXC_F_I2C_INT_EN0_RX_MODE_POS 1 /**< INT_EN0_RX_MODE Position */ 275 #define MXC_F_I2C_INT_EN0_RX_MODE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_RX_MODE_POS)) /**< INT_EN0_RX_MODE Mask */ 276 277 #define MXC_F_I2C_INT_EN0_GEN_CALL_ADDR_POS 2 /**< INT_EN0_GEN_CALL_ADDR Position */ 278 #define MXC_F_I2C_INT_EN0_GEN_CALL_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_GEN_CALL_ADDR_POS)) /**< INT_EN0_GEN_CALL_ADDR Mask */ 279 280 #define MXC_F_I2C_INT_EN0_ADDR_MATCH_POS 3 /**< INT_EN0_ADDR_MATCH Position */ 281 #define MXC_F_I2C_INT_EN0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ADDR_MATCH_POS)) /**< INT_EN0_ADDR_MATCH Mask */ 282 283 #define MXC_F_I2C_INT_EN0_RX_THRESH_POS 4 /**< INT_EN0_RX_THRESH Position */ 284 #define MXC_F_I2C_INT_EN0_RX_THRESH ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_RX_THRESH_POS)) /**< INT_EN0_RX_THRESH Mask */ 285 286 #define MXC_F_I2C_INT_EN0_TX_THRESH_POS 5 /**< INT_EN0_TX_THRESH Position */ 287 #define MXC_F_I2C_INT_EN0_TX_THRESH ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_TX_THRESH_POS)) /**< INT_EN0_TX_THRESH Mask */ 288 289 #define MXC_F_I2C_INT_EN0_STOP_POS 6 /**< INT_EN0_STOP Position */ 290 #define MXC_F_I2C_INT_EN0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_STOP_POS)) /**< INT_EN0_STOP Mask */ 291 292 #define MXC_F_I2C_INT_EN0_ADDR_ACK_POS 7 /**< INT_EN0_ADDR_ACK Position */ 293 #define MXC_F_I2C_INT_EN0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ADDR_ACK_POS)) /**< INT_EN0_ADDR_ACK Mask */ 294 295 #define MXC_F_I2C_INT_EN0_ARB_ER_POS 8 /**< INT_EN0_ARB_ER Position */ 296 #define MXC_F_I2C_INT_EN0_ARB_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ARB_ER_POS)) /**< INT_EN0_ARB_ER Mask */ 297 298 #define MXC_F_I2C_INT_EN0_TO_ER_POS 9 /**< INT_EN0_TO_ER Position */ 299 #define MXC_F_I2C_INT_EN0_TO_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_TO_ER_POS)) /**< INT_EN0_TO_ER Mask */ 300 301 #define MXC_F_I2C_INT_EN0_ADDR_NACK_ER_POS 10 /**< INT_EN0_ADDR_NACK_ER Position */ 302 #define MXC_F_I2C_INT_EN0_ADDR_NACK_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ADDR_NACK_ER_POS)) /**< INT_EN0_ADDR_NACK_ER Mask */ 303 304 #define MXC_F_I2C_INT_EN0_DATA_ER_POS 11 /**< INT_EN0_DATA_ER Position */ 305 #define MXC_F_I2C_INT_EN0_DATA_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_DATA_ER_POS)) /**< INT_EN0_DATA_ER Mask */ 306 307 #define MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS 12 /**< INT_EN0_DO_NOT_RESP_ER Position */ 308 #define MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS)) /**< INT_EN0_DO_NOT_RESP_ER Mask */ 309 310 #define MXC_F_I2C_INT_EN0_START_ER_POS 13 /**< INT_EN0_START_ER Position */ 311 #define MXC_F_I2C_INT_EN0_START_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_START_ER_POS)) /**< INT_EN0_START_ER Mask */ 312 313 #define MXC_F_I2C_INT_EN0_STOP_ER_POS 14 /**< INT_EN0_STOP_ER Position */ 314 #define MXC_F_I2C_INT_EN0_STOP_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_STOP_ER_POS)) /**< INT_EN0_STOP_ER Mask */ 315 316 #define MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS 15 /**< INT_EN0_TX_LOCK_OUT Position */ 317 #define MXC_F_I2C_INT_EN0_TX_LOCK_OUT ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS)) /**< INT_EN0_TX_LOCK_OUT Mask */ 318 319 #define MXC_F_I2C_INT_EN0_RD_ADDR_MATCH_POS 22 /**< INT_EN0_RD_ADDR_MATCH Position */ 320 #define MXC_F_I2C_INT_EN0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_RD_ADDR_MATCH_POS)) /**< INT_EN0_RD_ADDR_MATCH Mask */ 321 322 #define MXC_F_I2C_INT_EN0_WR_ADDR_MATCH_POS 23 /**< INT_EN0_WR_ADDR_MATCH Position */ 323 #define MXC_F_I2C_INT_EN0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_WR_ADDR_MATCH_POS)) /**< INT_EN0_WR_ADDR_MATCH Mask */ 324 325 /**@} end of group I2C_INT_EN0_Register */ 326 327 /** 328 * @ingroup i2c_registers 329 * @defgroup I2C_INT_FL1 I2C_INT_FL1 330 * @brief Interrupt Status Register 1. 331 * @{ 332 */ 333 #define MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS 0 /**< INT_FL1_RX_OVERFLOW Position */ 334 #define MXC_F_I2C_INT_FL1_RX_OVERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS)) /**< INT_FL1_RX_OVERFLOW Mask */ 335 336 #define MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS 1 /**< INT_FL1_TX_UNDERFLOW Position */ 337 #define MXC_F_I2C_INT_FL1_TX_UNDERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS)) /**< INT_FL1_TX_UNDERFLOW Mask */ 338 339 #define MXC_F_I2C_INT_FL1_START_POS 2 /**< INT_FL1_START Position */ 340 #define MXC_F_I2C_INT_FL1_START ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL1_START_POS)) /**< INT_FL1_START Mask */ 341 342 /**@} end of group I2C_INT_FL1_Register */ 343 344 /** 345 * @ingroup i2c_registers 346 * @defgroup I2C_INT_EN1 I2C_INT_EN1 347 * @brief Interrupt Staus Register 1. 348 * @{ 349 */ 350 #define MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS 0 /**< INT_EN1_RX_OVERFLOW Position */ 351 #define MXC_F_I2C_INT_EN1_RX_OVERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS)) /**< INT_EN1_RX_OVERFLOW Mask */ 352 353 #define MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS 1 /**< INT_EN1_TX_UNDERFLOW Position */ 354 #define MXC_F_I2C_INT_EN1_TX_UNDERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS)) /**< INT_EN1_TX_UNDERFLOW Mask */ 355 356 #define MXC_F_I2C_INT_EN1_START_POS 2 /**< INT_EN1_START Position */ 357 #define MXC_F_I2C_INT_EN1_START ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN1_START_POS)) /**< INT_EN1_START Mask */ 358 359 /**@} end of group I2C_INT_EN1_Register */ 360 361 /** 362 * @ingroup i2c_registers 363 * @defgroup I2C_FIFO_LEN I2C_FIFO_LEN 364 * @brief FIFO Configuration Register. 365 * @{ 366 */ 367 #define MXC_F_I2C_FIFO_LEN_RX_LEN_POS 0 /**< FIFO_LEN_RX_LEN Position */ 368 #define MXC_F_I2C_FIFO_LEN_RX_LEN ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_LEN_RX_LEN_POS)) /**< FIFO_LEN_RX_LEN Mask */ 369 370 #define MXC_F_I2C_FIFO_LEN_TX_LEN_POS 8 /**< FIFO_LEN_TX_LEN Position */ 371 #define MXC_F_I2C_FIFO_LEN_TX_LEN ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_LEN_TX_LEN_POS)) /**< FIFO_LEN_TX_LEN Mask */ 372 373 /**@} end of group I2C_FIFO_LEN_Register */ 374 375 /** 376 * @ingroup i2c_registers 377 * @defgroup I2C_RX_CTRL0 I2C_RX_CTRL0 378 * @brief Receive Control Register 0. 379 * @{ 380 */ 381 #define MXC_F_I2C_RX_CTRL0_DNR_POS 0 /**< RX_CTRL0_DNR Position */ 382 #define MXC_F_I2C_RX_CTRL0_DNR ((uint32_t)(0x1UL << MXC_F_I2C_RX_CTRL0_DNR_POS)) /**< RX_CTRL0_DNR Mask */ 383 384 #define MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS 7 /**< RX_CTRL0_RX_FLUSH Position */ 385 #define MXC_F_I2C_RX_CTRL0_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS)) /**< RX_CTRL0_RX_FLUSH Mask */ 386 387 #define MXC_F_I2C_RX_CTRL0_RX_THRESH_POS 8 /**< RX_CTRL0_RX_THRESH Position */ 388 #define MXC_F_I2C_RX_CTRL0_RX_THRESH ((uint32_t)(0xFUL << MXC_F_I2C_RX_CTRL0_RX_THRESH_POS)) /**< RX_CTRL0_RX_THRESH Mask */ 389 390 /**@} end of group I2C_RX_CTRL0_Register */ 391 392 /** 393 * @ingroup i2c_registers 394 * @defgroup I2C_RX_CTRL1 I2C_RX_CTRL1 395 * @brief Receive Control Register 1. 396 * @{ 397 */ 398 #define MXC_F_I2C_RX_CTRL1_RX_CNT_POS 0 /**< RX_CTRL1_RX_CNT Position */ 399 #define MXC_F_I2C_RX_CTRL1_RX_CNT ((uint32_t)(0xFFUL << MXC_F_I2C_RX_CTRL1_RX_CNT_POS)) /**< RX_CTRL1_RX_CNT Mask */ 400 401 #define MXC_F_I2C_RX_CTRL1_RX_FIFO_POS 8 /**< RX_CTRL1_RX_FIFO Position */ 402 #define MXC_F_I2C_RX_CTRL1_RX_FIFO ((uint32_t)(0xFUL << MXC_F_I2C_RX_CTRL1_RX_FIFO_POS)) /**< RX_CTRL1_RX_FIFO Mask */ 403 404 /**@} end of group I2C_RX_CTRL1_Register */ 405 406 /** 407 * @ingroup i2c_registers 408 * @defgroup I2C_TX_CTRL0 I2C_TX_CTRL0 409 * @brief Transmit Control Register 0. 410 * @{ 411 */ 412 #define MXC_F_I2C_TX_CTRL0_TX_PRELOAD_POS 0 /**< TX_CTRL0_TX_PRELOAD Position */ 413 #define MXC_F_I2C_TX_CTRL0_TX_PRELOAD ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_PRELOAD_POS)) /**< TX_CTRL0_TX_PRELOAD Mask */ 414 415 #define MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS 1 /**< TX_CTRL0_TX_READY_MODE Position */ 416 #define MXC_F_I2C_TX_CTRL0_TX_READY_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS)) /**< TX_CTRL0_TX_READY_MODE Mask */ 417 418 #define MXC_F_I2C_TX_CTRL0_TX_AMGC_AFD_POS 2 /**< TX_CTRL0_TX_AMGC_AFD Position */ 419 #define MXC_F_I2C_TX_CTRL0_TX_AMGC_AFD ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_AMGC_AFD_POS)) /**< TX_CTRL0_TX_AMGC_AFD Mask */ 420 421 #define MXC_F_I2C_TX_CTRL0_TX_AMW_AFD_POS 3 /**< TX_CTRL0_TX_AMW_AFD Position */ 422 #define MXC_F_I2C_TX_CTRL0_TX_AMW_AFD ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_AMW_AFD_POS)) /**< TX_CTRL0_TX_AMW_AFD Mask */ 423 424 #define MXC_F_I2C_TX_CTRL0_TX_AMR_AFD_POS 4 /**< TX_CTRL0_TX_AMR_AFD Position */ 425 #define MXC_F_I2C_TX_CTRL0_TX_AMR_AFD ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_AMR_AFD_POS)) /**< TX_CTRL0_TX_AMR_AFD Mask */ 426 427 #define MXC_F_I2C_TX_CTRL0_TX_NACK_AFD_POS 5 /**< TX_CTRL0_TX_NACK_AFD Position */ 428 #define MXC_F_I2C_TX_CTRL0_TX_NACK_AFD ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_NACK_AFD_POS)) /**< TX_CTRL0_TX_NACK_AFD Mask */ 429 430 #define MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS 7 /**< TX_CTRL0_TX_FLUSH Position */ 431 #define MXC_F_I2C_TX_CTRL0_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS)) /**< TX_CTRL0_TX_FLUSH Mask */ 432 433 #define MXC_F_I2C_TX_CTRL0_TX_THRESH_POS 8 /**< TX_CTRL0_TX_THRESH Position */ 434 #define MXC_F_I2C_TX_CTRL0_TX_THRESH ((uint32_t)(0xFUL << MXC_F_I2C_TX_CTRL0_TX_THRESH_POS)) /**< TX_CTRL0_TX_THRESH Mask */ 435 436 /**@} end of group I2C_TX_CTRL0_Register */ 437 438 /** 439 * @ingroup i2c_registers 440 * @defgroup I2C_TX_CTRL1 I2C_TX_CTRL1 441 * @brief Transmit Control Register 1. 442 * @{ 443 */ 444 #define MXC_F_I2C_TX_CTRL1_TX_READY_POS 0 /**< TX_CTRL1_TX_READY Position */ 445 #define MXC_F_I2C_TX_CTRL1_TX_READY ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL1_TX_READY_POS)) /**< TX_CTRL1_TX_READY Mask */ 446 447 #define MXC_F_I2C_TX_CTRL1_TXFIFO_POS 8 /**< TX_CTRL1_TXFIFO Position */ 448 #define MXC_F_I2C_TX_CTRL1_TXFIFO ((uint32_t)(0xFUL << MXC_F_I2C_TX_CTRL1_TXFIFO_POS)) /**< TX_CTRL1_TXFIFO Mask */ 449 450 /**@} end of group I2C_TX_CTRL1_Register */ 451 452 /** 453 * @ingroup i2c_registers 454 * @defgroup I2C_FIFO I2C_FIFO 455 * @brief Data Register. 456 * @{ 457 */ 458 #define MXC_F_I2C_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ 459 #define MXC_F_I2C_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ 460 461 /**@} end of group I2C_FIFO_Register */ 462 463 /** 464 * @ingroup i2c_registers 465 * @defgroup I2C_MASTER_CTRL I2C_MASTER_CTRL 466 * @brief Master Control Register. 467 * @{ 468 */ 469 #define MXC_F_I2C_MASTER_CTRL_START_POS 0 /**< MASTER_CTRL_START Position */ 470 #define MXC_F_I2C_MASTER_CTRL_START ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_START_POS)) /**< MASTER_CTRL_START Mask */ 471 472 #define MXC_F_I2C_MASTER_CTRL_RESTART_POS 1 /**< MASTER_CTRL_RESTART Position */ 473 #define MXC_F_I2C_MASTER_CTRL_RESTART ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_RESTART_POS)) /**< MASTER_CTRL_RESTART Mask */ 474 475 #define MXC_F_I2C_MASTER_CTRL_STOP_POS 2 /**< MASTER_CTRL_STOP Position */ 476 #define MXC_F_I2C_MASTER_CTRL_STOP ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_STOP_POS)) /**< MASTER_CTRL_STOP Mask */ 477 478 #define MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS 7 /**< MASTER_CTRL_SL_EX_ADDR Position */ 479 #define MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS)) /**< MASTER_CTRL_SL_EX_ADDR Mask */ 480 481 #define MXC_F_I2C_MASTER_CTRL_MCODE_POS 8 /**< MASTER_CTRL_MCODE Position */ 482 #define MXC_F_I2C_MASTER_CTRL_MCODE ((uint32_t)(0x7UL << MXC_F_I2C_MASTER_CTRL_MCODE_POS)) /**< MASTER_CTRL_MCODE Mask */ 483 484 #define MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS 11 /**< MASTER_CTRL_SCL_SPEED_UP Position */ 485 #define MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS)) /**< MASTER_CTRL_SCL_SPEED_UP Mask */ 486 487 /**@} end of group I2C_MASTER_CTRL_Register */ 488 489 /** 490 * @ingroup i2c_registers 491 * @defgroup I2C_CLK_LO I2C_CLK_LO 492 * @brief Clock Low Register. 493 * @{ 494 */ 495 #define MXC_F_I2C_CLK_LO_SCL_LO_POS 0 /**< CLK_LO_SCL_LO Position */ 496 #define MXC_F_I2C_CLK_LO_SCL_LO ((uint32_t)(0x1FFUL << MXC_F_I2C_CLK_LO_SCL_LO_POS)) /**< CLK_LO_SCL_LO Mask */ 497 498 /**@} end of group I2C_CLK_LO_Register */ 499 500 /** 501 * @ingroup i2c_registers 502 * @defgroup I2C_CLK_HI I2C_CLK_HI 503 * @brief Clock high Register. 504 * @{ 505 */ 506 #define MXC_F_I2C_CLK_HI_SCL_HI_POS 0 /**< CLK_HI_SCL_HI Position */ 507 #define MXC_F_I2C_CLK_HI_SCL_HI ((uint32_t)(0x1FFUL << MXC_F_I2C_CLK_HI_SCL_HI_POS)) /**< CLK_HI_SCL_HI Mask */ 508 509 /**@} end of group I2C_CLK_HI_Register */ 510 511 /** 512 * @ingroup i2c_registers 513 * @defgroup I2C_HS_CLK I2C_HS_CLK 514 * @brief HS-Mode Clock Control Register 515 * @{ 516 */ 517 #define MXC_F_I2C_HS_CLK_HS_CLK_LO_POS 0 /**< HS_CLK_HS_CLK_LO Position */ 518 #define MXC_F_I2C_HS_CLK_HS_CLK_LO ((uint32_t)(0xFFUL << MXC_F_I2C_HS_CLK_HS_CLK_LO_POS)) /**< HS_CLK_HS_CLK_LO Mask */ 519 520 #define MXC_F_I2C_HS_CLK_HS_CLK_HI_POS 8 /**< HS_CLK_HS_CLK_HI Position */ 521 #define MXC_F_I2C_HS_CLK_HS_CLK_HI ((uint32_t)(0xFFUL << MXC_F_I2C_HS_CLK_HS_CLK_HI_POS)) /**< HS_CLK_HS_CLK_HI Mask */ 522 523 /**@} end of group I2C_HS_CLK_Register */ 524 525 /** 526 * @ingroup i2c_registers 527 * @defgroup I2C_TIMEOUT I2C_TIMEOUT 528 * @brief Timeout Register 529 * @{ 530 */ 531 #define MXC_F_I2C_TIMEOUT_TO_POS 0 /**< TIMEOUT_TO Position */ 532 #define MXC_F_I2C_TIMEOUT_TO ((uint32_t)(0xFFFFUL << MXC_F_I2C_TIMEOUT_TO_POS)) /**< TIMEOUT_TO Mask */ 533 534 /**@} end of group I2C_TIMEOUT_Register */ 535 536 /** 537 * @ingroup i2c_registers 538 * @defgroup I2C_DMA I2C_DMA 539 * @brief DMA Register. 540 * @{ 541 */ 542 #define MXC_F_I2C_DMA_TXEN_POS 0 /**< DMA_TXEN Position */ 543 #define MXC_F_I2C_DMA_TXEN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_TXEN_POS)) /**< DMA_TXEN Mask */ 544 545 #define MXC_F_I2C_DMA_RXEN_POS 1 /**< DMA_RXEN Position */ 546 #define MXC_F_I2C_DMA_RXEN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_RXEN_POS)) /**< DMA_RXEN Mask */ 547 548 /**@} end of group I2C_DMA_Register */ 549 550 /** 551 * @ingroup i2c_registers 552 * @defgroup I2C_SLAVE_ADDR I2C_SLAVE_ADDR 553 * @brief Slave Address Register. 554 * @{ 555 */ 556 #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_POS 0 /**< SLAVE_ADDR_SLAVE_ADDR Position */ 557 #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR ((uint32_t)(0x3FFUL << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_POS)) /**< SLAVE_ADDR_SLAVE_ADDR Mask */ 558 559 #define MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS 15 /**< SLAVE_ADDR_EX_ADDR Position */ 560 #define MXC_F_I2C_SLAVE_ADDR_EX_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS)) /**< SLAVE_ADDR_EX_ADDR Mask */ 561 562 /**@} end of group I2C_SLAVE_ADDR_Register */ 563 564 #ifdef __cplusplus 565 } 566 #endif 567 568 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_I2C_REGS_H_ 569
