1 /** 2 * @file htmr_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the HTMR Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup htmr_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_HTMR_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_HTMR_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup htmr 67 * @defgroup htmr_registers HTMR_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the HTMR Peripheral Module. 69 * @details High Speed Timer Module. 70 */ 71 72 /** 73 * @ingroup htmr_registers 74 * Structure type to access the HTMR Registers. 75 */ 76 typedef struct { 77 __IO uint32_t sec; /**< <tt>\b 0x00:</tt> HTMR SEC Register */ 78 __IO uint32_t ssec; /**< <tt>\b 0x04:</tt> HTMR SSEC Register */ 79 __IO uint32_t ras; /**< <tt>\b 0x08:</tt> HTMR RAS Register */ 80 __IO uint32_t rssa; /**< <tt>\b 0x0C:</tt> HTMR RSSA Register */ 81 __IO uint32_t ctrl; /**< <tt>\b 0x10:</tt> HTMR CTRL Register */ 82 } mxc_htmr_regs_t; 83 84 /* Register offsets for module HTMR */ 85 /** 86 * @ingroup htmr_registers 87 * @defgroup HTMR_Register_Offsets Register Offsets 88 * @brief HTMR Peripheral Register Offsets from the HTMR Base Peripheral Address. 89 * @{ 90 */ 91 #define MXC_R_HTMR_SEC ((uint32_t)0x00000000UL) /**< Offset from HTMR Base Address: <tt> 0x0000</tt> */ 92 #define MXC_R_HTMR_SSEC ((uint32_t)0x00000004UL) /**< Offset from HTMR Base Address: <tt> 0x0004</tt> */ 93 #define MXC_R_HTMR_RAS ((uint32_t)0x00000008UL) /**< Offset from HTMR Base Address: <tt> 0x0008</tt> */ 94 #define MXC_R_HTMR_RSSA ((uint32_t)0x0000000CUL) /**< Offset from HTMR Base Address: <tt> 0x000C</tt> */ 95 #define MXC_R_HTMR_CTRL ((uint32_t)0x00000010UL) /**< Offset from HTMR Base Address: <tt> 0x0010</tt> */ 96 /**@} end of group htmr_registers */ 97 98 /** 99 * @ingroup htmr_registers 100 * @defgroup HTMR_SEC HTMR_SEC 101 * @brief HTimer Long-Interval Counter. This register contains the 32 most significant 102 * bits of the counter. 103 * @{ 104 */ 105 #define MXC_F_HTMR_SEC_RTS_POS 0 /**< SEC_RTS Position */ 106 #define MXC_F_HTMR_SEC_RTS ((uint32_t)(0x7FFFFFFFUL << MXC_F_HTMR_SEC_RTS_POS)) /**< SEC_RTS Mask */ 107 108 /**@} end of group HTMR_SEC_Register */ 109 110 /** 111 * @ingroup htmr_registers 112 * @defgroup HTMR_SSEC HTMR_SSEC 113 * @brief HTimer Short Interval Counter. This counter ticks ever t_htclk (16.48uS). 114 * HTIMER_SEC is incremented when this register rolls over from 0xFF to 0x00. 115 * @{ 116 */ 117 #define MXC_F_HTMR_SSEC_RTSS_POS 0 /**< SSEC_RTSS Position */ 118 #define MXC_F_HTMR_SSEC_RTSS ((uint32_t)(0xFFUL << MXC_F_HTMR_SSEC_RTSS_POS)) /**< SSEC_RTSS Mask */ 119 120 /**@} end of group HTMR_SSEC_Register */ 121 122 /** 123 * @ingroup htmr_registers 124 * @defgroup HTMR_RAS HTMR_RAS 125 * @brief Long Interval Alarm. 126 * @{ 127 */ 128 #define MXC_F_HTMR_RAS_RAS_POS 0 /**< RAS_RAS Position */ 129 #define MXC_F_HTMR_RAS_RAS ((uint32_t)(0xFFFFFUL << MXC_F_HTMR_RAS_RAS_POS)) /**< RAS_RAS Mask */ 130 131 /**@} end of group HTMR_RAS_Register */ 132 133 /** 134 * @ingroup htmr_registers 135 * @defgroup HTMR_RSSA HTMR_RSSA 136 * @brief HTimer Short Interval Alarm. This register contains the reload value for the 137 * short interval alarm, HTIMER_CTRL.alarm_ss_fl is raised on rollover. 138 * @{ 139 */ 140 #define MXC_F_HTMR_RSSA_RSSA_POS 0 /**< RSSA_RSSA Position */ 141 #define MXC_F_HTMR_RSSA_RSSA ((uint32_t)(0xFFFFFFFFUL << MXC_F_HTMR_RSSA_RSSA_POS)) /**< RSSA_RSSA Mask */ 142 143 /**@} end of group HTMR_RSSA_Register */ 144 145 /** 146 * @ingroup htmr_registers 147 * @defgroup HTMR_CTRL HTMR_CTRL 148 * @brief HTimer Control Register. 149 * @{ 150 */ 151 #define MXC_F_HTMR_CTRL_HTEN_POS 0 /**< CTRL_HTEN Position */ 152 #define MXC_F_HTMR_CTRL_HTEN ((uint32_t)(0x1UL << MXC_F_HTMR_CTRL_HTEN_POS)) /**< CTRL_HTEN Mask */ 153 154 #define MXC_F_HTMR_CTRL_ADE_POS 1 /**< CTRL_ADE Position */ 155 #define MXC_F_HTMR_CTRL_ADE ((uint32_t)(0x1UL << MXC_F_HTMR_CTRL_ADE_POS)) /**< CTRL_ADE Mask */ 156 157 #define MXC_F_HTMR_CTRL_ASE_POS 2 /**< CTRL_ASE Position */ 158 #define MXC_F_HTMR_CTRL_ASE ((uint32_t)(0x1UL << MXC_F_HTMR_CTRL_ASE_POS)) /**< CTRL_ASE Mask */ 159 160 #define MXC_F_HTMR_CTRL_BUSY_POS 3 /**< CTRL_BUSY Position */ 161 #define MXC_F_HTMR_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_HTMR_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */ 162 163 #define MXC_F_HTMR_CTRL_RDY_POS 4 /**< CTRL_RDY Position */ 164 #define MXC_F_HTMR_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_HTMR_CTRL_RDY_POS)) /**< CTRL_RDY Mask */ 165 166 #define MXC_F_HTMR_CTRL_RDYE_POS 5 /**< CTRL_RDYE Position */ 167 #define MXC_F_HTMR_CTRL_RDYE ((uint32_t)(0x1UL << MXC_F_HTMR_CTRL_RDYE_POS)) /**< CTRL_RDYE Mask */ 168 169 #define MXC_F_HTMR_CTRL_ALDF_POS 6 /**< CTRL_ALDF Position */ 170 #define MXC_F_HTMR_CTRL_ALDF ((uint32_t)(0x1UL << MXC_F_HTMR_CTRL_ALDF_POS)) /**< CTRL_ALDF Mask */ 171 172 #define MXC_F_HTMR_CTRL_ALSF_POS 7 /**< CTRL_ALSF Position */ 173 #define MXC_F_HTMR_CTRL_ALSF ((uint32_t)(0x1UL << MXC_F_HTMR_CTRL_ALSF_POS)) /**< CTRL_ALSF Mask */ 174 175 #define MXC_F_HTMR_CTRL_WE_POS 15 /**< CTRL_WE Position */ 176 #define MXC_F_HTMR_CTRL_WE ((uint32_t)(0x1UL << MXC_F_HTMR_CTRL_WE_POS)) /**< CTRL_WE Mask */ 177 178 /**@} end of group HTMR_CTRL_Register */ 179 180 #ifdef __cplusplus 181 } 182 #endif 183 184 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_HTMR_REGS_H_ 185
