1 /** 2 * @file flc_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup flc_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_FLC_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_FLC_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup flc 67 * @defgroup flc_registers FLC_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module. 69 * @details Flash Memory Control. 70 */ 71 72 /** 73 * @ingroup flc_registers 74 * Structure type to access the FLC Registers. 75 */ 76 typedef struct { 77 __IO uint32_t addr; /**< <tt>\b 0x00:</tt> FLC ADDR Register */ 78 __IO uint32_t clkdiv; /**< <tt>\b 0x04:</tt> FLC CLKDIV Register */ 79 __IO uint32_t cn; /**< <tt>\b 0x08:</tt> FLC CN Register */ 80 __R uint32_t rsv_0xc_0x23[6]; 81 __IO uint32_t intr; /**< <tt>\b 0x024:</tt> FLC INTR Register */ 82 __I uint32_t ecc_data; /**< <tt>\b 0x28:</tt> FLC ECC_DATA Register */ 83 __R uint32_t rsv_0x2c; 84 __IO uint32_t data[4]; /**< <tt>\b 0x30:</tt> FLC DATA Register */ 85 __O uint32_t actnl; /**< <tt>\b 0x40:</tt> FLC ACTNL Register */ 86 } mxc_flc_regs_t; 87 88 /* Register offsets for module FLC */ 89 /** 90 * @ingroup flc_registers 91 * @defgroup FLC_Register_Offsets Register Offsets 92 * @brief FLC Peripheral Register Offsets from the FLC Base Peripheral Address. 93 * @{ 94 */ 95 #define MXC_R_FLC_ADDR ((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: <tt> 0x0000</tt> */ 96 #define MXC_R_FLC_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: <tt> 0x0004</tt> */ 97 #define MXC_R_FLC_CN ((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: <tt> 0x0008</tt> */ 98 #define MXC_R_FLC_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: <tt> 0x0024</tt> */ 99 #define MXC_R_FLC_ECC_DATA ((uint32_t)0x00000028UL) /**< Offset from FLC Base Address: <tt> 0x0028</tt> */ 100 #define MXC_R_FLC_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: <tt> 0x0030</tt> */ 101 #define MXC_R_FLC_ACTNL ((uint32_t)0x00000040UL) /**< Offset from FLC Base Address: <tt> 0x0040</tt> */ 102 /**@} end of group flc_registers */ 103 104 /** 105 * @ingroup flc_registers 106 * @defgroup FLC_ADDR FLC_ADDR 107 * @brief Flash Write Address. 108 * @{ 109 */ 110 #define MXC_F_FLC_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */ 111 #define MXC_F_FLC_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */ 112 113 /**@} end of group FLC_ADDR_Register */ 114 115 /** 116 * @ingroup flc_registers 117 * @defgroup FLC_CLKDIV FLC_CLKDIV 118 * @brief Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 119 * MHz clock for Flash controller. 120 * @{ 121 */ 122 #define MXC_F_FLC_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */ 123 #define MXC_F_FLC_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */ 124 125 /**@} end of group FLC_CLKDIV_Register */ 126 127 /** 128 * @ingroup flc_registers 129 * @defgroup FLC_CN FLC_CN 130 * @brief Flash Control Register. 131 * @{ 132 */ 133 #define MXC_F_FLC_CN_WR_POS 0 /**< CN_WR Position */ 134 #define MXC_F_FLC_CN_WR ((uint32_t)(0x1UL << MXC_F_FLC_CN_WR_POS)) /**< CN_WR Mask */ 135 136 #define MXC_F_FLC_CN_ME_POS 1 /**< CN_ME Position */ 137 #define MXC_F_FLC_CN_ME ((uint32_t)(0x1UL << MXC_F_FLC_CN_ME_POS)) /**< CN_ME Mask */ 138 139 #define MXC_F_FLC_CN_PGE_POS 2 /**< CN_PGE Position */ 140 #define MXC_F_FLC_CN_PGE ((uint32_t)(0x1UL << MXC_F_FLC_CN_PGE_POS)) /**< CN_PGE Mask */ 141 142 #define MXC_F_FLC_CN_ERASE_CODE_POS 8 /**< CN_ERASE_CODE Position */ 143 #define MXC_F_FLC_CN_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_CN_ERASE_CODE_POS)) /**< CN_ERASE_CODE Mask */ 144 #define MXC_V_FLC_CN_ERASE_CODE_NOP ((uint32_t)0x0UL) /**< CN_ERASE_CODE_NOP Value */ 145 #define MXC_S_FLC_CN_ERASE_CODE_NOP (MXC_V_FLC_CN_ERASE_CODE_NOP << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_NOP Setting */ 146 #define MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL) /**< CN_ERASE_CODE_ERASEPAGE Value */ 147 #define MXC_S_FLC_CN_ERASE_CODE_ERASEPAGE (MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_ERASEPAGE Setting */ 148 #define MXC_V_FLC_CN_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL) /**< CN_ERASE_CODE_ERASEALL Value */ 149 #define MXC_S_FLC_CN_ERASE_CODE_ERASEALL (MXC_V_FLC_CN_ERASE_CODE_ERASEALL << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_ERASEALL Setting */ 150 151 #define MXC_F_FLC_CN_PEND_POS 24 /**< CN_PEND Position */ 152 #define MXC_F_FLC_CN_PEND ((uint32_t)(0x1UL << MXC_F_FLC_CN_PEND_POS)) /**< CN_PEND Mask */ 153 154 #define MXC_F_FLC_CN_UNLOCK_POS 28 /**< CN_UNLOCK Position */ 155 #define MXC_F_FLC_CN_UNLOCK ((uint32_t)(0xFUL << MXC_F_FLC_CN_UNLOCK_POS)) /**< CN_UNLOCK Mask */ 156 #define MXC_V_FLC_CN_UNLOCK_UNLOCKED ((uint32_t)0x2UL) /**< CN_UNLOCK_UNLOCKED Value */ 157 #define MXC_S_FLC_CN_UNLOCK_UNLOCKED (MXC_V_FLC_CN_UNLOCK_UNLOCKED << MXC_F_FLC_CN_UNLOCK_POS) /**< CN_UNLOCK_UNLOCKED Setting */ 158 #define MXC_V_FLC_CN_UNLOCK_LOCKED ((uint32_t)0x3UL) /**< CN_UNLOCK_LOCKED Value */ 159 #define MXC_S_FLC_CN_UNLOCK_LOCKED (MXC_V_FLC_CN_UNLOCK_LOCKED << MXC_F_FLC_CN_UNLOCK_POS) /**< CN_UNLOCK_LOCKED Setting */ 160 161 /**@} end of group FLC_CN_Register */ 162 163 /** 164 * @ingroup flc_registers 165 * @defgroup FLC_INTR FLC_INTR 166 * @brief Flash Interrupt Register. 167 * @{ 168 */ 169 #define MXC_F_FLC_INTR_DONE_POS 0 /**< INTR_DONE Position */ 170 #define MXC_F_FLC_INTR_DONE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_POS)) /**< INTR_DONE Mask */ 171 172 #define MXC_F_FLC_INTR_AF_POS 1 /**< INTR_AF Position */ 173 #define MXC_F_FLC_INTR_AF ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AF_POS)) /**< INTR_AF Mask */ 174 175 #define MXC_F_FLC_INTR_DONEIE_POS 8 /**< INTR_DONEIE Position */ 176 #define MXC_F_FLC_INTR_DONEIE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask */ 177 178 #define MXC_F_FLC_INTR_AFIE_POS 9 /**< INTR_AFIE Position */ 179 #define MXC_F_FLC_INTR_AFIE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AFIE_POS)) /**< INTR_AFIE Mask */ 180 181 /**@} end of group FLC_INTR_Register */ 182 183 /** 184 * @ingroup flc_registers 185 * @defgroup FLC_ECC_DATA FLC_ECC_DATA 186 * @brief Flash Controller ECC Data Register. 187 * @{ 188 */ 189 #define MXC_F_FLC_ECC_DATA_ECC_EVEN_POS 0 /**< ECC_DATA_ECC_EVEN Position */ 190 #define MXC_F_FLC_ECC_DATA_ECC_EVEN ((uint32_t)(0xFFUL << MXC_F_FLC_ECC_DATA_ECC_EVEN_POS)) /**< ECC_DATA_ECC_EVEN Mask */ 191 192 #define MXC_F_FLC_ECC_DATA_ECC_ODD_POS 16 /**< ECC_DATA_ECC_ODD Position */ 193 #define MXC_F_FLC_ECC_DATA_ECC_ODD ((uint32_t)(0xFFUL << MXC_F_FLC_ECC_DATA_ECC_ODD_POS)) /**< ECC_DATA_ECC_ODD Mask */ 194 195 /**@} end of group FLC_ECC_DATA_Register */ 196 197 /** 198 * @ingroup flc_registers 199 * @defgroup FLC_DATA FLC_DATA 200 * @brief Flash Write Data. 201 * @{ 202 */ 203 #define MXC_F_FLC_DATA_DATA_POS 0 /**< DATA_DATA Position */ 204 #define MXC_F_FLC_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_DATA_DATA_POS)) /**< DATA_DATA Mask */ 205 206 /**@} end of group FLC_DATA_Register */ 207 208 /** 209 * @ingroup flc_registers 210 * @defgroup FLC_ACTNL FLC_ACTNL 211 * @brief Access Control Register. Writing the ACNTL register with the following values in 212 * the order shown, allows read and write access to the system and user Information 213 * block: pflc-acntl = 0x3a7f5ca3; pflc-acntl = 0xa1e34f20; pflc-acntl = 214 * 0x9608b2c1. When unlocked, a write of any word will disable access to system and 215 * user information block. Readback of this register is always zero. 216 * @{ 217 */ 218 #define MXC_F_FLC_ACTNL_ACNTL_POS 0 /**< ACTNL_ACNTL Position */ 219 #define MXC_F_FLC_ACTNL_ACNTL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ACTNL_ACNTL_POS)) /**< ACTNL_ACNTL Mask */ 220 221 /**@} end of group FLC_ACTNL_Register */ 222 223 #ifdef __cplusplus 224 } 225 #endif 226 227 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_FLC_REGS_H_ 228
