1 /** 2 * @file dma_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup dma_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_DMA_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_DMA_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup dma 67 * @defgroup dma_registers DMA_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module. 69 * @details DMA Controller Fully programmable, chaining capable DMA channels. 70 */ 71 72 /** 73 * @ingroup dma_registers 74 * Structure type to access the DMA Registers. 75 */ 76 typedef struct { 77 __IO uint32_t cfg; /**< <tt>\b 0x000:</tt> DMA CFG Register */ 78 __IO uint32_t st; /**< <tt>\b 0x004:</tt> DMA ST Register */ 79 __IO uint32_t src; /**< <tt>\b 0x008:</tt> DMA SRC Register */ 80 __IO uint32_t dst; /**< <tt>\b 0x00C:</tt> DMA DST Register */ 81 __IO uint32_t cnt; /**< <tt>\b 0x010:</tt> DMA CNT Register */ 82 __IO uint32_t src_rld; /**< <tt>\b 0x014:</tt> DMA SRC_RLD Register */ 83 __IO uint32_t dst_rld; /**< <tt>\b 0x018:</tt> DMA DST_RLD Register */ 84 __IO uint32_t cnt_rld; /**< <tt>\b 0x01C:</tt> DMA CNT_RLD Register */ 85 } mxc_dma_ch_regs_t; 86 87 typedef struct { 88 __IO uint32_t cn; /**< <tt>\b 0x000:</tt> DMA CN Register */ 89 __I uint32_t intr; /**< <tt>\b 0x004:</tt> DMA INTR Register */ 90 __R uint32_t rsv_0x8_0xff[62]; 91 __IO mxc_dma_ch_regs_t ch[8]; /**< <tt>\b 0x100:</tt> DMA CH Register */ 92 } mxc_dma_regs_t; 93 94 /* Register offsets for module DMA */ 95 /** 96 * @ingroup dma_registers 97 * @defgroup DMA_Register_Offsets Register Offsets 98 * @brief DMA Peripheral Register Offsets from the DMA Base Peripheral Address. 99 * @{ 100 */ 101 #define MXC_R_DMA_CFG ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: <tt> 0x0000</tt> */ 102 #define MXC_R_DMA_ST ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: <tt> 0x0004</tt> */ 103 #define MXC_R_DMA_SRC ((uint32_t)0x00000008UL) /**< Offset from DMA Base Address: <tt> 0x0008</tt> */ 104 #define MXC_R_DMA_DST ((uint32_t)0x0000000CUL) /**< Offset from DMA Base Address: <tt> 0x000C</tt> */ 105 #define MXC_R_DMA_CNT ((uint32_t)0x00000010UL) /**< Offset from DMA Base Address: <tt> 0x0010</tt> */ 106 #define MXC_R_DMA_SRC_RLD ((uint32_t)0x00000014UL) /**< Offset from DMA Base Address: <tt> 0x0014</tt> */ 107 #define MXC_R_DMA_DST_RLD ((uint32_t)0x00000018UL) /**< Offset from DMA Base Address: <tt> 0x0018</tt> */ 108 #define MXC_R_DMA_CNT_RLD ((uint32_t)0x0000001CUL) /**< Offset from DMA Base Address: <tt> 0x001C</tt> */ 109 #define MXC_R_DMA_CN ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: <tt> 0x0000</tt> */ 110 #define MXC_R_DMA_INTR ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: <tt> 0x0004</tt> */ 111 #define MXC_R_DMA_CH ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */ 112 /**@} end of group dma_registers */ 113 114 /** 115 * @ingroup dma_registers 116 * @defgroup DMA_CN DMA_CN 117 * @brief DMA Control Register. 118 * @{ 119 */ 120 #define MXC_F_DMA_CN_CH0_IEN_POS 0 /**< CN_CH0_IEN Position */ 121 #define MXC_F_DMA_CN_CH0_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH0_IEN_POS)) /**< CN_CH0_IEN Mask */ 122 123 #define MXC_F_DMA_CN_CH1_IEN_POS 1 /**< CN_CH1_IEN Position */ 124 #define MXC_F_DMA_CN_CH1_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH1_IEN_POS)) /**< CN_CH1_IEN Mask */ 125 126 #define MXC_F_DMA_CN_CH2_IEN_POS 2 /**< CN_CH2_IEN Position */ 127 #define MXC_F_DMA_CN_CH2_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH2_IEN_POS)) /**< CN_CH2_IEN Mask */ 128 129 #define MXC_F_DMA_CN_CH3_IEN_POS 3 /**< CN_CH3_IEN Position */ 130 #define MXC_F_DMA_CN_CH3_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH3_IEN_POS)) /**< CN_CH3_IEN Mask */ 131 132 #define MXC_F_DMA_CN_CH4_IEN_POS 4 /**< CN_CH4_IEN Position */ 133 #define MXC_F_DMA_CN_CH4_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH4_IEN_POS)) /**< CN_CH4_IEN Mask */ 134 135 #define MXC_F_DMA_CN_CH5_IEN_POS 5 /**< CN_CH5_IEN Position */ 136 #define MXC_F_DMA_CN_CH5_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH5_IEN_POS)) /**< CN_CH5_IEN Mask */ 137 138 #define MXC_F_DMA_CN_CH6_IEN_POS 6 /**< CN_CH6_IEN Position */ 139 #define MXC_F_DMA_CN_CH6_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH6_IEN_POS)) /**< CN_CH6_IEN Mask */ 140 141 #define MXC_F_DMA_CN_CH7_IEN_POS 7 /**< CN_CH7_IEN Position */ 142 #define MXC_F_DMA_CN_CH7_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH7_IEN_POS)) /**< CN_CH7_IEN Mask */ 143 144 /**@} end of group DMA_CN_Register */ 145 146 /** 147 * @ingroup dma_registers 148 * @defgroup DMA_INTR DMA_INTR 149 * @brief DMA Interrupt Register. 150 * @{ 151 */ 152 #define MXC_F_DMA_INTR_CH0_IPEND_POS 0 /**< INTR_CH0_IPEND Position */ 153 #define MXC_F_DMA_INTR_CH0_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH0_IPEND_POS)) /**< INTR_CH0_IPEND Mask */ 154 155 #define MXC_F_DMA_INTR_CH1_IPEND_POS 1 /**< INTR_CH1_IPEND Position */ 156 #define MXC_F_DMA_INTR_CH1_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH1_IPEND_POS)) /**< INTR_CH1_IPEND Mask */ 157 158 #define MXC_F_DMA_INTR_CH2_IPEND_POS 2 /**< INTR_CH2_IPEND Position */ 159 #define MXC_F_DMA_INTR_CH2_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH2_IPEND_POS)) /**< INTR_CH2_IPEND Mask */ 160 161 #define MXC_F_DMA_INTR_CH3_IPEND_POS 3 /**< INTR_CH3_IPEND Position */ 162 #define MXC_F_DMA_INTR_CH3_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH3_IPEND_POS)) /**< INTR_CH3_IPEND Mask */ 163 164 #define MXC_F_DMA_INTR_CH4_IPEND_POS 4 /**< INTR_CH4_IPEND Position */ 165 #define MXC_F_DMA_INTR_CH4_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH4_IPEND_POS)) /**< INTR_CH4_IPEND Mask */ 166 167 #define MXC_F_DMA_INTR_CH5_IPEND_POS 5 /**< INTR_CH5_IPEND Position */ 168 #define MXC_F_DMA_INTR_CH5_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH5_IPEND_POS)) /**< INTR_CH5_IPEND Mask */ 169 170 #define MXC_F_DMA_INTR_CH6_IPEND_POS 6 /**< INTR_CH6_IPEND Position */ 171 #define MXC_F_DMA_INTR_CH6_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH6_IPEND_POS)) /**< INTR_CH6_IPEND Mask */ 172 173 #define MXC_F_DMA_INTR_CH7_IPEND_POS 7 /**< INTR_CH7_IPEND Position */ 174 #define MXC_F_DMA_INTR_CH7_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH7_IPEND_POS)) /**< INTR_CH7_IPEND Mask */ 175 176 /**@} end of group DMA_INTR_Register */ 177 178 /** 179 * @ingroup dma_registers 180 * @defgroup DMA_CFG DMA_CFG 181 * @brief DMA Channel Configuration Register. 182 * @{ 183 */ 184 #define MXC_F_DMA_CFG_CHEN_POS 0 /**< CFG_CHEN Position */ 185 #define MXC_F_DMA_CFG_CHEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CHEN_POS)) /**< CFG_CHEN Mask */ 186 187 #define MXC_F_DMA_CFG_RLDEN_POS 1 /**< CFG_RLDEN Position */ 188 #define MXC_F_DMA_CFG_RLDEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_RLDEN_POS)) /**< CFG_RLDEN Mask */ 189 190 #define MXC_F_DMA_CFG_PRI_POS 2 /**< CFG_PRI Position */ 191 #define MXC_F_DMA_CFG_PRI ((uint32_t)(0x3UL << MXC_F_DMA_CFG_PRI_POS)) /**< CFG_PRI Mask */ 192 #define MXC_V_DMA_CFG_PRI_HIGH ((uint32_t)0x0UL) /**< CFG_PRI_HIGH Value */ 193 #define MXC_S_DMA_CFG_PRI_HIGH (MXC_V_DMA_CFG_PRI_HIGH << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_HIGH Setting */ 194 #define MXC_V_DMA_CFG_PRI_MEDHIGH ((uint32_t)0x1UL) /**< CFG_PRI_MEDHIGH Value */ 195 #define MXC_S_DMA_CFG_PRI_MEDHIGH (MXC_V_DMA_CFG_PRI_MEDHIGH << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_MEDHIGH Setting */ 196 #define MXC_V_DMA_CFG_PRI_MEDLOW ((uint32_t)0x2UL) /**< CFG_PRI_MEDLOW Value */ 197 #define MXC_S_DMA_CFG_PRI_MEDLOW (MXC_V_DMA_CFG_PRI_MEDLOW << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_MEDLOW Setting */ 198 #define MXC_V_DMA_CFG_PRI_LOW ((uint32_t)0x3UL) /**< CFG_PRI_LOW Value */ 199 #define MXC_S_DMA_CFG_PRI_LOW (MXC_V_DMA_CFG_PRI_LOW << MXC_F_DMA_CFG_PRI_POS) /**< CFG_PRI_LOW Setting */ 200 201 #define MXC_F_DMA_CFG_REQSEL_POS 4 /**< CFG_REQSEL Position */ 202 #define MXC_F_DMA_CFG_REQSEL ((uint32_t)(0x3FUL << MXC_F_DMA_CFG_REQSEL_POS)) /**< CFG_REQSEL Mask */ 203 #define MXC_V_DMA_CFG_REQSEL_MEMTOMEM ((uint32_t)0x0UL) /**< CFG_REQSEL_MEMTOMEM Value */ 204 #define MXC_S_DMA_CFG_REQSEL_MEMTOMEM (MXC_V_DMA_CFG_REQSEL_MEMTOMEM << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_MEMTOMEM Setting */ 205 #define MXC_V_DMA_CFG_REQSEL_SPI1RX ((uint32_t)0x1UL) /**< CFG_REQSEL_SPI1RX Value */ 206 #define MXC_S_DMA_CFG_REQSEL_SPI1RX (MXC_V_DMA_CFG_REQSEL_SPI1RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI1RX Setting */ 207 #define MXC_V_DMA_CFG_REQSEL_SPI2RX ((uint32_t)0x2UL) /**< CFG_REQSEL_SPI2RX Value */ 208 #define MXC_S_DMA_CFG_REQSEL_SPI2RX (MXC_V_DMA_CFG_REQSEL_SPI2RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI2RX Setting */ 209 #define MXC_V_DMA_CFG_REQSEL_UART0RX ((uint32_t)0x4UL) /**< CFG_REQSEL_UART0RX Value */ 210 #define MXC_S_DMA_CFG_REQSEL_UART0RX (MXC_V_DMA_CFG_REQSEL_UART0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART0RX Setting */ 211 #define MXC_V_DMA_CFG_REQSEL_UART1RX ((uint32_t)0x5UL) /**< CFG_REQSEL_UART1RX Value */ 212 #define MXC_S_DMA_CFG_REQSEL_UART1RX (MXC_V_DMA_CFG_REQSEL_UART1RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART1RX Setting */ 213 #define MXC_V_DMA_CFG_REQSEL_I2C0RX ((uint32_t)0x7UL) /**< CFG_REQSEL_I2C0RX Value */ 214 #define MXC_S_DMA_CFG_REQSEL_I2C0RX (MXC_V_DMA_CFG_REQSEL_I2C0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C0RX Setting */ 215 #define MXC_V_DMA_CFG_REQSEL_I2C1RX ((uint32_t)0x8UL) /**< CFG_REQSEL_I2C1RX Value */ 216 #define MXC_S_DMA_CFG_REQSEL_I2C1RX (MXC_V_DMA_CFG_REQSEL_I2C1RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C1RX Setting */ 217 #define MXC_V_DMA_CFG_REQSEL_ADC ((uint32_t)0x9UL) /**< CFG_REQSEL_ADC Value */ 218 #define MXC_S_DMA_CFG_REQSEL_ADC (MXC_V_DMA_CFG_REQSEL_ADC << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_ADC Setting */ 219 #define MXC_V_DMA_CFG_REQSEL_I2C2RX ((uint32_t)0xAUL) /**< CFG_REQSEL_I2C2RX Value */ 220 #define MXC_S_DMA_CFG_REQSEL_I2C2RX (MXC_V_DMA_CFG_REQSEL_I2C2RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C2RX Setting */ 221 #define MXC_V_DMA_CFG_REQSEL_UART2RX ((uint32_t)0xEUL) /**< CFG_REQSEL_UART2RX Value */ 222 #define MXC_S_DMA_CFG_REQSEL_UART2RX (MXC_V_DMA_CFG_REQSEL_UART2RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART2RX Setting */ 223 #define MXC_V_DMA_CFG_REQSEL_SPI0RX ((uint32_t)0xFUL) /**< CFG_REQSEL_SPI0RX Value */ 224 #define MXC_S_DMA_CFG_REQSEL_SPI0RX (MXC_V_DMA_CFG_REQSEL_SPI0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI0RX Setting */ 225 #define MXC_V_DMA_CFG_REQSEL_USBRXEP1 ((uint32_t)0x11UL) /**< CFG_REQSEL_USBRXEP1 Value */ 226 #define MXC_S_DMA_CFG_REQSEL_USBRXEP1 (MXC_V_DMA_CFG_REQSEL_USBRXEP1 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBRXEP1 Setting */ 227 #define MXC_V_DMA_CFG_REQSEL_USBRXEP2 ((uint32_t)0x12UL) /**< CFG_REQSEL_USBRXEP2 Value */ 228 #define MXC_S_DMA_CFG_REQSEL_USBRXEP2 (MXC_V_DMA_CFG_REQSEL_USBRXEP2 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBRXEP2 Setting */ 229 #define MXC_V_DMA_CFG_REQSEL_USBRXEP3 ((uint32_t)0x13UL) /**< CFG_REQSEL_USBRXEP3 Value */ 230 #define MXC_S_DMA_CFG_REQSEL_USBRXEP3 (MXC_V_DMA_CFG_REQSEL_USBRXEP3 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBRXEP3 Setting */ 231 #define MXC_V_DMA_CFG_REQSEL_USBRXEP4 ((uint32_t)0x14UL) /**< CFG_REQSEL_USBRXEP4 Value */ 232 #define MXC_S_DMA_CFG_REQSEL_USBRXEP4 (MXC_V_DMA_CFG_REQSEL_USBRXEP4 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBRXEP4 Setting */ 233 #define MXC_V_DMA_CFG_REQSEL_USBRXEP5 ((uint32_t)0x15UL) /**< CFG_REQSEL_USBRXEP5 Value */ 234 #define MXC_S_DMA_CFG_REQSEL_USBRXEP5 (MXC_V_DMA_CFG_REQSEL_USBRXEP5 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBRXEP5 Setting */ 235 #define MXC_V_DMA_CFG_REQSEL_USBRXEP6 ((uint32_t)0x16UL) /**< CFG_REQSEL_USBRXEP6 Value */ 236 #define MXC_S_DMA_CFG_REQSEL_USBRXEP6 (MXC_V_DMA_CFG_REQSEL_USBRXEP6 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBRXEP6 Setting */ 237 #define MXC_V_DMA_CFG_REQSEL_USBRXEP7 ((uint32_t)0x17UL) /**< CFG_REQSEL_USBRXEP7 Value */ 238 #define MXC_S_DMA_CFG_REQSEL_USBRXEP7 (MXC_V_DMA_CFG_REQSEL_USBRXEP7 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBRXEP7 Setting */ 239 #define MXC_V_DMA_CFG_REQSEL_USBRXEP8 ((uint32_t)0x18UL) /**< CFG_REQSEL_USBRXEP8 Value */ 240 #define MXC_S_DMA_CFG_REQSEL_USBRXEP8 (MXC_V_DMA_CFG_REQSEL_USBRXEP8 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBRXEP8 Setting */ 241 #define MXC_V_DMA_CFG_REQSEL_USBRXEP9 ((uint32_t)0x19UL) /**< CFG_REQSEL_USBRXEP9 Value */ 242 #define MXC_S_DMA_CFG_REQSEL_USBRXEP9 (MXC_V_DMA_CFG_REQSEL_USBRXEP9 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBRXEP9 Setting */ 243 #define MXC_V_DMA_CFG_REQSEL_USBRXEP10 ((uint32_t)0x1AUL) /**< CFG_REQSEL_USBRXEP10 Value */ 244 #define MXC_S_DMA_CFG_REQSEL_USBRXEP10 (MXC_V_DMA_CFG_REQSEL_USBRXEP10 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBRXEP10 Setting */ 245 #define MXC_V_DMA_CFG_REQSEL_USBRXEP11 ((uint32_t)0x1BUL) /**< CFG_REQSEL_USBRXEP11 Value */ 246 #define MXC_S_DMA_CFG_REQSEL_USBRXEP11 (MXC_V_DMA_CFG_REQSEL_USBRXEP11 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBRXEP11 Setting */ 247 #define MXC_V_DMA_CFG_REQSEL_SPI1TX ((uint32_t)0x21UL) /**< CFG_REQSEL_SPI1TX Value */ 248 #define MXC_S_DMA_CFG_REQSEL_SPI1TX (MXC_V_DMA_CFG_REQSEL_SPI1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI1TX Setting */ 249 #define MXC_V_DMA_CFG_REQSEL_SPI2TX ((uint32_t)0x22UL) /**< CFG_REQSEL_SPI2TX Value */ 250 #define MXC_S_DMA_CFG_REQSEL_SPI2TX (MXC_V_DMA_CFG_REQSEL_SPI2TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI2TX Setting */ 251 #define MXC_V_DMA_CFG_REQSEL_UART0TX ((uint32_t)0x24UL) /**< CFG_REQSEL_UART0TX Value */ 252 #define MXC_S_DMA_CFG_REQSEL_UART0TX (MXC_V_DMA_CFG_REQSEL_UART0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART0TX Setting */ 253 #define MXC_V_DMA_CFG_REQSEL_UART1TX ((uint32_t)0x25UL) /**< CFG_REQSEL_UART1TX Value */ 254 #define MXC_S_DMA_CFG_REQSEL_UART1TX (MXC_V_DMA_CFG_REQSEL_UART1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART1TX Setting */ 255 #define MXC_V_DMA_CFG_REQSEL_I2C0TX ((uint32_t)0x27UL) /**< CFG_REQSEL_I2C0TX Value */ 256 #define MXC_S_DMA_CFG_REQSEL_I2C0TX (MXC_V_DMA_CFG_REQSEL_I2C0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C0TX Setting */ 257 #define MXC_V_DMA_CFG_REQSEL_I2C1TX ((uint32_t)0x28UL) /**< CFG_REQSEL_I2C1TX Value */ 258 #define MXC_S_DMA_CFG_REQSEL_I2C1TX (MXC_V_DMA_CFG_REQSEL_I2C1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C1TX Setting */ 259 #define MXC_V_DMA_CFG_REQSEL_I2C2TX ((uint32_t)0x2AUL) /**< CFG_REQSEL_I2C2TX Value */ 260 #define MXC_S_DMA_CFG_REQSEL_I2C2TX (MXC_V_DMA_CFG_REQSEL_I2C2TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C2TX Setting */ 261 #define MXC_V_DMA_CFG_REQSEL_UART2TX ((uint32_t)0x2EUL) /**< CFG_REQSEL_UART2TX Value */ 262 #define MXC_S_DMA_CFG_REQSEL_UART2TX (MXC_V_DMA_CFG_REQSEL_UART2TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART2TX Setting */ 263 #define MXC_V_DMA_CFG_REQSEL_SPI0TX ((uint32_t)0x2FUL) /**< CFG_REQSEL_SPI0TX Value */ 264 #define MXC_S_DMA_CFG_REQSEL_SPI0TX (MXC_V_DMA_CFG_REQSEL_SPI0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI0TX Setting */ 265 #define MXC_V_DMA_CFG_REQSEL_USBTXEP1 ((uint32_t)0x31UL) /**< CFG_REQSEL_USBTXEP1 Value */ 266 #define MXC_S_DMA_CFG_REQSEL_USBTXEP1 (MXC_V_DMA_CFG_REQSEL_USBTXEP1 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBTXEP1 Setting */ 267 #define MXC_V_DMA_CFG_REQSEL_USBTXEP2 ((uint32_t)0x32UL) /**< CFG_REQSEL_USBTXEP2 Value */ 268 #define MXC_S_DMA_CFG_REQSEL_USBTXEP2 (MXC_V_DMA_CFG_REQSEL_USBTXEP2 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBTXEP2 Setting */ 269 #define MXC_V_DMA_CFG_REQSEL_USBTXEP3 ((uint32_t)0x33UL) /**< CFG_REQSEL_USBTXEP3 Value */ 270 #define MXC_S_DMA_CFG_REQSEL_USBTXEP3 (MXC_V_DMA_CFG_REQSEL_USBTXEP3 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBTXEP3 Setting */ 271 #define MXC_V_DMA_CFG_REQSEL_USBTXEP4 ((uint32_t)0x34UL) /**< CFG_REQSEL_USBTXEP4 Value */ 272 #define MXC_S_DMA_CFG_REQSEL_USBTXEP4 (MXC_V_DMA_CFG_REQSEL_USBTXEP4 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBTXEP4 Setting */ 273 #define MXC_V_DMA_CFG_REQSEL_USBTXEP5 ((uint32_t)0x35UL) /**< CFG_REQSEL_USBTXEP5 Value */ 274 #define MXC_S_DMA_CFG_REQSEL_USBTXEP5 (MXC_V_DMA_CFG_REQSEL_USBTXEP5 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBTXEP5 Setting */ 275 #define MXC_V_DMA_CFG_REQSEL_USBTXEP6 ((uint32_t)0x36UL) /**< CFG_REQSEL_USBTXEP6 Value */ 276 #define MXC_S_DMA_CFG_REQSEL_USBTXEP6 (MXC_V_DMA_CFG_REQSEL_USBTXEP6 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBTXEP6 Setting */ 277 #define MXC_V_DMA_CFG_REQSEL_USBTXEP7 ((uint32_t)0x37UL) /**< CFG_REQSEL_USBTXEP7 Value */ 278 #define MXC_S_DMA_CFG_REQSEL_USBTXEP7 (MXC_V_DMA_CFG_REQSEL_USBTXEP7 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBTXEP7 Setting */ 279 #define MXC_V_DMA_CFG_REQSEL_USBTXEP8 ((uint32_t)0x38UL) /**< CFG_REQSEL_USBTXEP8 Value */ 280 #define MXC_S_DMA_CFG_REQSEL_USBTXEP8 (MXC_V_DMA_CFG_REQSEL_USBTXEP8 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBTXEP8 Setting */ 281 #define MXC_V_DMA_CFG_REQSEL_USBTXEP9 ((uint32_t)0x39UL) /**< CFG_REQSEL_USBTXEP9 Value */ 282 #define MXC_S_DMA_CFG_REQSEL_USBTXEP9 (MXC_V_DMA_CFG_REQSEL_USBTXEP9 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBTXEP9 Setting */ 283 #define MXC_V_DMA_CFG_REQSEL_USBTXEP10 ((uint32_t)0x3AUL) /**< CFG_REQSEL_USBTXEP10 Value */ 284 #define MXC_S_DMA_CFG_REQSEL_USBTXEP10 (MXC_V_DMA_CFG_REQSEL_USBTXEP10 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBTXEP10 Setting */ 285 #define MXC_V_DMA_CFG_REQSEL_USBTXEP11 ((uint32_t)0x3BUL) /**< CFG_REQSEL_USBTXEP11 Value */ 286 #define MXC_S_DMA_CFG_REQSEL_USBTXEP11 (MXC_V_DMA_CFG_REQSEL_USBTXEP11 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBTXEP11 Setting */ 287 288 #define MXC_F_DMA_CFG_REQWAIT_POS 10 /**< CFG_REQWAIT Position */ 289 #define MXC_F_DMA_CFG_REQWAIT ((uint32_t)(0x1UL << MXC_F_DMA_CFG_REQWAIT_POS)) /**< CFG_REQWAIT Mask */ 290 291 #define MXC_F_DMA_CFG_TOSEL_POS 11 /**< CFG_TOSEL Position */ 292 #define MXC_F_DMA_CFG_TOSEL ((uint32_t)(0x7UL << MXC_F_DMA_CFG_TOSEL_POS)) /**< CFG_TOSEL Mask */ 293 #define MXC_V_DMA_CFG_TOSEL_TO4 ((uint32_t)0x0UL) /**< CFG_TOSEL_TO4 Value */ 294 #define MXC_S_DMA_CFG_TOSEL_TO4 (MXC_V_DMA_CFG_TOSEL_TO4 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO4 Setting */ 295 #define MXC_V_DMA_CFG_TOSEL_TO8 ((uint32_t)0x1UL) /**< CFG_TOSEL_TO8 Value */ 296 #define MXC_S_DMA_CFG_TOSEL_TO8 (MXC_V_DMA_CFG_TOSEL_TO8 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO8 Setting */ 297 #define MXC_V_DMA_CFG_TOSEL_TO16 ((uint32_t)0x2UL) /**< CFG_TOSEL_TO16 Value */ 298 #define MXC_S_DMA_CFG_TOSEL_TO16 (MXC_V_DMA_CFG_TOSEL_TO16 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO16 Setting */ 299 #define MXC_V_DMA_CFG_TOSEL_TO32 ((uint32_t)0x3UL) /**< CFG_TOSEL_TO32 Value */ 300 #define MXC_S_DMA_CFG_TOSEL_TO32 (MXC_V_DMA_CFG_TOSEL_TO32 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO32 Setting */ 301 #define MXC_V_DMA_CFG_TOSEL_TO64 ((uint32_t)0x4UL) /**< CFG_TOSEL_TO64 Value */ 302 #define MXC_S_DMA_CFG_TOSEL_TO64 (MXC_V_DMA_CFG_TOSEL_TO64 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO64 Setting */ 303 #define MXC_V_DMA_CFG_TOSEL_TO128 ((uint32_t)0x5UL) /**< CFG_TOSEL_TO128 Value */ 304 #define MXC_S_DMA_CFG_TOSEL_TO128 (MXC_V_DMA_CFG_TOSEL_TO128 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO128 Setting */ 305 #define MXC_V_DMA_CFG_TOSEL_TO256 ((uint32_t)0x6UL) /**< CFG_TOSEL_TO256 Value */ 306 #define MXC_S_DMA_CFG_TOSEL_TO256 (MXC_V_DMA_CFG_TOSEL_TO256 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO256 Setting */ 307 #define MXC_V_DMA_CFG_TOSEL_TO512 ((uint32_t)0x7UL) /**< CFG_TOSEL_TO512 Value */ 308 #define MXC_S_DMA_CFG_TOSEL_TO512 (MXC_V_DMA_CFG_TOSEL_TO512 << MXC_F_DMA_CFG_TOSEL_POS) /**< CFG_TOSEL_TO512 Setting */ 309 310 #define MXC_F_DMA_CFG_PSSEL_POS 14 /**< CFG_PSSEL Position */ 311 #define MXC_F_DMA_CFG_PSSEL ((uint32_t)(0x3UL << MXC_F_DMA_CFG_PSSEL_POS)) /**< CFG_PSSEL Mask */ 312 #define MXC_V_DMA_CFG_PSSEL_DIS ((uint32_t)0x0UL) /**< CFG_PSSEL_DIS Value */ 313 #define MXC_S_DMA_CFG_PSSEL_DIS (MXC_V_DMA_CFG_PSSEL_DIS << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIS Setting */ 314 #define MXC_V_DMA_CFG_PSSEL_DIV256 ((uint32_t)0x1UL) /**< CFG_PSSEL_DIV256 Value */ 315 #define MXC_S_DMA_CFG_PSSEL_DIV256 (MXC_V_DMA_CFG_PSSEL_DIV256 << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIV256 Setting */ 316 #define MXC_V_DMA_CFG_PSSEL_DIV64K ((uint32_t)0x2UL) /**< CFG_PSSEL_DIV64K Value */ 317 #define MXC_S_DMA_CFG_PSSEL_DIV64K (MXC_V_DMA_CFG_PSSEL_DIV64K << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIV64K Setting */ 318 #define MXC_V_DMA_CFG_PSSEL_DIV16M ((uint32_t)0x3UL) /**< CFG_PSSEL_DIV16M Value */ 319 #define MXC_S_DMA_CFG_PSSEL_DIV16M (MXC_V_DMA_CFG_PSSEL_DIV16M << MXC_F_DMA_CFG_PSSEL_POS) /**< CFG_PSSEL_DIV16M Setting */ 320 321 #define MXC_F_DMA_CFG_SRCWD_POS 16 /**< CFG_SRCWD Position */ 322 #define MXC_F_DMA_CFG_SRCWD ((uint32_t)(0x3UL << MXC_F_DMA_CFG_SRCWD_POS)) /**< CFG_SRCWD Mask */ 323 #define MXC_V_DMA_CFG_SRCWD_BYTE ((uint32_t)0x0UL) /**< CFG_SRCWD_BYTE Value */ 324 #define MXC_S_DMA_CFG_SRCWD_BYTE (MXC_V_DMA_CFG_SRCWD_BYTE << MXC_F_DMA_CFG_SRCWD_POS) /**< CFG_SRCWD_BYTE Setting */ 325 #define MXC_V_DMA_CFG_SRCWD_HALFWORD ((uint32_t)0x1UL) /**< CFG_SRCWD_HALFWORD Value */ 326 #define MXC_S_DMA_CFG_SRCWD_HALFWORD (MXC_V_DMA_CFG_SRCWD_HALFWORD << MXC_F_DMA_CFG_SRCWD_POS) /**< CFG_SRCWD_HALFWORD Setting */ 327 #define MXC_V_DMA_CFG_SRCWD_WORD ((uint32_t)0x2UL) /**< CFG_SRCWD_WORD Value */ 328 #define MXC_S_DMA_CFG_SRCWD_WORD (MXC_V_DMA_CFG_SRCWD_WORD << MXC_F_DMA_CFG_SRCWD_POS) /**< CFG_SRCWD_WORD Setting */ 329 330 #define MXC_F_DMA_CFG_SRINC_POS 18 /**< CFG_SRINC Position */ 331 #define MXC_F_DMA_CFG_SRINC ((uint32_t)(0x1UL << MXC_F_DMA_CFG_SRINC_POS)) /**< CFG_SRINC Mask */ 332 333 #define MXC_F_DMA_CFG_DSTWD_POS 20 /**< CFG_DSTWD Position */ 334 #define MXC_F_DMA_CFG_DSTWD ((uint32_t)(0x3UL << MXC_F_DMA_CFG_DSTWD_POS)) /**< CFG_DSTWD Mask */ 335 #define MXC_V_DMA_CFG_DSTWD_BYTE ((uint32_t)0x0UL) /**< CFG_DSTWD_BYTE Value */ 336 #define MXC_S_DMA_CFG_DSTWD_BYTE (MXC_V_DMA_CFG_DSTWD_BYTE << MXC_F_DMA_CFG_DSTWD_POS) /**< CFG_DSTWD_BYTE Setting */ 337 #define MXC_V_DMA_CFG_DSTWD_HALFWORD ((uint32_t)0x1UL) /**< CFG_DSTWD_HALFWORD Value */ 338 #define MXC_S_DMA_CFG_DSTWD_HALFWORD (MXC_V_DMA_CFG_DSTWD_HALFWORD << MXC_F_DMA_CFG_DSTWD_POS) /**< CFG_DSTWD_HALFWORD Setting */ 339 #define MXC_V_DMA_CFG_DSTWD_WORD ((uint32_t)0x2UL) /**< CFG_DSTWD_WORD Value */ 340 #define MXC_S_DMA_CFG_DSTWD_WORD (MXC_V_DMA_CFG_DSTWD_WORD << MXC_F_DMA_CFG_DSTWD_POS) /**< CFG_DSTWD_WORD Setting */ 341 342 #define MXC_F_DMA_CFG_DISTINC_POS 22 /**< CFG_DISTINC Position */ 343 #define MXC_F_DMA_CFG_DISTINC ((uint32_t)(0x1UL << MXC_F_DMA_CFG_DISTINC_POS)) /**< CFG_DISTINC Mask */ 344 345 #define MXC_F_DMA_CFG_BRST_POS 24 /**< CFG_BRST Position */ 346 #define MXC_F_DMA_CFG_BRST ((uint32_t)(0x1FUL << MXC_F_DMA_CFG_BRST_POS)) /**< CFG_BRST Mask */ 347 348 #define MXC_F_DMA_CFG_CHDIEN_POS 30 /**< CFG_CHDIEN Position */ 349 #define MXC_F_DMA_CFG_CHDIEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CHDIEN_POS)) /**< CFG_CHDIEN Mask */ 350 351 #define MXC_F_DMA_CFG_CTZIEN_POS 31 /**< CFG_CTZIEN Position */ 352 #define MXC_F_DMA_CFG_CTZIEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CTZIEN_POS)) /**< CFG_CTZIEN Mask */ 353 354 /**@} end of group DMA_CFG_Register */ 355 356 /** 357 * @ingroup dma_registers 358 * @defgroup DMA_ST DMA_ST 359 * @brief DMA Channel Status Register. 360 * @{ 361 */ 362 #define MXC_F_DMA_ST_CH_ST_POS 0 /**< ST_CH_ST Position */ 363 #define MXC_F_DMA_ST_CH_ST ((uint32_t)(0x1UL << MXC_F_DMA_ST_CH_ST_POS)) /**< ST_CH_ST Mask */ 364 365 #define MXC_F_DMA_ST_IPEND_POS 1 /**< ST_IPEND Position */ 366 #define MXC_F_DMA_ST_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_ST_IPEND_POS)) /**< ST_IPEND Mask */ 367 368 #define MXC_F_DMA_ST_CTZ_ST_POS 2 /**< ST_CTZ_ST Position */ 369 #define MXC_F_DMA_ST_CTZ_ST ((uint32_t)(0x1UL << MXC_F_DMA_ST_CTZ_ST_POS)) /**< ST_CTZ_ST Mask */ 370 371 #define MXC_F_DMA_ST_RLD_ST_POS 3 /**< ST_RLD_ST Position */ 372 #define MXC_F_DMA_ST_RLD_ST ((uint32_t)(0x1UL << MXC_F_DMA_ST_RLD_ST_POS)) /**< ST_RLD_ST Mask */ 373 374 #define MXC_F_DMA_ST_BUS_ERR_POS 4 /**< ST_BUS_ERR Position */ 375 #define MXC_F_DMA_ST_BUS_ERR ((uint32_t)(0x1UL << MXC_F_DMA_ST_BUS_ERR_POS)) /**< ST_BUS_ERR Mask */ 376 377 #define MXC_F_DMA_ST_TO_ST_POS 6 /**< ST_TO_ST Position */ 378 #define MXC_F_DMA_ST_TO_ST ((uint32_t)(0x1UL << MXC_F_DMA_ST_TO_ST_POS)) /**< ST_TO_ST Mask */ 379 380 /**@} end of group DMA_ST_Register */ 381 382 /** 383 * @ingroup dma_registers 384 * @defgroup DMA_SRC DMA_SRC 385 * @brief Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 386 * 4, depending on the data width of each AHB cycle. For peripheral transfers, some 387 * or all of the actual address bits are fixed. If SRCINC=0, this register remains 388 * constant. In the case where a count-to-zero condition occurs while RLDEN=1, the 389 * register is reloaded with the contents of DMA_SRC_RLD. 390 * @{ 391 */ 392 #define MXC_F_DMA_SRC_ADDR_POS 0 /**< SRC_ADDR Position */ 393 #define MXC_F_DMA_SRC_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_SRC_ADDR_POS)) /**< SRC_ADDR Mask */ 394 395 /**@} end of group DMA_SRC_Register */ 396 397 /** 398 * @ingroup dma_registers 399 * @defgroup DMA_DST DMA_DST 400 * @brief Destination Device Address. For peripheral transfers, some or all of the actual 401 * address bits are fixed. If DSTINC=1, this register is incremented on every AHB 402 * write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the 403 * data width of each AHB cycle. In the case where a count-to-zero condition occurs 404 * while RLDEN=1, the register is reloaded with DMA_DST_RLD. 405 * @{ 406 */ 407 #define MXC_F_DMA_DST_ADDR_POS 0 /**< DST_ADDR Position */ 408 #define MXC_F_DMA_DST_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_DST_ADDR_POS)) /**< DST_ADDR Mask */ 409 410 /**@} end of group DMA_DST_Register */ 411 412 /** 413 * @ingroup dma_registers 414 * @defgroup DMA_CNT DMA_CNT 415 * @brief DMA Counter. The user loads this register with the number of bytes to transfer. 416 * This counter decreases on every AHB cycle into the DMA FIFO. The decrement will 417 * be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter 418 * reaches 0, a count-to-zero condition is triggered. 419 * @{ 420 */ 421 #define MXC_F_DMA_CNT_CNT_POS 0 /**< CNT_CNT Position */ 422 #define MXC_F_DMA_CNT_CNT ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNT_CNT_POS)) /**< CNT_CNT Mask */ 423 424 /**@} end of group DMA_CNT_Register */ 425 426 /** 427 * @ingroup dma_registers 428 * @defgroup DMA_SRC_RLD DMA_SRC_RLD 429 * @brief Source Address Reload Value. The value of this register is loaded into DMA0_SRC 430 * upon a count-to-zero condition. 431 * @{ 432 */ 433 #define MXC_F_DMA_SRC_RLD_SRC_RLD_POS 0 /**< SRC_RLD_SRC_RLD Position */ 434 #define MXC_F_DMA_SRC_RLD_SRC_RLD ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_SRC_RLD_SRC_RLD_POS)) /**< SRC_RLD_SRC_RLD Mask */ 435 436 /**@} end of group DMA_SRC_RLD_Register */ 437 438 /** 439 * @ingroup dma_registers 440 * @defgroup DMA_DST_RLD DMA_DST_RLD 441 * @brief Destination Address Reload Value. The value of this register is loaded into 442 * DMA0_DST upon a count-to-zero condition. 443 * @{ 444 */ 445 #define MXC_F_DMA_DST_RLD_DST_RLD_POS 0 /**< DST_RLD_DST_RLD Position */ 446 #define MXC_F_DMA_DST_RLD_DST_RLD ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_DST_RLD_DST_RLD_POS)) /**< DST_RLD_DST_RLD Mask */ 447 448 /**@} end of group DMA_DST_RLD_Register */ 449 450 /** 451 * @ingroup dma_registers 452 * @defgroup DMA_CNT_RLD DMA_CNT_RLD 453 * @brief DMA Channel Count Reload Register. 454 * @{ 455 */ 456 #define MXC_F_DMA_CNT_RLD_CNT_RLD_POS 0 /**< CNT_RLD_CNT_RLD Position */ 457 #define MXC_F_DMA_CNT_RLD_CNT_RLD ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNT_RLD_CNT_RLD_POS)) /**< CNT_RLD_CNT_RLD Mask */ 458 459 #define MXC_F_DMA_CNT_RLD_RLDEN_POS 31 /**< CNT_RLD_RLDEN Position */ 460 #define MXC_F_DMA_CNT_RLD_RLDEN ((uint32_t)(0x1UL << MXC_F_DMA_CNT_RLD_RLDEN_POS)) /**< CNT_RLD_RLDEN Mask */ 461 462 /**@} end of group DMA_CNT_RLD_Register */ 463 464 #ifdef __cplusplus 465 } 466 #endif 467 468 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_DMA_REGS_H_ 469
