1 /** 2 * @file trimsir_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the TRIMSIR Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup trimsir_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32662_INCLUDE_TRIMSIR_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32662_INCLUDE_TRIMSIR_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup trimsir 67 * @defgroup trimsir_registers TRIMSIR_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the TRIMSIR Peripheral Module. 69 * @details Trim System Initilazation Registers 70 */ 71 72 /** 73 * @ingroup trimsir_registers 74 * Structure type to access the TRIMSIR Registers. 75 */ 76 typedef struct { 77 __R uint32_t rsv_0x0_0x7[2]; 78 __IO uint32_t bb_sir2; /**< <tt>\b 0x08:</tt> TRIMSIR BB_SIR2 Register */ 79 __IO uint32_t bb_sir3; /**< <tt>\b 0x0C:</tt> TRIMSIR BB_SIR3 Register */ 80 __R uint32_t rsv_0x10_0x17[2]; 81 __I uint32_t bb_sir6; /**< <tt>\b 0x18:</tt> TRIMSIR BB_SIR6 Register */ 82 } mxc_trimsir_regs_t; 83 84 /* Register offsets for module TRIMSIR */ 85 /** 86 * @ingroup trimsir_registers 87 * @defgroup TRIMSIR_Register_Offsets Register Offsets 88 * @brief TRIMSIR Peripheral Register Offsets from the TRIMSIR Base Peripheral Address. 89 * @{ 90 */ 91 #define MXC_R_TRIMSIR_BB_SIR2 ((uint32_t)0x00000008UL) /**< Offset from TRIMSIR Base Address: <tt> 0x0008</tt> */ 92 #define MXC_R_TRIMSIR_BB_SIR3 ((uint32_t)0x0000000CUL) /**< Offset from TRIMSIR Base Address: <tt> 0x000C</tt> */ 93 #define MXC_R_TRIMSIR_BB_SIR6 ((uint32_t)0x00000018UL) /**< Offset from TRIMSIR Base Address: <tt> 0x0018</tt> */ 94 /**@} end of group trimsir_registers */ 95 96 /** 97 * @ingroup trimsir_registers 98 * @defgroup TRIMSIR_BB_SIR2 TRIMSIR_BB_SIR2 99 * @brief System Init. Configuration Register 2. 100 * @{ 101 */ 102 #define MXC_F_TRIMSIR_BB_SIR2_TRIM_IBRO_RBIAS_POS 0 /**< BB_SIR2_TRIM_IBRO_RBIAS Position */ 103 #define MXC_F_TRIMSIR_BB_SIR2_TRIM_IBRO_RBIAS ((uint32_t)(0x3FUL << MXC_F_TRIMSIR_BB_SIR2_TRIM_IBRO_RBIAS_POS)) /**< BB_SIR2_TRIM_IBRO_RBIAS Mask */ 104 105 #define MXC_F_TRIMSIR_BB_SIR2_RAM0_1ECCEN_POS 8 /**< BB_SIR2_RAM0_1ECCEN Position */ 106 #define MXC_F_TRIMSIR_BB_SIR2_RAM0_1ECCEN ((uint32_t)(0x1UL << MXC_F_TRIMSIR_BB_SIR2_RAM0_1ECCEN_POS)) /**< BB_SIR2_RAM0_1ECCEN Mask */ 107 108 #define MXC_F_TRIMSIR_BB_SIR2_RAM2ECCEN_POS 9 /**< BB_SIR2_RAM2ECCEN Position */ 109 #define MXC_F_TRIMSIR_BB_SIR2_RAM2ECCEN ((uint32_t)(0x1UL << MXC_F_TRIMSIR_BB_SIR2_RAM2ECCEN_POS)) /**< BB_SIR2_RAM2ECCEN Mask */ 110 111 #define MXC_F_TRIMSIR_BB_SIR2_RAM3ECCEN_POS 10 /**< BB_SIR2_RAM3ECCEN Position */ 112 #define MXC_F_TRIMSIR_BB_SIR2_RAM3ECCEN ((uint32_t)(0x1UL << MXC_F_TRIMSIR_BB_SIR2_RAM3ECCEN_POS)) /**< BB_SIR2_RAM3ECCEN Mask */ 113 114 #define MXC_F_TRIMSIR_BB_SIR2_ICC0ECCEN_POS 11 /**< BB_SIR2_ICC0ECCEN Position */ 115 #define MXC_F_TRIMSIR_BB_SIR2_ICC0ECCEN ((uint32_t)(0x1UL << MXC_F_TRIMSIR_BB_SIR2_ICC0ECCEN_POS)) /**< BB_SIR2_ICC0ECCEN Mask */ 116 117 #define MXC_F_TRIMSIR_BB_SIR2_FL0ECCEN_POS 12 /**< BB_SIR2_FL0ECCEN Position */ 118 #define MXC_F_TRIMSIR_BB_SIR2_FL0ECCEN ((uint32_t)(0x1UL << MXC_F_TRIMSIR_BB_SIR2_FL0ECCEN_POS)) /**< BB_SIR2_FL0ECCEN Mask */ 119 120 #define MXC_F_TRIMSIR_BB_SIR2_FL1ECCEN_POS 13 /**< BB_SIR2_FL1ECCEN Position */ 121 #define MXC_F_TRIMSIR_BB_SIR2_FL1ECCEN ((uint32_t)(0x1UL << MXC_F_TRIMSIR_BB_SIR2_FL1ECCEN_POS)) /**< BB_SIR2_FL1ECCEN Mask */ 122 123 #define MXC_F_TRIMSIR_BB_SIR2_TRIM_IBRO_POS 16 /**< BB_SIR2_TRIM_IBRO Position */ 124 #define MXC_F_TRIMSIR_BB_SIR2_TRIM_IBRO ((uint32_t)(0xFFFFUL << MXC_F_TRIMSIR_BB_SIR2_TRIM_IBRO_POS)) /**< BB_SIR2_TRIM_IBRO Mask */ 125 126 /**@} end of group TRIMSIR_BB_SIR2_Register */ 127 128 /** 129 * @ingroup trimsir_registers 130 * @defgroup TRIMSIR_BB_SIR6 TRIMSIR_BB_SIR6 131 * @brief System Init. Configuration Register 6. 132 * @{ 133 */ 134 #define MXC_F_TRIMSIR_BB_SIR6_RTCX1TRIM_POS 4 /**< BB_SIR6_RTCX1TRIM Position */ 135 #define MXC_F_TRIMSIR_BB_SIR6_RTCX1TRIM ((uint32_t)(0x1FUL << MXC_F_TRIMSIR_BB_SIR6_RTCX1TRIM_POS)) /**< BB_SIR6_RTCX1TRIM Mask */ 136 137 #define MXC_F_TRIMSIR_BB_SIR6_RTCX2TRIM_POS 9 /**< BB_SIR6_RTCX2TRIM Position */ 138 #define MXC_F_TRIMSIR_BB_SIR6_RTCX2TRIM ((uint32_t)(0x1FUL << MXC_F_TRIMSIR_BB_SIR6_RTCX2TRIM_POS)) /**< BB_SIR6_RTCX2TRIM Mask */ 139 140 /**@} end of group TRIMSIR_BB_SIR6_Register */ 141 142 #ifdef __cplusplus 143 } 144 #endif 145 146 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32662_INCLUDE_TRIMSIR_REGS_H_ 147
