1 /** 2 * @file pwrseq_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup pwrseq_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32662_INCLUDE_PWRSEQ_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32662_INCLUDE_PWRSEQ_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup pwrseq 67 * @defgroup pwrseq_registers PWRSEQ_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module. 69 * @details Power Sequencer / Low Power Control Register. 70 */ 71 72 /** 73 * @ingroup pwrseq_registers 74 * Structure type to access the PWRSEQ Registers. 75 */ 76 typedef struct { 77 __IO uint32_t lpctrl; /**< <tt>\b 0x00:</tt> PWRSEQ LPCTRL Register */ 78 __IO uint32_t lpwkfl0; /**< <tt>\b 0x04:</tt> PWRSEQ LPWKFL0 Register */ 79 __IO uint32_t lpwken0; /**< <tt>\b 0x08:</tt> PWRSEQ LPWKEN0 Register */ 80 __R uint32_t rsv_0xc_0x2f[9]; 81 __IO uint32_t lppwkfl; /**< <tt>\b 0x30:</tt> PWRSEQ LPPWKFL Register */ 82 __IO uint32_t lppwken; /**< <tt>\b 0x34:</tt> PWRSEQ LPPWKEN Register */ 83 __R uint32_t rsv_0x38_0x3f[2]; 84 __IO uint32_t lpmemsd; /**< <tt>\b 0x40:</tt> PWRSEQ LPMEMSD Register */ 85 } mxc_pwrseq_regs_t; 86 87 /* Register offsets for module PWRSEQ */ 88 /** 89 * @ingroup pwrseq_registers 90 * @defgroup PWRSEQ_Register_Offsets Register Offsets 91 * @brief PWRSEQ Peripheral Register Offsets from the PWRSEQ Base Peripheral Address. 92 * @{ 93 */ 94 #define MXC_R_PWRSEQ_LPCTRL ((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0000</tt> */ 95 #define MXC_R_PWRSEQ_LPWKFL0 ((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0004</tt> */ 96 #define MXC_R_PWRSEQ_LPWKEN0 ((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0008</tt> */ 97 #define MXC_R_PWRSEQ_LPPWKFL ((uint32_t)0x00000030UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0030</tt> */ 98 #define MXC_R_PWRSEQ_LPPWKEN ((uint32_t)0x00000034UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0034</tt> */ 99 #define MXC_R_PWRSEQ_LPMEMSD ((uint32_t)0x00000040UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0040</tt> */ 100 /**@} end of group pwrseq_registers */ 101 102 /** 103 * @ingroup pwrseq_registers 104 * @defgroup PWRSEQ_LPCTRL PWRSEQ_LPCTRL 105 * @brief Low Power Control Register. 106 * @{ 107 */ 108 #define MXC_F_PWRSEQ_LPCTRL_RAM0RET_EN_POS 0 /**< LPCTRL_RAM0RET_EN Position */ 109 #define MXC_F_PWRSEQ_LPCTRL_RAM0RET_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_RAM0RET_EN_POS)) /**< LPCTRL_RAM0RET_EN Mask */ 110 111 #define MXC_F_PWRSEQ_LPCTRL_RAM1RET_EN_POS 1 /**< LPCTRL_RAM1RET_EN Position */ 112 #define MXC_F_PWRSEQ_LPCTRL_RAM1RET_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_RAM1RET_EN_POS)) /**< LPCTRL_RAM1RET_EN Mask */ 113 114 #define MXC_F_PWRSEQ_LPCTRL_RAM2RET_EN_POS 2 /**< LPCTRL_RAM2RET_EN Position */ 115 #define MXC_F_PWRSEQ_LPCTRL_RAM2RET_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_RAM2RET_EN_POS)) /**< LPCTRL_RAM2RET_EN Mask */ 116 117 #define MXC_F_PWRSEQ_LPCTRL_RAM3RET_EN_POS 3 /**< LPCTRL_RAM3RET_EN Position */ 118 #define MXC_F_PWRSEQ_LPCTRL_RAM3RET_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_RAM3RET_EN_POS)) /**< LPCTRL_RAM3RET_EN Mask */ 119 120 #define MXC_F_PWRSEQ_LPCTRL_OVR_POS 4 /**< LPCTRL_OVR Position */ 121 #define MXC_F_PWRSEQ_LPCTRL_OVR ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPCTRL_OVR_POS)) /**< LPCTRL_OVR Mask */ 122 #define MXC_V_PWRSEQ_LPCTRL_OVR_0_9V ((uint32_t)0x0UL) /**< LPCTRL_OVR_0_9V Value */ 123 #define MXC_S_PWRSEQ_LPCTRL_OVR_0_9V (MXC_V_PWRSEQ_LPCTRL_OVR_0_9V << MXC_F_PWRSEQ_LPCTRL_OVR_POS) /**< LPCTRL_OVR_0_9V Setting */ 124 #define MXC_V_PWRSEQ_LPCTRL_OVR_1_0V ((uint32_t)0x1UL) /**< LPCTRL_OVR_1_0V Value */ 125 #define MXC_S_PWRSEQ_LPCTRL_OVR_1_0V (MXC_V_PWRSEQ_LPCTRL_OVR_1_0V << MXC_F_PWRSEQ_LPCTRL_OVR_POS) /**< LPCTRL_OVR_1_0V Setting */ 126 #define MXC_V_PWRSEQ_LPCTRL_OVR_1_1V ((uint32_t)0x2UL) /**< LPCTRL_OVR_1_1V Value */ 127 #define MXC_S_PWRSEQ_LPCTRL_OVR_1_1V (MXC_V_PWRSEQ_LPCTRL_OVR_1_1V << MXC_F_PWRSEQ_LPCTRL_OVR_POS) /**< LPCTRL_OVR_1_1V Setting */ 128 129 #define MXC_F_PWRSEQ_LPCTRL_VCORE_DET_BYPASS_POS 6 /**< LPCTRL_VCORE_DET_BYPASS Position */ 130 #define MXC_F_PWRSEQ_LPCTRL_VCORE_DET_BYPASS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VCORE_DET_BYPASS_POS)) /**< LPCTRL_VCORE_DET_BYPASS Mask */ 131 132 #define MXC_F_PWRSEQ_LPCTRL_FVDD_EN_POS 7 /**< LPCTRL_FVDD_EN Position */ 133 #define MXC_F_PWRSEQ_LPCTRL_FVDD_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_FVDD_EN_POS)) /**< LPCTRL_FVDD_EN Mask */ 134 135 #define MXC_F_PWRSEQ_LPCTRL_RETREG_EN_POS 8 /**< LPCTRL_RETREG_EN Position */ 136 #define MXC_F_PWRSEQ_LPCTRL_RETREG_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_RETREG_EN_POS)) /**< LPCTRL_RETREG_EN Mask */ 137 138 #define MXC_F_PWRSEQ_LPCTRL_STORAGE_EN_POS 9 /**< LPCTRL_STORAGE_EN Position */ 139 #define MXC_F_PWRSEQ_LPCTRL_STORAGE_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_STORAGE_EN_POS)) /**< LPCTRL_STORAGE_EN Mask */ 140 141 #define MXC_F_PWRSEQ_LPCTRL_FASTWK_EN_POS 10 /**< LPCTRL_FASTWK_EN Position */ 142 #define MXC_F_PWRSEQ_LPCTRL_FASTWK_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_FASTWK_EN_POS)) /**< LPCTRL_FASTWK_EN Mask */ 143 144 #define MXC_F_PWRSEQ_LPCTRL_BG_DIS_POS 11 /**< LPCTRL_BG_DIS Position */ 145 #define MXC_F_PWRSEQ_LPCTRL_BG_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_BG_DIS_POS)) /**< LPCTRL_BG_DIS Mask */ 146 147 #define MXC_F_PWRSEQ_LPCTRL_VCOREPOR_DIS_POS 12 /**< LPCTRL_VCOREPOR_DIS Position */ 148 #define MXC_F_PWRSEQ_LPCTRL_VCOREPOR_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VCOREPOR_DIS_POS)) /**< LPCTRL_VCOREPOR_DIS Mask */ 149 150 #define MXC_F_PWRSEQ_LPCTRL_LDO_DIS_POS 16 /**< LPCTRL_LDO_DIS Position */ 151 #define MXC_F_PWRSEQ_LPCTRL_LDO_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_LDO_DIS_POS)) /**< LPCTRL_LDO_DIS Mask */ 152 153 #define MXC_F_PWRSEQ_LPCTRL_VCORE_EXT_POS 17 /**< LPCTRL_VCORE_EXT Position */ 154 #define MXC_F_PWRSEQ_LPCTRL_VCORE_EXT ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VCORE_EXT_POS)) /**< LPCTRL_VCORE_EXT Mask */ 155 156 #define MXC_F_PWRSEQ_LPCTRL_VCOREMON_DIS_POS 20 /**< LPCTRL_VCOREMON_DIS Position */ 157 #define MXC_F_PWRSEQ_LPCTRL_VCOREMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VCOREMON_DIS_POS)) /**< LPCTRL_VCOREMON_DIS Mask */ 158 159 #define MXC_F_PWRSEQ_LPCTRL_VDDAMON_DIS_POS 22 /**< LPCTRL_VDDAMON_DIS Position */ 160 #define MXC_F_PWRSEQ_LPCTRL_VDDAMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VDDAMON_DIS_POS)) /**< LPCTRL_VDDAMON_DIS Mask */ 161 162 #define MXC_F_PWRSEQ_LPCTRL_PORVDDMON_DIS_POS 25 /**< LPCTRL_PORVDDMON_DIS Position */ 163 #define MXC_F_PWRSEQ_LPCTRL_PORVDDMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_PORVDDMON_DIS_POS)) /**< LPCTRL_PORVDDMON_DIS Mask */ 164 165 #define MXC_F_PWRSEQ_LPCTRL_VBBMON_DIS_POS 27 /**< LPCTRL_VBBMON_DIS Position */ 166 #define MXC_F_PWRSEQ_LPCTRL_VBBMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VBBMON_DIS_POS)) /**< LPCTRL_VBBMON_DIS Mask */ 167 168 #define MXC_F_PWRSEQ_LPCTRL_INRO_EN_POS 28 /**< LPCTRL_INRO_EN Position */ 169 #define MXC_F_PWRSEQ_LPCTRL_INRO_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_INRO_EN_POS)) /**< LPCTRL_INRO_EN Mask */ 170 171 #define MXC_F_PWRSEQ_LPCTRL_ERTCO_EN_POS 29 /**< LPCTRL_ERTCO_EN Position */ 172 #define MXC_F_PWRSEQ_LPCTRL_ERTCO_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_ERTCO_EN_POS)) /**< LPCTRL_ERTCO_EN Mask */ 173 174 /**@} end of group PWRSEQ_LPCTRL_Register */ 175 176 /** 177 * @ingroup pwrseq_registers 178 * @defgroup PWRSEQ_LPWKFL0 PWRSEQ_LPWKFL0 179 * @brief Low Power I/O Wakeup Status Flag Register 0. This register indicates the low 180 * power wakeup status for GPIO0. 181 * @{ 182 */ 183 #define MXC_F_PWRSEQ_LPWKFL0_WAKEFL_POS 0 /**< LPWKFL0_WAKEFL Position */ 184 #define MXC_F_PWRSEQ_LPWKFL0_WAKEFL ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRSEQ_LPWKFL0_WAKEFL_POS)) /**< LPWKFL0_WAKEFL Mask */ 185 186 /**@} end of group PWRSEQ_LPWKFL0_Register */ 187 188 /** 189 * @ingroup pwrseq_registers 190 * @defgroup PWRSEQ_LPWKEN0 PWRSEQ_LPWKEN0 191 * @brief Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup 192 * functionality for GPIO0. 193 * @{ 194 */ 195 #define MXC_F_PWRSEQ_LPWKEN0_WAKEEN_POS 0 /**< LPWKEN0_WAKEEN Position */ 196 #define MXC_F_PWRSEQ_LPWKEN0_WAKEEN ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRSEQ_LPWKEN0_WAKEEN_POS)) /**< LPWKEN0_WAKEEN Mask */ 197 198 /**@} end of group PWRSEQ_LPWKEN0_Register */ 199 200 /** 201 * @ingroup pwrseq_registers 202 * @defgroup PWRSEQ_LPPWKFL PWRSEQ_LPPWKFL 203 * @brief Low Power Peripheral Wakeup Status Flag Register. 204 * @{ 205 */ 206 #define MXC_F_PWRSEQ_LPPWKFL_TMR3_POS 0 /**< LPPWKFL_TMR3 Position */ 207 #define MXC_F_PWRSEQ_LPPWKFL_TMR3 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKFL_TMR3_POS)) /**< LPPWKFL_TMR3 Mask */ 208 209 #define MXC_F_PWRSEQ_LPPWKFL_AINCOMP0_POS 3 /**< LPPWKFL_AINCOMP0 Position */ 210 #define MXC_F_PWRSEQ_LPPWKFL_AINCOMP0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKFL_AINCOMP0_POS)) /**< LPPWKFL_AINCOMP0 Mask */ 211 212 #define MXC_F_PWRSEQ_LPPWKFL_AINCOMP1_POS 4 /**< LPPWKFL_AINCOMP1 Position */ 213 #define MXC_F_PWRSEQ_LPPWKFL_AINCOMP1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKFL_AINCOMP1_POS)) /**< LPPWKFL_AINCOMP1 Mask */ 214 215 #define MXC_F_PWRSEQ_LPPWKFL_AINCOMP0_ST_POS 5 /**< LPPWKFL_AINCOMP0_ST Position */ 216 #define MXC_F_PWRSEQ_LPPWKFL_AINCOMP0_ST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKFL_AINCOMP0_ST_POS)) /**< LPPWKFL_AINCOMP0_ST Mask */ 217 218 #define MXC_F_PWRSEQ_LPPWKFL_AINCOMP1_ST_POS 6 /**< LPPWKFL_AINCOMP1_ST Position */ 219 #define MXC_F_PWRSEQ_LPPWKFL_AINCOMP1_ST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKFL_AINCOMP1_ST_POS)) /**< LPPWKFL_AINCOMP1_ST Mask */ 220 221 #define MXC_F_PWRSEQ_LPPWKFL_BACKUP_POS 16 /**< LPPWKFL_BACKUP Position */ 222 #define MXC_F_PWRSEQ_LPPWKFL_BACKUP ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKFL_BACKUP_POS)) /**< LPPWKFL_BACKUP Mask */ 223 224 /**@} end of group PWRSEQ_LPPWKFL_Register */ 225 226 /** 227 * @ingroup pwrseq_registers 228 * @defgroup PWRSEQ_LPPWKEN PWRSEQ_LPPWKEN 229 * @brief Low Power Peripheral Wakeup Enable Register. 230 * @{ 231 */ 232 #define MXC_F_PWRSEQ_LPPWKEN_LPTMR0_POS 0 /**< LPPWKEN_LPTMR0 Position */ 233 #define MXC_F_PWRSEQ_LPPWKEN_LPTMR0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_LPTMR0_POS)) /**< LPPWKEN_LPTMR0 Mask */ 234 235 #define MXC_F_PWRSEQ_LPPWKEN_AINCOMP0_POS 3 /**< LPPWKEN_AINCOMP0 Position */ 236 #define MXC_F_PWRSEQ_LPPWKEN_AINCOMP0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_AINCOMP0_POS)) /**< LPPWKEN_AINCOMP0 Mask */ 237 238 #define MXC_F_PWRSEQ_LPPWKEN_AINCOMP1_POS 4 /**< LPPWKEN_AINCOMP1 Position */ 239 #define MXC_F_PWRSEQ_LPPWKEN_AINCOMP1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_AINCOMP1_POS)) /**< LPPWKEN_AINCOMP1 Mask */ 240 241 /**@} end of group PWRSEQ_LPPWKEN_Register */ 242 243 /** 244 * @ingroup pwrseq_registers 245 * @defgroup PWRSEQ_LPMEMSD PWRSEQ_LPMEMSD 246 * @brief Low Power Memory Shutdown Register. 247 * @{ 248 */ 249 #define MXC_F_PWRSEQ_LPMEMSD_RAM0_POS 0 /**< LPMEMSD_RAM0 Position */ 250 #define MXC_F_PWRSEQ_LPMEMSD_RAM0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM0_POS)) /**< LPMEMSD_RAM0 Mask */ 251 252 #define MXC_F_PWRSEQ_LPMEMSD_RAM1_POS 1 /**< LPMEMSD_RAM1 Position */ 253 #define MXC_F_PWRSEQ_LPMEMSD_RAM1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM1_POS)) /**< LPMEMSD_RAM1 Mask */ 254 255 #define MXC_F_PWRSEQ_LPMEMSD_RAM2_POS 2 /**< LPMEMSD_RAM2 Position */ 256 #define MXC_F_PWRSEQ_LPMEMSD_RAM2 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM2_POS)) /**< LPMEMSD_RAM2 Mask */ 257 258 #define MXC_F_PWRSEQ_LPMEMSD_RAM3_POS 3 /**< LPMEMSD_RAM3 Position */ 259 #define MXC_F_PWRSEQ_LPMEMSD_RAM3 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM3_POS)) /**< LPMEMSD_RAM3 Mask */ 260 261 /**@} end of group PWRSEQ_LPMEMSD_Register */ 262 263 #ifdef __cplusplus 264 } 265 #endif 266 267 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32662_INCLUDE_PWRSEQ_REGS_H_ 268
