1 /** 2 * @file mcr_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the MCR Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup mcr_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32662_INCLUDE_MCR_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32662_INCLUDE_MCR_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup mcr 67 * @defgroup mcr_registers MCR_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the MCR Peripheral Module. 69 * @details Misc Control. 70 */ 71 72 /** 73 * @ingroup mcr_registers 74 * Structure type to access the MCR Registers. 75 */ 76 typedef struct { 77 __R uint32_t rsv_0x0; 78 __IO uint32_t rst; /**< <tt>\b 0x04:</tt> MCR RST Register */ 79 __IO uint32_t clkctrl; /**< <tt>\b 0x08:</tt> MCR CLKCTRL Register */ 80 __IO uint32_t aincomp; /**< <tt>\b 0x0C:</tt> MCR AINCOMP Register */ 81 __IO uint32_t lppioctrl; /**< <tt>\b 0x10:</tt> MCR LPPIOCTRL Register */ 82 __R uint32_t rsv_0x14_0x23[4]; 83 __IO uint32_t pclkdis; /**< <tt>\b 0x24:</tt> MCR PCLKDIS Register */ 84 __R uint32_t rsv_0x28_0x33[3]; 85 __IO uint32_t aeskey; /**< <tt>\b 0x34:</tt> MCR AESKEY Register */ 86 __IO uint32_t adccfg0; /**< <tt>\b 0x38:</tt> MCR ADCCFG0 Register */ 87 __IO uint32_t adccfg1; /**< <tt>\b 0x3C:</tt> MCR ADCCFG1 Register */ 88 __IO uint32_t adccfg2; /**< <tt>\b 0x40:</tt> MCR ADCCFG2 Register */ 89 } mxc_mcr_regs_t; 90 91 /* Register offsets for module MCR */ 92 /** 93 * @ingroup mcr_registers 94 * @defgroup MCR_Register_Offsets Register Offsets 95 * @brief MCR Peripheral Register Offsets from the MCR Base Peripheral Address. 96 * @{ 97 */ 98 #define MXC_R_MCR_RST ((uint32_t)0x00000004UL) /**< Offset from MCR Base Address: <tt> 0x0004</tt> */ 99 #define MXC_R_MCR_CLKCTRL ((uint32_t)0x00000008UL) /**< Offset from MCR Base Address: <tt> 0x0008</tt> */ 100 #define MXC_R_MCR_AINCOMP ((uint32_t)0x0000000CUL) /**< Offset from MCR Base Address: <tt> 0x000C</tt> */ 101 #define MXC_R_MCR_LPPIOCTRL ((uint32_t)0x00000010UL) /**< Offset from MCR Base Address: <tt> 0x0010</tt> */ 102 #define MXC_R_MCR_PCLKDIS ((uint32_t)0x00000024UL) /**< Offset from MCR Base Address: <tt> 0x0024</tt> */ 103 #define MXC_R_MCR_AESKEY ((uint32_t)0x00000034UL) /**< Offset from MCR Base Address: <tt> 0x0034</tt> */ 104 #define MXC_R_MCR_ADCCFG0 ((uint32_t)0x00000038UL) /**< Offset from MCR Base Address: <tt> 0x0038</tt> */ 105 #define MXC_R_MCR_ADCCFG1 ((uint32_t)0x0000003CUL) /**< Offset from MCR Base Address: <tt> 0x003C</tt> */ 106 #define MXC_R_MCR_ADCCFG2 ((uint32_t)0x00000040UL) /**< Offset from MCR Base Address: <tt> 0x0040</tt> */ 107 /**@} end of group mcr_registers */ 108 109 /** 110 * @ingroup mcr_registers 111 * @defgroup MCR_RST MCR_RST 112 * @brief Reset Register. 113 * @{ 114 */ 115 #define MXC_F_MCR_RST_TMR3_POS 0 /**< RST_TMR3 Position */ 116 #define MXC_F_MCR_RST_TMR3 ((uint32_t)(0x1UL << MXC_F_MCR_RST_TMR3_POS)) /**< RST_TMR3 Mask */ 117 118 #define MXC_F_MCR_RST_RTC_POS 3 /**< RST_RTC Position */ 119 #define MXC_F_MCR_RST_RTC ((uint32_t)(0x1UL << MXC_F_MCR_RST_RTC_POS)) /**< RST_RTC Mask */ 120 121 /**@} end of group MCR_RST_Register */ 122 123 /** 124 * @ingroup mcr_registers 125 * @defgroup MCR_CLKCTRL MCR_CLKCTRL 126 * @brief System CLock Control Register. 127 * @{ 128 */ 129 #define MXC_F_MCR_CLKCTRL_ERTCO_PD_POS 16 /**< CLKCTRL_ERTCO_PD Position */ 130 #define MXC_F_MCR_CLKCTRL_ERTCO_PD ((uint32_t)(0x1UL << MXC_F_MCR_CLKCTRL_ERTCO_PD_POS)) /**< CLKCTRL_ERTCO_PD Mask */ 131 132 #define MXC_F_MCR_CLKCTRL_ERTCO_EN_POS 17 /**< CLKCTRL_ERTCO_EN Position */ 133 #define MXC_F_MCR_CLKCTRL_ERTCO_EN ((uint32_t)(0x1UL << MXC_F_MCR_CLKCTRL_ERTCO_EN_POS)) /**< CLKCTRL_ERTCO_EN Mask */ 134 135 /**@} end of group MCR_CLKCTRL_Register */ 136 137 /** 138 * @ingroup mcr_registers 139 * @defgroup MCR_AINCOMP MCR_AINCOMP 140 * @brief AIN Comparator Control Register. 141 * @{ 142 */ 143 #define MXC_F_MCR_AINCOMP_PD_POS 0 /**< AINCOMP_PD Position */ 144 #define MXC_F_MCR_AINCOMP_PD ((uint32_t)(0x3UL << MXC_F_MCR_AINCOMP_PD_POS)) /**< AINCOMP_PD Mask */ 145 146 #define MXC_F_MCR_AINCOMP_HYST_POS 2 /**< AINCOMP_HYST Position */ 147 #define MXC_F_MCR_AINCOMP_HYST ((uint32_t)(0x3UL << MXC_F_MCR_AINCOMP_HYST_POS)) /**< AINCOMP_HYST Mask */ 148 149 #define MXC_F_MCR_AINCOMP_NSEL_COMP0_POS 16 /**< AINCOMP_NSEL_COMP0 Position */ 150 #define MXC_F_MCR_AINCOMP_NSEL_COMP0 ((uint32_t)(0x3UL << MXC_F_MCR_AINCOMP_NSEL_COMP0_POS)) /**< AINCOMP_NSEL_COMP0 Mask */ 151 152 #define MXC_F_MCR_AINCOMP_PSEL_COMP0_POS 20 /**< AINCOMP_PSEL_COMP0 Position */ 153 #define MXC_F_MCR_AINCOMP_PSEL_COMP0 ((uint32_t)(0x3UL << MXC_F_MCR_AINCOMP_PSEL_COMP0_POS)) /**< AINCOMP_PSEL_COMP0 Mask */ 154 155 #define MXC_F_MCR_AINCOMP_NSEL_COMP1_POS 24 /**< AINCOMP_NSEL_COMP1 Position */ 156 #define MXC_F_MCR_AINCOMP_NSEL_COMP1 ((uint32_t)(0x3UL << MXC_F_MCR_AINCOMP_NSEL_COMP1_POS)) /**< AINCOMP_NSEL_COMP1 Mask */ 157 158 #define MXC_F_MCR_AINCOMP_PSEL_COMP1_POS 28 /**< AINCOMP_PSEL_COMP1 Position */ 159 #define MXC_F_MCR_AINCOMP_PSEL_COMP1 ((uint32_t)(0x3UL << MXC_F_MCR_AINCOMP_PSEL_COMP1_POS)) /**< AINCOMP_PSEL_COMP1 Mask */ 160 161 /**@} end of group MCR_AINCOMP_Register */ 162 163 /** 164 * @ingroup mcr_registers 165 * @defgroup MCR_LPPIOCTRL MCR_LPPIOCTRL 166 * @brief Low Power Peripheral IO Control Register. 167 * @{ 168 */ 169 #define MXC_F_MCR_LPPIOCTRL_TMR3_IN_POS 0 /**< LPPIOCTRL_TMR3_IN Position */ 170 #define MXC_F_MCR_LPPIOCTRL_TMR3_IN ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_TMR3_IN_POS)) /**< LPPIOCTRL_TMR3_IN Mask */ 171 172 #define MXC_F_MCR_LPPIOCTRL_TMR3_OUT_POS 1 /**< LPPIOCTRL_TMR3_OUT Position */ 173 #define MXC_F_MCR_LPPIOCTRL_TMR3_OUT ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_TMR3_OUT_POS)) /**< LPPIOCTRL_TMR3_OUT Mask */ 174 175 #define MXC_F_MCR_LPPIOCTRL_TMR3_OUT_N_POS 2 /**< LPPIOCTRL_TMR3_OUT_N Position */ 176 #define MXC_F_MCR_LPPIOCTRL_TMR3_OUT_N ((uint32_t)(0x1UL << MXC_F_MCR_LPPIOCTRL_TMR3_OUT_N_POS)) /**< LPPIOCTRL_TMR3_OUT_N Mask */ 177 178 /**@} end of group MCR_LPPIOCTRL_Register */ 179 180 /** 181 * @ingroup mcr_registers 182 * @defgroup MCR_PCLKDIS MCR_PCLKDIS 183 * @brief Peripheral Clock Disable Register. 184 * @{ 185 */ 186 #define MXC_F_MCR_PCLKDIS_TMR3_POS 0 /**< PCLKDIS_TMR3 Position */ 187 #define MXC_F_MCR_PCLKDIS_TMR3 ((uint32_t)(0x1UL << MXC_F_MCR_PCLKDIS_TMR3_POS)) /**< PCLKDIS_TMR3 Mask */ 188 189 /**@} end of group MCR_PCLKDIS_Register */ 190 191 /** 192 * @ingroup mcr_registers 193 * @defgroup MCR_AESKEY MCR_AESKEY 194 * @brief AES Key Pointer and Status Register. 195 * @{ 196 */ 197 #define MXC_F_MCR_AESKEY_PTR_POS 0 /**< AESKEY_PTR Position */ 198 #define MXC_F_MCR_AESKEY_PTR ((uint32_t)(0xFFFFUL << MXC_F_MCR_AESKEY_PTR_POS)) /**< AESKEY_PTR Mask */ 199 200 /**@} end of group MCR_AESKEY_Register */ 201 202 /** 203 * @ingroup mcr_registers 204 * @defgroup MCR_ADCCFG0 MCR_ADCCFG0 205 * @brief ADC Config Register 0. 206 * @{ 207 */ 208 #define MXC_F_MCR_ADCCFG0_LP_EXTCLK_EN_POS 0 /**< ADCCFG0_LP_EXTCLK_EN Position */ 209 #define MXC_F_MCR_ADCCFG0_LP_EXTCLK_EN ((uint32_t)(0x1UL << MXC_F_MCR_ADCCFG0_LP_EXTCLK_EN_POS)) /**< ADCCFG0_LP_EXTCLK_EN Mask */ 210 211 #define MXC_F_MCR_ADCCFG0_EXT_REF_POS 2 /**< ADCCFG0_EXT_REF Position */ 212 #define MXC_F_MCR_ADCCFG0_EXT_REF ((uint32_t)(0x1UL << MXC_F_MCR_ADCCFG0_EXT_REF_POS)) /**< ADCCFG0_EXT_REF Mask */ 213 214 #define MXC_F_MCR_ADCCFG0_INT_REF_POS 3 /**< ADCCFG0_INT_REF Position */ 215 #define MXC_F_MCR_ADCCFG0_INT_REF ((uint32_t)(0x1UL << MXC_F_MCR_ADCCFG0_INT_REF_POS)) /**< ADCCFG0_INT_REF Mask */ 216 217 /**@} end of group MCR_ADCCFG0_Register */ 218 219 /** 220 * @ingroup mcr_registers 221 * @defgroup MCR_ADCCFG1 MCR_ADCCFG1 222 * @brief ADC Config Register 1. 223 * @{ 224 */ 225 #define MXC_F_MCR_ADCCFG1_THRU_PAD_SW_EN_POS 0 /**< ADCCFG1_THRU_PAD_SW_EN Position */ 226 #define MXC_F_MCR_ADCCFG1_THRU_PAD_SW_EN ((uint32_t)(0xFUL << MXC_F_MCR_ADCCFG1_THRU_PAD_SW_EN_POS)) /**< ADCCFG1_THRU_PAD_SW_EN Mask */ 227 228 #define MXC_F_MCR_ADCCFG1_AIN_INP_EN_POS 4 /**< ADCCFG1_AIN_INP_EN Position */ 229 #define MXC_F_MCR_ADCCFG1_AIN_INP_EN ((uint32_t)(0xFUL << MXC_F_MCR_ADCCFG1_AIN_INP_EN_POS)) /**< ADCCFG1_AIN_INP_EN Mask */ 230 231 #define MXC_F_MCR_ADCCFG1_THRU_EN_POS 8 /**< ADCCFG1_THRU_EN Position */ 232 #define MXC_F_MCR_ADCCFG1_THRU_EN ((uint32_t)(0x1UL << MXC_F_MCR_ADCCFG1_THRU_EN_POS)) /**< ADCCFG1_THRU_EN Mask */ 233 234 #define MXC_F_MCR_ADCCFG1_AMP_EN_POS 9 /**< ADCCFG1_AMP_EN Position */ 235 #define MXC_F_MCR_ADCCFG1_AMP_EN ((uint32_t)(0x1UL << MXC_F_MCR_ADCCFG1_AMP_EN_POS)) /**< ADCCFG1_AMP_EN Mask */ 236 237 #define MXC_F_MCR_ADCCFG1_AMP_RRI_EN_POS 10 /**< ADCCFG1_AMP_RRI_EN Position */ 238 #define MXC_F_MCR_ADCCFG1_AMP_RRI_EN ((uint32_t)(0x1UL << MXC_F_MCR_ADCCFG1_AMP_RRI_EN_POS)) /**< ADCCFG1_AMP_RRI_EN Mask */ 239 240 #define MXC_F_MCR_ADCCFG1_DIVSEL_POS 11 /**< ADCCFG1_DIVSEL Position */ 241 #define MXC_F_MCR_ADCCFG1_DIVSEL ((uint32_t)(0x3UL << MXC_F_MCR_ADCCFG1_DIVSEL_POS)) /**< ADCCFG1_DIVSEL Mask */ 242 243 /**@} end of group MCR_ADCCFG1_Register */ 244 245 /** 246 * @ingroup mcr_registers 247 * @defgroup MCR_ADCCFG2 MCR_ADCCFG2 248 * @brief ADC Config Register 2. 249 * @{ 250 */ 251 #define MXC_F_MCR_ADCCFG2_VREFM_POS 0 /**< ADCCFG2_VREFM Position */ 252 #define MXC_F_MCR_ADCCFG2_VREFM ((uint32_t)(0x7FUL << MXC_F_MCR_ADCCFG2_VREFM_POS)) /**< ADCCFG2_VREFM Mask */ 253 254 #define MXC_F_MCR_ADCCFG2_VREFP_POS 8 /**< ADCCFG2_VREFP Position */ 255 #define MXC_F_MCR_ADCCFG2_VREFP ((uint32_t)(0x7FUL << MXC_F_MCR_ADCCFG2_VREFP_POS)) /**< ADCCFG2_VREFP Mask */ 256 257 #define MXC_F_MCR_ADCCFG2_IDRV_POS 16 /**< ADCCFG2_IDRV Position */ 258 #define MXC_F_MCR_ADCCFG2_IDRV ((uint32_t)(0xFUL << MXC_F_MCR_ADCCFG2_IDRV_POS)) /**< ADCCFG2_IDRV Mask */ 259 260 #define MXC_F_MCR_ADCCFG2_VCM_POS 20 /**< ADCCFG2_VCM Position */ 261 #define MXC_F_MCR_ADCCFG2_VCM ((uint32_t)(0x3UL << MXC_F_MCR_ADCCFG2_VCM_POS)) /**< ADCCFG2_VCM Mask */ 262 263 #define MXC_F_MCR_ADCCFG2_D_IBOOST_POS 24 /**< ADCCFG2_D_IBOOST Position */ 264 #define MXC_F_MCR_ADCCFG2_D_IBOOST ((uint32_t)(0x1UL << MXC_F_MCR_ADCCFG2_D_IBOOST_POS)) /**< ADCCFG2_D_IBOOST Mask */ 265 266 /**@} end of group MCR_ADCCFG2_Register */ 267 268 #ifdef __cplusplus 269 } 270 #endif 271 272 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32662_INCLUDE_MCR_REGS_H_ 273
