1 /** 2 * @file flc_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup flc_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32662_INCLUDE_FLC_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32662_INCLUDE_FLC_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup flc 67 * @defgroup flc_registers FLC_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module. 69 * @details Flash Memory Control. 70 */ 71 72 /** 73 * @ingroup flc_registers 74 * Structure type to access the FLC Registers. 75 */ 76 typedef struct { 77 __IO uint32_t addr; /**< <tt>\b 0x00:</tt> FLC ADDR Register */ 78 __IO uint32_t clkdiv; /**< <tt>\b 0x04:</tt> FLC CLKDIV Register */ 79 __IO uint32_t ctrl; /**< <tt>\b 0x08:</tt> FLC CTRL Register */ 80 __R uint32_t rsv_0xc_0x23[6]; 81 __IO uint32_t intr; /**< <tt>\b 0x024:</tt> FLC INTR Register */ 82 __R uint32_t rsv_0x28_0x2f[2]; 83 __IO uint32_t data[4]; /**< <tt>\b 0x30:</tt> FLC DATA Register */ 84 __O uint32_t actrl; /**< <tt>\b 0x40:</tt> FLC ACTRL Register */ 85 __R uint32_t rsv_0x44_0x7f[15]; 86 __IO uint32_t welr0; /**< <tt>\b 0x80:</tt> FLC WELR0 Register */ 87 __IO uint32_t rlr0; /**< <tt>\b 0x84:</tt> FLC RLR0 Register */ 88 __IO uint32_t welr1; /**< <tt>\b 0x88:</tt> FLC WELR1 Register */ 89 __IO uint32_t rlr1; /**< <tt>\b 0x8C:</tt> FLC RLR1 Register */ 90 __IO uint32_t welr2; /**< <tt>\b 0x90:</tt> FLC WELR2 Register */ 91 __IO uint32_t rlr2; /**< <tt>\b 0x94:</tt> FLC RLR2 Register */ 92 __IO uint32_t welr3; /**< <tt>\b 0x98:</tt> FLC WELR3 Register */ 93 __IO uint32_t rlr3; /**< <tt>\b 0x9C:</tt> FLC RLR3 Register */ 94 __IO uint32_t welr4; /**< <tt>\b 0xA0:</tt> FLC WELR4 Register */ 95 __IO uint32_t rlr4; /**< <tt>\b 0xA4:</tt> FLC RLR4 Register */ 96 __IO uint32_t welr5; /**< <tt>\b 0xA8:</tt> FLC WELR5 Register */ 97 __IO uint32_t rlr5; /**< <tt>\b 0xAC:</tt> FLC RLR5 Register */ 98 } mxc_flc_regs_t; 99 100 /* Register offsets for module FLC */ 101 /** 102 * @ingroup flc_registers 103 * @defgroup FLC_Register_Offsets Register Offsets 104 * @brief FLC Peripheral Register Offsets from the FLC Base Peripheral Address. 105 * @{ 106 */ 107 #define MXC_R_FLC_ADDR ((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: <tt> 0x0000</tt> */ 108 #define MXC_R_FLC_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: <tt> 0x0004</tt> */ 109 #define MXC_R_FLC_CTRL ((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: <tt> 0x0008</tt> */ 110 #define MXC_R_FLC_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: <tt> 0x0024</tt> */ 111 #define MXC_R_FLC_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: <tt> 0x0030</tt> */ 112 #define MXC_R_FLC_ACTRL ((uint32_t)0x00000040UL) /**< Offset from FLC Base Address: <tt> 0x0040</tt> */ 113 #define MXC_R_FLC_WELR0 ((uint32_t)0x00000080UL) /**< Offset from FLC Base Address: <tt> 0x0080</tt> */ 114 #define MXC_R_FLC_RLR0 ((uint32_t)0x00000084UL) /**< Offset from FLC Base Address: <tt> 0x0084</tt> */ 115 #define MXC_R_FLC_WELR1 ((uint32_t)0x00000088UL) /**< Offset from FLC Base Address: <tt> 0x0088</tt> */ 116 #define MXC_R_FLC_RLR1 ((uint32_t)0x0000008CUL) /**< Offset from FLC Base Address: <tt> 0x008C</tt> */ 117 #define MXC_R_FLC_WELR2 ((uint32_t)0x00000090UL) /**< Offset from FLC Base Address: <tt> 0x0090</tt> */ 118 #define MXC_R_FLC_RLR2 ((uint32_t)0x00000094UL) /**< Offset from FLC Base Address: <tt> 0x0094</tt> */ 119 #define MXC_R_FLC_WELR3 ((uint32_t)0x00000098UL) /**< Offset from FLC Base Address: <tt> 0x0098</tt> */ 120 #define MXC_R_FLC_RLR3 ((uint32_t)0x0000009CUL) /**< Offset from FLC Base Address: <tt> 0x009C</tt> */ 121 #define MXC_R_FLC_WELR4 ((uint32_t)0x000000A0UL) /**< Offset from FLC Base Address: <tt> 0x00A0</tt> */ 122 #define MXC_R_FLC_RLR4 ((uint32_t)0x000000A4UL) /**< Offset from FLC Base Address: <tt> 0x00A4</tt> */ 123 #define MXC_R_FLC_WELR5 ((uint32_t)0x000000A8UL) /**< Offset from FLC Base Address: <tt> 0x00A8</tt> */ 124 #define MXC_R_FLC_RLR5 ((uint32_t)0x000000ACUL) /**< Offset from FLC Base Address: <tt> 0x00AC</tt> */ 125 /**@} end of group flc_registers */ 126 127 /** 128 * @ingroup flc_registers 129 * @defgroup FLC_ADDR FLC_ADDR 130 * @brief Flash Write Address. 131 * @{ 132 */ 133 #define MXC_F_FLC_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */ 134 #define MXC_F_FLC_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */ 135 136 /**@} end of group FLC_ADDR_Register */ 137 138 /** 139 * @ingroup flc_registers 140 * @defgroup FLC_CLKDIV FLC_CLKDIV 141 * @brief Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 142 * MHz clock for Flash controller. 143 * @{ 144 */ 145 #define MXC_F_FLC_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */ 146 #define MXC_F_FLC_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */ 147 148 /**@} end of group FLC_CLKDIV_Register */ 149 150 /** 151 * @ingroup flc_registers 152 * @defgroup FLC_CTRL FLC_CTRL 153 * @brief Flash Control Register. 154 * @{ 155 */ 156 #define MXC_F_FLC_CTRL_WR_POS 0 /**< CTRL_WR Position */ 157 #define MXC_F_FLC_CTRL_WR ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_WR_POS)) /**< CTRL_WR Mask */ 158 159 #define MXC_F_FLC_CTRL_ME_POS 1 /**< CTRL_ME Position */ 160 #define MXC_F_FLC_CTRL_ME ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_ME_POS)) /**< CTRL_ME Mask */ 161 162 #define MXC_F_FLC_CTRL_PGE_POS 2 /**< CTRL_PGE Position */ 163 #define MXC_F_FLC_CTRL_PGE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_PGE_POS)) /**< CTRL_PGE Mask */ 164 165 #define MXC_F_FLC_CTRL_WDTH_POS 4 /**< CTRL_WDTH Position */ 166 #define MXC_F_FLC_CTRL_WDTH ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_WDTH_POS)) /**< CTRL_WDTH Mask */ 167 168 #define MXC_F_FLC_CTRL_ERASE_CODE_POS 8 /**< CTRL_ERASE_CODE Position */ 169 #define MXC_F_FLC_CTRL_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS)) /**< CTRL_ERASE_CODE Mask */ 170 #define MXC_V_FLC_CTRL_ERASE_CODE_NOP ((uint32_t)0x0UL) /**< CTRL_ERASE_CODE_NOP Value */ 171 #define MXC_S_FLC_CTRL_ERASE_CODE_NOP (MXC_V_FLC_CTRL_ERASE_CODE_NOP << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_NOP Setting */ 172 #define MXC_V_FLC_CTRL_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL) /**< CTRL_ERASE_CODE_ERASEPAGE Value */ 173 #define MXC_S_FLC_CTRL_ERASE_CODE_ERASEPAGE (MXC_V_FLC_CTRL_ERASE_CODE_ERASEPAGE << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEPAGE Setting */ 174 #define MXC_V_FLC_CTRL_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL) /**< CTRL_ERASE_CODE_ERASEALL Value */ 175 #define MXC_S_FLC_CTRL_ERASE_CODE_ERASEALL (MXC_V_FLC_CTRL_ERASE_CODE_ERASEALL << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEALL Setting */ 176 177 #define MXC_F_FLC_CTRL_PEND_POS 24 /**< CTRL_PEND Position */ 178 #define MXC_F_FLC_CTRL_PEND ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_PEND_POS)) /**< CTRL_PEND Mask */ 179 180 #define MXC_F_FLC_CTRL_LVE_POS 25 /**< CTRL_LVE Position */ 181 #define MXC_F_FLC_CTRL_LVE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_LVE_POS)) /**< CTRL_LVE Mask */ 182 183 #define MXC_F_FLC_CTRL_UNLOCK_POS 28 /**< CTRL_UNLOCK Position */ 184 #define MXC_F_FLC_CTRL_UNLOCK ((uint32_t)(0xFUL << MXC_F_FLC_CTRL_UNLOCK_POS)) /**< CTRL_UNLOCK Mask */ 185 #define MXC_V_FLC_CTRL_UNLOCK_UNLOCKED ((uint32_t)0x2UL) /**< CTRL_UNLOCK_UNLOCKED Value */ 186 #define MXC_S_FLC_CTRL_UNLOCK_UNLOCKED (MXC_V_FLC_CTRL_UNLOCK_UNLOCKED << MXC_F_FLC_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_UNLOCKED Setting */ 187 #define MXC_V_FLC_CTRL_UNLOCK_LOCKED ((uint32_t)0x3UL) /**< CTRL_UNLOCK_LOCKED Value */ 188 #define MXC_S_FLC_CTRL_UNLOCK_LOCKED (MXC_V_FLC_CTRL_UNLOCK_LOCKED << MXC_F_FLC_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_LOCKED Setting */ 189 190 /**@} end of group FLC_CTRL_Register */ 191 192 /** 193 * @ingroup flc_registers 194 * @defgroup FLC_INTR FLC_INTR 195 * @brief Flash Interrupt Register. 196 * @{ 197 */ 198 #define MXC_F_FLC_INTR_DONE_IF_POS 0 /**< INTR_DONE_IF Position */ 199 #define MXC_F_FLC_INTR_DONE_IF ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_IF_POS)) /**< INTR_DONE_IF Mask */ 200 201 #define MXC_F_FLC_INTR_AF_IF_POS 1 /**< INTR_AF_IF Position */ 202 #define MXC_F_FLC_INTR_AF_IF ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AF_IF_POS)) /**< INTR_AF_IF Mask */ 203 204 #define MXC_F_FLC_INTR_PROG_PROT_ERR_IF_POS 2 /**< INTR_PROG_PROT_ERR_IF Position */ 205 #define MXC_F_FLC_INTR_PROG_PROT_ERR_IF ((uint32_t)(0x1UL << MXC_F_FLC_INTR_PROG_PROT_ERR_IF_POS)) /**< INTR_PROG_PROT_ERR_IF Mask */ 206 207 #define MXC_F_FLC_INTR_MASS_ER_PROT_ERR_IF_POS 3 /**< INTR_MASS_ER_PROT_ERR_IF Position */ 208 #define MXC_F_FLC_INTR_MASS_ER_PROT_ERR_IF ((uint32_t)(0x1UL << MXC_F_FLC_INTR_MASS_ER_PROT_ERR_IF_POS)) /**< INTR_MASS_ER_PROT_ERR_IF Mask */ 209 210 #define MXC_F_FLC_INTR_PAGE_ER_PROT_ERR_IF_POS 4 /**< INTR_PAGE_ER_PROT_ERR_IF Position */ 211 #define MXC_F_FLC_INTR_PAGE_ER_PROT_ERR_IF ((uint32_t)(0x1UL << MXC_F_FLC_INTR_PAGE_ER_PROT_ERR_IF_POS)) /**< INTR_PAGE_ER_PROT_ERR_IF Mask */ 212 213 #define MXC_F_FLC_INTR_PROT_AREA_PROT_ERR_IF_POS 5 /**< INTR_PROT_AREA_PROT_ERR_IF Position */ 214 #define MXC_F_FLC_INTR_PROT_AREA_PROT_ERR_IF ((uint32_t)(0x1UL << MXC_F_FLC_INTR_PROT_AREA_PROT_ERR_IF_POS)) /**< INTR_PROT_AREA_PROT_ERR_IF Mask */ 215 216 #define MXC_F_FLC_INTR_DONE_IE_POS 8 /**< INTR_DONE_IE Position */ 217 #define MXC_F_FLC_INTR_DONE_IE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_IE_POS)) /**< INTR_DONE_IE Mask */ 218 219 #define MXC_F_FLC_INTR_AF_IE_POS 9 /**< INTR_AF_IE Position */ 220 #define MXC_F_FLC_INTR_AF_IE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AF_IE_POS)) /**< INTR_AF_IE Mask */ 221 222 #define MXC_F_FLC_INTR_PROT_IE_POS 10 /**< INTR_PROT_IE Position */ 223 #define MXC_F_FLC_INTR_PROT_IE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_PROT_IE_POS)) /**< INTR_PROT_IE Mask */ 224 225 /**@} end of group FLC_INTR_Register */ 226 227 /** 228 * @ingroup flc_registers 229 * @defgroup FLC_DATA FLC_DATA 230 * @brief Flash Write Data. 231 * @{ 232 */ 233 #define MXC_F_FLC_DATA_DATA_POS 0 /**< DATA_DATA Position */ 234 #define MXC_F_FLC_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_DATA_DATA_POS)) /**< DATA_DATA Mask */ 235 236 /**@} end of group FLC_DATA_Register */ 237 238 /** 239 * @ingroup flc_registers 240 * @defgroup FLC_ACTRL FLC_ACTRL 241 * @brief Access Control Register. Writing the ACNTL register with the following values in 242 * the order shown, allows read and write access to the system and user Information 243 * block: pflc-acntl = 0x3a7f5ca3; pflc-acntl = 0xa1e34f20; pflc-acntl = 244 * 0x9608b2c1. When unlocked, a write of any word will disable access to system and 245 * user information block. Readback of this register is always zero. 246 * @{ 247 */ 248 #define MXC_F_FLC_ACTRL_ACTRL_POS 0 /**< ACTRL_ACTRL Position */ 249 #define MXC_F_FLC_ACTRL_ACTRL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ACTRL_ACTRL_POS)) /**< ACTRL_ACTRL Mask */ 250 251 /**@} end of group FLC_ACTRL_Register */ 252 253 /** 254 * @ingroup flc_registers 255 * @defgroup FLC_WELR0 FLC_WELR0 256 * @brief Access control. 257 * @{ 258 */ 259 #define MXC_F_FLC_WELR0_WELR0_POS 0 /**< WELR0_WELR0 Position */ 260 #define MXC_F_FLC_WELR0_WELR0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_WELR0_WELR0_POS)) /**< WELR0_WELR0 Mask */ 261 262 /**@} end of group FLC_WELR0_Register */ 263 264 /** 265 * @ingroup flc_registers 266 * @defgroup FLC_RLR0 FLC_RLR0 267 * @brief Access control. 268 * @{ 269 */ 270 #define MXC_F_FLC_RLR0_RLR0_POS 0 /**< RLR0_RLR0 Position */ 271 #define MXC_F_FLC_RLR0_RLR0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_RLR0_RLR0_POS)) /**< RLR0_RLR0 Mask */ 272 273 /**@} end of group FLC_RLR0_Register */ 274 275 /** 276 * @ingroup flc_registers 277 * @defgroup FLC_WELR1 FLC_WELR1 278 * @brief Access control. 279 * @{ 280 */ 281 #define MXC_F_FLC_WELR1_WELR1_POS 0 /**< WELR1_WELR1 Position */ 282 #define MXC_F_FLC_WELR1_WELR1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_WELR1_WELR1_POS)) /**< WELR1_WELR1 Mask */ 283 284 /**@} end of group FLC_WELR1_Register */ 285 286 /** 287 * @ingroup flc_registers 288 * @defgroup FLC_RLR1 FLC_RLR1 289 * @brief Access control. 290 * @{ 291 */ 292 #define MXC_F_FLC_RLR1_RLR1_POS 0 /**< RLR1_RLR1 Position */ 293 #define MXC_F_FLC_RLR1_RLR1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_RLR1_RLR1_POS)) /**< RLR1_RLR1 Mask */ 294 295 /**@} end of group FLC_RLR1_Register */ 296 297 /** 298 * @ingroup flc_registers 299 * @defgroup FLC_WELR2 FLC_WELR2 300 * @brief Access control. 301 * @{ 302 */ 303 #define MXC_F_FLC_WELR2_WELR2_POS 0 /**< WELR2_WELR2 Position */ 304 #define MXC_F_FLC_WELR2_WELR2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_WELR2_WELR2_POS)) /**< WELR2_WELR2 Mask */ 305 306 /**@} end of group FLC_WELR2_Register */ 307 308 /** 309 * @ingroup flc_registers 310 * @defgroup FLC_RLR2 FLC_RLR2 311 * @brief Access control. 312 * @{ 313 */ 314 #define MXC_F_FLC_RLR2_RLR2_POS 0 /**< RLR2_RLR2 Position */ 315 #define MXC_F_FLC_RLR2_RLR2 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_RLR2_RLR2_POS)) /**< RLR2_RLR2 Mask */ 316 317 /**@} end of group FLC_RLR2_Register */ 318 319 /** 320 * @ingroup flc_registers 321 * @defgroup FLC_WELR3 FLC_WELR3 322 * @brief Access control. 323 * @{ 324 */ 325 #define MXC_F_FLC_WELR3_WELR3_POS 0 /**< WELR3_WELR3 Position */ 326 #define MXC_F_FLC_WELR3_WELR3 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_WELR3_WELR3_POS)) /**< WELR3_WELR3 Mask */ 327 328 /**@} end of group FLC_WELR3_Register */ 329 330 /** 331 * @ingroup flc_registers 332 * @defgroup FLC_RLR3 FLC_RLR3 333 * @brief Access control. 334 * @{ 335 */ 336 #define MXC_F_FLC_RLR3_RLR3_POS 0 /**< RLR3_RLR3 Position */ 337 #define MXC_F_FLC_RLR3_RLR3 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_RLR3_RLR3_POS)) /**< RLR3_RLR3 Mask */ 338 339 /**@} end of group FLC_RLR3_Register */ 340 341 /** 342 * @ingroup flc_registers 343 * @defgroup FLC_WELR4 FLC_WELR4 344 * @brief Access control. 345 * @{ 346 */ 347 #define MXC_F_FLC_WELR4_WELR4_POS 0 /**< WELR4_WELR4 Position */ 348 #define MXC_F_FLC_WELR4_WELR4 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_WELR4_WELR4_POS)) /**< WELR4_WELR4 Mask */ 349 350 /**@} end of group FLC_WELR4_Register */ 351 352 /** 353 * @ingroup flc_registers 354 * @defgroup FLC_RLR4 FLC_RLR4 355 * @brief Access control. 356 * @{ 357 */ 358 #define MXC_F_FLC_RLR4_RLR4_POS 0 /**< RLR4_RLR4 Position */ 359 #define MXC_F_FLC_RLR4_RLR4 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_RLR4_RLR4_POS)) /**< RLR4_RLR4 Mask */ 360 361 /**@} end of group FLC_RLR4_Register */ 362 363 /** 364 * @ingroup flc_registers 365 * @defgroup FLC_WELR5 FLC_WELR5 366 * @brief Access control. 367 * @{ 368 */ 369 #define MXC_F_FLC_WELR5_WELR5_POS 0 /**< WELR5_WELR5 Position */ 370 #define MXC_F_FLC_WELR5_WELR5 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_WELR5_WELR5_POS)) /**< WELR5_WELR5 Mask */ 371 372 /**@} end of group FLC_WELR5_Register */ 373 374 /** 375 * @ingroup flc_registers 376 * @defgroup FLC_RLR5 FLC_RLR5 377 * @brief Access control. 378 * @{ 379 */ 380 #define MXC_F_FLC_RLR5_RLR5_POS 0 /**< RLR5_RLR5 Position */ 381 #define MXC_F_FLC_RLR5_RLR5 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_RLR5_RLR5_POS)) /**< RLR5_RLR5 Mask */ 382 383 /**@} end of group FLC_RLR5_Register */ 384 385 #ifdef __cplusplus 386 } 387 #endif 388 389 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32662_INCLUDE_FLC_REGS_H_ 390
