1 /** 2 * @file dma_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup dma_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32662_INCLUDE_DMA_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32662_INCLUDE_DMA_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup dma 67 * @defgroup dma_registers DMA_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module. 69 * @details DMA Controller Fully programmable, chaining capable DMA channels. 70 */ 71 72 /** 73 * @ingroup dma_registers 74 * Structure type to access the DMA Registers. 75 */ 76 typedef struct { 77 __IO uint32_t ctrl; /**< <tt>\b 0x000:</tt> DMA CTRL Register */ 78 __IO uint32_t status; /**< <tt>\b 0x004:</tt> DMA STATUS Register */ 79 __IO uint32_t src; /**< <tt>\b 0x008:</tt> DMA SRC Register */ 80 __IO uint32_t dst; /**< <tt>\b 0x00C:</tt> DMA DST Register */ 81 __IO uint32_t cnt; /**< <tt>\b 0x010:</tt> DMA CNT Register */ 82 __IO uint32_t srcrld; /**< <tt>\b 0x014:</tt> DMA SRCRLD Register */ 83 __IO uint32_t dstrld; /**< <tt>\b 0x018:</tt> DMA DSTRLD Register */ 84 __IO uint32_t cntrld; /**< <tt>\b 0x01C:</tt> DMA CNTRLD Register */ 85 } mxc_dma_ch_regs_t; 86 87 typedef struct { 88 __IO uint32_t inten; /**< <tt>\b 0x000:</tt> DMA INTEN Register */ 89 __I uint32_t intfl; /**< <tt>\b 0x004:</tt> DMA INTFL Register */ 90 __R uint32_t rsv_0x8_0xff[62]; 91 __IO mxc_dma_ch_regs_t ch[4]; /**< <tt>\b 0x100:</tt> DMA CH Register */ 92 } mxc_dma_regs_t; 93 94 /* Register offsets for module DMA */ 95 /** 96 * @ingroup dma_registers 97 * @defgroup DMA_Register_Offsets Register Offsets 98 * @brief DMA Peripheral Register Offsets from the DMA Base Peripheral Address. 99 * @{ 100 */ 101 #define MXC_R_DMA_CTRL ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: <tt> 0x0000</tt> */ 102 #define MXC_R_DMA_STATUS ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: <tt> 0x0004</tt> */ 103 #define MXC_R_DMA_SRC ((uint32_t)0x00000008UL) /**< Offset from DMA Base Address: <tt> 0x0008</tt> */ 104 #define MXC_R_DMA_DST ((uint32_t)0x0000000CUL) /**< Offset from DMA Base Address: <tt> 0x000C</tt> */ 105 #define MXC_R_DMA_CNT ((uint32_t)0x00000010UL) /**< Offset from DMA Base Address: <tt> 0x0010</tt> */ 106 #define MXC_R_DMA_SRCRLD ((uint32_t)0x00000014UL) /**< Offset from DMA Base Address: <tt> 0x0014</tt> */ 107 #define MXC_R_DMA_DSTRLD ((uint32_t)0x00000018UL) /**< Offset from DMA Base Address: <tt> 0x0018</tt> */ 108 #define MXC_R_DMA_CNTRLD ((uint32_t)0x0000001CUL) /**< Offset from DMA Base Address: <tt> 0x001C</tt> */ 109 #define MXC_R_DMA_INTEN ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: <tt> 0x0000</tt> */ 110 #define MXC_R_DMA_INTFL ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: <tt> 0x0004</tt> */ 111 #define MXC_R_DMA_CH ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: <tt> 0x0100</tt> */ 112 /**@} end of group dma_registers */ 113 114 /** 115 * @ingroup dma_registers 116 * @defgroup DMA_INTEN DMA_INTEN 117 * @brief DMA Control Register. 118 * @{ 119 */ 120 #define MXC_F_DMA_INTEN_CH0_POS 0 /**< INTEN_CH0 Position */ 121 #define MXC_F_DMA_INTEN_CH0 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH0_POS)) /**< INTEN_CH0 Mask */ 122 123 #define MXC_F_DMA_INTEN_CH1_POS 1 /**< INTEN_CH1 Position */ 124 #define MXC_F_DMA_INTEN_CH1 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH1_POS)) /**< INTEN_CH1 Mask */ 125 126 #define MXC_F_DMA_INTEN_CH2_POS 2 /**< INTEN_CH2 Position */ 127 #define MXC_F_DMA_INTEN_CH2 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH2_POS)) /**< INTEN_CH2 Mask */ 128 129 #define MXC_F_DMA_INTEN_CH3_POS 3 /**< INTEN_CH3 Position */ 130 #define MXC_F_DMA_INTEN_CH3 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH3_POS)) /**< INTEN_CH3 Mask */ 131 132 /**@} end of group DMA_INTEN_Register */ 133 134 /** 135 * @ingroup dma_registers 136 * @defgroup DMA_INTFL DMA_INTFL 137 * @brief DMA Interrupt Register. 138 * @{ 139 */ 140 #define MXC_F_DMA_INTFL_CH0_POS 0 /**< INTFL_CH0 Position */ 141 #define MXC_F_DMA_INTFL_CH0 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH0_POS)) /**< INTFL_CH0 Mask */ 142 143 #define MXC_F_DMA_INTFL_CH1_POS 1 /**< INTFL_CH1 Position */ 144 #define MXC_F_DMA_INTFL_CH1 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH1_POS)) /**< INTFL_CH1 Mask */ 145 146 #define MXC_F_DMA_INTFL_CH2_POS 2 /**< INTFL_CH2 Position */ 147 #define MXC_F_DMA_INTFL_CH2 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH2_POS)) /**< INTFL_CH2 Mask */ 148 149 #define MXC_F_DMA_INTFL_CH3_POS 3 /**< INTFL_CH3 Position */ 150 #define MXC_F_DMA_INTFL_CH3 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH3_POS)) /**< INTFL_CH3 Mask */ 151 152 /**@} end of group DMA_INTFL_Register */ 153 154 /** 155 * @ingroup dma_registers 156 * @defgroup DMA_CTRL DMA_CTRL 157 * @brief DMA Channel Control Register. 158 * @{ 159 */ 160 #define MXC_F_DMA_CTRL_EN_POS 0 /**< CTRL_EN Position */ 161 #define MXC_F_DMA_CTRL_EN ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_EN_POS)) /**< CTRL_EN Mask */ 162 163 #define MXC_F_DMA_CTRL_RLDEN_POS 1 /**< CTRL_RLDEN Position */ 164 #define MXC_F_DMA_CTRL_RLDEN ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_RLDEN_POS)) /**< CTRL_RLDEN Mask */ 165 166 #define MXC_F_DMA_CTRL_PRI_POS 2 /**< CTRL_PRI Position */ 167 #define MXC_F_DMA_CTRL_PRI ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_PRI_POS)) /**< CTRL_PRI Mask */ 168 #define MXC_V_DMA_CTRL_PRI_HIGH ((uint32_t)0x0UL) /**< CTRL_PRI_HIGH Value */ 169 #define MXC_S_DMA_CTRL_PRI_HIGH (MXC_V_DMA_CTRL_PRI_HIGH << MXC_F_DMA_CTRL_PRI_POS) /**< CTRL_PRI_HIGH Setting */ 170 #define MXC_V_DMA_CTRL_PRI_MEDHIGH ((uint32_t)0x1UL) /**< CTRL_PRI_MEDHIGH Value */ 171 #define MXC_S_DMA_CTRL_PRI_MEDHIGH (MXC_V_DMA_CTRL_PRI_MEDHIGH << MXC_F_DMA_CTRL_PRI_POS) /**< CTRL_PRI_MEDHIGH Setting */ 172 #define MXC_V_DMA_CTRL_PRI_MEDLOW ((uint32_t)0x2UL) /**< CTRL_PRI_MEDLOW Value */ 173 #define MXC_S_DMA_CTRL_PRI_MEDLOW (MXC_V_DMA_CTRL_PRI_MEDLOW << MXC_F_DMA_CTRL_PRI_POS) /**< CTRL_PRI_MEDLOW Setting */ 174 #define MXC_V_DMA_CTRL_PRI_LOW ((uint32_t)0x3UL) /**< CTRL_PRI_LOW Value */ 175 #define MXC_S_DMA_CTRL_PRI_LOW (MXC_V_DMA_CTRL_PRI_LOW << MXC_F_DMA_CTRL_PRI_POS) /**< CTRL_PRI_LOW Setting */ 176 177 #define MXC_F_DMA_CTRL_REQUEST_POS 4 /**< CTRL_REQUEST Position */ 178 #define MXC_F_DMA_CTRL_REQUEST ((uint32_t)(0x3FUL << MXC_F_DMA_CTRL_REQUEST_POS)) /**< CTRL_REQUEST Mask */ 179 #define MXC_V_DMA_CTRL_REQUEST_MEMTOMEM ((uint32_t)0x0UL) /**< CTRL_REQUEST_MEMTOMEM Value */ 180 #define MXC_S_DMA_CTRL_REQUEST_MEMTOMEM (MXC_V_DMA_CTRL_REQUEST_MEMTOMEM << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_MEMTOMEM Setting */ 181 #define MXC_V_DMA_CTRL_REQUEST_SPI0RX ((uint32_t)0x1UL) /**< CTRL_REQUEST_SPI0RX Value */ 182 #define MXC_S_DMA_CTRL_REQUEST_SPI0RX (MXC_V_DMA_CTRL_REQUEST_SPI0RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI0RX Setting */ 183 #define MXC_V_DMA_CTRL_REQUEST_SPI1RX ((uint32_t)0x2UL) /**< CTRL_REQUEST_SPI1RX Value */ 184 #define MXC_S_DMA_CTRL_REQUEST_SPI1RX (MXC_V_DMA_CTRL_REQUEST_SPI1RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI1RX Setting */ 185 #define MXC_V_DMA_CTRL_REQUEST_UART0RX ((uint32_t)0x4UL) /**< CTRL_REQUEST_UART0RX Value */ 186 #define MXC_S_DMA_CTRL_REQUEST_UART0RX (MXC_V_DMA_CTRL_REQUEST_UART0RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART0RX Setting */ 187 #define MXC_V_DMA_CTRL_REQUEST_UART1RX ((uint32_t)0x5UL) /**< CTRL_REQUEST_UART1RX Value */ 188 #define MXC_S_DMA_CTRL_REQUEST_UART1RX (MXC_V_DMA_CTRL_REQUEST_UART1RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART1RX Setting */ 189 #define MXC_V_DMA_CTRL_REQUEST_CANRX ((uint32_t)0x6UL) /**< CTRL_REQUEST_CANRX Value */ 190 #define MXC_S_DMA_CTRL_REQUEST_CANRX (MXC_V_DMA_CTRL_REQUEST_CANRX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_CANRX Setting */ 191 #define MXC_V_DMA_CTRL_REQUEST_I2C0RX ((uint32_t)0x7UL) /**< CTRL_REQUEST_I2C0RX Value */ 192 #define MXC_S_DMA_CTRL_REQUEST_I2C0RX (MXC_V_DMA_CTRL_REQUEST_I2C0RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C0RX Setting */ 193 #define MXC_V_DMA_CTRL_REQUEST_I2C1RX ((uint32_t)0x8UL) /**< CTRL_REQUEST_I2C1RX Value */ 194 #define MXC_S_DMA_CTRL_REQUEST_I2C1RX (MXC_V_DMA_CTRL_REQUEST_I2C1RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C1RX Setting */ 195 #define MXC_V_DMA_CTRL_REQUEST_ADC ((uint32_t)0x9UL) /**< CTRL_REQUEST_ADC Value */ 196 #define MXC_S_DMA_CTRL_REQUEST_ADC (MXC_V_DMA_CTRL_REQUEST_ADC << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_ADC Setting */ 197 #define MXC_V_DMA_CTRL_REQUEST_AESRX ((uint32_t)0x10UL) /**< CTRL_REQUEST_AESRX Value */ 198 #define MXC_S_DMA_CTRL_REQUEST_AESRX (MXC_V_DMA_CTRL_REQUEST_AESRX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_AESRX Setting */ 199 #define MXC_V_DMA_CTRL_REQUEST_I2SRX ((uint32_t)0x1EUL) /**< CTRL_REQUEST_I2SRX Value */ 200 #define MXC_S_DMA_CTRL_REQUEST_I2SRX (MXC_V_DMA_CTRL_REQUEST_I2SRX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2SRX Setting */ 201 #define MXC_V_DMA_CTRL_REQUEST_SPI0TX ((uint32_t)0x21UL) /**< CTRL_REQUEST_SPI0TX Value */ 202 #define MXC_S_DMA_CTRL_REQUEST_SPI0TX (MXC_V_DMA_CTRL_REQUEST_SPI0TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI0TX Setting */ 203 #define MXC_V_DMA_CTRL_REQUEST_SPI1TX ((uint32_t)0x22UL) /**< CTRL_REQUEST_SPI1TX Value */ 204 #define MXC_S_DMA_CTRL_REQUEST_SPI1TX (MXC_V_DMA_CTRL_REQUEST_SPI1TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI1TX Setting */ 205 #define MXC_V_DMA_CTRL_REQUEST_UART0TX ((uint32_t)0x24UL) /**< CTRL_REQUEST_UART0TX Value */ 206 #define MXC_S_DMA_CTRL_REQUEST_UART0TX (MXC_V_DMA_CTRL_REQUEST_UART0TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART0TX Setting */ 207 #define MXC_V_DMA_CTRL_REQUEST_UART1TX ((uint32_t)0x25UL) /**< CTRL_REQUEST_UART1TX Value */ 208 #define MXC_S_DMA_CTRL_REQUEST_UART1TX (MXC_V_DMA_CTRL_REQUEST_UART1TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART1TX Setting */ 209 #define MXC_V_DMA_CTRL_REQUEST_CANTX ((uint32_t)0x26UL) /**< CTRL_REQUEST_CANTX Value */ 210 #define MXC_S_DMA_CTRL_REQUEST_CANTX (MXC_V_DMA_CTRL_REQUEST_CANTX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_CANTX Setting */ 211 #define MXC_V_DMA_CTRL_REQUEST_I2C0TX ((uint32_t)0x27UL) /**< CTRL_REQUEST_I2C0TX Value */ 212 #define MXC_S_DMA_CTRL_REQUEST_I2C0TX (MXC_V_DMA_CTRL_REQUEST_I2C0TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C0TX Setting */ 213 #define MXC_V_DMA_CTRL_REQUEST_I2C1TX ((uint32_t)0x28UL) /**< CTRL_REQUEST_I2C1TX Value */ 214 #define MXC_S_DMA_CTRL_REQUEST_I2C1TX (MXC_V_DMA_CTRL_REQUEST_I2C1TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C1TX Setting */ 215 #define MXC_V_DMA_CTRL_REQUEST_AESTX ((uint32_t)0x30UL) /**< CTRL_REQUEST_AESTX Value */ 216 #define MXC_S_DMA_CTRL_REQUEST_AESTX (MXC_V_DMA_CTRL_REQUEST_AESTX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_AESTX Setting */ 217 #define MXC_V_DMA_CTRL_REQUEST_I2STX ((uint32_t)0x3EUL) /**< CTRL_REQUEST_I2STX Value */ 218 #define MXC_S_DMA_CTRL_REQUEST_I2STX (MXC_V_DMA_CTRL_REQUEST_I2STX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2STX Setting */ 219 220 #define MXC_F_DMA_CTRL_TO_WAIT_POS 10 /**< CTRL_TO_WAIT Position */ 221 #define MXC_F_DMA_CTRL_TO_WAIT ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_TO_WAIT_POS)) /**< CTRL_TO_WAIT Mask */ 222 223 #define MXC_F_DMA_CTRL_TO_PER_POS 11 /**< CTRL_TO_PER Position */ 224 #define MXC_F_DMA_CTRL_TO_PER ((uint32_t)(0x7UL << MXC_F_DMA_CTRL_TO_PER_POS)) /**< CTRL_TO_PER Mask */ 225 #define MXC_V_DMA_CTRL_TO_PER_TO4 ((uint32_t)0x0UL) /**< CTRL_TO_PER_TO4 Value */ 226 #define MXC_S_DMA_CTRL_TO_PER_TO4 (MXC_V_DMA_CTRL_TO_PER_TO4 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO4 Setting */ 227 #define MXC_V_DMA_CTRL_TO_PER_TO8 ((uint32_t)0x1UL) /**< CTRL_TO_PER_TO8 Value */ 228 #define MXC_S_DMA_CTRL_TO_PER_TO8 (MXC_V_DMA_CTRL_TO_PER_TO8 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO8 Setting */ 229 #define MXC_V_DMA_CTRL_TO_PER_TO16 ((uint32_t)0x2UL) /**< CTRL_TO_PER_TO16 Value */ 230 #define MXC_S_DMA_CTRL_TO_PER_TO16 (MXC_V_DMA_CTRL_TO_PER_TO16 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO16 Setting */ 231 #define MXC_V_DMA_CTRL_TO_PER_TO32 ((uint32_t)0x3UL) /**< CTRL_TO_PER_TO32 Value */ 232 #define MXC_S_DMA_CTRL_TO_PER_TO32 (MXC_V_DMA_CTRL_TO_PER_TO32 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO32 Setting */ 233 #define MXC_V_DMA_CTRL_TO_PER_TO64 ((uint32_t)0x4UL) /**< CTRL_TO_PER_TO64 Value */ 234 #define MXC_S_DMA_CTRL_TO_PER_TO64 (MXC_V_DMA_CTRL_TO_PER_TO64 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO64 Setting */ 235 #define MXC_V_DMA_CTRL_TO_PER_TO128 ((uint32_t)0x5UL) /**< CTRL_TO_PER_TO128 Value */ 236 #define MXC_S_DMA_CTRL_TO_PER_TO128 (MXC_V_DMA_CTRL_TO_PER_TO128 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO128 Setting */ 237 #define MXC_V_DMA_CTRL_TO_PER_TO256 ((uint32_t)0x6UL) /**< CTRL_TO_PER_TO256 Value */ 238 #define MXC_S_DMA_CTRL_TO_PER_TO256 (MXC_V_DMA_CTRL_TO_PER_TO256 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO256 Setting */ 239 #define MXC_V_DMA_CTRL_TO_PER_TO512 ((uint32_t)0x7UL) /**< CTRL_TO_PER_TO512 Value */ 240 #define MXC_S_DMA_CTRL_TO_PER_TO512 (MXC_V_DMA_CTRL_TO_PER_TO512 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO512 Setting */ 241 242 #define MXC_F_DMA_CTRL_TO_CLKDIV_POS 14 /**< CTRL_TO_CLKDIV Position */ 243 #define MXC_F_DMA_CTRL_TO_CLKDIV ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_TO_CLKDIV_POS)) /**< CTRL_TO_CLKDIV Mask */ 244 #define MXC_V_DMA_CTRL_TO_CLKDIV_DIS ((uint32_t)0x0UL) /**< CTRL_TO_CLKDIV_DIS Value */ 245 #define MXC_S_DMA_CTRL_TO_CLKDIV_DIS (MXC_V_DMA_CTRL_TO_CLKDIV_DIS << MXC_F_DMA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIS Setting */ 246 #define MXC_V_DMA_CTRL_TO_CLKDIV_DIV256 ((uint32_t)0x1UL) /**< CTRL_TO_CLKDIV_DIV256 Value */ 247 #define MXC_S_DMA_CTRL_TO_CLKDIV_DIV256 (MXC_V_DMA_CTRL_TO_CLKDIV_DIV256 << MXC_F_DMA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIV256 Setting */ 248 #define MXC_V_DMA_CTRL_TO_CLKDIV_DIV64K ((uint32_t)0x2UL) /**< CTRL_TO_CLKDIV_DIV64K Value */ 249 #define MXC_S_DMA_CTRL_TO_CLKDIV_DIV64K (MXC_V_DMA_CTRL_TO_CLKDIV_DIV64K << MXC_F_DMA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIV64K Setting */ 250 #define MXC_V_DMA_CTRL_TO_CLKDIV_DIV16M ((uint32_t)0x3UL) /**< CTRL_TO_CLKDIV_DIV16M Value */ 251 #define MXC_S_DMA_CTRL_TO_CLKDIV_DIV16M (MXC_V_DMA_CTRL_TO_CLKDIV_DIV16M << MXC_F_DMA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIV16M Setting */ 252 253 #define MXC_F_DMA_CTRL_SRCWD_POS 16 /**< CTRL_SRCWD Position */ 254 #define MXC_F_DMA_CTRL_SRCWD ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_SRCWD_POS)) /**< CTRL_SRCWD Mask */ 255 #define MXC_V_DMA_CTRL_SRCWD_BYTE ((uint32_t)0x0UL) /**< CTRL_SRCWD_BYTE Value */ 256 #define MXC_S_DMA_CTRL_SRCWD_BYTE (MXC_V_DMA_CTRL_SRCWD_BYTE << MXC_F_DMA_CTRL_SRCWD_POS) /**< CTRL_SRCWD_BYTE Setting */ 257 #define MXC_V_DMA_CTRL_SRCWD_HALFWORD ((uint32_t)0x1UL) /**< CTRL_SRCWD_HALFWORD Value */ 258 #define MXC_S_DMA_CTRL_SRCWD_HALFWORD (MXC_V_DMA_CTRL_SRCWD_HALFWORD << MXC_F_DMA_CTRL_SRCWD_POS) /**< CTRL_SRCWD_HALFWORD Setting */ 259 #define MXC_V_DMA_CTRL_SRCWD_WORD ((uint32_t)0x2UL) /**< CTRL_SRCWD_WORD Value */ 260 #define MXC_S_DMA_CTRL_SRCWD_WORD (MXC_V_DMA_CTRL_SRCWD_WORD << MXC_F_DMA_CTRL_SRCWD_POS) /**< CTRL_SRCWD_WORD Setting */ 261 262 #define MXC_F_DMA_CTRL_SRCINC_POS 18 /**< CTRL_SRCINC Position */ 263 #define MXC_F_DMA_CTRL_SRCINC ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_SRCINC_POS)) /**< CTRL_SRCINC Mask */ 264 265 #define MXC_F_DMA_CTRL_DSTWD_POS 20 /**< CTRL_DSTWD Position */ 266 #define MXC_F_DMA_CTRL_DSTWD ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_DSTWD_POS)) /**< CTRL_DSTWD Mask */ 267 #define MXC_V_DMA_CTRL_DSTWD_BYTE ((uint32_t)0x0UL) /**< CTRL_DSTWD_BYTE Value */ 268 #define MXC_S_DMA_CTRL_DSTWD_BYTE (MXC_V_DMA_CTRL_DSTWD_BYTE << MXC_F_DMA_CTRL_DSTWD_POS) /**< CTRL_DSTWD_BYTE Setting */ 269 #define MXC_V_DMA_CTRL_DSTWD_HALFWORD ((uint32_t)0x1UL) /**< CTRL_DSTWD_HALFWORD Value */ 270 #define MXC_S_DMA_CTRL_DSTWD_HALFWORD (MXC_V_DMA_CTRL_DSTWD_HALFWORD << MXC_F_DMA_CTRL_DSTWD_POS) /**< CTRL_DSTWD_HALFWORD Setting */ 271 #define MXC_V_DMA_CTRL_DSTWD_WORD ((uint32_t)0x2UL) /**< CTRL_DSTWD_WORD Value */ 272 #define MXC_S_DMA_CTRL_DSTWD_WORD (MXC_V_DMA_CTRL_DSTWD_WORD << MXC_F_DMA_CTRL_DSTWD_POS) /**< CTRL_DSTWD_WORD Setting */ 273 274 #define MXC_F_DMA_CTRL_DSTINC_POS 22 /**< CTRL_DSTINC Position */ 275 #define MXC_F_DMA_CTRL_DSTINC ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_DSTINC_POS)) /**< CTRL_DSTINC Mask */ 276 277 #define MXC_F_DMA_CTRL_BURST_SIZE_POS 24 /**< CTRL_BURST_SIZE Position */ 278 #define MXC_F_DMA_CTRL_BURST_SIZE ((uint32_t)(0x1FUL << MXC_F_DMA_CTRL_BURST_SIZE_POS)) /**< CTRL_BURST_SIZE Mask */ 279 280 #define MXC_F_DMA_CTRL_DIS_IE_POS 30 /**< CTRL_DIS_IE Position */ 281 #define MXC_F_DMA_CTRL_DIS_IE ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_DIS_IE_POS)) /**< CTRL_DIS_IE Mask */ 282 283 #define MXC_F_DMA_CTRL_CTZ_IE_POS 31 /**< CTRL_CTZ_IE Position */ 284 #define MXC_F_DMA_CTRL_CTZ_IE ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_CTZ_IE_POS)) /**< CTRL_CTZ_IE Mask */ 285 286 /**@} end of group DMA_CTRL_Register */ 287 288 /** 289 * @ingroup dma_registers 290 * @defgroup DMA_STATUS DMA_STATUS 291 * @brief DMA Channel Status Register. 292 * @{ 293 */ 294 #define MXC_F_DMA_STATUS_STATUS_POS 0 /**< STATUS_STATUS Position */ 295 #define MXC_F_DMA_STATUS_STATUS ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_STATUS_POS)) /**< STATUS_STATUS Mask */ 296 297 #define MXC_F_DMA_STATUS_IPEND_POS 1 /**< STATUS_IPEND Position */ 298 #define MXC_F_DMA_STATUS_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_IPEND_POS)) /**< STATUS_IPEND Mask */ 299 300 #define MXC_F_DMA_STATUS_CTZ_IF_POS 2 /**< STATUS_CTZ_IF Position */ 301 #define MXC_F_DMA_STATUS_CTZ_IF ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_CTZ_IF_POS)) /**< STATUS_CTZ_IF Mask */ 302 303 #define MXC_F_DMA_STATUS_RLD_IF_POS 3 /**< STATUS_RLD_IF Position */ 304 #define MXC_F_DMA_STATUS_RLD_IF ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_RLD_IF_POS)) /**< STATUS_RLD_IF Mask */ 305 306 #define MXC_F_DMA_STATUS_BUS_ERR_POS 4 /**< STATUS_BUS_ERR Position */ 307 #define MXC_F_DMA_STATUS_BUS_ERR ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_BUS_ERR_POS)) /**< STATUS_BUS_ERR Mask */ 308 309 #define MXC_F_DMA_STATUS_TO_IF_POS 6 /**< STATUS_TO_IF Position */ 310 #define MXC_F_DMA_STATUS_TO_IF ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_TO_IF_POS)) /**< STATUS_TO_IF Mask */ 311 312 /**@} end of group DMA_STATUS_Register */ 313 314 /** 315 * @ingroup dma_registers 316 * @defgroup DMA_SRC DMA_SRC 317 * @brief Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 318 * 4, depending on the data width of each AHB cycle. For peripheral transfers, some 319 * or all of the actual address bits are fixed. If SRCINC=0, this register remains 320 * constant. In the case where a count-to-zero condition occurs while RLDEN=1, the 321 * register is reloaded with the contents of DMA_SRC_RLD. 322 * @{ 323 */ 324 #define MXC_F_DMA_SRC_ADDR_POS 0 /**< SRC_ADDR Position */ 325 #define MXC_F_DMA_SRC_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_SRC_ADDR_POS)) /**< SRC_ADDR Mask */ 326 327 /**@} end of group DMA_SRC_Register */ 328 329 /** 330 * @ingroup dma_registers 331 * @defgroup DMA_DST DMA_DST 332 * @brief Destination Device Address. For peripheral transfers, some or all of the actual 333 * address bits are fixed. If DSTINC=1, this register is incremented on every AHB 334 * write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the 335 * data width of each AHB cycle. In the case where a count-to-zero condition occurs 336 * while RLDEN=1, the register is reloaded with DMA_DST_RLD. 337 * @{ 338 */ 339 #define MXC_F_DMA_DST_ADDR_POS 0 /**< DST_ADDR Position */ 340 #define MXC_F_DMA_DST_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_DST_ADDR_POS)) /**< DST_ADDR Mask */ 341 342 /**@} end of group DMA_DST_Register */ 343 344 /** 345 * @ingroup dma_registers 346 * @defgroup DMA_CNT DMA_CNT 347 * @brief DMA Counter. The user loads this register with the number of bytes to transfer. 348 * This counter decreases on every AHB cycle into the DMA FIFO. The decrement will 349 * be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter 350 * reaches 0, a count-to-zero condition is triggered. 351 * @{ 352 */ 353 #define MXC_F_DMA_CNT_CNT_POS 0 /**< CNT_CNT Position */ 354 #define MXC_F_DMA_CNT_CNT ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNT_CNT_POS)) /**< CNT_CNT Mask */ 355 356 /**@} end of group DMA_CNT_Register */ 357 358 /** 359 * @ingroup dma_registers 360 * @defgroup DMA_SRCRLD DMA_SRCRLD 361 * @brief Source Address Reload Value. The value of this register is loaded into DMA0_SRC 362 * upon a count-to-zero condition. 363 * @{ 364 */ 365 #define MXC_F_DMA_SRCRLD_ADDR_POS 0 /**< SRCRLD_ADDR Position */ 366 #define MXC_F_DMA_SRCRLD_ADDR ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_SRCRLD_ADDR_POS)) /**< SRCRLD_ADDR Mask */ 367 368 /**@} end of group DMA_SRCRLD_Register */ 369 370 /** 371 * @ingroup dma_registers 372 * @defgroup DMA_DSTRLD DMA_DSTRLD 373 * @brief Destination Address Reload Value. The value of this register is loaded into 374 * DMA0_DST upon a count-to-zero condition. 375 * @{ 376 */ 377 #define MXC_F_DMA_DSTRLD_ADDR_POS 0 /**< DSTRLD_ADDR Position */ 378 #define MXC_F_DMA_DSTRLD_ADDR ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_DSTRLD_ADDR_POS)) /**< DSTRLD_ADDR Mask */ 379 380 /**@} end of group DMA_DSTRLD_Register */ 381 382 /** 383 * @ingroup dma_registers 384 * @defgroup DMA_CNTRLD DMA_CNTRLD 385 * @brief DMA Channel Count Reload Register. 386 * @{ 387 */ 388 #define MXC_F_DMA_CNTRLD_CNT_POS 0 /**< CNTRLD_CNT Position */ 389 #define MXC_F_DMA_CNTRLD_CNT ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNTRLD_CNT_POS)) /**< CNTRLD_CNT Mask */ 390 391 #define MXC_F_DMA_CNTRLD_EN_POS 31 /**< CNTRLD_EN Position */ 392 #define MXC_F_DMA_CNTRLD_EN ((uint32_t)(0x1UL << MXC_F_DMA_CNTRLD_EN_POS)) /**< CNTRLD_EN Mask */ 393 394 /**@} end of group DMA_CNTRLD_Register */ 395 396 #ifdef __cplusplus 397 } 398 #endif 399 400 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32662_INCLUDE_DMA_REGS_H_ 401
