1 /** 2 * @file can_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the CAN Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup can_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32662_INCLUDE_CAN_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32662_INCLUDE_CAN_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup can 67 * @defgroup can_registers CAN_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the CAN Peripheral Module. 69 * @details Controller Area Network Registers 70 */ 71 72 /** 73 * @ingroup can_registers 74 * Structure type to access the CAN Registers. 75 */ 76 typedef struct { 77 __IO uint8_t mode; /**< <tt>\b 0x0000:</tt> CAN MODE Register */ 78 __IO uint8_t cmd; /**< <tt>\b 0x0001:</tt> CAN CMD Register */ 79 __I uint8_t stat; /**< <tt>\b 0x0002:</tt> CAN STAT Register */ 80 __IO uint8_t intfl; /**< <tt>\b 0x0003:</tt> CAN INTFL Register */ 81 __IO uint8_t inten; /**< <tt>\b 0x0004:</tt> CAN INTEN Register */ 82 __IO uint8_t rmc; /**< <tt>\b 0x0005:</tt> CAN RMC Register */ 83 __IO uint8_t bustim0; /**< <tt>\b 0x0006:</tt> CAN BUSTIM0 Register */ 84 __IO uint8_t bustim1; /**< <tt>\b 0x0007:</tt> CAN BUSTIM1 Register */ 85 union { 86 __IO uint32_t txfifo32; /**< <tt>\b 0x0008:</tt> CAN TXFIFO32 Register */ 87 __IO uint16_t txfifo16[2]; /**< <tt>\b 0x0008:</tt> CAN TXFIFO16 Register */ 88 __IO uint8_t txfifo8[4]; /**< <tt>\b 0x0008:</tt> CAN TXFIFO8 Register */ 89 }; 90 union { 91 __I uint32_t rxfifo32; /**< <tt>\b 0x000C:</tt> CAN RXFIFO32 Register */ 92 __I uint16_t rxfifo16[2]; /**< <tt>\b 0x000C:</tt> CAN RXFIFO16 Register */ 93 __I uint8_t rxfifo8[4]; /**< <tt>\b 0x000C:</tt> CAN RXFIFO8 Register */ 94 }; 95 union { 96 __IO uint32_t acr32; /**< <tt>\b 0x0010:</tt> CAN ACR32 Register */ 97 __IO uint16_t acr16[2]; /**< <tt>\b 0x0010:</tt> CAN ACR16 Register */ 98 __IO uint8_t acr8[4]; /**< <tt>\b 0x0010:</tt> CAN ACR8 Register */ 99 }; 100 union { 101 __IO uint32_t amr32; /**< <tt>\b 0x0014:</tt> CAN AMR32 Register */ 102 __IO uint16_t amr16[2]; /**< <tt>\b 0x0014:</tt> CAN AMR16 Register */ 103 __IO uint8_t amr8[4]; /**< <tt>\b 0x0014:</tt> CAN AMR8 Register */ 104 }; 105 __I uint8_t ecc; /**< <tt>\b 0x0018:</tt> CAN ECC Register */ 106 __IO uint8_t rxerr; /**< <tt>\b 0x0019:</tt> CAN RXERR Register */ 107 __IO uint8_t txerr; /**< <tt>\b 0x001A:</tt> CAN TXERR Register */ 108 __I uint8_t alc; /**< <tt>\b 0x001B:</tt> CAN ALC Register */ 109 __IO uint32_t nbt; /**< <tt>\b 0x001C:</tt> CAN NBT Register */ 110 __IO uint32_t dbt_sspp; /**< <tt>\b 0x0020:</tt> CAN DBT_SSPP Register */ 111 __IO uint8_t fdctrl; /**< <tt>\b 0x0024:</tt> CAN FDCTRL Register */ 112 __I uint8_t fdstat; /**< <tt>\b 0x0025:</tt> CAN FDSTAT Register */ 113 __I uint8_t dperr; /**< <tt>\b 0x0026:</tt> CAN DPERR Register */ 114 __I uint8_t aperr; /**< <tt>\b 0x0027:</tt> CAN APERR Register */ 115 __IO uint8_t test; /**< <tt>\b 0x0028:</tt> CAN TEST Register */ 116 __IO uint8_t wupclkdiv; /**< <tt>\b 0x0029:</tt> CAN WUPCLKDIV Register */ 117 __IO uint16_t wupft; /**< <tt>\b 0x002A:</tt> CAN WUPFT Register */ 118 __IO uint32_t wupet; /**< <tt>\b 0x002C:</tt> CAN WUPET Register */ 119 __IO uint16_t rxdcnt; /**< <tt>\b 0x0030:</tt> CAN RXDCNT Register */ 120 __IO uint8_t txscnt; /**< <tt>\b 0x0032:</tt> CAN TXSCNT Register */ 121 __IO uint8_t txdecmp; /**< <tt>\b 0x0033:</tt> CAN TXDECMP Register */ 122 __IO uint8_t eintfl; /**< <tt>\b 0x0034:</tt> CAN EINTFL Register */ 123 __IO uint8_t einten; /**< <tt>\b 0x0035:</tt> CAN EINTEN Register */ 124 __IO uint16_t rxto; /**< <tt>\b 0x0036:</tt> CAN RXTO Register */ 125 } mxc_can_regs_t; 126 127 /* Register offsets for module CAN */ 128 /** 129 * @ingroup can_registers 130 * @defgroup CAN_Register_Offsets Register Offsets 131 * @brief CAN Peripheral Register Offsets from the CAN Base Peripheral Address. 132 * @{ 133 */ 134 #define MXC_R_CAN_MODE ((uint32_t)0x00000000UL) /**< Offset from CAN Base Address: <tt> 0x0000</tt> */ 135 #define MXC_R_CAN_CMD ((uint32_t)0x00000001UL) /**< Offset from CAN Base Address: <tt> 0x0001</tt> */ 136 #define MXC_R_CAN_STAT ((uint32_t)0x00000002UL) /**< Offset from CAN Base Address: <tt> 0x0002</tt> */ 137 #define MXC_R_CAN_INTFL ((uint32_t)0x00000003UL) /**< Offset from CAN Base Address: <tt> 0x0003</tt> */ 138 #define MXC_R_CAN_INTEN ((uint32_t)0x00000004UL) /**< Offset from CAN Base Address: <tt> 0x0004</tt> */ 139 #define MXC_R_CAN_RMC ((uint32_t)0x00000005UL) /**< Offset from CAN Base Address: <tt> 0x0005</tt> */ 140 #define MXC_R_CAN_BUSTIM0 ((uint32_t)0x00000006UL) /**< Offset from CAN Base Address: <tt> 0x0006</tt> */ 141 #define MXC_R_CAN_BUSTIM1 ((uint32_t)0x00000007UL) /**< Offset from CAN Base Address: <tt> 0x0007</tt> */ 142 #define MXC_R_CAN_TXFIFO32 ((uint32_t)0x00000008UL) /**< Offset from CAN Base Address: <tt> 0x0008</tt> */ 143 #define MXC_R_CAN_TXFIFO16 ((uint32_t)0x00000008UL) /**< Offset from CAN Base Address: <tt> 0x0008</tt> */ 144 #define MXC_R_CAN_TXFIFO8 ((uint32_t)0x00000008UL) /**< Offset from CAN Base Address: <tt> 0x0008</tt> */ 145 #define MXC_R_CAN_RXFIFO32 ((uint32_t)0x0000000CUL) /**< Offset from CAN Base Address: <tt> 0x000C</tt> */ 146 #define MXC_R_CAN_RXFIFO16 ((uint32_t)0x0000000CUL) /**< Offset from CAN Base Address: <tt> 0x000C</tt> */ 147 #define MXC_R_CAN_RXFIFO8 ((uint32_t)0x0000000CUL) /**< Offset from CAN Base Address: <tt> 0x000C</tt> */ 148 #define MXC_R_CAN_ACR32 ((uint32_t)0x00000010UL) /**< Offset from CAN Base Address: <tt> 0x0010</tt> */ 149 #define MXC_R_CAN_ACR16 ((uint32_t)0x00000010UL) /**< Offset from CAN Base Address: <tt> 0x0010</tt> */ 150 #define MXC_R_CAN_ACR8 ((uint32_t)0x00000010UL) /**< Offset from CAN Base Address: <tt> 0x0010</tt> */ 151 #define MXC_R_CAN_AMR32 ((uint32_t)0x00000014UL) /**< Offset from CAN Base Address: <tt> 0x0014</tt> */ 152 #define MXC_R_CAN_AMR16 ((uint32_t)0x00000014UL) /**< Offset from CAN Base Address: <tt> 0x0014</tt> */ 153 #define MXC_R_CAN_AMR8 ((uint32_t)0x00000014UL) /**< Offset from CAN Base Address: <tt> 0x0014</tt> */ 154 #define MXC_R_CAN_ECC ((uint32_t)0x00000018UL) /**< Offset from CAN Base Address: <tt> 0x0018</tt> */ 155 #define MXC_R_CAN_RXERR ((uint32_t)0x00000019UL) /**< Offset from CAN Base Address: <tt> 0x0019</tt> */ 156 #define MXC_R_CAN_TXERR ((uint32_t)0x0000001AUL) /**< Offset from CAN Base Address: <tt> 0x001A</tt> */ 157 #define MXC_R_CAN_ALC ((uint32_t)0x0000001BUL) /**< Offset from CAN Base Address: <tt> 0x001B</tt> */ 158 #define MXC_R_CAN_NBT ((uint32_t)0x0000001CUL) /**< Offset from CAN Base Address: <tt> 0x001C</tt> */ 159 #define MXC_R_CAN_DBT_SSPP ((uint32_t)0x00000020UL) /**< Offset from CAN Base Address: <tt> 0x0020</tt> */ 160 #define MXC_R_CAN_FDCTRL ((uint32_t)0x00000024UL) /**< Offset from CAN Base Address: <tt> 0x0024</tt> */ 161 #define MXC_R_CAN_FDSTAT ((uint32_t)0x00000025UL) /**< Offset from CAN Base Address: <tt> 0x0025</tt> */ 162 #define MXC_R_CAN_DPERR ((uint32_t)0x00000026UL) /**< Offset from CAN Base Address: <tt> 0x0026</tt> */ 163 #define MXC_R_CAN_APERR ((uint32_t)0x00000027UL) /**< Offset from CAN Base Address: <tt> 0x0027</tt> */ 164 #define MXC_R_CAN_TEST ((uint32_t)0x00000028UL) /**< Offset from CAN Base Address: <tt> 0x0028</tt> */ 165 #define MXC_R_CAN_WUPCLKDIV ((uint32_t)0x00000029UL) /**< Offset from CAN Base Address: <tt> 0x0029</tt> */ 166 #define MXC_R_CAN_WUPFT ((uint32_t)0x0000002AUL) /**< Offset from CAN Base Address: <tt> 0x002A</tt> */ 167 #define MXC_R_CAN_WUPET ((uint32_t)0x0000002CUL) /**< Offset from CAN Base Address: <tt> 0x002C</tt> */ 168 #define MXC_R_CAN_RXDCNT ((uint32_t)0x00000030UL) /**< Offset from CAN Base Address: <tt> 0x0030</tt> */ 169 #define MXC_R_CAN_TXSCNT ((uint32_t)0x00000032UL) /**< Offset from CAN Base Address: <tt> 0x0032</tt> */ 170 #define MXC_R_CAN_TXDECMP ((uint32_t)0x00000033UL) /**< Offset from CAN Base Address: <tt> 0x0033</tt> */ 171 #define MXC_R_CAN_EINTFL ((uint32_t)0x00000034UL) /**< Offset from CAN Base Address: <tt> 0x0034</tt> */ 172 #define MXC_R_CAN_EINTEN ((uint32_t)0x00000035UL) /**< Offset from CAN Base Address: <tt> 0x0035</tt> */ 173 #define MXC_R_CAN_RXTO ((uint32_t)0x00000036UL) /**< Offset from CAN Base Address: <tt> 0x0036</tt> */ 174 /**@} end of group can_registers */ 175 176 /** 177 * @ingroup can_registers 178 * @defgroup CAN_MODE CAN_MODE 179 * @brief Mode Register. 180 * @{ 181 */ 182 #define MXC_F_CAN_MODE_AFM_POS 0 /**< MODE_AFM Position */ 183 #define MXC_F_CAN_MODE_AFM ((uint8_t)(0x1UL << MXC_F_CAN_MODE_AFM_POS)) /**< MODE_AFM Mask */ 184 185 #define MXC_F_CAN_MODE_LOM_POS 1 /**< MODE_LOM Position */ 186 #define MXC_F_CAN_MODE_LOM ((uint8_t)(0x1UL << MXC_F_CAN_MODE_LOM_POS)) /**< MODE_LOM Mask */ 187 188 #define MXC_F_CAN_MODE_RST_POS 2 /**< MODE_RST Position */ 189 #define MXC_F_CAN_MODE_RST ((uint8_t)(0x1UL << MXC_F_CAN_MODE_RST_POS)) /**< MODE_RST Mask */ 190 191 #define MXC_F_CAN_MODE_RXTRIG_POS 3 /**< MODE_RXTRIG Position */ 192 #define MXC_F_CAN_MODE_RXTRIG ((uint8_t)(0x7UL << MXC_F_CAN_MODE_RXTRIG_POS)) /**< MODE_RXTRIG Mask */ 193 #define MXC_V_CAN_MODE_RXTRIG_1W ((uint8_t)0x0UL) /**< MODE_RXTRIG_1W Value */ 194 #define MXC_S_CAN_MODE_RXTRIG_1W (MXC_V_CAN_MODE_RXTRIG_1W << MXC_F_CAN_MODE_RXTRIG_POS) /**< MODE_RXTRIG_1W Setting */ 195 #define MXC_V_CAN_MODE_RXTRIG_4W ((uint8_t)0x1UL) /**< MODE_RXTRIG_4W Value */ 196 #define MXC_S_CAN_MODE_RXTRIG_4W (MXC_V_CAN_MODE_RXTRIG_4W << MXC_F_CAN_MODE_RXTRIG_POS) /**< MODE_RXTRIG_4W Setting */ 197 #define MXC_V_CAN_MODE_RXTRIG_8W ((uint8_t)0x2UL) /**< MODE_RXTRIG_8W Value */ 198 #define MXC_S_CAN_MODE_RXTRIG_8W (MXC_V_CAN_MODE_RXTRIG_8W << MXC_F_CAN_MODE_RXTRIG_POS) /**< MODE_RXTRIG_8W Setting */ 199 #define MXC_V_CAN_MODE_RXTRIG_16W ((uint8_t)0x3UL) /**< MODE_RXTRIG_16W Value */ 200 #define MXC_S_CAN_MODE_RXTRIG_16W (MXC_V_CAN_MODE_RXTRIG_16W << MXC_F_CAN_MODE_RXTRIG_POS) /**< MODE_RXTRIG_16W Setting */ 201 #define MXC_V_CAN_MODE_RXTRIG_32W ((uint8_t)0x4UL) /**< MODE_RXTRIG_32W Value */ 202 #define MXC_S_CAN_MODE_RXTRIG_32W (MXC_V_CAN_MODE_RXTRIG_32W << MXC_F_CAN_MODE_RXTRIG_POS) /**< MODE_RXTRIG_32W Setting */ 203 #define MXC_V_CAN_MODE_RXTRIG_64W ((uint8_t)0x5UL) /**< MODE_RXTRIG_64W Value */ 204 #define MXC_S_CAN_MODE_RXTRIG_64W (MXC_V_CAN_MODE_RXTRIG_64W << MXC_F_CAN_MODE_RXTRIG_POS) /**< MODE_RXTRIG_64W Setting */ 205 206 #define MXC_F_CAN_MODE_DMA_POS 6 /**< MODE_DMA Position */ 207 #define MXC_F_CAN_MODE_DMA ((uint8_t)(0x1UL << MXC_F_CAN_MODE_DMA_POS)) /**< MODE_DMA Mask */ 208 209 #define MXC_F_CAN_MODE_SLP_POS 7 /**< MODE_SLP Position */ 210 #define MXC_F_CAN_MODE_SLP ((uint8_t)(0x1UL << MXC_F_CAN_MODE_SLP_POS)) /**< MODE_SLP Mask */ 211 212 /**@} end of group CAN_MODE_Register */ 213 214 /** 215 * @ingroup can_registers 216 * @defgroup CAN_CMD CAN_CMD 217 * @brief Command Register. 218 * @{ 219 */ 220 #define MXC_F_CAN_CMD_ABORT_POS 1 /**< CMD_ABORT Position */ 221 #define MXC_F_CAN_CMD_ABORT ((uint8_t)(0x1UL << MXC_F_CAN_CMD_ABORT_POS)) /**< CMD_ABORT Mask */ 222 223 #define MXC_F_CAN_CMD_TXREQ_POS 2 /**< CMD_TXREQ Position */ 224 #define MXC_F_CAN_CMD_TXREQ ((uint8_t)(0x1UL << MXC_F_CAN_CMD_TXREQ_POS)) /**< CMD_TXREQ Mask */ 225 226 /**@} end of group CAN_CMD_Register */ 227 228 /** 229 * @ingroup can_registers 230 * @defgroup CAN_STAT CAN_STAT 231 * @brief Status Register. 232 * @{ 233 */ 234 #define MXC_F_CAN_STAT_BUS_OFF_POS 0 /**< STAT_BUS_OFF Position */ 235 #define MXC_F_CAN_STAT_BUS_OFF ((uint8_t)(0x1UL << MXC_F_CAN_STAT_BUS_OFF_POS)) /**< STAT_BUS_OFF Mask */ 236 237 #define MXC_F_CAN_STAT_ERR_POS 1 /**< STAT_ERR Position */ 238 #define MXC_F_CAN_STAT_ERR ((uint8_t)(0x1UL << MXC_F_CAN_STAT_ERR_POS)) /**< STAT_ERR Mask */ 239 240 #define MXC_F_CAN_STAT_TX_POS 2 /**< STAT_TX Position */ 241 #define MXC_F_CAN_STAT_TX ((uint8_t)(0x1UL << MXC_F_CAN_STAT_TX_POS)) /**< STAT_TX Mask */ 242 243 #define MXC_F_CAN_STAT_RX_POS 3 /**< STAT_RX Position */ 244 #define MXC_F_CAN_STAT_RX ((uint8_t)(0x1UL << MXC_F_CAN_STAT_RX_POS)) /**< STAT_RX Mask */ 245 246 #define MXC_F_CAN_STAT_TXBUF_POS 5 /**< STAT_TXBUF Position */ 247 #define MXC_F_CAN_STAT_TXBUF ((uint8_t)(0x1UL << MXC_F_CAN_STAT_TXBUF_POS)) /**< STAT_TXBUF Mask */ 248 249 #define MXC_F_CAN_STAT_DOR_POS 6 /**< STAT_DOR Position */ 250 #define MXC_F_CAN_STAT_DOR ((uint8_t)(0x1UL << MXC_F_CAN_STAT_DOR_POS)) /**< STAT_DOR Mask */ 251 252 #define MXC_F_CAN_STAT_RXBUF_POS 7 /**< STAT_RXBUF Position */ 253 #define MXC_F_CAN_STAT_RXBUF ((uint8_t)(0x1UL << MXC_F_CAN_STAT_RXBUF_POS)) /**< STAT_RXBUF Mask */ 254 255 /**@} end of group CAN_STAT_Register */ 256 257 /** 258 * @ingroup can_registers 259 * @defgroup CAN_INTFL CAN_INTFL 260 * @brief Interrupt Status Register. 261 * @{ 262 */ 263 #define MXC_F_CAN_INTFL_DOR_POS 0 /**< INTFL_DOR Position */ 264 #define MXC_F_CAN_INTFL_DOR ((uint8_t)(0x1UL << MXC_F_CAN_INTFL_DOR_POS)) /**< INTFL_DOR Mask */ 265 266 #define MXC_F_CAN_INTFL_BERR_POS 1 /**< INTFL_BERR Position */ 267 #define MXC_F_CAN_INTFL_BERR ((uint8_t)(0x1UL << MXC_F_CAN_INTFL_BERR_POS)) /**< INTFL_BERR Mask */ 268 269 #define MXC_F_CAN_INTFL_TX_POS 2 /**< INTFL_TX Position */ 270 #define MXC_F_CAN_INTFL_TX ((uint8_t)(0x1UL << MXC_F_CAN_INTFL_TX_POS)) /**< INTFL_TX Mask */ 271 272 #define MXC_F_CAN_INTFL_RX_POS 3 /**< INTFL_RX Position */ 273 #define MXC_F_CAN_INTFL_RX ((uint8_t)(0x1UL << MXC_F_CAN_INTFL_RX_POS)) /**< INTFL_RX Mask */ 274 275 #define MXC_F_CAN_INTFL_ERPSV_POS 4 /**< INTFL_ERPSV Position */ 276 #define MXC_F_CAN_INTFL_ERPSV ((uint8_t)(0x1UL << MXC_F_CAN_INTFL_ERPSV_POS)) /**< INTFL_ERPSV Mask */ 277 278 #define MXC_F_CAN_INTFL_ERWARN_POS 5 /**< INTFL_ERWARN Position */ 279 #define MXC_F_CAN_INTFL_ERWARN ((uint8_t)(0x1UL << MXC_F_CAN_INTFL_ERWARN_POS)) /**< INTFL_ERWARN Mask */ 280 281 #define MXC_F_CAN_INTFL_AL_POS 6 /**< INTFL_AL Position */ 282 #define MXC_F_CAN_INTFL_AL ((uint8_t)(0x1UL << MXC_F_CAN_INTFL_AL_POS)) /**< INTFL_AL Mask */ 283 284 #define MXC_F_CAN_INTFL_WU_POS 7 /**< INTFL_WU Position */ 285 #define MXC_F_CAN_INTFL_WU ((uint8_t)(0x1UL << MXC_F_CAN_INTFL_WU_POS)) /**< INTFL_WU Mask */ 286 287 /**@} end of group CAN_INTFL_Register */ 288 289 /** 290 * @ingroup can_registers 291 * @defgroup CAN_INTEN CAN_INTEN 292 * @brief Interrupt Enable Register. 293 * @{ 294 */ 295 #define MXC_F_CAN_INTEN_DOR_POS 0 /**< INTEN_DOR Position */ 296 #define MXC_F_CAN_INTEN_DOR ((uint8_t)(0x1UL << MXC_F_CAN_INTEN_DOR_POS)) /**< INTEN_DOR Mask */ 297 298 #define MXC_F_CAN_INTEN_BERR_POS 1 /**< INTEN_BERR Position */ 299 #define MXC_F_CAN_INTEN_BERR ((uint8_t)(0x1UL << MXC_F_CAN_INTEN_BERR_POS)) /**< INTEN_BERR Mask */ 300 301 #define MXC_F_CAN_INTEN_TX_POS 2 /**< INTEN_TX Position */ 302 #define MXC_F_CAN_INTEN_TX ((uint8_t)(0x1UL << MXC_F_CAN_INTEN_TX_POS)) /**< INTEN_TX Mask */ 303 304 #define MXC_F_CAN_INTEN_RX_POS 3 /**< INTEN_RX Position */ 305 #define MXC_F_CAN_INTEN_RX ((uint8_t)(0x1UL << MXC_F_CAN_INTEN_RX_POS)) /**< INTEN_RX Mask */ 306 307 #define MXC_F_CAN_INTEN_ERPSV_POS 4 /**< INTEN_ERPSV Position */ 308 #define MXC_F_CAN_INTEN_ERPSV ((uint8_t)(0x1UL << MXC_F_CAN_INTEN_ERPSV_POS)) /**< INTEN_ERPSV Mask */ 309 310 #define MXC_F_CAN_INTEN_ERWARN_POS 5 /**< INTEN_ERWARN Position */ 311 #define MXC_F_CAN_INTEN_ERWARN ((uint8_t)(0x1UL << MXC_F_CAN_INTEN_ERWARN_POS)) /**< INTEN_ERWARN Mask */ 312 313 #define MXC_F_CAN_INTEN_AL_POS 6 /**< INTEN_AL Position */ 314 #define MXC_F_CAN_INTEN_AL ((uint8_t)(0x1UL << MXC_F_CAN_INTEN_AL_POS)) /**< INTEN_AL Mask */ 315 316 #define MXC_F_CAN_INTEN_WU_POS 7 /**< INTEN_WU Position */ 317 #define MXC_F_CAN_INTEN_WU ((uint8_t)(0x1UL << MXC_F_CAN_INTEN_WU_POS)) /**< INTEN_WU Mask */ 318 319 /**@} end of group CAN_INTEN_Register */ 320 321 /** 322 * @ingroup can_registers 323 * @defgroup CAN_RMC CAN_RMC 324 * @brief Receive Message Counter Register. 325 * @{ 326 */ 327 #define MXC_F_CAN_RMC_NUM_MSGS_POS 0 /**< RMC_NUM_MSGS Position */ 328 #define MXC_F_CAN_RMC_NUM_MSGS ((uint8_t)(0x1FUL << MXC_F_CAN_RMC_NUM_MSGS_POS)) /**< RMC_NUM_MSGS Mask */ 329 330 /**@} end of group CAN_RMC_Register */ 331 332 /** 333 * @ingroup can_registers 334 * @defgroup CAN_BUSTIM0 CAN_BUSTIM0 335 * @brief Bus Timing Register 0. 336 * @{ 337 */ 338 #define MXC_F_CAN_BUSTIM0_BR_CLKDIV_POS 0 /**< BUSTIM0_BR_CLKDIV Position */ 339 #define MXC_F_CAN_BUSTIM0_BR_CLKDIV ((uint8_t)(0x3FUL << MXC_F_CAN_BUSTIM0_BR_CLKDIV_POS)) /**< BUSTIM0_BR_CLKDIV Mask */ 340 341 #define MXC_F_CAN_BUSTIM0_SJW_POS 6 /**< BUSTIM0_SJW Position */ 342 #define MXC_F_CAN_BUSTIM0_SJW ((uint8_t)(0x3UL << MXC_F_CAN_BUSTIM0_SJW_POS)) /**< BUSTIM0_SJW Mask */ 343 344 /**@} end of group CAN_BUSTIM0_Register */ 345 346 /** 347 * @ingroup can_registers 348 * @defgroup CAN_BUSTIM1 CAN_BUSTIM1 349 * @brief Bus Timing Register 1. 350 * @{ 351 */ 352 #define MXC_F_CAN_BUSTIM1_TSEG1_POS 0 /**< BUSTIM1_TSEG1 Position */ 353 #define MXC_F_CAN_BUSTIM1_TSEG1 ((uint8_t)(0xFUL << MXC_F_CAN_BUSTIM1_TSEG1_POS)) /**< BUSTIM1_TSEG1 Mask */ 354 355 #define MXC_F_CAN_BUSTIM1_TSEG2_POS 4 /**< BUSTIM1_TSEG2 Position */ 356 #define MXC_F_CAN_BUSTIM1_TSEG2 ((uint8_t)(0x7UL << MXC_F_CAN_BUSTIM1_TSEG2_POS)) /**< BUSTIM1_TSEG2 Mask */ 357 358 #define MXC_F_CAN_BUSTIM1_SAM_POS 7 /**< BUSTIM1_SAM Position */ 359 #define MXC_F_CAN_BUSTIM1_SAM ((uint8_t)(0x1UL << MXC_F_CAN_BUSTIM1_SAM_POS)) /**< BUSTIM1_SAM Mask */ 360 361 /**@} end of group CAN_BUSTIM1_Register */ 362 363 /** 364 * @ingroup can_registers 365 * @defgroup CAN_TXFIFO32 CAN_TXFIFO32 366 * @brief Transmit FIFO Register. 367 * @{ 368 */ 369 #define MXC_F_CAN_TXFIFO32_DATA_POS 0 /**< TXFIFO32_DATA Position */ 370 #define MXC_F_CAN_TXFIFO32_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_CAN_TXFIFO32_DATA_POS)) /**< TXFIFO32_DATA Mask */ 371 372 /**@} end of group CAN_TXFIFO32_Register */ 373 374 /** 375 * @ingroup can_registers 376 * @defgroup CAN_TXFIFO16 CAN_TXFIFO16 377 * @brief Transmit FIFO Register. 378 * @{ 379 */ 380 #define MXC_F_CAN_TXFIFO16_DATA_POS 0 /**< TXFIFO16_DATA Position */ 381 #define MXC_F_CAN_TXFIFO16_DATA ((uint16_t)(0xFFFFUL << MXC_F_CAN_TXFIFO16_DATA_POS)) /**< TXFIFO16_DATA Mask */ 382 383 /**@} end of group CAN_TXFIFO16_Register */ 384 385 /** 386 * @ingroup can_registers 387 * @defgroup CAN_TXFIFO8 CAN_TXFIFO8 388 * @brief Transmit FIFO Register. 389 * @{ 390 */ 391 #define MXC_F_CAN_TXFIFO8_DATA_POS 0 /**< TXFIFO8_DATA Position */ 392 #define MXC_F_CAN_TXFIFO8_DATA ((uint8_t)(0xFFUL << MXC_F_CAN_TXFIFO8_DATA_POS)) /**< TXFIFO8_DATA Mask */ 393 394 /**@} end of group CAN_TXFIFO8_Register */ 395 396 /** 397 * @ingroup can_registers 398 * @defgroup CAN_RXFIFO32 CAN_RXFIFO32 399 * @brief Receive FIFO Register. 400 * @{ 401 */ 402 #define MXC_F_CAN_RXFIFO32_DATA_POS 0 /**< RXFIFO32_DATA Position */ 403 #define MXC_F_CAN_RXFIFO32_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_CAN_RXFIFO32_DATA_POS)) /**< RXFIFO32_DATA Mask */ 404 405 /**@} end of group CAN_RXFIFO32_Register */ 406 407 /** 408 * @ingroup can_registers 409 * @defgroup CAN_RXFIFO16 CAN_RXFIFO16 410 * @brief Receive FIFO Register. 411 * @{ 412 */ 413 #define MXC_F_CAN_RXFIFO16_DATA_POS 0 /**< RXFIFO16_DATA Position */ 414 #define MXC_F_CAN_RXFIFO16_DATA ((uint16_t)(0xFFFFUL << MXC_F_CAN_RXFIFO16_DATA_POS)) /**< RXFIFO16_DATA Mask */ 415 416 /**@} end of group CAN_RXFIFO16_Register */ 417 418 /** 419 * @ingroup can_registers 420 * @defgroup CAN_RXFIFO8 CAN_RXFIFO8 421 * @brief Receive FIFO Register. 422 * @{ 423 */ 424 #define MXC_F_CAN_RXFIFO8_DATA_POS 0 /**< RXFIFO8_DATA Position */ 425 #define MXC_F_CAN_RXFIFO8_DATA ((uint8_t)(0xFFUL << MXC_F_CAN_RXFIFO8_DATA_POS)) /**< RXFIFO8_DATA Mask */ 426 427 /**@} end of group CAN_RXFIFO8_Register */ 428 429 /** 430 * @ingroup can_registers 431 * @defgroup CAN_ACR32 CAN_ACR32 432 * @brief Acceptance Code Register. 433 * @{ 434 */ 435 #define MXC_F_CAN_ACR32_ACR_POS 0 /**< ACR32_ACR Position */ 436 #define MXC_F_CAN_ACR32_ACR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CAN_ACR32_ACR_POS)) /**< ACR32_ACR Mask */ 437 438 /**@} end of group CAN_ACR32_Register */ 439 440 /** 441 * @ingroup can_registers 442 * @defgroup CAN_ACR16 CAN_ACR16 443 * @brief Acceptance Code Register. 444 * @{ 445 */ 446 #define MXC_F_CAN_ACR16_ACR_POS 0 /**< ACR16_ACR Position */ 447 #define MXC_F_CAN_ACR16_ACR ((uint16_t)(0xFFFFUL << MXC_F_CAN_ACR16_ACR_POS)) /**< ACR16_ACR Mask */ 448 449 /**@} end of group CAN_ACR16_Register */ 450 451 /** 452 * @ingroup can_registers 453 * @defgroup CAN_ACR8 CAN_ACR8 454 * @brief Acceptance Code Register. 455 * @{ 456 */ 457 #define MXC_F_CAN_ACR8_ACR_POS 0 /**< ACR8_ACR Position */ 458 #define MXC_F_CAN_ACR8_ACR ((uint8_t)(0xFFUL << MXC_F_CAN_ACR8_ACR_POS)) /**< ACR8_ACR Mask */ 459 460 /**@} end of group CAN_ACR8_Register */ 461 462 /** 463 * @ingroup can_registers 464 * @defgroup CAN_AMR32 CAN_AMR32 465 * @brief Acceptance Mask Register. 466 * @{ 467 */ 468 #define MXC_F_CAN_AMR32_AMR_POS 0 /**< AMR32_AMR Position */ 469 #define MXC_F_CAN_AMR32_AMR ((uint32_t)(0xFFFFFFFFUL << MXC_F_CAN_AMR32_AMR_POS)) /**< AMR32_AMR Mask */ 470 471 /**@} end of group CAN_AMR32_Register */ 472 473 /** 474 * @ingroup can_registers 475 * @defgroup CAN_AMR16 CAN_AMR16 476 * @brief Acceptance Mask Register. 477 * @{ 478 */ 479 #define MXC_F_CAN_AMR16_AMR_POS 0 /**< AMR16_AMR Position */ 480 #define MXC_F_CAN_AMR16_AMR ((uint16_t)(0xFFFFUL << MXC_F_CAN_AMR16_AMR_POS)) /**< AMR16_AMR Mask */ 481 482 /**@} end of group CAN_AMR16_Register */ 483 484 /** 485 * @ingroup can_registers 486 * @defgroup CAN_AMR8 CAN_AMR8 487 * @brief Acceptance Mask Register. 488 * @{ 489 */ 490 #define MXC_F_CAN_AMR8_AMR_POS 0 /**< AMR8_AMR Position */ 491 #define MXC_F_CAN_AMR8_AMR ((uint8_t)(0xFFUL << MXC_F_CAN_AMR8_AMR_POS)) /**< AMR8_AMR Mask */ 492 493 /**@} end of group CAN_AMR8_Register */ 494 495 /** 496 * @ingroup can_registers 497 * @defgroup CAN_ECC CAN_ECC 498 * @brief Error Code Capture Register. 499 * @{ 500 */ 501 #define MXC_F_CAN_ECC_BER_POS 0 /**< ECC_BER Position */ 502 #define MXC_F_CAN_ECC_BER ((uint8_t)(0x1UL << MXC_F_CAN_ECC_BER_POS)) /**< ECC_BER Mask */ 503 504 #define MXC_F_CAN_ECC_STFER_POS 1 /**< ECC_STFER Position */ 505 #define MXC_F_CAN_ECC_STFER ((uint8_t)(0x1UL << MXC_F_CAN_ECC_STFER_POS)) /**< ECC_STFER Mask */ 506 507 #define MXC_F_CAN_ECC_CRCER_POS 2 /**< ECC_CRCER Position */ 508 #define MXC_F_CAN_ECC_CRCER ((uint8_t)(0x1UL << MXC_F_CAN_ECC_CRCER_POS)) /**< ECC_CRCER Mask */ 509 510 #define MXC_F_CAN_ECC_FRMER_POS 3 /**< ECC_FRMER Position */ 511 #define MXC_F_CAN_ECC_FRMER ((uint8_t)(0x1UL << MXC_F_CAN_ECC_FRMER_POS)) /**< ECC_FRMER Mask */ 512 513 #define MXC_F_CAN_ECC_ACKER_POS 4 /**< ECC_ACKER Position */ 514 #define MXC_F_CAN_ECC_ACKER ((uint8_t)(0x1UL << MXC_F_CAN_ECC_ACKER_POS)) /**< ECC_ACKER Mask */ 515 516 #define MXC_F_CAN_ECC_EDIR_POS 5 /**< ECC_EDIR Position */ 517 #define MXC_F_CAN_ECC_EDIR ((uint8_t)(0x1UL << MXC_F_CAN_ECC_EDIR_POS)) /**< ECC_EDIR Mask */ 518 519 #define MXC_F_CAN_ECC_TXWRN_POS 6 /**< ECC_TXWRN Position */ 520 #define MXC_F_CAN_ECC_TXWRN ((uint8_t)(0x1UL << MXC_F_CAN_ECC_TXWRN_POS)) /**< ECC_TXWRN Mask */ 521 522 #define MXC_F_CAN_ECC_RXWRN_POS 7 /**< ECC_RXWRN Position */ 523 #define MXC_F_CAN_ECC_RXWRN ((uint8_t)(0x1UL << MXC_F_CAN_ECC_RXWRN_POS)) /**< ECC_RXWRN Mask */ 524 525 /**@} end of group CAN_ECC_Register */ 526 527 /** 528 * @ingroup can_registers 529 * @defgroup CAN_RXERR CAN_RXERR 530 * @brief Receive Error Counter. 531 * @{ 532 */ 533 #define MXC_F_CAN_RXERR_RXERR_POS 0 /**< RXERR_RXERR Position */ 534 #define MXC_F_CAN_RXERR_RXERR ((uint8_t)(0xFFUL << MXC_F_CAN_RXERR_RXERR_POS)) /**< RXERR_RXERR Mask */ 535 536 /**@} end of group CAN_RXERR_Register */ 537 538 /** 539 * @ingroup can_registers 540 * @defgroup CAN_TXERR CAN_TXERR 541 * @brief Invalidate All Registers. 542 * @{ 543 */ 544 #define MXC_F_CAN_TXERR_TXERR_POS 0 /**< TXERR_TXERR Position */ 545 #define MXC_F_CAN_TXERR_TXERR ((uint8_t)(0xFFUL << MXC_F_CAN_TXERR_TXERR_POS)) /**< TXERR_TXERR Mask */ 546 547 /**@} end of group CAN_TXERR_Register */ 548 549 /** 550 * @ingroup can_registers 551 * @defgroup CAN_ALC CAN_ALC 552 * @brief Arbitration Lost Code Capture Register. 553 * @{ 554 */ 555 #define MXC_F_CAN_ALC_ALC_POS 0 /**< ALC_ALC Position */ 556 #define MXC_F_CAN_ALC_ALC ((uint8_t)(0x1FUL << MXC_F_CAN_ALC_ALC_POS)) /**< ALC_ALC Mask */ 557 558 /**@} end of group CAN_ALC_Register */ 559 560 /** 561 * @ingroup can_registers 562 * @defgroup CAN_NBT CAN_NBT 563 * @brief Nominal Bit Timing Register. 564 * @{ 565 */ 566 #define MXC_F_CAN_NBT_NBRP_POS 0 /**< NBT_NBRP Position */ 567 #define MXC_F_CAN_NBT_NBRP ((uint32_t)(0x3FFUL << MXC_F_CAN_NBT_NBRP_POS)) /**< NBT_NBRP Mask */ 568 569 #define MXC_F_CAN_NBT_NSEG1_POS 10 /**< NBT_NSEG1 Position */ 570 #define MXC_F_CAN_NBT_NSEG1 ((uint32_t)(0xFFUL << MXC_F_CAN_NBT_NSEG1_POS)) /**< NBT_NSEG1 Mask */ 571 572 #define MXC_F_CAN_NBT_NSEG2_POS 18 /**< NBT_NSEG2 Position */ 573 #define MXC_F_CAN_NBT_NSEG2 ((uint32_t)(0x7FUL << MXC_F_CAN_NBT_NSEG2_POS)) /**< NBT_NSEG2 Mask */ 574 575 #define MXC_F_CAN_NBT_NSJW_POS 25 /**< NBT_NSJW Position */ 576 #define MXC_F_CAN_NBT_NSJW ((uint32_t)(0x7FUL << MXC_F_CAN_NBT_NSJW_POS)) /**< NBT_NSJW Mask */ 577 578 /**@} end of group CAN_NBT_Register */ 579 580 /** 581 * @ingroup can_registers 582 * @defgroup CAN_DBT_SSPP CAN_DBT_SSPP 583 * @brief Data Bit Timing Register. 584 * @{ 585 */ 586 #define MXC_F_CAN_DBT_SSPP_DBRP_POS 0 /**< DBT_SSPP_DBRP Position */ 587 #define MXC_F_CAN_DBT_SSPP_DBRP ((uint32_t)(0x3FFUL << MXC_F_CAN_DBT_SSPP_DBRP_POS)) /**< DBT_SSPP_DBRP Mask */ 588 589 #define MXC_F_CAN_DBT_SSPP_DSEG1_POS 10 /**< DBT_SSPP_DSEG1 Position */ 590 #define MXC_F_CAN_DBT_SSPP_DSEG1 ((uint32_t)(0x3FUL << MXC_F_CAN_DBT_SSPP_DSEG1_POS)) /**< DBT_SSPP_DSEG1 Mask */ 591 592 #define MXC_F_CAN_DBT_SSPP_DSEG2_POS 16 /**< DBT_SSPP_DSEG2 Position */ 593 #define MXC_F_CAN_DBT_SSPP_DSEG2 ((uint32_t)(0xFUL << MXC_F_CAN_DBT_SSPP_DSEG2_POS)) /**< DBT_SSPP_DSEG2 Mask */ 594 595 #define MXC_F_CAN_DBT_SSPP_DSJW_POS 20 /**< DBT_SSPP_DSJW Position */ 596 #define MXC_F_CAN_DBT_SSPP_DSJW ((uint32_t)(0xFUL << MXC_F_CAN_DBT_SSPP_DSJW_POS)) /**< DBT_SSPP_DSJW Mask */ 597 598 #define MXC_F_CAN_DBT_SSPP_SSPP_POS 24 /**< DBT_SSPP_SSPP Position */ 599 #define MXC_F_CAN_DBT_SSPP_SSPP ((uint32_t)(0x7FUL << MXC_F_CAN_DBT_SSPP_SSPP_POS)) /**< DBT_SSPP_SSPP Mask */ 600 601 /**@} end of group CAN_DBT_SSPP_Register */ 602 603 /** 604 * @ingroup can_registers 605 * @defgroup CAN_FDCTRL CAN_FDCTRL 606 * @brief FD Control Register. 607 * @{ 608 */ 609 #define MXC_F_CAN_FDCTRL_FDEN_POS 0 /**< FDCTRL_FDEN Position */ 610 #define MXC_F_CAN_FDCTRL_FDEN ((uint8_t)(0x1UL << MXC_F_CAN_FDCTRL_FDEN_POS)) /**< FDCTRL_FDEN Mask */ 611 612 #define MXC_F_CAN_FDCTRL_BRSEN_POS 1 /**< FDCTRL_BRSEN Position */ 613 #define MXC_F_CAN_FDCTRL_BRSEN ((uint8_t)(0x1UL << MXC_F_CAN_FDCTRL_BRSEN_POS)) /**< FDCTRL_BRSEN Mask */ 614 615 #define MXC_F_CAN_FDCTRL_EXTBT_POS 2 /**< FDCTRL_EXTBT Position */ 616 #define MXC_F_CAN_FDCTRL_EXTBT ((uint8_t)(0x1UL << MXC_F_CAN_FDCTRL_EXTBT_POS)) /**< FDCTRL_EXTBT Mask */ 617 618 #define MXC_F_CAN_FDCTRL_ISO_POS 3 /**< FDCTRL_ISO Position */ 619 #define MXC_F_CAN_FDCTRL_ISO ((uint8_t)(0x1UL << MXC_F_CAN_FDCTRL_ISO_POS)) /**< FDCTRL_ISO Mask */ 620 621 #define MXC_F_CAN_FDCTRL_DAR_POS 4 /**< FDCTRL_DAR Position */ 622 #define MXC_F_CAN_FDCTRL_DAR ((uint8_t)(0x1UL << MXC_F_CAN_FDCTRL_DAR_POS)) /**< FDCTRL_DAR Mask */ 623 624 #define MXC_F_CAN_FDCTRL_REOM_POS 5 /**< FDCTRL_REOM Position */ 625 #define MXC_F_CAN_FDCTRL_REOM ((uint8_t)(0x1UL << MXC_F_CAN_FDCTRL_REOM_POS)) /**< FDCTRL_REOM Mask */ 626 627 #define MXC_F_CAN_FDCTRL_PED_POS 6 /**< FDCTRL_PED Position */ 628 #define MXC_F_CAN_FDCTRL_PED ((uint8_t)(0x1UL << MXC_F_CAN_FDCTRL_PED_POS)) /**< FDCTRL_PED Mask */ 629 630 /**@} end of group CAN_FDCTRL_Register */ 631 632 /** 633 * @ingroup can_registers 634 * @defgroup CAN_FDSTAT CAN_FDSTAT 635 * @brief Invalidate All Registers. 636 * @{ 637 */ 638 #define MXC_F_CAN_FDSTAT_BITERR_POS 0 /**< FDSTAT_BITERR Position */ 639 #define MXC_F_CAN_FDSTAT_BITERR ((uint8_t)(0x1UL << MXC_F_CAN_FDSTAT_BITERR_POS)) /**< FDSTAT_BITERR Mask */ 640 641 #define MXC_F_CAN_FDSTAT_CRCERR_POS 1 /**< FDSTAT_CRCERR Position */ 642 #define MXC_F_CAN_FDSTAT_CRCERR ((uint8_t)(0x1UL << MXC_F_CAN_FDSTAT_CRCERR_POS)) /**< FDSTAT_CRCERR Mask */ 643 644 #define MXC_F_CAN_FDSTAT_FRMERR_POS 2 /**< FDSTAT_FRMERR Position */ 645 #define MXC_F_CAN_FDSTAT_FRMERR ((uint8_t)(0x1UL << MXC_F_CAN_FDSTAT_FRMERR_POS)) /**< FDSTAT_FRMERR Mask */ 646 647 #define MXC_F_CAN_FDSTAT_STFERR_POS 3 /**< FDSTAT_STFERR Position */ 648 #define MXC_F_CAN_FDSTAT_STFERR ((uint8_t)(0x1UL << MXC_F_CAN_FDSTAT_STFERR_POS)) /**< FDSTAT_STFERR Mask */ 649 650 #define MXC_F_CAN_FDSTAT_PEE_POS 4 /**< FDSTAT_PEE Position */ 651 #define MXC_F_CAN_FDSTAT_PEE ((uint8_t)(0x1UL << MXC_F_CAN_FDSTAT_PEE_POS)) /**< FDSTAT_PEE Mask */ 652 653 #define MXC_F_CAN_FDSTAT_STATE_POS 6 /**< FDSTAT_STATE Position */ 654 #define MXC_F_CAN_FDSTAT_STATE ((uint8_t)(0x3UL << MXC_F_CAN_FDSTAT_STATE_POS)) /**< FDSTAT_STATE Mask */ 655 #define MXC_V_CAN_FDSTAT_STATE_INT ((uint8_t)0x0UL) /**< FDSTAT_STATE_INT Value */ 656 #define MXC_S_CAN_FDSTAT_STATE_INT (MXC_V_CAN_FDSTAT_STATE_INT << MXC_F_CAN_FDSTAT_STATE_POS) /**< FDSTAT_STATE_INT Setting */ 657 #define MXC_V_CAN_FDSTAT_STATE_IDLE ((uint8_t)0x1UL) /**< FDSTAT_STATE_IDLE Value */ 658 #define MXC_S_CAN_FDSTAT_STATE_IDLE (MXC_V_CAN_FDSTAT_STATE_IDLE << MXC_F_CAN_FDSTAT_STATE_POS) /**< FDSTAT_STATE_IDLE Setting */ 659 #define MXC_V_CAN_FDSTAT_STATE_RX ((uint8_t)0x2UL) /**< FDSTAT_STATE_RX Value */ 660 #define MXC_S_CAN_FDSTAT_STATE_RX (MXC_V_CAN_FDSTAT_STATE_RX << MXC_F_CAN_FDSTAT_STATE_POS) /**< FDSTAT_STATE_RX Setting */ 661 #define MXC_V_CAN_FDSTAT_STATE_TX ((uint8_t)0x3UL) /**< FDSTAT_STATE_TX Value */ 662 #define MXC_S_CAN_FDSTAT_STATE_TX (MXC_V_CAN_FDSTAT_STATE_TX << MXC_F_CAN_FDSTAT_STATE_POS) /**< FDSTAT_STATE_TX Setting */ 663 664 /**@} end of group CAN_FDSTAT_Register */ 665 666 /** 667 * @ingroup can_registers 668 * @defgroup CAN_DPERR CAN_DPERR 669 * @brief Data Phase Error Counter Register. 670 * @{ 671 */ 672 #define MXC_F_CAN_DPERR_DPERR_POS 0 /**< DPERR_DPERR Position */ 673 #define MXC_F_CAN_DPERR_DPERR ((uint8_t)(0xFFUL << MXC_F_CAN_DPERR_DPERR_POS)) /**< DPERR_DPERR Mask */ 674 675 /**@} end of group CAN_DPERR_Register */ 676 677 /** 678 * @ingroup can_registers 679 * @defgroup CAN_APERR CAN_APERR 680 * @brief Arbitration Phase Error Counter Register. 681 * @{ 682 */ 683 #define MXC_F_CAN_APERR_APERR_POS 0 /**< APERR_APERR Position */ 684 #define MXC_F_CAN_APERR_APERR ((uint8_t)(0xFFUL << MXC_F_CAN_APERR_APERR_POS)) /**< APERR_APERR Mask */ 685 686 /**@} end of group CAN_APERR_Register */ 687 688 /** 689 * @ingroup can_registers 690 * @defgroup CAN_TEST CAN_TEST 691 * @brief Invalidate All Registers. 692 * @{ 693 */ 694 #define MXC_F_CAN_TEST_LBEN_POS 0 /**< TEST_LBEN Position */ 695 #define MXC_F_CAN_TEST_LBEN ((uint8_t)(0x1UL << MXC_F_CAN_TEST_LBEN_POS)) /**< TEST_LBEN Mask */ 696 697 #define MXC_F_CAN_TEST_TXC_POS 1 /**< TEST_TXC Position */ 698 #define MXC_F_CAN_TEST_TXC ((uint8_t)(0x1UL << MXC_F_CAN_TEST_TXC_POS)) /**< TEST_TXC Mask */ 699 700 /**@} end of group CAN_TEST_Register */ 701 702 /** 703 * @ingroup can_registers 704 * @defgroup CAN_WUPCLKDIV CAN_WUPCLKDIV 705 * @brief Wake-up timer prescaler. 706 * @{ 707 */ 708 #define MXC_F_CAN_WUPCLKDIV_WUPDIV_POS 0 /**< WUPCLKDIV_WUPDIV Position */ 709 #define MXC_F_CAN_WUPCLKDIV_WUPDIV ((uint8_t)(0xFFUL << MXC_F_CAN_WUPCLKDIV_WUPDIV_POS)) /**< WUPCLKDIV_WUPDIV Mask */ 710 711 /**@} end of group CAN_WUPCLKDIV_Register */ 712 713 /** 714 * @ingroup can_registers 715 * @defgroup CAN_WUPFT CAN_WUPFT 716 * @brief Wake up Filter Time Register. 717 * @{ 718 */ 719 #define MXC_F_CAN_WUPFT_WUPFT_POS 0 /**< WUPFT_WUPFT Position */ 720 #define MXC_F_CAN_WUPFT_WUPFT ((uint16_t)(0xFFFFUL << MXC_F_CAN_WUPFT_WUPFT_POS)) /**< WUPFT_WUPFT Mask */ 721 722 /**@} end of group CAN_WUPFT_Register */ 723 724 /** 725 * @ingroup can_registers 726 * @defgroup CAN_WUPET CAN_WUPET 727 * @brief Wake-up Expire Time Register. 728 * @{ 729 */ 730 #define MXC_F_CAN_WUPET_WUPET_POS 0 /**< WUPET_WUPET Position */ 731 #define MXC_F_CAN_WUPET_WUPET ((uint32_t)(0xFFFFFUL << MXC_F_CAN_WUPET_WUPET_POS)) /**< WUPET_WUPET Mask */ 732 733 /**@} end of group CAN_WUPET_Register */ 734 735 /** 736 * @ingroup can_registers 737 * @defgroup CAN_RXDCNT CAN_RXDCNT 738 * @brief RX FIFO Data Counter Register. 739 * @{ 740 */ 741 #define MXC_F_CAN_RXDCNT_RXDCNT_POS 0 /**< RXDCNT_RXDCNT Position */ 742 #define MXC_F_CAN_RXDCNT_RXDCNT ((uint16_t)(0xFFFFUL << MXC_F_CAN_RXDCNT_RXDCNT_POS)) /**< RXDCNT_RXDCNT Mask */ 743 744 /**@} end of group CAN_RXDCNT_Register */ 745 746 /** 747 * @ingroup can_registers 748 * @defgroup CAN_TXSCNT CAN_TXSCNT 749 * @brief TX FIFO Space Counter. 750 * @{ 751 */ 752 #define MXC_F_CAN_TXSCNT_TXSCNT_POS 0 /**< TXSCNT_TXSCNT Position */ 753 #define MXC_F_CAN_TXSCNT_TXSCNT ((uint8_t)(0xFFUL << MXC_F_CAN_TXSCNT_TXSCNT_POS)) /**< TXSCNT_TXSCNT Mask */ 754 755 /**@} end of group CAN_TXSCNT_Register */ 756 757 /** 758 * @ingroup can_registers 759 * @defgroup CAN_TXDECMP CAN_TXDECMP 760 * @brief Invalidate All Registers. 761 * @{ 762 */ 763 #define MXC_F_CAN_TXDECMP_TDCO_POS 0 /**< TXDECMP_TDCO Position */ 764 #define MXC_F_CAN_TXDECMP_TDCO ((uint8_t)(0x7FUL << MXC_F_CAN_TXDECMP_TDCO_POS)) /**< TXDECMP_TDCO Mask */ 765 766 #define MXC_F_CAN_TXDECMP_TDCEN_POS 7 /**< TXDECMP_TDCEN Position */ 767 #define MXC_F_CAN_TXDECMP_TDCEN ((uint8_t)(0x1UL << MXC_F_CAN_TXDECMP_TDCEN_POS)) /**< TXDECMP_TDCEN Mask */ 768 769 /**@} end of group CAN_TXDECMP_Register */ 770 771 /** 772 * @ingroup can_registers 773 * @defgroup CAN_EINTFL CAN_EINTFL 774 * @brief Extended Interrupt Flag Register. 775 * @{ 776 */ 777 #define MXC_F_CAN_EINTFL_RX_THD_POS 0 /**< EINTFL_RX_THD Position */ 778 #define MXC_F_CAN_EINTFL_RX_THD ((uint8_t)(0x1UL << MXC_F_CAN_EINTFL_RX_THD_POS)) /**< EINTFL_RX_THD Mask */ 779 780 #define MXC_F_CAN_EINTFL_RX_TO_POS 1 /**< EINTFL_RX_TO Position */ 781 #define MXC_F_CAN_EINTFL_RX_TO ((uint8_t)(0x1UL << MXC_F_CAN_EINTFL_RX_TO_POS)) /**< EINTFL_RX_TO Mask */ 782 783 /**@} end of group CAN_EINTFL_Register */ 784 785 /** 786 * @ingroup can_registers 787 * @defgroup CAN_EINTEN CAN_EINTEN 788 * @brief Extended Interrupt Enable Register. 789 * @{ 790 */ 791 #define MXC_F_CAN_EINTEN_RX_THD_POS 0 /**< EINTEN_RX_THD Position */ 792 #define MXC_F_CAN_EINTEN_RX_THD ((uint8_t)(0x1UL << MXC_F_CAN_EINTEN_RX_THD_POS)) /**< EINTEN_RX_THD Mask */ 793 794 #define MXC_F_CAN_EINTEN_RX_TO_POS 1 /**< EINTEN_RX_TO Position */ 795 #define MXC_F_CAN_EINTEN_RX_TO ((uint8_t)(0x1UL << MXC_F_CAN_EINTEN_RX_TO_POS)) /**< EINTEN_RX_TO Mask */ 796 797 /**@} end of group CAN_EINTEN_Register */ 798 799 /** 800 * @ingroup can_registers 801 * @defgroup CAN_RXTO CAN_RXTO 802 * @brief RX FIFO Timeout Register. 803 * @{ 804 */ 805 #define MXC_F_CAN_RXTO_RX_TO_POS 0 /**< RXTO_RX_TO Position */ 806 #define MXC_F_CAN_RXTO_RX_TO ((uint16_t)(0xFFFFUL << MXC_F_CAN_RXTO_RX_TO_POS)) /**< RXTO_RX_TO Mask */ 807 808 /**@} end of group CAN_RXTO_Register */ 809 810 #ifdef __cplusplus 811 } 812 #endif 813 814 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32662_INCLUDE_CAN_REGS_H_ 815
