1 /** 2 * @file adc_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the ADC Peripheral Module. 4 * @note This file is @generated. 5 * @ingroup adc_registers 6 */ 7 8 /****************************************************************************** 9 * 10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 11 * Analog Devices, Inc.), 12 * Copyright (C) 2023-2024 Analog Devices, Inc. 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 ******************************************************************************/ 27 28 #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32662_INCLUDE_ADC_REGS_H_ 29 #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32662_INCLUDE_ADC_REGS_H_ 30 31 /* **** Includes **** */ 32 #include <stdint.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #if defined (__ICCARM__) 39 #pragma system_include 40 #endif 41 42 #if defined (__CC_ARM) 43 #pragma anon_unions 44 #endif 45 /// @cond 46 /* 47 If types are not defined elsewhere (CMSIS) define them here 48 */ 49 #ifndef __IO 50 #define __IO volatile 51 #endif 52 #ifndef __I 53 #define __I volatile const 54 #endif 55 #ifndef __O 56 #define __O volatile 57 #endif 58 #ifndef __R 59 #define __R volatile const 60 #endif 61 /// @endcond 62 63 /* **** Definitions **** */ 64 65 /** 66 * @ingroup adc 67 * @defgroup adc_registers ADC_Registers 68 * @brief Registers, Bit Masks and Bit Positions for the ADC Peripheral Module. 69 * @details Inter-Integrated Circuit. 70 */ 71 72 /** 73 * @ingroup adc_registers 74 * Structure type to access the ADC Registers. 75 */ 76 typedef struct { 77 __IO uint32_t ctrl0; /**< <tt>\b 0x00:</tt> ADC CTRL0 Register */ 78 __IO uint32_t ctrl1; /**< <tt>\b 0x04:</tt> ADC CTRL1 Register */ 79 __IO uint32_t clkctrl; /**< <tt>\b 0x08:</tt> ADC CLKCTRL Register */ 80 __IO uint32_t sampclkctrl; /**< <tt>\b 0x0C:</tt> ADC SAMPCLKCTRL Register */ 81 __IO uint32_t chsel0; /**< <tt>\b 0x10:</tt> ADC CHSEL0 Register */ 82 __IO uint32_t chsel1; /**< <tt>\b 0x14:</tt> ADC CHSEL1 Register */ 83 __IO uint32_t chsel2; /**< <tt>\b 0x18:</tt> ADC CHSEL2 Register */ 84 __IO uint32_t chsel3; /**< <tt>\b 0x1C:</tt> ADC CHSEL3 Register */ 85 __R uint32_t rsv_0x20_0x2f[4]; 86 __IO uint32_t restart; /**< <tt>\b 0x30:</tt> ADC RESTART Register */ 87 __R uint32_t rsv_0x34_0x3b[2]; 88 __IO uint32_t datafmt; /**< <tt>\b 0x3C:</tt> ADC DATAFMT Register */ 89 __IO uint32_t fifodmactrl; /**< <tt>\b 0x40:</tt> ADC FIFODMACTRL Register */ 90 __IO uint32_t data; /**< <tt>\b 0x44:</tt> ADC DATA Register */ 91 __IO uint32_t status; /**< <tt>\b 0x48:</tt> ADC STATUS Register */ 92 __IO uint32_t chstatus; /**< <tt>\b 0x4C:</tt> ADC CHSTATUS Register */ 93 __IO uint32_t inten; /**< <tt>\b 0x50:</tt> ADC INTEN Register */ 94 __IO uint32_t intfl; /**< <tt>\b 0x54:</tt> ADC INTFL Register */ 95 __R uint32_t rsv_0x58_0x5f[2]; 96 __IO uint32_t sfraddroffset; /**< <tt>\b 0x60:</tt> ADC SFRADDROFFSET Register */ 97 __IO uint32_t sfraddr; /**< <tt>\b 0x64:</tt> ADC SFRADDR Register */ 98 __IO uint32_t sfrwrdata; /**< <tt>\b 0x68:</tt> ADC SFRWRDATA Register */ 99 __IO uint32_t sfrrddata; /**< <tt>\b 0x6C:</tt> ADC SFRRDDATA Register */ 100 __IO uint32_t sfrstatus; /**< <tt>\b 0x70:</tt> ADC SFRSTATUS Register */ 101 } mxc_adc_regs_t; 102 103 /* Register offsets for module ADC */ 104 /** 105 * @ingroup adc_registers 106 * @defgroup ADC_Register_Offsets Register Offsets 107 * @brief ADC Peripheral Register Offsets from the ADC Base Peripheral Address. 108 * @{ 109 */ 110 #define MXC_R_ADC_CTRL0 ((uint32_t)0x00000000UL) /**< Offset from ADC Base Address: <tt> 0x0000</tt> */ 111 #define MXC_R_ADC_CTRL1 ((uint32_t)0x00000004UL) /**< Offset from ADC Base Address: <tt> 0x0004</tt> */ 112 #define MXC_R_ADC_CLKCTRL ((uint32_t)0x00000008UL) /**< Offset from ADC Base Address: <tt> 0x0008</tt> */ 113 #define MXC_R_ADC_SAMPCLKCTRL ((uint32_t)0x0000000CUL) /**< Offset from ADC Base Address: <tt> 0x000C</tt> */ 114 #define MXC_R_ADC_CHSEL0 ((uint32_t)0x00000010UL) /**< Offset from ADC Base Address: <tt> 0x0010</tt> */ 115 #define MXC_R_ADC_CHSEL1 ((uint32_t)0x00000014UL) /**< Offset from ADC Base Address: <tt> 0x0014</tt> */ 116 #define MXC_R_ADC_CHSEL2 ((uint32_t)0x00000018UL) /**< Offset from ADC Base Address: <tt> 0x0018</tt> */ 117 #define MXC_R_ADC_CHSEL3 ((uint32_t)0x0000001CUL) /**< Offset from ADC Base Address: <tt> 0x001C</tt> */ 118 #define MXC_R_ADC_RESTART ((uint32_t)0x00000030UL) /**< Offset from ADC Base Address: <tt> 0x0030</tt> */ 119 #define MXC_R_ADC_DATAFMT ((uint32_t)0x0000003CUL) /**< Offset from ADC Base Address: <tt> 0x003C</tt> */ 120 #define MXC_R_ADC_FIFODMACTRL ((uint32_t)0x00000040UL) /**< Offset from ADC Base Address: <tt> 0x0040</tt> */ 121 #define MXC_R_ADC_DATA ((uint32_t)0x00000044UL) /**< Offset from ADC Base Address: <tt> 0x0044</tt> */ 122 #define MXC_R_ADC_STATUS ((uint32_t)0x00000048UL) /**< Offset from ADC Base Address: <tt> 0x0048</tt> */ 123 #define MXC_R_ADC_CHSTATUS ((uint32_t)0x0000004CUL) /**< Offset from ADC Base Address: <tt> 0x004C</tt> */ 124 #define MXC_R_ADC_INTEN ((uint32_t)0x00000050UL) /**< Offset from ADC Base Address: <tt> 0x0050</tt> */ 125 #define MXC_R_ADC_INTFL ((uint32_t)0x00000054UL) /**< Offset from ADC Base Address: <tt> 0x0054</tt> */ 126 #define MXC_R_ADC_SFRADDROFFSET ((uint32_t)0x00000060UL) /**< Offset from ADC Base Address: <tt> 0x0060</tt> */ 127 #define MXC_R_ADC_SFRADDR ((uint32_t)0x00000064UL) /**< Offset from ADC Base Address: <tt> 0x0064</tt> */ 128 #define MXC_R_ADC_SFRWRDATA ((uint32_t)0x00000068UL) /**< Offset from ADC Base Address: <tt> 0x0068</tt> */ 129 #define MXC_R_ADC_SFRRDDATA ((uint32_t)0x0000006CUL) /**< Offset from ADC Base Address: <tt> 0x006C</tt> */ 130 #define MXC_R_ADC_SFRSTATUS ((uint32_t)0x00000070UL) /**< Offset from ADC Base Address: <tt> 0x0070</tt> */ 131 /**@} end of group adc_registers */ 132 133 /** 134 * @ingroup adc_registers 135 * @defgroup ADC_CTRL0 ADC_CTRL0 136 * @brief Control Register 0. 137 * @{ 138 */ 139 #define MXC_F_ADC_CTRL0_ADC_EN_POS 0 /**< CTRL0_ADC_EN Position */ 140 #define MXC_F_ADC_CTRL0_ADC_EN ((uint32_t)(0x1UL << MXC_F_ADC_CTRL0_ADC_EN_POS)) /**< CTRL0_ADC_EN Mask */ 141 142 #define MXC_F_ADC_CTRL0_BIAS_EN_POS 1 /**< CTRL0_BIAS_EN Position */ 143 #define MXC_F_ADC_CTRL0_BIAS_EN ((uint32_t)(0x1UL << MXC_F_ADC_CTRL0_BIAS_EN_POS)) /**< CTRL0_BIAS_EN Mask */ 144 145 #define MXC_F_ADC_CTRL0_SKIP_CAL_POS 2 /**< CTRL0_SKIP_CAL Position */ 146 #define MXC_F_ADC_CTRL0_SKIP_CAL ((uint32_t)(0x1UL << MXC_F_ADC_CTRL0_SKIP_CAL_POS)) /**< CTRL0_SKIP_CAL Mask */ 147 148 #define MXC_F_ADC_CTRL0_CHOP_FORCE_POS 3 /**< CTRL0_CHOP_FORCE Position */ 149 #define MXC_F_ADC_CTRL0_CHOP_FORCE ((uint32_t)(0x1UL << MXC_F_ADC_CTRL0_CHOP_FORCE_POS)) /**< CTRL0_CHOP_FORCE Mask */ 150 151 #define MXC_F_ADC_CTRL0_RESETB_POS 4 /**< CTRL0_RESETB Position */ 152 #define MXC_F_ADC_CTRL0_RESETB ((uint32_t)(0x1UL << MXC_F_ADC_CTRL0_RESETB_POS)) /**< CTRL0_RESETB Mask */ 153 154 /**@} end of group ADC_CTRL0_Register */ 155 156 /** 157 * @ingroup adc_registers 158 * @defgroup ADC_CTRL1 ADC_CTRL1 159 * @brief Control Register 1. 160 * @{ 161 */ 162 #define MXC_F_ADC_CTRL1_START_POS 0 /**< CTRL1_START Position */ 163 #define MXC_F_ADC_CTRL1_START ((uint32_t)(0x1UL << MXC_F_ADC_CTRL1_START_POS)) /**< CTRL1_START Mask */ 164 165 #define MXC_F_ADC_CTRL1_TRIG_MODE_POS 1 /**< CTRL1_TRIG_MODE Position */ 166 #define MXC_F_ADC_CTRL1_TRIG_MODE ((uint32_t)(0x1UL << MXC_F_ADC_CTRL1_TRIG_MODE_POS)) /**< CTRL1_TRIG_MODE Mask */ 167 168 #define MXC_F_ADC_CTRL1_CNV_MODE_POS 2 /**< CTRL1_CNV_MODE Position */ 169 #define MXC_F_ADC_CTRL1_CNV_MODE ((uint32_t)(0x1UL << MXC_F_ADC_CTRL1_CNV_MODE_POS)) /**< CTRL1_CNV_MODE Mask */ 170 171 #define MXC_F_ADC_CTRL1_SAMP_CK_OFF_POS 3 /**< CTRL1_SAMP_CK_OFF Position */ 172 #define MXC_F_ADC_CTRL1_SAMP_CK_OFF ((uint32_t)(0x1UL << MXC_F_ADC_CTRL1_SAMP_CK_OFF_POS)) /**< CTRL1_SAMP_CK_OFF Mask */ 173 174 #define MXC_F_ADC_CTRL1_TRIG_SEL_POS 4 /**< CTRL1_TRIG_SEL Position */ 175 #define MXC_F_ADC_CTRL1_TRIG_SEL ((uint32_t)(0x7UL << MXC_F_ADC_CTRL1_TRIG_SEL_POS)) /**< CTRL1_TRIG_SEL Mask */ 176 177 #define MXC_F_ADC_CTRL1_TS_SEL_POS 7 /**< CTRL1_TS_SEL Position */ 178 #define MXC_F_ADC_CTRL1_TS_SEL ((uint32_t)(0x1UL << MXC_F_ADC_CTRL1_TS_SEL_POS)) /**< CTRL1_TS_SEL Mask */ 179 180 #define MXC_F_ADC_CTRL1_AVG_POS 8 /**< CTRL1_AVG Position */ 181 #define MXC_F_ADC_CTRL1_AVG ((uint32_t)(0x7UL << MXC_F_ADC_CTRL1_AVG_POS)) /**< CTRL1_AVG Mask */ 182 #define MXC_V_ADC_CTRL1_AVG_AVG1 ((uint32_t)0x0UL) /**< CTRL1_AVG_AVG1 Value */ 183 #define MXC_S_ADC_CTRL1_AVG_AVG1 (MXC_V_ADC_CTRL1_AVG_AVG1 << MXC_F_ADC_CTRL1_AVG_POS) /**< CTRL1_AVG_AVG1 Setting */ 184 #define MXC_V_ADC_CTRL1_AVG_AVG2 ((uint32_t)0x1UL) /**< CTRL1_AVG_AVG2 Value */ 185 #define MXC_S_ADC_CTRL1_AVG_AVG2 (MXC_V_ADC_CTRL1_AVG_AVG2 << MXC_F_ADC_CTRL1_AVG_POS) /**< CTRL1_AVG_AVG2 Setting */ 186 #define MXC_V_ADC_CTRL1_AVG_AVG4 ((uint32_t)0x2UL) /**< CTRL1_AVG_AVG4 Value */ 187 #define MXC_S_ADC_CTRL1_AVG_AVG4 (MXC_V_ADC_CTRL1_AVG_AVG4 << MXC_F_ADC_CTRL1_AVG_POS) /**< CTRL1_AVG_AVG4 Setting */ 188 #define MXC_V_ADC_CTRL1_AVG_AVG8 ((uint32_t)0x3UL) /**< CTRL1_AVG_AVG8 Value */ 189 #define MXC_S_ADC_CTRL1_AVG_AVG8 (MXC_V_ADC_CTRL1_AVG_AVG8 << MXC_F_ADC_CTRL1_AVG_POS) /**< CTRL1_AVG_AVG8 Setting */ 190 #define MXC_V_ADC_CTRL1_AVG_AVG16 ((uint32_t)0x4UL) /**< CTRL1_AVG_AVG16 Value */ 191 #define MXC_S_ADC_CTRL1_AVG_AVG16 (MXC_V_ADC_CTRL1_AVG_AVG16 << MXC_F_ADC_CTRL1_AVG_POS) /**< CTRL1_AVG_AVG16 Setting */ 192 #define MXC_V_ADC_CTRL1_AVG_AVG32 ((uint32_t)0x5UL) /**< CTRL1_AVG_AVG32 Value */ 193 #define MXC_S_ADC_CTRL1_AVG_AVG32 (MXC_V_ADC_CTRL1_AVG_AVG32 << MXC_F_ADC_CTRL1_AVG_POS) /**< CTRL1_AVG_AVG32 Setting */ 194 195 #define MXC_F_ADC_CTRL1_NUM_SLOTS_POS 16 /**< CTRL1_NUM_SLOTS Position */ 196 #define MXC_F_ADC_CTRL1_NUM_SLOTS ((uint32_t)(0x1FUL << MXC_F_ADC_CTRL1_NUM_SLOTS_POS)) /**< CTRL1_NUM_SLOTS Mask */ 197 198 /**@} end of group ADC_CTRL1_Register */ 199 200 /** 201 * @ingroup adc_registers 202 * @defgroup ADC_CLKCTRL ADC_CLKCTRL 203 * @brief Clock Control Register. 204 * @{ 205 */ 206 #define MXC_F_ADC_CLKCTRL_CLKSEL_POS 0 /**< CLKCTRL_CLKSEL Position */ 207 #define MXC_F_ADC_CLKCTRL_CLKSEL ((uint32_t)(0x3UL << MXC_F_ADC_CLKCTRL_CLKSEL_POS)) /**< CLKCTRL_CLKSEL Mask */ 208 #define MXC_V_ADC_CLKCTRL_CLKSEL_HCLK ((uint32_t)0x0UL) /**< CLKCTRL_CLKSEL_HCLK Value */ 209 #define MXC_S_ADC_CLKCTRL_CLKSEL_HCLK (MXC_V_ADC_CLKCTRL_CLKSEL_HCLK << MXC_F_ADC_CLKCTRL_CLKSEL_POS) /**< CLKCTRL_CLKSEL_HCLK Setting */ 210 #define MXC_V_ADC_CLKCTRL_CLKSEL_CLK_ADC0 ((uint32_t)0x1UL) /**< CLKCTRL_CLKSEL_CLK_ADC0 Value */ 211 #define MXC_S_ADC_CLKCTRL_CLKSEL_CLK_ADC0 (MXC_V_ADC_CLKCTRL_CLKSEL_CLK_ADC0 << MXC_F_ADC_CLKCTRL_CLKSEL_POS) /**< CLKCTRL_CLKSEL_CLK_ADC0 Setting */ 212 #define MXC_V_ADC_CLKCTRL_CLKSEL_CLK_ADC1 ((uint32_t)0x2UL) /**< CLKCTRL_CLKSEL_CLK_ADC1 Value */ 213 #define MXC_S_ADC_CLKCTRL_CLKSEL_CLK_ADC1 (MXC_V_ADC_CLKCTRL_CLKSEL_CLK_ADC1 << MXC_F_ADC_CLKCTRL_CLKSEL_POS) /**< CLKCTRL_CLKSEL_CLK_ADC1 Setting */ 214 #define MXC_V_ADC_CLKCTRL_CLKSEL_CLK_ADC2 ((uint32_t)0x3UL) /**< CLKCTRL_CLKSEL_CLK_ADC2 Value */ 215 #define MXC_S_ADC_CLKCTRL_CLKSEL_CLK_ADC2 (MXC_V_ADC_CLKCTRL_CLKSEL_CLK_ADC2 << MXC_F_ADC_CLKCTRL_CLKSEL_POS) /**< CLKCTRL_CLKSEL_CLK_ADC2 Setting */ 216 217 #define MXC_F_ADC_CLKCTRL_CLKDIV_POS 4 /**< CLKCTRL_CLKDIV Position */ 218 #define MXC_F_ADC_CLKCTRL_CLKDIV ((uint32_t)(0x7UL << MXC_F_ADC_CLKCTRL_CLKDIV_POS)) /**< CLKCTRL_CLKDIV Mask */ 219 #define MXC_V_ADC_CLKCTRL_CLKDIV_DIV2 ((uint32_t)0x0UL) /**< CLKCTRL_CLKDIV_DIV2 Value */ 220 #define MXC_S_ADC_CLKCTRL_CLKDIV_DIV2 (MXC_V_ADC_CLKCTRL_CLKDIV_DIV2 << MXC_F_ADC_CLKCTRL_CLKDIV_POS) /**< CLKCTRL_CLKDIV_DIV2 Setting */ 221 #define MXC_V_ADC_CLKCTRL_CLKDIV_DIV4 ((uint32_t)0x1UL) /**< CLKCTRL_CLKDIV_DIV4 Value */ 222 #define MXC_S_ADC_CLKCTRL_CLKDIV_DIV4 (MXC_V_ADC_CLKCTRL_CLKDIV_DIV4 << MXC_F_ADC_CLKCTRL_CLKDIV_POS) /**< CLKCTRL_CLKDIV_DIV4 Setting */ 223 #define MXC_V_ADC_CLKCTRL_CLKDIV_DIV8 ((uint32_t)0x2UL) /**< CLKCTRL_CLKDIV_DIV8 Value */ 224 #define MXC_S_ADC_CLKCTRL_CLKDIV_DIV8 (MXC_V_ADC_CLKCTRL_CLKDIV_DIV8 << MXC_F_ADC_CLKCTRL_CLKDIV_POS) /**< CLKCTRL_CLKDIV_DIV8 Setting */ 225 #define MXC_V_ADC_CLKCTRL_CLKDIV_DIV16 ((uint32_t)0x3UL) /**< CLKCTRL_CLKDIV_DIV16 Value */ 226 #define MXC_S_ADC_CLKCTRL_CLKDIV_DIV16 (MXC_V_ADC_CLKCTRL_CLKDIV_DIV16 << MXC_F_ADC_CLKCTRL_CLKDIV_POS) /**< CLKCTRL_CLKDIV_DIV16 Setting */ 227 #define MXC_V_ADC_CLKCTRL_CLKDIV_DIV1 ((uint32_t)0x4UL) /**< CLKCTRL_CLKDIV_DIV1 Value */ 228 #define MXC_S_ADC_CLKCTRL_CLKDIV_DIV1 (MXC_V_ADC_CLKCTRL_CLKDIV_DIV1 << MXC_F_ADC_CLKCTRL_CLKDIV_POS) /**< CLKCTRL_CLKDIV_DIV1 Setting */ 229 230 /**@} end of group ADC_CLKCTRL_Register */ 231 232 /** 233 * @ingroup adc_registers 234 * @defgroup ADC_SAMPCLKCTRL ADC_SAMPCLKCTRL 235 * @brief Sample Clock Control Register. 236 * @{ 237 */ 238 #define MXC_F_ADC_SAMPCLKCTRL_TRACK_CNT_POS 0 /**< SAMPCLKCTRL_TRACK_CNT Position */ 239 #define MXC_F_ADC_SAMPCLKCTRL_TRACK_CNT ((uint32_t)(0xFFFFUL << MXC_F_ADC_SAMPCLKCTRL_TRACK_CNT_POS)) /**< SAMPCLKCTRL_TRACK_CNT Mask */ 240 241 #define MXC_F_ADC_SAMPCLKCTRL_IDLE_CNT_POS 16 /**< SAMPCLKCTRL_IDLE_CNT Position */ 242 #define MXC_F_ADC_SAMPCLKCTRL_IDLE_CNT ((uint32_t)(0xFFFFUL << MXC_F_ADC_SAMPCLKCTRL_IDLE_CNT_POS)) /**< SAMPCLKCTRL_IDLE_CNT Mask */ 243 244 /**@} end of group ADC_SAMPCLKCTRL_Register */ 245 246 /** 247 * @ingroup adc_registers 248 * @defgroup ADC_CHSEL0 ADC_CHSEL0 249 * @brief Channel Select Register 0. 250 * @{ 251 */ 252 #define MXC_F_ADC_CHSEL0_SLOT0_ID_POS 0 /**< CHSEL0_SLOT0_ID Position */ 253 #define MXC_F_ADC_CHSEL0_SLOT0_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL0_SLOT0_ID_POS)) /**< CHSEL0_SLOT0_ID Mask */ 254 255 #define MXC_F_ADC_CHSEL0_SLOT1_ID_POS 8 /**< CHSEL0_SLOT1_ID Position */ 256 #define MXC_F_ADC_CHSEL0_SLOT1_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL0_SLOT1_ID_POS)) /**< CHSEL0_SLOT1_ID Mask */ 257 258 #define MXC_F_ADC_CHSEL0_SLOT2_ID_POS 16 /**< CHSEL0_SLOT2_ID Position */ 259 #define MXC_F_ADC_CHSEL0_SLOT2_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL0_SLOT2_ID_POS)) /**< CHSEL0_SLOT2_ID Mask */ 260 261 #define MXC_F_ADC_CHSEL0_SLOT3_ID_POS 24 /**< CHSEL0_SLOT3_ID Position */ 262 #define MXC_F_ADC_CHSEL0_SLOT3_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL0_SLOT3_ID_POS)) /**< CHSEL0_SLOT3_ID Mask */ 263 264 /**@} end of group ADC_CHSEL0_Register */ 265 266 /** 267 * @ingroup adc_registers 268 * @defgroup ADC_CHSEL1 ADC_CHSEL1 269 * @brief Channel Select Register 1. 270 * @{ 271 */ 272 #define MXC_F_ADC_CHSEL1_SLOT4_ID_POS 0 /**< CHSEL1_SLOT4_ID Position */ 273 #define MXC_F_ADC_CHSEL1_SLOT4_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL1_SLOT4_ID_POS)) /**< CHSEL1_SLOT4_ID Mask */ 274 275 #define MXC_F_ADC_CHSEL1_SLOT5_ID_POS 8 /**< CHSEL1_SLOT5_ID Position */ 276 #define MXC_F_ADC_CHSEL1_SLOT5_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL1_SLOT5_ID_POS)) /**< CHSEL1_SLOT5_ID Mask */ 277 278 #define MXC_F_ADC_CHSEL1_SLOT6_ID_POS 16 /**< CHSEL1_SLOT6_ID Position */ 279 #define MXC_F_ADC_CHSEL1_SLOT6_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL1_SLOT6_ID_POS)) /**< CHSEL1_SLOT6_ID Mask */ 280 281 #define MXC_F_ADC_CHSEL1_SLOT7_ID_POS 24 /**< CHSEL1_SLOT7_ID Position */ 282 #define MXC_F_ADC_CHSEL1_SLOT7_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL1_SLOT7_ID_POS)) /**< CHSEL1_SLOT7_ID Mask */ 283 284 /**@} end of group ADC_CHSEL1_Register */ 285 286 /** 287 * @ingroup adc_registers 288 * @defgroup ADC_CHSEL2 ADC_CHSEL2 289 * @brief Channel Select Register 2. 290 * @{ 291 */ 292 #define MXC_F_ADC_CHSEL2_SLOT8_ID_POS 0 /**< CHSEL2_SLOT8_ID Position */ 293 #define MXC_F_ADC_CHSEL2_SLOT8_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL2_SLOT8_ID_POS)) /**< CHSEL2_SLOT8_ID Mask */ 294 295 #define MXC_F_ADC_CHSEL2_SLOT9_ID_POS 8 /**< CHSEL2_SLOT9_ID Position */ 296 #define MXC_F_ADC_CHSEL2_SLOT9_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL2_SLOT9_ID_POS)) /**< CHSEL2_SLOT9_ID Mask */ 297 298 #define MXC_F_ADC_CHSEL2_SLOT10_ID_POS 16 /**< CHSEL2_SLOT10_ID Position */ 299 #define MXC_F_ADC_CHSEL2_SLOT10_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL2_SLOT10_ID_POS)) /**< CHSEL2_SLOT10_ID Mask */ 300 301 #define MXC_F_ADC_CHSEL2_SLOT11_ID_POS 24 /**< CHSEL2_SLOT11_ID Position */ 302 #define MXC_F_ADC_CHSEL2_SLOT11_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL2_SLOT11_ID_POS)) /**< CHSEL2_SLOT11_ID Mask */ 303 304 /**@} end of group ADC_CHSEL2_Register */ 305 306 /** 307 * @ingroup adc_registers 308 * @defgroup ADC_CHSEL3 ADC_CHSEL3 309 * @brief Channel Select Register 3. 310 * @{ 311 */ 312 #define MXC_F_ADC_CHSEL3_SLOT12_ID_POS 0 /**< CHSEL3_SLOT12_ID Position */ 313 #define MXC_F_ADC_CHSEL3_SLOT12_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL3_SLOT12_ID_POS)) /**< CHSEL3_SLOT12_ID Mask */ 314 315 #define MXC_F_ADC_CHSEL3_SLOT13_ID_POS 8 /**< CHSEL3_SLOT13_ID Position */ 316 #define MXC_F_ADC_CHSEL3_SLOT13_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL3_SLOT13_ID_POS)) /**< CHSEL3_SLOT13_ID Mask */ 317 318 #define MXC_F_ADC_CHSEL3_SLOT14_ID_POS 16 /**< CHSEL3_SLOT14_ID Position */ 319 #define MXC_F_ADC_CHSEL3_SLOT14_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL3_SLOT14_ID_POS)) /**< CHSEL3_SLOT14_ID Mask */ 320 321 #define MXC_F_ADC_CHSEL3_SLOT15_ID_POS 24 /**< CHSEL3_SLOT15_ID Position */ 322 #define MXC_F_ADC_CHSEL3_SLOT15_ID ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL3_SLOT15_ID_POS)) /**< CHSEL3_SLOT15_ID Mask */ 323 324 /**@} end of group ADC_CHSEL3_Register */ 325 326 /** 327 * @ingroup adc_registers 328 * @defgroup ADC_RESTART ADC_RESTART 329 * @brief Restart Count Control Register 330 * @{ 331 */ 332 #define MXC_F_ADC_RESTART_CNT_POS 0 /**< RESTART_CNT Position */ 333 #define MXC_F_ADC_RESTART_CNT ((uint32_t)(0xFFFFUL << MXC_F_ADC_RESTART_CNT_POS)) /**< RESTART_CNT Mask */ 334 335 /**@} end of group ADC_RESTART_Register */ 336 337 /** 338 * @ingroup adc_registers 339 * @defgroup ADC_DATAFMT ADC_DATAFMT 340 * @brief Channel Data Format Register 341 * @{ 342 */ 343 #define MXC_F_ADC_DATAFMT_MODE_POS 0 /**< DATAFMT_MODE Position */ 344 #define MXC_F_ADC_DATAFMT_MODE ((uint32_t)(0xFFFFFFFFUL << MXC_F_ADC_DATAFMT_MODE_POS)) /**< DATAFMT_MODE Mask */ 345 346 /**@} end of group ADC_DATAFMT_Register */ 347 348 /** 349 * @ingroup adc_registers 350 * @defgroup ADC_FIFODMACTRL ADC_FIFODMACTRL 351 * @brief FIFO and DMA control 352 * @{ 353 */ 354 #define MXC_F_ADC_FIFODMACTRL_DMA_EN_POS 0 /**< FIFODMACTRL_DMA_EN Position */ 355 #define MXC_F_ADC_FIFODMACTRL_DMA_EN ((uint32_t)(0x1UL << MXC_F_ADC_FIFODMACTRL_DMA_EN_POS)) /**< FIFODMACTRL_DMA_EN Mask */ 356 357 #define MXC_F_ADC_FIFODMACTRL_FLUSH_POS 1 /**< FIFODMACTRL_FLUSH Position */ 358 #define MXC_F_ADC_FIFODMACTRL_FLUSH ((uint32_t)(0x1UL << MXC_F_ADC_FIFODMACTRL_FLUSH_POS)) /**< FIFODMACTRL_FLUSH Mask */ 359 360 #define MXC_F_ADC_FIFODMACTRL_DATA_FORMAT_POS 2 /**< FIFODMACTRL_DATA_FORMAT Position */ 361 #define MXC_F_ADC_FIFODMACTRL_DATA_FORMAT ((uint32_t)(0x3UL << MXC_F_ADC_FIFODMACTRL_DATA_FORMAT_POS)) /**< FIFODMACTRL_DATA_FORMAT Mask */ 362 #define MXC_V_ADC_FIFODMACTRL_DATA_FORMAT_DATA_STATUS ((uint32_t)0x0UL) /**< FIFODMACTRL_DATA_FORMAT_DATA_STATUS Value */ 363 #define MXC_S_ADC_FIFODMACTRL_DATA_FORMAT_DATA_STATUS (MXC_V_ADC_FIFODMACTRL_DATA_FORMAT_DATA_STATUS << MXC_F_ADC_FIFODMACTRL_DATA_FORMAT_POS) /**< FIFODMACTRL_DATA_FORMAT_DATA_STATUS Setting */ 364 #define MXC_V_ADC_FIFODMACTRL_DATA_FORMAT_DATA_ONLY ((uint32_t)0x1UL) /**< FIFODMACTRL_DATA_FORMAT_DATA_ONLY Value */ 365 #define MXC_S_ADC_FIFODMACTRL_DATA_FORMAT_DATA_ONLY (MXC_V_ADC_FIFODMACTRL_DATA_FORMAT_DATA_ONLY << MXC_F_ADC_FIFODMACTRL_DATA_FORMAT_POS) /**< FIFODMACTRL_DATA_FORMAT_DATA_ONLY Setting */ 366 #define MXC_V_ADC_FIFODMACTRL_DATA_FORMAT_RAW_DATA_ONLY ((uint32_t)0x2UL) /**< FIFODMACTRL_DATA_FORMAT_RAW_DATA_ONLY Value */ 367 #define MXC_S_ADC_FIFODMACTRL_DATA_FORMAT_RAW_DATA_ONLY (MXC_V_ADC_FIFODMACTRL_DATA_FORMAT_RAW_DATA_ONLY << MXC_F_ADC_FIFODMACTRL_DATA_FORMAT_POS) /**< FIFODMACTRL_DATA_FORMAT_RAW_DATA_ONLY Setting */ 368 369 #define MXC_F_ADC_FIFODMACTRL_THRESH_POS 8 /**< FIFODMACTRL_THRESH Position */ 370 #define MXC_F_ADC_FIFODMACTRL_THRESH ((uint32_t)(0xFFUL << MXC_F_ADC_FIFODMACTRL_THRESH_POS)) /**< FIFODMACTRL_THRESH Mask */ 371 372 /**@} end of group ADC_FIFODMACTRL_Register */ 373 374 /** 375 * @ingroup adc_registers 376 * @defgroup ADC_DATA ADC_DATA 377 * @brief Data Register (FIFO). 378 * @{ 379 */ 380 #define MXC_F_ADC_DATA_DATA_POS 0 /**< DATA_DATA Position */ 381 #define MXC_F_ADC_DATA_DATA ((uint32_t)(0xFFFFUL << MXC_F_ADC_DATA_DATA_POS)) /**< DATA_DATA Mask */ 382 383 #define MXC_F_ADC_DATA_CHAN_POS 16 /**< DATA_CHAN Position */ 384 #define MXC_F_ADC_DATA_CHAN ((uint32_t)(0x1FUL << MXC_F_ADC_DATA_CHAN_POS)) /**< DATA_CHAN Mask */ 385 386 #define MXC_F_ADC_DATA_INVALID_POS 24 /**< DATA_INVALID Position */ 387 #define MXC_F_ADC_DATA_INVALID ((uint32_t)(0x1UL << MXC_F_ADC_DATA_INVALID_POS)) /**< DATA_INVALID Mask */ 388 389 #define MXC_F_ADC_DATA_CLIPPED_POS 31 /**< DATA_CLIPPED Position */ 390 #define MXC_F_ADC_DATA_CLIPPED ((uint32_t)(0x1UL << MXC_F_ADC_DATA_CLIPPED_POS)) /**< DATA_CLIPPED Mask */ 391 392 /**@} end of group ADC_DATA_Register */ 393 394 /** 395 * @ingroup adc_registers 396 * @defgroup ADC_STATUS ADC_STATUS 397 * @brief Status Register 398 * @{ 399 */ 400 #define MXC_F_ADC_STATUS_READY_POS 0 /**< STATUS_READY Position */ 401 #define MXC_F_ADC_STATUS_READY ((uint32_t)(0x1UL << MXC_F_ADC_STATUS_READY_POS)) /**< STATUS_READY Mask */ 402 403 #define MXC_F_ADC_STATUS_EMPTY_POS 1 /**< STATUS_EMPTY Position */ 404 #define MXC_F_ADC_STATUS_EMPTY ((uint32_t)(0x1UL << MXC_F_ADC_STATUS_EMPTY_POS)) /**< STATUS_EMPTY Mask */ 405 406 #define MXC_F_ADC_STATUS_FULL_POS 2 /**< STATUS_FULL Position */ 407 #define MXC_F_ADC_STATUS_FULL ((uint32_t)(0x1UL << MXC_F_ADC_STATUS_FULL_POS)) /**< STATUS_FULL Mask */ 408 409 #define MXC_F_ADC_STATUS_FIFO_LEVEL_POS 8 /**< STATUS_FIFO_LEVEL Position */ 410 #define MXC_F_ADC_STATUS_FIFO_LEVEL ((uint32_t)(0xFFUL << MXC_F_ADC_STATUS_FIFO_LEVEL_POS)) /**< STATUS_FIFO_LEVEL Mask */ 411 412 /**@} end of group ADC_STATUS_Register */ 413 414 /** 415 * @ingroup adc_registers 416 * @defgroup ADC_CHSTATUS ADC_CHSTATUS 417 * @brief Channel Status 418 * @{ 419 */ 420 #define MXC_F_ADC_CHSTATUS_CLIPPED_POS 0 /**< CHSTATUS_CLIPPED Position */ 421 #define MXC_F_ADC_CHSTATUS_CLIPPED ((uint32_t)(0xFFFFFFFFUL << MXC_F_ADC_CHSTATUS_CLIPPED_POS)) /**< CHSTATUS_CLIPPED Mask */ 422 423 /**@} end of group ADC_CHSTATUS_Register */ 424 425 /** 426 * @ingroup adc_registers 427 * @defgroup ADC_INTEN ADC_INTEN 428 * @brief Interrupt Enable Register. 429 * @{ 430 */ 431 #define MXC_F_ADC_INTEN_READY_POS 0 /**< INTEN_READY Position */ 432 #define MXC_F_ADC_INTEN_READY ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_READY_POS)) /**< INTEN_READY Mask */ 433 434 #define MXC_F_ADC_INTEN_ABORT_POS 2 /**< INTEN_ABORT Position */ 435 #define MXC_F_ADC_INTEN_ABORT ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_ABORT_POS)) /**< INTEN_ABORT Mask */ 436 437 #define MXC_F_ADC_INTEN_START_DET_POS 3 /**< INTEN_START_DET Position */ 438 #define MXC_F_ADC_INTEN_START_DET ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_START_DET_POS)) /**< INTEN_START_DET Mask */ 439 440 #define MXC_F_ADC_INTEN_SEQ_STARTED_POS 4 /**< INTEN_SEQ_STARTED Position */ 441 #define MXC_F_ADC_INTEN_SEQ_STARTED ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_SEQ_STARTED_POS)) /**< INTEN_SEQ_STARTED Mask */ 442 443 #define MXC_F_ADC_INTEN_SEQ_DONE_POS 5 /**< INTEN_SEQ_DONE Position */ 444 #define MXC_F_ADC_INTEN_SEQ_DONE ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_SEQ_DONE_POS)) /**< INTEN_SEQ_DONE Mask */ 445 446 #define MXC_F_ADC_INTEN_CONV_DONE_POS 6 /**< INTEN_CONV_DONE Position */ 447 #define MXC_F_ADC_INTEN_CONV_DONE ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_CONV_DONE_POS)) /**< INTEN_CONV_DONE Mask */ 448 449 #define MXC_F_ADC_INTEN_CLIPPED_POS 7 /**< INTEN_CLIPPED Position */ 450 #define MXC_F_ADC_INTEN_CLIPPED ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_CLIPPED_POS)) /**< INTEN_CLIPPED Mask */ 451 452 #define MXC_F_ADC_INTEN_FIFO_LVL_POS 8 /**< INTEN_FIFO_LVL Position */ 453 #define MXC_F_ADC_INTEN_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_FIFO_LVL_POS)) /**< INTEN_FIFO_LVL Mask */ 454 455 #define MXC_F_ADC_INTEN_FIFO_UFL_POS 9 /**< INTEN_FIFO_UFL Position */ 456 #define MXC_F_ADC_INTEN_FIFO_UFL ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_FIFO_UFL_POS)) /**< INTEN_FIFO_UFL Mask */ 457 458 #define MXC_F_ADC_INTEN_FIFO_OFL_POS 10 /**< INTEN_FIFO_OFL Position */ 459 #define MXC_F_ADC_INTEN_FIFO_OFL ((uint32_t)(0x1UL << MXC_F_ADC_INTEN_FIFO_OFL_POS)) /**< INTEN_FIFO_OFL Mask */ 460 461 /**@} end of group ADC_INTEN_Register */ 462 463 /** 464 * @ingroup adc_registers 465 * @defgroup ADC_INTFL ADC_INTFL 466 * @brief Interrupt Flags Register. 467 * @{ 468 */ 469 #define MXC_F_ADC_INTFL_READY_POS 0 /**< INTFL_READY Position */ 470 #define MXC_F_ADC_INTFL_READY ((uint32_t)(0x1UL << MXC_F_ADC_INTFL_READY_POS)) /**< INTFL_READY Mask */ 471 472 #define MXC_F_ADC_INTFL_ABORT_POS 2 /**< INTFL_ABORT Position */ 473 #define MXC_F_ADC_INTFL_ABORT ((uint32_t)(0x1UL << MXC_F_ADC_INTFL_ABORT_POS)) /**< INTFL_ABORT Mask */ 474 475 #define MXC_F_ADC_INTFL_START_DET_POS 3 /**< INTFL_START_DET Position */ 476 #define MXC_F_ADC_INTFL_START_DET ((uint32_t)(0x1UL << MXC_F_ADC_INTFL_START_DET_POS)) /**< INTFL_START_DET Mask */ 477 478 #define MXC_F_ADC_INTFL_SEQ_STARTED_POS 4 /**< INTFL_SEQ_STARTED Position */ 479 #define MXC_F_ADC_INTFL_SEQ_STARTED ((uint32_t)(0x1UL << MXC_F_ADC_INTFL_SEQ_STARTED_POS)) /**< INTFL_SEQ_STARTED Mask */ 480 481 #define MXC_F_ADC_INTFL_SEQ_DONE_POS 5 /**< INTFL_SEQ_DONE Position */ 482 #define MXC_F_ADC_INTFL_SEQ_DONE ((uint32_t)(0x1UL << MXC_F_ADC_INTFL_SEQ_DONE_POS)) /**< INTFL_SEQ_DONE Mask */ 483 484 #define MXC_F_ADC_INTFL_CONV_DONE_POS 6 /**< INTFL_CONV_DONE Position */ 485 #define MXC_F_ADC_INTFL_CONV_DONE ((uint32_t)(0x1UL << MXC_F_ADC_INTFL_CONV_DONE_POS)) /**< INTFL_CONV_DONE Mask */ 486 487 #define MXC_F_ADC_INTFL_CLIPPED_POS 7 /**< INTFL_CLIPPED Position */ 488 #define MXC_F_ADC_INTFL_CLIPPED ((uint32_t)(0x1UL << MXC_F_ADC_INTFL_CLIPPED_POS)) /**< INTFL_CLIPPED Mask */ 489 490 #define MXC_F_ADC_INTFL_FIFO_LVL_POS 8 /**< INTFL_FIFO_LVL Position */ 491 #define MXC_F_ADC_INTFL_FIFO_LVL ((uint32_t)(0x1UL << MXC_F_ADC_INTFL_FIFO_LVL_POS)) /**< INTFL_FIFO_LVL Mask */ 492 493 #define MXC_F_ADC_INTFL_FIFO_UFL_POS 9 /**< INTFL_FIFO_UFL Position */ 494 #define MXC_F_ADC_INTFL_FIFO_UFL ((uint32_t)(0x1UL << MXC_F_ADC_INTFL_FIFO_UFL_POS)) /**< INTFL_FIFO_UFL Mask */ 495 496 #define MXC_F_ADC_INTFL_FIFO_OFL_POS 10 /**< INTFL_FIFO_OFL Position */ 497 #define MXC_F_ADC_INTFL_FIFO_OFL ((uint32_t)(0x1UL << MXC_F_ADC_INTFL_FIFO_OFL_POS)) /**< INTFL_FIFO_OFL Mask */ 498 499 /**@} end of group ADC_INTFL_Register */ 500 501 /** 502 * @ingroup adc_registers 503 * @defgroup ADC_SFRADDROFFSET ADC_SFRADDROFFSET 504 * @brief SFR Address Offset Register 505 * @{ 506 */ 507 #define MXC_F_ADC_SFRADDROFFSET_OFFSET_POS 0 /**< SFRADDROFFSET_OFFSET Position */ 508 #define MXC_F_ADC_SFRADDROFFSET_OFFSET ((uint32_t)(0xFFUL << MXC_F_ADC_SFRADDROFFSET_OFFSET_POS)) /**< SFRADDROFFSET_OFFSET Mask */ 509 510 /**@} end of group ADC_SFRADDROFFSET_Register */ 511 512 /** 513 * @ingroup adc_registers 514 * @defgroup ADC_SFRADDR ADC_SFRADDR 515 * @brief SFR Address Register 516 * @{ 517 */ 518 #define MXC_F_ADC_SFRADDR_ADDR_POS 0 /**< SFRADDR_ADDR Position */ 519 #define MXC_F_ADC_SFRADDR_ADDR ((uint32_t)(0xFFUL << MXC_F_ADC_SFRADDR_ADDR_POS)) /**< SFRADDR_ADDR Mask */ 520 521 /**@} end of group ADC_SFRADDR_Register */ 522 523 /** 524 * @ingroup adc_registers 525 * @defgroup ADC_SFRWRDATA ADC_SFRWRDATA 526 * @brief SFR Write Data Register 527 * @{ 528 */ 529 #define MXC_F_ADC_SFRWRDATA_DATA_POS 0 /**< SFRWRDATA_DATA Position */ 530 #define MXC_F_ADC_SFRWRDATA_DATA ((uint32_t)(0xFFUL << MXC_F_ADC_SFRWRDATA_DATA_POS)) /**< SFRWRDATA_DATA Mask */ 531 532 /**@} end of group ADC_SFRWRDATA_Register */ 533 534 /** 535 * @ingroup adc_registers 536 * @defgroup ADC_SFRRDDATA ADC_SFRRDDATA 537 * @brief SFR Read Data Register 538 * @{ 539 */ 540 #define MXC_F_ADC_SFRRDDATA_DATA_POS 0 /**< SFRRDDATA_DATA Position */ 541 #define MXC_F_ADC_SFRRDDATA_DATA ((uint32_t)(0xFFUL << MXC_F_ADC_SFRRDDATA_DATA_POS)) /**< SFRRDDATA_DATA Mask */ 542 543 /**@} end of group ADC_SFRRDDATA_Register */ 544 545 /** 546 * @ingroup adc_registers 547 * @defgroup ADC_SFRSTATUS ADC_SFRSTATUS 548 * @brief SFR Status Register 549 * @{ 550 */ 551 #define MXC_F_ADC_SFRSTATUS_NACK_POS 0 /**< SFRSTATUS_NACK Position */ 552 #define MXC_F_ADC_SFRSTATUS_NACK ((uint32_t)(0x1UL << MXC_F_ADC_SFRSTATUS_NACK_POS)) /**< SFRSTATUS_NACK Mask */ 553 554 /**@} end of group ADC_SFRSTATUS_Register */ 555 556 #ifdef __cplusplus 557 } 558 #endif 559 560 #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32662_INCLUDE_ADC_REGS_H_ 561
